Ruben Undheim d5aac2650f Basic test for checking correct synthesis of SystemVerilog interfaces		2018-10-18 22:40:53 +02:00
..
.gitignore
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v	Fixed typo in tests/simple/arraycells.v	2017-01-04 12:39:01 +01:00
arrays01.v
carryadd.v
constmuldivmod.v	Added opt_expr support for div/mod by power-of-two	2016-05-29 12:17:36 +02:00
constpower.v
dff_different_styles.v
fiedler-cooley.v
forgen01.v
forgen02.v
fsm.v
generate.v
graphtest.v	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
hierarchy.v
hierdefparam.v	Added support for hierarchical defparams	2016-11-15 13:35:19 +01:00
i2c_master_tests.v
loops.v
macros.v
mem2reg.v	Added another mem2reg test case	2016-08-21 13:45:46 +02:00
mem_arst.v
memory.v	Fixed bug with memories that do not have a down-to-zero data width	2016-08-22 14:27:46 +02:00
multiplier.v
muxtree.v
omsp_dbg_uart.v
operators.v
paramods.v
partsel.v
process.v
realexpr.v
repwhile.v
rotate.v
run-test.sh	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
scopes.v
signedexpr.v
sincos.v
specify.v	Fix tests/simple/specify.v	2018-03-27 14:34:00 +02:00
subbytes.v
task_func.v
undef_eqx_nex.v
usb_phy_tests.v
values.v
vloghammer.v
wreduce.v