yosys/tests/verilog/signed_concat.ys at ef9772bd8d4186071cf1d500541a74fecb51ec1d - mirrors/yosys - Libre-Chip.org

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Zachary Snow 73cf658996 verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.

2025-03-07 20:27:02 +01:00

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 read_verilog signed_concat.v
 hierarchy
 proc
 flatten gate
 equiv_make gold gate equiv
 equiv_simple
 equiv_status -assert