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yosys/tests/verific/README.md
Akash Levy 0db45a6796 Reenable VHDL
2026-04-16 04:03:31 -07:00

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Verific Test Cases

Disabled

  • memory_semantics: relies on initial values being retained, which we do not want
  • rom_case: we need different behavior for multi-port memories
  • blackbox*: we need different behavior for parametrized blackboxes
  • chformal: relies on initial values being retained, which we do not want