mirror of
https://github.com/YosysHQ/yosys
synced 2025-09-30 21:19:30 +00:00
e9aacd8a05
This code is quite confusing because there are two "is the cell known" filters applied, one while building the cell vector and one after building the cell vector, and they're subtly different. I'm preserving the actual behaviour here but it looks like there is, or was, a bug here.
387 lines
12 KiB
C++
387 lines
12 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/ffinit.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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#include "libs/sha1/sha1.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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#include <unordered_map>
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#include <array>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptMergeWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap assign_map;
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FfInitVals initvals;
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bool mode_share_all;
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CellTypes ct;
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int total_count;
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static Hasher hash_pmux_in(const SigSpec& sig_s, const SigSpec& sig_b, Hasher h)
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{
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int s_width = GetSize(sig_s);
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int width = GetSize(sig_b) / s_width;
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hashlib::commutative_hash comm;
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for (int i = 0; i < s_width; i++)
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comm.eat(hash_ops<std::pair<SigBit, SigSpec>>::hash({sig_s[i], sig_b.extract(i*width, width)}));
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return comm.hash_into(h);
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}
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static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
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{
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SigSpec sig_s = conn.at(ID::S);
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SigSpec sig_b = conn.at(ID::B);
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int s_width = GetSize(sig_s);
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int width = GetSize(sig_b) / s_width;
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vector<pair<SigBit, SigSpec>> sb_pairs;
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for (int i = 0; i < s_width; i++)
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sb_pairs.push_back(pair<SigBit, SigSpec>(sig_s[i], sig_b.extract(i*width, width)));
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std::sort(sb_pairs.begin(), sb_pairs.end());
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conn[ID::S] = SigSpec();
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conn[ID::B] = SigSpec();
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for (auto &it : sb_pairs) {
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conn[ID::S].append(it.first);
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conn[ID::B].append(it.second);
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}
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}
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Hasher hash_cell_inputs(const RTLIL::Cell *cell, Hasher h) const
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{
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// TODO: when implemented, use celltypes to match:
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// (builtin || stdcell) && (unary || binary) && symmetrical
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
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ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
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hashlib::commutative_hash comm;
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comm.eat(hash_ops<RTLIL::SigSpec>::hash(assign_map(cell->getPort(ID::A))));
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comm.eat(hash_ops<RTLIL::SigSpec>::hash(assign_map(cell->getPort(ID::B))));
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h = comm.hash_into(h);
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} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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SigSpec a = assign_map(cell->getPort(ID::A));
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a.sort();
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h = a.hash_into(h);
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} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
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SigSpec a = assign_map(cell->getPort(ID::A));
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a.sort_and_unify();
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h = a.hash_into(h);
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} else if (cell->type == ID($pmux)) {
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SigSpec sig_s = assign_map(cell->getPort(ID::S));
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SigSpec sig_b = assign_map(cell->getPort(ID::B));
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h = hash_pmux_in(sig_s, sig_b, h);
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h = assign_map(cell->getPort(ID::A)).hash_into(h);
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} else {
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hashlib::commutative_hash comm;
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for (const auto& [port, sig] : cell->connections()) {
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if (cell->output(port))
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continue;
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comm.eat(hash_ops<std::pair<IdString, SigSpec>>::hash(port, assign_map(sig)));
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}
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h = comm.hash_into(h);
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if (cell->is_builtin_ff())
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h = initvals(cell->getPort(ID::Q)).hash_into(h);
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}
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return h;
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}
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static Hasher hash_cell_parameters(const RTLIL::Cell *cell, Hasher h)
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{
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hashlib::commutative_hash comm;
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for (const auto& param : cell->parameters) {
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comm.eat(hash_ops<std::pair<IdString, Const>>::hash(param));
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}
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return comm.hash_into(h);
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}
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Hasher hash_cell_function(const RTLIL::Cell *cell, Hasher h) const
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{
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h.eat(cell->type);
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h = hash_cell_inputs(cell, h);
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h = hash_cell_parameters(cell, h);
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return h;
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}
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bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const
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{
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if (cell1 == cell2) return true;
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if (cell1->type != cell2->type) return false;
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if (cell1->parameters != cell2->parameters)
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return false;
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if (cell1->connections_.size() != cell2->connections_.size())
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return false;
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for (const auto &it : cell1->connections_)
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if (!cell2->connections_.count(it.first))
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return false;
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decltype(Cell::connections_) conn1, conn2;
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conn1.reserve(cell1->connections_.size());
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conn2.reserve(cell1->connections_.size());
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for (const auto &it : cell1->connections_) {
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if (cell1->output(it.first)) {
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if (it.first == ID::Q && cell1->is_builtin_ff()) {
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// For the 'Q' output of state elements,
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// use the (* init *) attribute value
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conn1[it.first] = initvals(it.second);
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conn2[it.first] = initvals(cell2->getPort(it.first));
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}
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else {
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conn1[it.first] = RTLIL::SigSpec();
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conn2[it.first] = RTLIL::SigSpec();
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}
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}
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else {
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conn1[it.first] = assign_map(it.second);
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conn2[it.first] = assign_map(cell2->getPort(it.first));
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}
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}
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if (cell1->type == ID($and) || cell1->type == ID($or) || cell1->type == ID($xor) || cell1->type == ID($xnor) || cell1->type == ID($add) || cell1->type == ID($mul) ||
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cell1->type == ID($logic_and) || cell1->type == ID($logic_or) || cell1->type == ID($_AND_) || cell1->type == ID($_OR_) || cell1->type == ID($_XOR_)) {
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if (conn1.at(ID::A) < conn1.at(ID::B)) {
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RTLIL::SigSpec tmp = conn1[ID::A];
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conn1[ID::A] = conn1[ID::B];
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conn1[ID::B] = tmp;
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}
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if (conn2.at(ID::A) < conn2.at(ID::B)) {
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RTLIL::SigSpec tmp = conn2[ID::A];
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conn2[ID::A] = conn2[ID::B];
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conn2[ID::B] = tmp;
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}
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} else
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if (cell1->type == ID($reduce_xor) || cell1->type == ID($reduce_xnor)) {
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conn1[ID::A].sort();
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conn2[ID::A].sort();
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} else
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if (cell1->type == ID($reduce_and) || cell1->type == ID($reduce_or) || cell1->type == ID($reduce_bool)) {
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conn1[ID::A].sort_and_unify();
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conn2[ID::A].sort_and_unify();
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} else
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if (cell1->type == ID($pmux)) {
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sort_pmux_conn(conn1);
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sort_pmux_conn(conn2);
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}
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return conn1 == conn2;
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}
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bool has_dont_care_initval(const RTLIL::Cell *cell)
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{
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if (!cell->is_builtin_ff())
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return false;
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return !initvals(cell->getPort(ID::Q)).is_fully_def();
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}
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OptMergeWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all, bool mode_keepdc) :
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design(design), module(module), mode_share_all(mode_share_all)
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{
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total_count = 0;
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ct.setup_internals();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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if (mode_nomux) {
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ct.cell_types.erase(ID($mux));
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ct.cell_types.erase(ID($pmux));
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}
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ct.cell_types.erase(ID($tribuf));
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ct.cell_types.erase(ID($_TBUF_));
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ct.cell_types.erase(ID($anyseq));
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ct.cell_types.erase(ID($anyconst));
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ct.cell_types.erase(ID($allseq));
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ct.cell_types.erase(ID($allconst));
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log("Finding identical cells in module `%s'.\n", module->name);
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assign_map.set(module);
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initvals.set(&assign_map, module);
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bool did_something = true;
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// A cell may have to go through a lot of collisions if the hash
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// function is performing poorly, but it's a symptom of something bad
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// beyond the user's control.
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while (did_something)
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{
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std::vector<RTLIL::Cell*> cells;
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cells.reserve(module->cells().size());
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for (auto cell : module->cells()) {
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if (!design->selected(module, cell))
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continue;
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if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
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// Ignore those for performance: meminit can have an excessively large port,
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// mem can have an excessively large parameter holding the init data
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continue;
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}
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if (cell->type == ID($scopeinfo))
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continue;
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if (mode_keepdc && has_dont_care_initval(cell))
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continue;
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if (!cell->known())
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continue;
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if (!mode_share_all && !ct.cell_known(cell->type))
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continue;
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cells.push_back(cell);
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}
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did_something = false;
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// We keep a set of known cells. They're hashed with our hash_cell_function
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// and compared with our compare_cell_parameters_and_connections.
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// Both need to capture OptMergeWorker to access initvals
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struct CellPtrHash {
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const OptMergeWorker& worker;
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CellPtrHash(const OptMergeWorker& w) : worker(w) {}
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std::size_t operator()(const Cell* c) const {
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return (std::size_t)worker.hash_cell_function(c, Hasher()).yield();
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}
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};
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struct CellPtrEqual {
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const OptMergeWorker& worker;
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CellPtrEqual(const OptMergeWorker& w) : worker(w) {}
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bool operator()(const Cell* lhs, const Cell* rhs) const {
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return worker.compare_cell_parameters_and_connections(lhs, rhs);
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}
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};
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std::unordered_set<
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RTLIL::Cell*,
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CellPtrHash,
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CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this));
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for (auto cell : cells)
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{
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auto [cell_in_map, inserted] = known_cells.insert(cell);
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if (!inserted) {
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// We've failed to insert since we already have an equivalent cell
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Cell* other_cell = *cell_in_map;
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if (cell->has_keep_attr()) {
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if (other_cell->has_keep_attr())
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continue;
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known_cells.erase(other_cell);
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known_cells.insert(cell);
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std::swap(other_cell, cell);
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}
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did_something = true;
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log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), other_cell->name.c_str());
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for (auto &it : cell->connections()) {
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if (cell->output(it.first)) {
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RTLIL::SigSpec other_sig = other_cell->getPort(it.first);
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log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
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log_signal(it.second), log_signal(other_sig));
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Const init = initvals(other_sig);
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initvals.remove_init(it.second);
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initvals.remove_init(other_sig);
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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initvals.set_init(other_sig, init);
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}
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}
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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module->remove(cell);
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total_count++;
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}
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}
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}
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log_suppressed();
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}
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};
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struct OptMergePass : public Pass {
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OptMergePass() : Pass("opt_merge", "consolidate identical cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_merge [options] [selection]\n");
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log("\n");
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log("This pass identifies cells with identical type and input signals. Such cells\n");
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log("are then merged to one cell.\n");
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log("\n");
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log(" -nomux\n");
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log(" Do not merge MUX cells.\n");
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log("\n");
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log(" -share_all\n");
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log(" Operate on all cell types, not just built-in types.\n");
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log("\n");
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log(" -keepdc\n");
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log(" Do not merge flipflops with don't-care bits in their initial value.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n");
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bool mode_nomux = false;
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bool mode_share_all = false;
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bool mode_keepdc = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-nomux") {
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mode_nomux = true;
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continue;
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}
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if (arg == "-share_all") {
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mode_share_all = true;
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continue;
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}
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if (arg == "-keepdc") {
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mode_keepdc = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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OptMergeWorker worker(design, module, mode_nomux, mode_share_all, mode_keepdc);
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total_count += worker.total_count;
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("Removed a total of %d cells.\n", total_count);
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}
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} OptMergePass;
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PRIVATE_NAMESPACE_END
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