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78 lines
1.6 KiB
Verilog
78 lines
1.6 KiB
Verilog
module $__ANALOGDEVICES_BLOCKRAM_SDP_ (...);
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parameter INIT = 0;
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parameter OPTION_ENABLE_WIDTH = "BIT";
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parameter WIDTH = 40;
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`ifdef IS_T40LP
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parameter ABITS = 12;
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localparam NODE = "T40LP_Gen2.4";
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localparam BRAM_MODE = WIDTH == 5 ? "SDP_4096x05" :
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WIDTH == 10 ? "SDP_2048x10" : "SDP_1024x40";
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`elsif IS_T16FFC
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parameter ABITS = 13;
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localparam NODE = "T16FFC_Gen2.4";
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localparam BRAM_MODE = WIDTH == 5 ? "SDP_8192x05" :
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WIDTH == 10 ? "SDP_4096x10" : "SDP_2048x40";
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`endif
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parameter PORT_W_WR_EN_WIDTH = 5;
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parameter PORT_W_CLK_POL = 1;
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parameter PORT_R_CLK_POL = 1;
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input PORT_W_CLK;
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input PORT_W_CLK_EN;
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input [ABITS-1:0] PORT_W_ADDR;
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input [WIDTH-1:0] PORT_W_WR_DATA;
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input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
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input PORT_R_CLK;
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input PORT_R_CLK_EN;
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input [ABITS-1:0] PORT_R_ADDR;
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output [WIDTH-1:0] PORT_R_RD_DATA;
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`ifdef IS_T40LP
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RBRAM
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`endif
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`ifdef IS_T16FFC
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RBRAM2
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`endif
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#(
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.TARGET_NODE(NODE),
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.BRAM_MODE(BRAM_MODE),
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.QA_REG(0),
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.QB_REG(0),
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.CLKA_INV(!PORT_W_CLK_POL),
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.CLKB_INV(!PORT_R_CLK_POL),
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.DATA_WIDTH(WIDTH),
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.ADDR_WIDTH(
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WIDTH == 5 ? ABITS :
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WIDTH == 10 ? ABITS-1 : ABITS-2
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),
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.WE_WIDTH(OPTION_ENABLE_WIDTH == "BIT" ? WIDTH : PORT_W_WR_EN_WIDTH),
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.PERR_WIDTH(1),
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)
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_TECHMAP_REPLACE_
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(
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// .QA(0),
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.DA(PORT_W_WR_DATA),
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.CEA(PORT_W_CLK_EN),
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.WEA(PORT_W_WR_EN),
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.AA(
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WIDTH == 5 ? PORT_W_ADDR :
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WIDTH == 10 ? PORT_W_ADDR[ABITS-1:1] : PORT_W_ADDR[ABITS-1:2]
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),
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.CLKA(PORT_W_CLK),
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.QB(PORT_R_RD_DATA),
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// .DB(0),
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.CEB(PORT_R_CLK_EN),
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// .WEB(0),
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.AB(
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WIDTH == 5 ? PORT_R_ADDR :
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WIDTH == 10 ? PORT_R_ADDR[ABITS-1:1] : PORT_R_ADDR[ABITS-1:2]
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),
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.CLKB(PORT_R_CLK),
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);
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endmodule
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