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15 lines
236 B
Plaintext
15 lines
236 B
Plaintext
read_verilog -sv initval.v
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proc;;
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sat -seq 10 -prove-asserts
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design -reset
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read_verilog -icells <<EOT
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module top(input clk, i, output o, p);
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(* init = 1'bx *)
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wire p = o;
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$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
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endmodule
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EOT
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sat -seq 1
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