Emil J. Tywoniak 0c450ce8c8 WIP migration to twine		2026-06-18 19:27:41 +02:00
..
common	synth_quicklogic: rearrange files to prepare for adding more architectures	2023-12-04 15:52:02 +01:00
pp3	synth_quicklogic: rearrange files to prepare for adding more architectures	2023-12-04 15:52:02 +01:00
qlf_k6n10f	Drop timestamp in generate_bram_types_sim.py	2024-10-30 08:47:18 +01:00
.gitignore	add dsp inference	2023-12-04 15:52:02 +01:00
Makefile.inc	add ioff inference for qlf_k6n10f	2025-01-24 21:17:15 +01:00
ql_bram_merge.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
ql_bram_types.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
ql_dsp_io_regs.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
ql_dsp_macc.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
ql_dsp_macc.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00
ql_dsp_simd.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
ql_ioff.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
synth_quicklogic.cc	Add check before flatten in synth_*.	2026-05-05 14:06:58 +02:00