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https://github.com/YosysHQ/yosys
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c89cfe1e6e
Rewrite power-of-two indexed word selects to $bmux when the shift amount already carries the scale as low zero bits. Keep the rule to non-overlapping selections and bound the generated mux ways. Add regressions for aligned shifts, padding, signed extension, and shiftmul handoff cases.
87 lines
2.3 KiB
Text
87 lines
2.3 KiB
Text
pattern shiftpow2
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//
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// Optimize shifts that result from expressions such as foo[s*W+:W]
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// when W is a power of two and the multiply has been folded away.
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//
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match shift
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select shift->type.in($shift, $shiftx, $shr)
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filter !port(shift, \B).empty()
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endmatch
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code
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{
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// make sure the shift amount cannot be negative
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SigSpec amount = port(shift, \B);
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bool b_signed = shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool();
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if (!b_signed)
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amount.append(State::S0);
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if (amount.bits().back() != State::S0)
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reject;
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while (GetSize(amount) > 1 && amount.bits().back() == State::S0)
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amount.remove(GetSize(amount) - 1);
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// low zero bits encode the power-of-two scale
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int log2scale = 0;
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while (!amount.empty() && amount[0] == State::S0) {
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amount.remove(0);
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log2scale++;
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}
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if (log2scale < 1)
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reject;
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if (amount.empty() || amount.is_fully_const())
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reject;
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SigSpec sel = amount;
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int sel_width = GetSize(sel);
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int width = param(shift, \Y_WIDTH).as_int();
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if (log2scale >= 8 * (int)sizeof(int) - 1)
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reject;
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int stride = 1 << log2scale;
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// avoid overlapping selections
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if (width > stride)
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reject;
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if (sel_width > 20)
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reject;
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long long ways = 1LL << sel_width;
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SigSpec A = port(shift, \A);
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int a_width = GetSize(A);
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bool a_signed = !shift->type.in($shiftx) && param(shift, \A_SIGNED).as_bool();
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int extended_a_width = a_signed ? std::max(a_width, width) : a_width;
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// limit padding for out-of-range select values
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int max_ratio = module->design->scratchpad_get_int("peepopt.shiftpow2.max_data_multiple", 2);
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if (ways * (long long)width > (long long)max_ratio * std::max(a_width, width))
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reject;
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did_something = true;
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log("shiftpow2 pattern in %s: shift=%s, index=%s, stride=%d, width=%d, ways=%lld\n",
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module, shift, log_signal(sel), stride, width, ways);
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// way m holds A[m*stride +: width], way 0 in the LSBs
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State fill = shift->type.in($shiftx) ? State::Sx : State::S0;
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SigSpec bmux_a;
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for (long long m = 0; m < ways; m++) {
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long long base = m * (long long)stride;
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for (int b = 0; b < width; b++) {
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long long idx = base + b;
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if (idx < a_width)
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bmux_a.append(A[idx]);
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else if (idx < extended_a_width)
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bmux_a.append(A.back());
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else
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bmux_a.append(fill);
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}
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}
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module->addBmux(NEW_ID, bmux_a, sel, port(shift, \Y));
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autoremove(shift);
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accept;
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}
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endcode
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