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11 lines
742 B
Systemverilog
11 lines
742 B
Systemverilog
module yosys_latch (
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input logic dlatch_p_d, input logic dlatch_p_g, output logic dlatch_p_q,
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input logic dlatch_n_d, input logic dlatch_n_gn, output logic dlatch_n_q,
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input logic dlatch_pn0_d, input logic dlatch_pn0_rn, input logic dlatch_pn0_g, output logic dlatch_pn0_q,
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input logic dlatch_nn0_d, input logic dlatch_nn0_rn, input logic dlatch_nn0_gn, output logic dlatch_nn0_q
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);
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always_latch if (dlatch_p_g) dlatch_p_q <= dlatch_p_d;
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always_latch if (~dlatch_n_gn) dlatch_n_q <= dlatch_n_d;
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always_latch if (~dlatch_pn0_rn) dlatch_pn0_q <= 1'b0; else if (dlatch_pn0_g) dlatch_pn0_q <= dlatch_pn0_d;
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always @* if (dlatch_nn0_rn == 1'b0) dlatch_nn0_q <= 1'b0; else if (dlatch_nn0_gn == 1'b0) dlatch_nn0_q <= dlatch_nn0_d;
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endmodule
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