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2026-03-02 03:36:56 +00:00
Code
Activity
e2345d197b
yosys
/
passes
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Robert O'Callahan
cbb5d8fa12
Pass the module
Subpool
to
rmunused_module_cells
and parallelize that function
2026-02-17 03:24:52 +00:00
..
cmds
Merge pull request
#4303
from Coloquinte/sat_choice
2026-02-11 06:54:53 -08:00
equiv
Merge pull request
#5357
from rocallahan/builtin-ff
2025-09-17 11:37:16 +02:00
fsm
fsm_detect: add adff detection
2025-11-06 23:29:47 +02:00
hierarchy
hierarchy.cc: Tidying
2025-10-15 09:42:47 +13:00
memory
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
opt
Pass the module
Subpool
to
rmunused_module_cells
and parallelize that function
2026-02-17 03:24:52 +00:00
pmgen
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
proc
proc_clean: Removing an empty full_case is doing something
2026-01-07 13:10:32 +13:00
sat
Set solver from scratchpad or command line
2026-02-06 19:26:32 -08:00
techmap
Merge pull request
#5679
from YosysHQ/emil/abc9-remove-liberty
2026-02-11 12:36:29 +01:00
tests
test_cell.cc: Generate .aag for all compatible cells
2025-12-02 14:03:36 +13:00