mirror of
https://github.com/YosysHQ/yosys
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55 lines
1.7 KiB
C++
55 lines
1.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The Verilog frontend.
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*
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* This frontend is using the AST frontend library (see frontends/ast/).
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* Thus this frontend does not generate RTLIL code directly but creates an
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* AST directly from the Verilog parse tree and then passes this AST to
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* the AST frontend library.
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*
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*/
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#ifndef VERILOG_FRONTEND_H
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#define VERILOG_FRONTEND_H
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#include "kernel/yosys.h"
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#include "frontends/ast/ast.h"
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#if ! defined(yyFlexLexerOnce)
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#define yyFlexLexer frontend_verilog_yyFlexLexer
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#include <FlexLexer.h>
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#endif
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#include <stdio.h>
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#include <stdint.h>
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#include <list>
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YOSYS_NAMESPACE_BEGIN
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namespace VERILOG_FRONTEND
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{
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// this function converts a Verilog constant to an AST_CONSTANT node
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std::unique_ptr<AST::AstNode> const2ast(std::string code, char case_type = 0, bool warn_z = false);
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extern void frontend_verilog_yyerror(char const *fmt, ...);
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};
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YOSYS_NAMESPACE_END
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#endif
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