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messy

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This commit is contained in:
Emil J. Tywoniak 2025-05-23 20:15:49 +02:00
parent 1acbb5b89b
commit d9943b3727
12 changed files with 1132 additions and 1108 deletions
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4
backends/rtlil/rtlil_backend.cc
View file

@ -410,13 +410,17 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
f << stringf("autoidx %d\n", autoidx);
}
log("dumping %zu modules\n", design->modules().size());
log("selected is .%s. %d\n", design->selected_active_module.c_str(), only_selected);
for (auto module : design->modules()) {
log("dumping module %s %d\n", module->name.c_str(), design->selected(module));
if (!only_selected || design->selected(module)) {
if (only_selected)
f << stringf("\n");
dump_module(f, "", module, design, only_selected, flag_m, flag_n);
}
}
log("dumped modules\n");
log_assert(init_autoidx == autoidx);
}

7
frontends/ast/ast.cc
View file

@ -39,6 +39,7 @@ using namespace AST_INTERNAL;
// instantiate global variables (public API)
namespace AST {
std::string current_filename;
bool sv_mode;
unsigned long long astnodes = 0;
unsigned long long astnode_count() { return astnodes; }
}
@ -1402,6 +1403,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
log_assert(current_ast->type == AST_DESIGN);
for (const auto& child : current_ast->children)
{
child->dumpAst(stdout, "child: ");
if (child->type == AST_MODULE || child->type == AST_INTERFACE)
{
for (auto& n : design->verilog_globals)
@ -1459,6 +1461,10 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
process_module(design, child.get(), defer_local);
current_ast_mod = nullptr;
log("built this:\n");
log_module(design->module(child->str));
log("here:\n");
Pass::call(design, "dump");
}
else if (child->type == AST_PACKAGE) {
// process enum/other declarations
@ -1480,6 +1486,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
current_scope.clear();
}
}
}
// An interface port with modport is specified like this:

2
frontends/ast/ast.h
View file

@ -408,6 +408,8 @@ namespace AST
// the AstNode constructor then uses current_filename and get_line_num()
// to initialize the filename and linenum properties of new nodes
extern std::string current_filename;
// also set by the language frontend to control some AST processing
extern bool sv_mode;
// for stats
unsigned long long astnode_count();

2
frontends/ast/simplify.cc
View file

@ -2543,7 +2543,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
for (size_t i = 0; i < children.size(); i++)
if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF)
{
log_assert(!VERILOG_FRONTEND::sv_mode);
log_assert(!sv_mode);
children[i]->input_error("Local declaration in unnamed block is only supported in SystemVerilog mode!\n");
}
}

9
frontends/verilog/preproc.cc
View file

@ -34,6 +34,7 @@
#include "preproc.h"
#include "verilog_frontend.h"
#include "verilog_parser.tab.hh"
#include "kernel/log.h"
#include <assert.h>
#include <stack>
@ -749,7 +750,9 @@ frontend_verilog_preproc(std::istream &f,
std::string filename,
const define_map_t &pre_defines,
define_map_t &global_defines_cache,
const std::list<std::string> &include_dirs)
const std::list<std::string> &include_dirs,
ParseState &parse_state,
ParseMode &parse_mode)
{
define_map_t defines;
defines.merge(pre_defines);
@ -961,11 +964,11 @@ frontend_verilog_preproc(std::istream &f,
}
if (tok == "`resetall") {
default_nettype_wire = true;
parse_state.default_nettype_wire = true;
continue;
}
if (tok == "`undefineall" && sv_mode) {
if (tok == "`undefineall" && parse_mode.sv) {
defines.clear();
global_defines_cache.clear();
continue;

9
frontends/verilog/preproc.h
View file

@ -35,6 +35,11 @@ YOSYS_NAMESPACE_BEGIN
struct define_body_t;
struct arg_map_t;
namespace VERILOG_FRONTEND {
struct ParseState;
struct ParseMode;
};
struct define_map_t
{
define_map_t();
@ -71,7 +76,9 @@ frontend_verilog_preproc(std::istream &f,
std::string filename,
const define_map_t &pre_defines,
define_map_t &global_defines_cache,
const std::list<std::string> &include_dirs);
const std::list<std::string> &include_dirs,
VERILOG_FRONTEND::ParseState &parse_state,
VERILOG_FRONTEND::ParseMode &parse_mode);
YOSYS_NAMESPACE_END

97
frontends/verilog/verilog_frontend.cc
View file

@ -31,6 +31,7 @@
#endif
#include "verilog_frontend.h"
#include "verilog_lexer.h"
#include "preproc.h"
#include "kernel/yosys.h"
#include "libs/sha1/sha1.h"
@ -68,9 +69,15 @@ static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std
}
struct VerilogFrontend : public Frontend {
ParseMode parse_mode;
ParseState parse_state;
VerilogLexer lexer;
frontend_verilog_yy::parser parser;
VerilogFrontend() : Frontend("verilog", "read modules from Verilog file"), lexer(), parser(&lexer) { }
VerilogFrontend() : Frontend("verilog", "read modules from Verilog file"),
parse_mode(),
parse_state(),
lexer(&parse_state, &parse_mode),
parser(&lexer, &parse_state, &parse_mode) { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@ -276,16 +283,16 @@ struct VerilogFrontend : public Frontend {
lexer.set_debug(false);
parser.set_debug_level(0);
sv_mode = false;
formal_mode = false;
noassert_mode = false;
noassume_mode = false;
norestrict_mode = false;
assume_asserts_mode = false;
assert_assumes_mode = false;
lib_mode = false;
specify_mode = false;
default_nettype_wire = true;
parse_mode.sv = false;
parse_mode.formal = false;
parse_mode.noassert = false;
parse_mode.noassume = false;
parse_mode.norestrict = false;
parse_mode.assume_asserts = false;
parse_mode.assert_assumes = false;
parse_mode.lib = false;
parse_mode.specify = false;
parse_state.default_nettype_wire = true;
args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
@ -293,11 +300,11 @@ struct VerilogFrontend : public Frontend {
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if (arg == "-sv") {
sv_mode = true;
parse_mode.sv = true;
continue;
}
if (arg == "-formal") {
formal_mode = true;
parse_mode.formal = true;
continue;
}
if (arg == "-nosynthesis") {
@ -305,23 +312,23 @@ struct VerilogFrontend : public Frontend {
continue;
}
if (arg == "-noassert") {
noassert_mode = true;
parse_mode.noassert = true;
continue;
}
if (arg == "-noassume") {
noassume_mode = true;
parse_mode.noassume = true;
continue;
}
if (arg == "-norestrict") {
norestrict_mode = true;
parse_mode.norestrict = true;
continue;
}
if (arg == "-assume-asserts") {
assume_asserts_mode = true;
parse_mode.assume_asserts = true;
continue;
}
if (arg == "-assert-assumes") {
assert_assumes_mode = true;
parse_mode.assert_assumes = true;
continue;
}
if (arg == "-nodisplay") {
@ -398,7 +405,7 @@ struct VerilogFrontend : public Frontend {
continue;
}
if (arg == "-lib") {
lib_mode = true;
parse_mode.lib = true;
defines_map.add("BLACKBOX", "");
continue;
}
@ -407,7 +414,7 @@ struct VerilogFrontend : public Frontend {
continue;
}
if (arg == "-specify") {
specify_mode = true;
parse_mode.specify = true;
continue;
}
if (arg == "-noopt") {
@ -437,7 +444,7 @@ struct VerilogFrontend : public Frontend {
continue;
}
if (arg == "-noautowire") {
default_nettype_wire = false;
parse_state.default_nettype_wire = false;
continue;
}
if (arg == "-setattr" && argidx+1 < args.size()) {
@ -474,32 +481,33 @@ struct VerilogFrontend : public Frontend {
break;
}
if (formal_mode || !flag_nosynthesis)
defines_map.add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
if (parse_mode.formal || !flag_nosynthesis)
defines_map.add(parse_mode.formal ? "FORMAL" : "SYNTHESIS", "1");
extra_args(f, filename, args, argidx);
log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());
log("Parsing %s%s input from `%s' to AST representation.\n",
formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str());
parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str());
AST::current_filename = filename;
AST::sv_mode = parse_mode.sv;
current_ast = new AST::AstNode(AST::AST_DESIGN);
parse_state.current_ast = new AST::AstNode(AST::AST_DESIGN);
lexin = f;
parse_state.lexin = f;
std::string code_after_preproc;
if (!flag_nopp) {
code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs);
code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode);
if (flag_ppdump)
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
lexin = new std::istringstream(code_after_preproc);
parse_state.lexin = new std::istringstream(code_after_preproc);
}
// make package typedefs available to parser
add_package_types(pkg_user_types, design->verilog_packages);
add_package_types(parse_state.pkg_user_types, design->verilog_packages);
UserTypeMap global_types_map;
for (auto& def : design->verilog_globals) {
@ -508,16 +516,16 @@ struct VerilogFrontend : public Frontend {
}
}
log_assert(user_type_stack.empty());
log_assert(parse_state.user_type_stack.empty());
// use previous global typedefs as bottom level of user type stack
user_type_stack.push_back(std::move(global_types_map));
parse_state.user_type_stack.push_back(std::move(global_types_map));
// add a new empty type map to allow overriding existing global definitions
user_type_stack.push_back(UserTypeMap());
parse_state.user_type_stack.push_back(UserTypeMap());
parser.~parser();
lexer.~VerilogLexer();
new (&lexer) VerilogLexer();
new (&parser) frontend_verilog_yy::parser(&lexer);
new (&lexer) VerilogLexer(&parse_state, &parse_mode);
new (&parser) frontend_verilog_yy::parser(&lexer, &parse_state, &parse_mode);
if (flag_yydebug) {
lexer.set_debug(true);
parser.set_debug_level(1);
@ -525,7 +533,7 @@ struct VerilogFrontend : public Frontend {
parser.parse();
// frontend_verilog_yyset_lineno(1);
for (auto &child : current_ast->children) {
for (auto &child : parse_state.current_ast->children) {
if (child->type == AST::AST_MODULE)
for (auto &attr : attributes)
if (child->attributes.count(attr) == 0)
@ -533,21 +541,24 @@ struct VerilogFrontend : public Frontend {
}
if (flag_nodpi)
error_on_dpi_function(current_ast);
error_on_dpi_function(parse_state.current_ast);
AST::process(design, current_ast, flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
AST::process(design, parse_state.current_ast, flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, parse_mode.lib, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, parse_state.default_nettype_wire);
log("Got this:\n");
Pass::call(design, "dump");
if (!flag_nopp)
delete lexin;
delete parse_state.lexin;
// only the previous and new global type maps remain
log_assert(user_type_stack.size() == 2);
user_type_stack.clear();
log_assert(parse_state.user_type_stack.size() == 2);
parse_state.user_type_stack.clear();
delete current_ast;
current_ast = NULL;
delete parse_state.current_ast;
parse_state.current_ast = NULL;
log("Successfully finished Verilog frontend.\n");
}

72
frontends/verilog/verilog_frontend.h
View file

@ -36,12 +36,6 @@
#define yyFlexLexer frontend_verilog_yyFlexLexer
#include <FlexLexer.h>
#endif
YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND {
class VerilogLexer;
};
YOSYS_NAMESPACE_END
#include "frontends/verilog/verilog_parser.tab.hh"
#include <stdio.h>
#include <stdint.h>
@ -51,75 +45,9 @@ YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND
{
// this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
extern struct AST::AstNode *current_ast;
// this function converts a Verilog constant to an AST_CONSTANT node
std::unique_ptr<AST::AstNode> const2ast(std::string code, char case_type = 0, bool warn_z = false);
// names of locally typedef'ed types in a stack
typedef std::map<std::string, AST::AstNode*> UserTypeMap;
extern std::vector<UserTypeMap> user_type_stack;
// names of package typedef'ed types
extern dict<std::string, AST::AstNode*> pkg_user_types;
// state of `default_nettype
extern bool default_nettype_wire;
// running in SystemVerilog mode
extern bool sv_mode;
// running in -formal mode
extern bool formal_mode;
// running in -noassert mode
extern bool noassert_mode;
// running in -noassume mode
extern bool noassume_mode;
// running in -norestrict mode
extern bool norestrict_mode;
// running in -assume-asserts mode
extern bool assume_asserts_mode;
// running in -assert-assumes mode
extern bool assert_assumes_mode;
// running in -lib mode
extern bool lib_mode;
// running in -specify mode
extern bool specify_mode;
// lexer input stream
extern std::istream *lexin;
using parser = frontend_verilog_yy::parser;
class VerilogLexer : public frontend_verilog_yyFlexLexer {
public:
VerilogLexer(std::istream* in = nullptr) : frontend_verilog_yyFlexLexer(in) {}
~VerilogLexer() override {}
// autogenerated body due to YY_DECL
parser::symbol_type nextToken();
// get rid of override virtual function warning
using FlexLexer::yylex;
parser::symbol_type terminate() {
return parser::make_FRONTEND_VERILOG_YYEOF(out_loc);
}
parser::location_type out_loc;
private:
std::vector<std::string> fn_stack;
std::vector<int> ln_stack;
parser::location_type real_loc;
parser::location_type old_loc;
};
extern void frontend_verilog_yyerror(char const *fmt, ...);
// parser::symbol_type frontend_verilog_yylex(VerilogLexer& lexer) {
// return lexer.nextToken();
// };
};
YOSYS_NAMESPACE_END

54
frontends/verilog/verilog_lexer.l
View file

@ -40,8 +40,6 @@
%option prefix="frontend_verilog_yy"
%{
//%option bison-locations
//%option bison-bridge
#ifdef __clang__
// bison generates code using the 'register' storage class specifier
@ -50,7 +48,7 @@
#pragma clang diagnostic ignored "-Wmisleading-indentation"
#endif
#include "frontends/verilog/verilog_frontend.h"
#include "frontends/verilog/verilog_lexer.h"
#include "frontends/ast/ast.h"
#include "kernel/log.h"
#include <vector>
@ -72,7 +70,7 @@ YOSYS_NAMESPACE_BEGIN
YOSYS_NAMESPACE_END
#define SV_KEYWORD(_tok) \
if (sv_mode) return _tok; \
if (mode->sv) return _tok; \
log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
"recognized unless read_verilog is called with -sv!\n", YYText(), \
AST::current_filename.c_str(), yylineno); \
@ -83,8 +81,8 @@ YOSYS_NAMESPACE_END
string_t val = new std::string(std::string("\\") + YYText()); \
return parser::make_TOK_ID(val, out_loc);
#define YY_INPUT(buf,result,max_size) \
result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
// #define YY_INPUT(buf,result,max_size) \
// result = readsome(*extra->lexin, buf, max_size)
#define YY_USER_ACTION \
old_loc = real_loc; \
@ -106,10 +104,10 @@ YOSYS_NAMESPACE_END
#undef YY_BUF_SIZE
#define YY_BUF_SIZE 65536
static bool isUserType(std::string &s)
static bool isUserType(ParseState* extra, std::string &s)
{
// check current scope then outer scopes for a name
for (auto it = user_type_stack.rbegin(); it != user_type_stack.rend(); ++it) {
for (auto it = extra->user_type_stack.rbegin(); it != extra->user_type_stack.rend(); ++it) {
if (it->count(s) > 0) {
return true;
}
@ -225,9 +223,9 @@ TIME_SCALE_SUFFIX [munpf]?s
while (*p != 0 && *p != ' ' && *p != '\t') p++;
while (*p == ' ' || *p == '\t') p++;
if (!strcmp(p, "none"))
VERILOG_FRONTEND::default_nettype_wire = false;
extra->default_nettype_wire = false;
else if (!strcmp(p, "wire"))
VERILOG_FRONTEND::default_nettype_wire = true;
extra->default_nettype_wire = true;
else
frontend_verilog_yyerror("Unsupported default nettype: %s", p);
}
@ -245,7 +243,7 @@ TIME_SCALE_SUFFIX [munpf]?s
"endfunction" { return parser::make_TOK_ENDFUNCTION(out_loc); }
"task" { return parser::make_TOK_TASK(out_loc); }
"endtask" { return parser::make_TOK_ENDTASK(out_loc); }
"specify" { return specify_mode ? parser::make_TOK_SPECIFY(out_loc) : parser::make_TOK_IGNORED_SPECIFY(out_loc); }
"specify" { return mode->sv ? parser::make_TOK_SPECIFY(out_loc) : parser::make_TOK_IGNORED_SPECIFY(out_loc); }
"endspecify" { return parser::make_TOK_ENDSPECIFY(out_loc); }
"specparam" { return parser::make_TOK_SPECPARAM(out_loc); }
"package" { SV_KEYWORD(parser::make_TOK_PACKAGE(out_loc)); }
@ -296,16 +294,16 @@ TIME_SCALE_SUFFIX [munpf]?s
return parser::make_TOK_SVA_LABEL(val, out_loc);
}
"assert" { if (formal_mode) return parser::make_TOK_ASSERT(out_loc); SV_KEYWORD(parser::make_TOK_ASSERT(out_loc)); }
"assume" { if (formal_mode) return parser::make_TOK_ASSUME(out_loc); SV_KEYWORD(parser::make_TOK_ASSUME(out_loc)); }
"cover" { if (formal_mode) return parser::make_TOK_COVER(out_loc); SV_KEYWORD(parser::make_TOK_COVER(out_loc)); }
"restrict" { if (formal_mode) return parser::make_TOK_RESTRICT(out_loc); SV_KEYWORD(parser::make_TOK_RESTRICT(out_loc)); }
"property" { if (formal_mode) return parser::make_TOK_PROPERTY(out_loc); SV_KEYWORD(parser::make_TOK_PROPERTY(out_loc)); }
"rand" { if (formal_mode) return parser::make_TOK_RAND(out_loc); SV_KEYWORD(parser::make_TOK_RAND(out_loc)); }
"const" { if (formal_mode) return parser::make_TOK_CONST(out_loc); SV_KEYWORD(parser::make_TOK_CONST(out_loc)); }
"checker" { if (formal_mode) return parser::make_TOK_CHECKER(out_loc); SV_KEYWORD(parser::make_TOK_CHECKER(out_loc)); }
"endchecker" { if (formal_mode) return parser::make_TOK_ENDCHECKER(out_loc); SV_KEYWORD(parser::make_TOK_ENDCHECKER(out_loc)); }
"bind" { if (formal_mode) return parser::make_TOK_BIND(out_loc); SV_KEYWORD(parser::make_TOK_BIND(out_loc)); }
"assert" { if (mode->formal) return parser::make_TOK_ASSERT(out_loc); SV_KEYWORD(parser::make_TOK_ASSERT(out_loc)); }
"assume" { if (mode->formal) return parser::make_TOK_ASSUME(out_loc); SV_KEYWORD(parser::make_TOK_ASSUME(out_loc)); }
"cover" { if (mode->formal) return parser::make_TOK_COVER(out_loc); SV_KEYWORD(parser::make_TOK_COVER(out_loc)); }
"restrict" { if (mode->formal) return parser::make_TOK_RESTRICT(out_loc); SV_KEYWORD(parser::make_TOK_RESTRICT(out_loc)); }
"property" { if (mode->formal) return parser::make_TOK_PROPERTY(out_loc); SV_KEYWORD(parser::make_TOK_PROPERTY(out_loc)); }
"rand" { if (mode->formal) return parser::make_TOK_RAND(out_loc); SV_KEYWORD(parser::make_TOK_RAND(out_loc)); }
"const" { if (mode->formal) return parser::make_TOK_CONST(out_loc); SV_KEYWORD(parser::make_TOK_CONST(out_loc)); }
"checker" { if (mode->formal) return parser::make_TOK_CHECKER(out_loc); SV_KEYWORD(parser::make_TOK_CHECKER(out_loc)); }
"endchecker" { if (mode->formal) return parser::make_TOK_ENDCHECKER(out_loc); SV_KEYWORD(parser::make_TOK_ENDCHECKER(out_loc)); }
"bind" { if (mode->formal) return parser::make_TOK_BIND(out_loc); SV_KEYWORD(parser::make_TOK_BIND(out_loc)); }
"final" { SV_KEYWORD(parser::make_TOK_FINAL(out_loc)); }
"logic" { SV_KEYWORD(parser::make_TOK_LOGIC(out_loc)); }
"var" { SV_KEYWORD(parser::make_TOK_VAR(out_loc)); }
@ -316,8 +314,8 @@ TIME_SCALE_SUFFIX [munpf]?s
"longint" { SV_KEYWORD(parser::make_TOK_LONGINT(out_loc)); }
"void" { SV_KEYWORD(parser::make_TOK_VOID(out_loc)); }
"eventually" { if (formal_mode) return parser::make_TOK_EVENTUALLY(out_loc); SV_KEYWORD(parser::make_TOK_EVENTUALLY(out_loc)); }
"s_eventually" { if (formal_mode) return parser::make_TOK_EVENTUALLY(out_loc); SV_KEYWORD(parser::make_TOK_EVENTUALLY(out_loc)); }
"eventually" { if (mode->formal) return parser::make_TOK_EVENTUALLY(out_loc); SV_KEYWORD(parser::make_TOK_EVENTUALLY(out_loc)); }
"s_eventually" { if (mode->formal) return parser::make_TOK_EVENTUALLY(out_loc); SV_KEYWORD(parser::make_TOK_EVENTUALLY(out_loc)); }
"input" { return parser::make_TOK_INPUT(out_loc); }
"output" { return parser::make_TOK_OUTPUT(out_loc); }
@ -430,7 +428,7 @@ supply1 { return parser::make_TOK_SUPPLY1(out_loc); }
}
"$"(setup|hold|setuphold|removal|recovery|recrem|skew|timeskew|fullskew|nochange) {
if (!specify_mode) REJECT;
if (!mode->sv) REJECT;
auto val = new std::string(YYText());
return parser::make_TOK_ID(val, out_loc);
}
@ -446,7 +444,7 @@ supply1 { return parser::make_TOK_SUPPLY1(out_loc); }
[a-zA-Z_][a-zA-Z0-9_]*::[a-zA-Z_$][a-zA-Z0-9_$]* {
// package qualifier
auto s = std::string("\\") + YYText();
if (pkg_user_types.count(s) > 0) {
if (extra->pkg_user_types.count(s) > 0) {
// package qualified typedefed name
auto val = new std::string(s);
return parser::make_TOK_PKG_USER_TYPE(val, out_loc);
@ -462,7 +460,7 @@ supply1 { return parser::make_TOK_SUPPLY1(out_loc); }
[a-zA-Z_$][a-zA-Z0-9_$]* {
auto s = std::string("\\") + YYText();
if (isUserType(s)) {
if (isUserType(extra, s)) {
// previously typedefed name
auto val = new std::string(s);
return parser::make_TOK_USER_TYPE(val, out_loc);
@ -608,13 +606,13 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
">>>=" { SV_KEYWORD(parser::make_TOK_SSHR_ASSIGN(out_loc)); }
[-+]?[=*]> {
if (!specify_mode) REJECT;
if (!mode->sv) REJECT;
auto val = new std::string(YYText());
return parser::make_TOK_SPECIFY_OPER(val, out_loc);
}
"&&&" {
if (!specify_mode) return parser::make_TOK_IGNORED_SPECIFY_AND(out_loc);
if (!mode->sv) return parser::make_TOK_IGNORED_SPECIFY_AND(out_loc);
return parser::make_TOK_SPECIFY_AND(out_loc);
}

1971
frontends/verilog/verilog_parser.y
View file

File diff suppressed because it is too large Load diff

5
kernel/rtlil.cc
View file

@ -821,14 +821,19 @@ bool RTLIL::Selection::selected_module(const RTLIL::IdString &mod_name) const
bool RTLIL::Selection::selected_whole_module(const RTLIL::IdString &mod_name) const
{
log("one\n");
if (complete_selection)
return true;
log("two\n");
if (!selects_boxes && boxed_module(mod_name))
return false;
log("three\n");
if (full_selection)
return true;
log("four\n");
if (selected_modules.count(mod_name) > 0)
return true;
log("five\n");
return false;
}

8
tests/arch/microchip/reduce.ys
View file

@ -22,7 +22,9 @@ module reduce(
assign Y = ^data;
endmodule
EOT
synth_microchip -top reduce -family polarfire -noiopad
select -assert-count 1 t:XOR8
select -assert-none t:XOR8 %% t:* %D
read_verilog -lib -specify +/microchip/cells_sim.v
dump
# synth_microchip -top reduce -family polarfire -noiopad
# select -assert-count 1 t:XOR8
# select -assert-none t:XOR8 %% t:* %D