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yosys/techlibs/lattice
2026-07-24 12:20:35 +02:00
..
tests
arith_map_ccu2c.v
arith_map_ccu2d.v
arith_map_nexus.v
brams_8kc.txt
brams_16kd.txt
brams_map_8kc.v
brams_map_16kd.v
brams_map_nexus.v
brams_nexus.txt
ccu2c_sim.vh
ccu2d_sim.vh
cells_bb_ecp5.v End of file fix 2026-06-23 07:23:41 +02:00
cells_bb_nexus.v End of file fix 2026-06-23 07:23:41 +02:00
cells_bb_xo2.v End of file fix 2026-06-23 07:23:41 +02:00
cells_bb_xo3.v End of file fix 2026-06-23 07:23:41 +02:00
cells_bb_xo3d.v End of file fix 2026-06-23 07:23:41 +02:00
cells_ff.vh
cells_io.vh
cells_map_nexus.v
cells_map_trellis.v
cells_sim_ecp5.v
cells_sim_nexus.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
cells_sim_xo2.v
cells_sim_xo3.v
cells_sim_xo3d.v
cells_xtra.py
cells_xtra_nexus.py
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00
common_sim.vh
dsp_map_18x18.v
dsp_map_nexus.v Use Nexus DSP pipelined registers. 2026-07-24 12:10:07 +02:00
latches_map.v
lattice_dsp_nexus.cc Use Nexus DSP pipelined registers. 2026-07-24 12:10:07 +02:00
lattice_dsp_nexus.pmg Merge branch 'main' into nella/fuse-2 2026-07-24 12:20:35 +02:00
lattice_gsr.cc Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
lrams_map_nexus.v
lrams_nexus.txt
lutrams_map_nexus.v nexus: Fix Radiant netlist compatibility 2026-07-19 12:44:40 +02:00
lutrams_map_trellis.v
lutrams_nexus.txt
lutrams_trellis.txt
parse_init.vh
synth_lattice.cc Simplify check -latchonly calls in synth. 2026-07-07 10:10:00 +02:00