| .. | 
		
		
			
			
			
			
				| .gitignore | Update .gitignore | 2020-10-01 15:53:14 +01:00 | 
		
			
			
			
			
				| absurd_width.ys | verilog: impose limit on maximum expression width | 2021-03-04 15:20:52 -05:00 | 
		
			
			
			
			
				| absurd_width_const.ys | verilog: impose limit on maximum expression width | 2021-03-04 15:20:52 -05:00 | 
		
			
			
			
			
				| atom_type_signedness.ys | Add missing is_signed to type_atom | 2021-02-11 15:05:38 +01:00 | 
		
			
			
			
			
				| block_labels.ys | Add check of begin/end labels for genblock | 2021-02-04 17:16:30 +01:00 | 
		
			
			
			
			
				| bug656.v | verilog: significant block scoping improvements | 2021-01-31 09:42:09 -05:00 | 
		
			
			
			
			
				| bug656.ys | verilog: significant block scoping improvements | 2021-01-31 09:42:09 -05:00 | 
		
			
			
			
			
				| bug2037.ys | test: add attribute-before-stmt test from @nakengelhardt | 2020-05-25 07:36:53 -07:00 | 
		
			
			
			
			
				| bug2042-sv.ys | tests: fix some test warnings | 2020-05-25 10:07:58 -07:00 | 
		
			
			
			
			
				| bug2042.ys | tests: update/extend task argument tests | 2020-05-13 10:11:45 -07:00 | 
		
			
			
			
			
				| bug2493.ys | verilog: significant block scoping improvements | 2021-01-31 09:42:09 -05:00 | 
		
			
			
			
			
				| conflict_assert.ys | genrtlil: improve name conflict error messaging | 2021-02-26 18:08:23 -05:00 | 
		
			
			
			
			
				| conflict_cell_memory.ys | genrtlil: improve name conflict error messaging | 2021-02-26 18:08:23 -05:00 | 
		
			
			
			
			
				| conflict_interface_port.ys | genrtlil: improve name conflict error messaging | 2021-02-26 18:08:23 -05:00 | 
		
			
			
			
			
				| conflict_memory_wire.ys | genrtlil: improve name conflict error messaging | 2021-02-26 18:08:23 -05:00 | 
		
			
			
			
			
				| conflict_pwire.ys | genrtlil: improve name conflict error messaging | 2021-02-26 18:08:23 -05:00 | 
		
			
			
			
			
				| conflict_wire_memory.ys | genrtlil: improve name conflict error messaging | 2021-02-26 18:08:23 -05:00 | 
		
			
			
			
			
				| const_arst.ys | add tests | 2020-09-28 18:16:08 +02:00 | 
		
			
			
			
			
				| const_sr.ys | add tests | 2020-09-28 18:16:08 +02:00 | 
		
			
			
			
			
				| delay_mintypmax.ys | Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566) | 2021-02-24 15:48:15 -05:00 | 
		
			
			
			
			
				| delay_risefall.ys | Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566) | 2021-02-24 15:48:15 -05:00 | 
		
			
			
			
			
				| func_arg_mismatch_1.ys | verilog: fix sizing of constant args for tasks/functions | 2021-02-21 15:44:43 -05:00 | 
		
			
			
			
			
				| func_arg_mismatch_2.ys | verilog: fix sizing of constant args for tasks/functions | 2021-02-21 15:44:43 -05:00 | 
		
			
			
			
			
				| func_arg_mismatch_3.ys | verilog: fix sizing of constant args for tasks/functions | 2021-02-21 15:44:43 -05:00 | 
		
			
			
			
			
				| func_arg_mismatch_4.ys | verilog: fix sizing of constant args for tasks/functions | 2021-02-21 15:44:43 -05:00 | 
		
			
			
			
			
				| func_typename_ret.sv | sv: allow typenames as function return types | 2021-03-19 12:08:43 -04:00 | 
		
			
			
			
			
				| func_typename_ret.ys | sv: allow typenames as function return types | 2021-03-19 12:08:43 -04:00 | 
		
			
			
			
			
				| genblk_case.v | verilog: significant block scoping improvements | 2021-01-31 09:42:09 -05:00 | 
		
			
			
			
			
				| genblk_case.ys | verilog: significant block scoping improvements | 2021-01-31 09:42:09 -05:00 | 
		
			
			
			
			
				| genblk_port_decl.ys | verlog: allow shadowing module ports within generate blocks | 2021-02-07 11:48:39 -05:00 | 
		
			
			
			
			
				| global_parameter.ys | verilog: disallow overriding global parameters | 2021-03-11 12:36:51 -05:00 | 
		
			
			
			
			
				| hidden_decl.ys | verilog: significant block scoping improvements | 2021-01-31 09:42:09 -05:00 | 
		
			
			
			
			
				| include_self.v | verilog: fix handling of nested ifdef directives | 2021-03-01 12:28:33 -05:00 | 
		
			
			
			
			
				| include_self.ys | verilog: fix handling of nested ifdef directives | 2021-03-01 12:28:33 -05:00 | 
		
			
			
			
			
				| int_types.sv | sv: extended support for integer types | 2021-02-28 16:31:56 -05:00 | 
		
			
			
			
			
				| int_types.ys | sv: extended support for integer types | 2021-02-28 16:31:56 -05:00 | 
		
			
			
			
			
				| localparam_no_default_1.ys | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| localparam_no_default_2.ys | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| macro_unapplied.ys | verilog: error on macro invocations with missing argument lists | 2021-02-19 09:18:41 -05:00 | 
		
			
			
			
			
				| macro_unapplied_newline.ys | verilog: error on macro invocations with missing argument lists | 2021-02-19 09:18:41 -05:00 | 
		
			
			
			
			
				| param_int_types.sv | sv: extended support for integer types | 2021-02-28 16:31:56 -05:00 | 
		
			
			
			
			
				| param_int_types.ys | sv: extended support for integer types | 2021-02-28 16:31:56 -05:00 | 
		
			
			
			
			
				| param_no_default.sv | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| param_no_default.ys | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| param_no_default_not_svmode.ys | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| param_no_default_unbound_1.ys | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| param_no_default_unbound_2.ys | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| param_no_default_unbound_3.ys | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| param_no_default_unbound_4.ys | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| param_no_default_unbound_5.ys | sv: support for parameters without default values | 2021-03-02 10:43:53 -05:00 | 
		
			
			
			
			
				| parameters_across_files.ys | sv: allow globals in one file to depend on globals in another | 2021-03-12 11:22:41 -05:00 | 
		
			
			
			
			
				| port_int_types.sv | verilog: fix sizing of ports with int types in module headers | 2021-03-01 13:39:05 -05:00 | 
		
			
			
			
			
				| port_int_types.ys | verilog: fix sizing of ports with int types in module headers | 2021-03-01 13:39:05 -05:00 | 
		
			
			
			
			
				| run-test.sh | tests: Centralize test collection and Makefile generation | 2020-09-21 15:07:02 +02:00 | 
		
			
			
			
			
				| task_attr.ys | tests: attributes before task enable | 2020-05-14 16:09:41 -07:00 | 
		
			
			
			
			
				| typedef_across_files.ys | sv: carry over global typedefs from previous files | 2021-03-17 15:53:52 -04:00 | 
		
			
			
			
			
				| typedef_legacy_conflict.ys | sv: carry over global typedefs from previous files | 2021-03-17 15:53:52 -04:00 | 
		
			
			
			
			
				| unbased_unsized.sv | sv: fix some edge cases for unbased unsized literals | 2021-03-06 15:20:34 -05:00 | 
		
			
			
			
			
				| unbased_unsized.ys | sv: fix some edge cases for unbased unsized literals | 2021-03-06 15:20:34 -05:00 | 
		
			
			
			
			
				| unmatched_else.ys | verilog: fix handling of nested ifdef directives | 2021-03-01 12:28:33 -05:00 | 
		
			
			
			
			
				| unmatched_elsif.ys | verilog: fix handling of nested ifdef directives | 2021-03-01 12:28:33 -05:00 | 
		
			
			
			
			
				| unmatched_endif.ys | verilog: fix handling of nested ifdef directives | 2021-03-01 12:28:33 -05:00 | 
		
			
			
			
			
				| unnamed_block.ys | verilog: significant block scoping improvements | 2021-01-31 09:42:09 -05:00 | 
		
			
			
			
			
				| unnamed_genblk.sv | verilog: significant block scoping improvements | 2021-01-31 09:42:09 -05:00 | 
		
			
			
			
			
				| unnamed_genblk.ys | verilog: significant block scoping improvements | 2021-01-31 09:42:09 -05:00 | 
		
			
			
			
			
				| upto.ys | techlibs/common: more robustness when *_WIDTH = 0 | 2020-05-05 08:01:27 -07:00 | 
		
			
			
			
			
				| wire_and_var.sv | sv: fix support wire and var data type modifiers | 2021-01-20 09:16:21 -07:00 | 
		
			
			
			
			
				| wire_and_var.ys | sv: fix support wire and var data type modifiers | 2021-01-20 09:16:21 -07:00 |