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aiger
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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alumacc
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Use generic testing on few more places
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2026-03-16 10:13:10 +01:00 |
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arch
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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asicworld
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Convert autotest script wrapper
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2026-03-16 13:07:11 +01:00 |
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bind
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Use generic testing on few more places
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2026-03-16 10:13:10 +01:00 |
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blif
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Make test simple
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2026-03-20 16:16:58 +01:00 |
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bram
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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bugpoint
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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cxxrtl
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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errors
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
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2018-10-25 02:37:56 +03:00 |
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fmt
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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fsm
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Did share, opt_share and fsm
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2026-03-20 12:47:15 +01:00 |
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functional
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Cleanup
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2026-03-25 09:49:44 +01:00 |
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hana
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Convert autotest script wrapper
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2026-03-16 13:07:11 +01:00 |
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liberty
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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lut
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Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
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2025-07-22 10:38:38 +00:00 |
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memfile
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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memlib
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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memories
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Convert memories tests
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2026-03-18 08:46:58 +01:00 |
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opt
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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opt_share
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Did share, opt_share and fsm
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2026-03-20 12:47:15 +01:00 |
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peepopt
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Converted some more
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2026-03-18 09:54:33 +01:00 |
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proc
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Converted some more
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2026-03-18 09:54:33 +01:00 |
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pyosys
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Remove todo.
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2026-03-04 12:39:45 +01:00 |
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realmath
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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rpc
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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rtlil
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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sat
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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sdc
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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select
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Converted some more
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2026-03-18 09:54:33 +01:00 |
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share
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Did share, opt_share and fsm
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2026-03-20 12:47:15 +01:00 |
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sim
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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simple
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Convert autotest script wrapper
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2026-03-16 13:07:11 +01:00 |
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simple_abc9
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Convert autotest script wrapper
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2026-03-16 13:07:11 +01:00 |
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smv
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Remove references to ilang
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2024-11-05 12:36:31 +13:00 |
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sva
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tests/sva: Skip sva tests that use SBY until SBY is compatible again
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2024-03-05 14:37:33 +01:00 |
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svinterfaces
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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svtypes
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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techmap
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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tools
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Convert memories tests
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2026-03-18 08:46:58 +01:00 |
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unit
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rtlil use newcelltypes.
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2026-03-04 12:39:45 +01:00 |
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various
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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verific
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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verilog
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Convert gen-tests shell script to python
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2026-03-13 08:38:05 +01:00 |
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vloghtb
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tests: use /usr/bin/env for bash.
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2023-08-12 11:59:39 +10:00 |
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xprop
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Did share, opt_share and fsm
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2026-03-20 12:47:15 +01:00 |
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.gitignore
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Save results, and create summary and report
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2026-03-13 09:51:15 +01:00 |
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common.mk
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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gen_tests_makefile.py
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Move output redirect to one place
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2026-03-25 11:46:08 +01:00 |
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Makefile
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Disabled some in fmt for now
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2026-03-24 12:54:40 +01:00 |
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pass-fuzzing.md
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Add AFL++ Grammar-Generator grammar for RTLIL fuzzing, and instructions for how to use it.
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2025-12-22 21:56:26 +00:00 |
