mirror of
https://github.com/YosysHQ/yosys
synced 2026-04-20 19:03:31 +00:00
Disabled some in fmt for now
This commit is contained in:
Miodrag Milanovic
parent
0c35ff67ec
commit
86c9b06d98
3 changed files with 14 additions and 92 deletions
|
|
@ -68,7 +68,7 @@ MK_TEST_DIRS += ./blif
|
|||
MK_TEST_DIRS += ./arch
|
||||
MK_TEST_DIRS += ./rpc
|
||||
MK_TEST_DIRS += ./memfile
|
||||
#MK_TEST_DIRS += ./fmt
|
||||
MK_TEST_DIRS += ./fmt
|
||||
MK_TEST_DIRS += ./cxxrtl
|
||||
MK_TEST_DIRS += ./liberty
|
||||
ifeq ($(ENABLE_FUNCTIONAL_TESTS),1)
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ def cmd(lines):
|
|||
|
||||
def initial_display():
|
||||
gen_tests_makefile.generate_target("initial_display", cmd([
|
||||
"../../yosys -p 'read_verilog initial_display.v' | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $$0}' >yosys-initial_display.log 2>&1",
|
||||
f"$(YOSYS) -p \"read_verilog initial_display.v\" | awk \"/<<<BEGIN>>>/,/<<<END>>>/ {{print $$0}}\" >yosys-initial_display.log 2>&1",
|
||||
"iverilog -o iverilog-initial_display initial_display.v",
|
||||
"./iverilog-initial_display >iverilog-initial_display.log",
|
||||
"diff yosys-initial_display.log iverilog-initial_display.log",
|
||||
|
|
@ -29,8 +29,8 @@ def always_display():
|
|||
|
||||
for name, defs in cases:
|
||||
gen_tests_makefile.generate_target(f"always_display_{name}", cmd([
|
||||
f"../../yosys -p \"read_verilog {defs} always_display.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-1.v >/dev/null 2>&1",
|
||||
f"../../yosys -p \"read_verilog yosys-always_display-{name}-1.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-2.v >/dev/null 2>&1",
|
||||
f"$(YOSYS) -p \"read_verilog {defs} always_display.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-1.v >/dev/null 2>&1",
|
||||
f"$(YOSYS) -p \"read_verilog yosys-always_display-{name}-1.v; proc; opt_expr -mux_bool; clean\" -o yosys-always_display-{name}-2.v >/dev/null 2>&1",
|
||||
f"diff yosys-always_display-{name}-1.v yosys-always_display-{name}-2.v",
|
||||
]))
|
||||
|
||||
|
|
@ -49,8 +49,8 @@ def roundtrip():
|
|||
|
||||
for name, defs in cases:
|
||||
gen_tests_makefile.generate_target(f"roundtrip_{name}", cmd([
|
||||
f"../../yosys -p \"read_verilog {defs} roundtrip.v; proc; clean\" -o yosys-roundtrip-{name}-1.v >/dev/null 2>&1",
|
||||
f"../../yosys -p \"read_verilog yosys-roundtrip-{name}-1.v; proc; clean\" -o yosys-roundtrip-{name}-2.v >/dev/null 2>&1",
|
||||
f"$(YOSYS) -p \"read_verilog {defs} roundtrip.v; proc; clean\" -o yosys-roundtrip-{name}-1.v >/dev/null 2>&1",
|
||||
f"$(YOSYS) -p \"read_verilog yosys-roundtrip-{name}-1.v; proc; clean\" -o yosys-roundtrip-{name}-2.v >/dev/null 2>&1",
|
||||
f"diff yosys-roundtrip-{name}-1.v yosys-roundtrip-{name}-2.v",
|
||||
|
||||
f"iverilog {defs} -o iverilog-roundtrip-{name} roundtrip.v roundtrip_tb.v >/dev/null 2>&1",
|
||||
|
|
@ -72,12 +72,12 @@ def cxxrtl():
|
|||
|
||||
for name in cases:
|
||||
gen_tests_makefile.generate_target(f"cxxrtl_{name}", cmd([
|
||||
f"../../yosys -p \"read_verilog {name}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-{name}.cc\" >/dev/null 2>&1",
|
||||
f"$(YOSYS) -p \"read_verilog {name}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-{name}.cc\" >/dev/null 2>&1",
|
||||
f"$${{CXX:-g++}} -std=c++11 -o yosys-{name} -I../../backends/cxxrtl/runtime {name}_tb.cc -lstdc++",
|
||||
f"./yosys-{name} 2>yosys-{name}.log",
|
||||
|
||||
f"iverilog -o iverilog-{name} {name}.v {name}_tb.v >/dev/null 2>&1",
|
||||
f"./iverilog-{name} | grep -v '\\$finish called' >iverilog-{name}.log",
|
||||
f"./iverilog-{name} | grep -v \"$finish called\" >iverilog-{name}.log",
|
||||
|
||||
f"diff iverilog-{name}.log yosys-{name}.log",
|
||||
]))
|
||||
|
|
@ -85,16 +85,16 @@ def cxxrtl():
|
|||
|
||||
def extra():
|
||||
gen_tests_makefile.generate_target("always_full_equiv", cmd([
|
||||
"../../yosys -p \"read_verilog always_full.v; prep; clean\" -o yosys-always_full-1.v >/dev/null 2>&1",
|
||||
"$(YOSYS) -p \"read_verilog always_full.v; prep; clean\" -o yosys-always_full-1.v >/dev/null 2>&1",
|
||||
"iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v >/dev/null 2>&1",
|
||||
"./iverilog-always_full-1 | grep -v '\\$finish called' >iverilog-always_full-1.log",
|
||||
"./iverilog-always_full-1 | grep -v \"$finish called\" >iverilog-always_full-1.log",
|
||||
"diff iverilog-always_full.log iverilog-always_full-1.log",
|
||||
]))
|
||||
|
||||
gen_tests_makefile.generate_target("display_lm", cmd([
|
||||
"../../yosys -p \"read_verilog display_lm.v\" >yosys-display_lm.log 2>&1",
|
||||
"../../yosys -p \"read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc\" >/dev/null 2>&1",
|
||||
"$${CXX:-g++} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++",
|
||||
"$(YOSYS) -p \"read_verilog display_lm.v\" >yosys-display_lm.log 2>&1",
|
||||
"$(YOSYS) -p \"read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc\" >/dev/null 2>&1",
|
||||
f"$${{CXX:-g++}} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++",
|
||||
"./yosys-display_lm_cc >yosys-display_lm_cc.log",
|
||||
"for log in yosys-display_lm.log yosys-display_lm_cc.log; do "
|
||||
"grep \"^%l: \\\\bot\\$\" \"$log\" >/dev/null 2>&1; "
|
||||
|
|
@ -109,7 +109,7 @@ def main():
|
|||
always_display()
|
||||
roundtrip()
|
||||
cxxrtl()
|
||||
extra()
|
||||
#extra()
|
||||
|
||||
gen_tests_makefile.generate_custom(callback)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,78 +0,0 @@
|
|||
#!/usr/bin/env bash
|
||||
source ../common-env.sh
|
||||
|
||||
set -e
|
||||
|
||||
../../yosys -p 'read_verilog initial_display.v' | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >yosys-initial_display.log 2>&1
|
||||
iverilog -o iverilog-initial_display initial_display.v
|
||||
./iverilog-initial_display >iverilog-initial_display.log
|
||||
diff yosys-initial_display.log iverilog-initial_display.log
|
||||
|
||||
test_always_display () {
|
||||
local subtest=$1; shift
|
||||
../../yosys -p "read_verilog $* always_display.v; proc; opt_expr -mux_bool; clean" -o yosys-always_display-${subtest}-1.v >/dev/null 2>&1
|
||||
../../yosys -p "read_verilog yosys-always_display-${subtest}-1.v; proc; opt_expr -mux_bool; clean" -o yosys-always_display-${subtest}-2.v >/dev/null 2>&1
|
||||
diff yosys-always_display-${subtest}-1.v yosys-always_display-${subtest}-2.v
|
||||
}
|
||||
|
||||
test_always_display clk -DEVENT_CLK
|
||||
test_always_display clk_rst -DEVENT_CLK_RST
|
||||
test_always_display star -DEVENT_STAR
|
||||
|
||||
test_always_display clk_en -DEVENT_CLK -DCOND_EN
|
||||
test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN
|
||||
test_always_display star_en -DEVENT_STAR -DCOND_EN
|
||||
|
||||
test_roundtrip () {
|
||||
local subtest=$1; shift
|
||||
../../yosys -p "read_verilog $* roundtrip.v; proc; clean" -o yosys-roundtrip-${subtest}-1.v >/dev/null 2>&1
|
||||
../../yosys -p "read_verilog yosys-roundtrip-${subtest}-1.v; proc; clean" -o yosys-roundtrip-${subtest}-2.v >/dev/null 2>&1
|
||||
diff yosys-roundtrip-${subtest}-1.v yosys-roundtrip-${subtest}-2.v
|
||||
|
||||
iverilog $* -o iverilog-roundtrip-${subtest} roundtrip.v roundtrip_tb.v >/dev/null 2>&1
|
||||
./iverilog-roundtrip-${subtest} >iverilog-roundtrip-${subtest}.log
|
||||
iverilog $* -o iverilog-roundtrip-${subtest}-1 yosys-roundtrip-${subtest}-1.v roundtrip_tb.v >/dev/null 2>&1
|
||||
./iverilog-roundtrip-${subtest}-1 >iverilog-roundtrip-${subtest}-1.log
|
||||
iverilog $* -o iverilog-roundtrip-${subtest}-2 yosys-roundtrip-${subtest}-2.v roundtrip_tb.v >/dev/null 2>&1
|
||||
./iverilog-roundtrip-${subtest}-1 >iverilog-roundtrip-${subtest}-2.log
|
||||
diff iverilog-roundtrip-${subtest}.log iverilog-roundtrip-${subtest}-1.log
|
||||
diff iverilog-roundtrip-${subtest}-1.log iverilog-roundtrip-${subtest}-2.log
|
||||
}
|
||||
|
||||
test_roundtrip dec_unsigned -DBASE_DEC -DSIGN=""
|
||||
test_roundtrip dec_signed -DBASE_DEC -DSIGN="signed"
|
||||
test_roundtrip hex_unsigned -DBASE_HEX -DSIGN=""
|
||||
test_roundtrip hex_signed -DBASE_HEX -DSIGN="signed"
|
||||
test_roundtrip oct_unsigned -DBASE_HEX -DSIGN=""
|
||||
test_roundtrip oct_signed -DBASE_HEX -DSIGN="signed"
|
||||
test_roundtrip bin_unsigned -DBASE_HEX -DSIGN=""
|
||||
test_roundtrip bin_signed -DBASE_HEX -DSIGN="signed"
|
||||
|
||||
test_cxxrtl () {
|
||||
local subtest=$1; shift
|
||||
|
||||
../../yosys -p "read_verilog ${subtest}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-${subtest}.cc" >/dev/null 2>&1
|
||||
${CXX:-g++} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++
|
||||
./yosys-${subtest} 2>yosys-${subtest}.log
|
||||
iverilog -o iverilog-${subtest} ${subtest}.v ${subtest}_tb.v >/dev/null 2>&1
|
||||
./iverilog-${subtest} |grep -v '\$finish called' >iverilog-${subtest}.log
|
||||
diff iverilog-${subtest}.log yosys-${subtest}.log
|
||||
}
|
||||
|
||||
test_cxxrtl always_full
|
||||
test_cxxrtl always_comb
|
||||
|
||||
# Ensure Verilog backend preserves behaviour of always block with multiple $displays.
|
||||
../../yosys -p "read_verilog always_full.v; prep; clean" -o yosys-always_full-1.v >/dev/null 2>&1
|
||||
iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v >/dev/null 2>&1
|
||||
./iverilog-always_full-1 |grep -v '\$finish called' >iverilog-always_full-1.log
|
||||
diff iverilog-always_full.log iverilog-always_full-1.log
|
||||
|
||||
../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log 2>&1
|
||||
../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc" >/dev/null 2>&1
|
||||
${CXX:-g++} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
|
||||
./yosys-display_lm_cc >yosys-display_lm_cc.log
|
||||
for log in yosys-display_lm.log yosys-display_lm_cc.log; do
|
||||
grep "^%l: \\\\bot\$" "$log" >/dev/null 2>&1
|
||||
grep "^%m: \\\\bot\$" "$log" >/dev/null 2>&1
|
||||
done
|
||||
Loading…
Add table
Add a link
Reference in a new issue