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20 lines
301 B
Verilog
20 lines
301 B
Verilog
`timescale 1ns / 1ps
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module testbench;
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reg clk;
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reg signed [5:0] wire0;
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wire y;
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top uut (.y(y), .clk(clk), .wire0(wire0));
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initial begin
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clk = 0;
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wire0 = 6'b111101;
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forever #5 clk = ~clk;
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end
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initial begin
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#100;
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$display("y = %d", y);
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$finish;
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end
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endmodule
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