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https://github.com/YosysHQ/yosys
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d41688f7d7
* area should be 1 for all LUTs * clean up macros * add log_assert to fail noisily when encountering oddly configured DFF * clean help msg * flatten set to true by default * update * merge mult tests * remove redundant test * move all dsp tests to single file and remove redundant tests * update ram tests * add more dff tests * fix c++20 compile errors * add option to dump verilog * default to use abc9 * remove -abc9 option since its the default now --------- Co-authored-by: tony <minchunlin@gmail.com> |
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| common | ||
| coolrunner2 | ||
| easic | ||
| ecp5 | ||
| efinix | ||
| fabulous | ||
| gatemate | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
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| lattice | ||
| microchip | ||
| nexus | ||
| quicklogic | ||
| sf2 | ||
| xilinx | ||
| .gitignore | ||