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https://github.com/YosysHQ/yosys
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Add comments in setup-build-env/action.yml for where to document prereqs (and the separation between build/run and test). Add some initial (very basic) text for `test_suites.rst`, listing prereqs and how to run the tests (with subsections for the different optional tests, which is currently docs, functional and unit). Add sphinx-inline-tabs, use it for tidying up prereq instructions based on OS/platform (mostly helpful in the test suites doc where there are multiple sections split by OS). Also fixes some single backticks that should be double backtick.
287 lines
9.2 KiB
Markdown
287 lines
9.2 KiB
Markdown
yosys – Yosys Open SYnthesis Suite
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===================================
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This is a framework for RTL synthesis tools. It currently has
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extensive Verilog-2005 support and provides a basic set of
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synthesis algorithms for various application domains.
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Yosys can be adapted to perform any synthesis job by combining
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the existing passes (algorithms) using synthesis scripts and
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adding additional passes as needed by extending the yosys C++
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code base.
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Yosys is free software licensed under the ISC license (a GPL
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compatible license that is similar in terms to the MIT license
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or the 2-clause BSD license).
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Third-party software distributed alongside this software
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is licensed under compatible licenses.
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Please refer to `abc` and `libs` subdirectories for their license terms.
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Web Site and Other Resources
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============================
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More information and documentation can be found on the Yosys web site:
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- https://yosyshq.net/yosys/
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If you have any Yosys-related questions, please post them on the Discourse group:
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- https://yosyshq.discourse.group
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Documentation from this repository is automatically built and available on Read
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the Docs:
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- https://yosyshq.readthedocs.io/projects/yosys
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Users interested in formal verification might want to use the formal
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verification front-end for Yosys, SBY:
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- https://yosyshq.readthedocs.io/projects/sby/
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- https://github.com/YosysHQ/sby
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The Yosys blog has news and articles from users:
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- https://blog.yosyshq.com
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Installation
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============
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Yosys is part of the [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) and the [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build)! The easiest way to use yosys is to install the binary software suite, which contains all required dependencies and related tools.
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* [Contact YosysHQ](https://www.yosyshq.com/contact) for a [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) Evaluation License and download link
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* OR go to https://github.com/YosysHQ/oss-cad-suite-build/releases to download the free OSS CAD Suite
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* Follow the [Install Instructions on GitHub](https://github.com/YosysHQ/oss-cad-suite-build#installation)
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Make sure to get a Tabby CAD Suite Evaluation License if you need features such as industry-grade SystemVerilog and VHDL parsers!
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For more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet
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Many Linux distributions also provide Yosys binaries, some more up to date than others. Check with your package manager!
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Building from Source
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====================
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For more details, and instructions for other platforms, check [building from
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source](https://yosyshq.readthedocs.io/projects/yosys/en/latest/getting_started/installation.html#building-from-source)
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on Read the Docs.
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When cloning Yosys, some required libraries are included as git submodules. Make
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sure to call e.g.
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$ git clone --recurse-submodules https://github.com/YosysHQ/yosys.git
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or
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$ git clone https://github.com/YosysHQ/yosys.git
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$ cd yosys
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$ git submodule update --init --recursive
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You need a C++ compiler with C++17 support (up-to-date CLANG or GCC is
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recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
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TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
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Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.
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For example on Ubuntu Linux 22.04 LTS the following commands will install all
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prerequisites for building yosys:
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$ sudo apt-get install gawk git make python3 lld \
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bison clang flex libboost-filesystem-dev libboost-python-dev \
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libboost-system-dev libbz2-dev libffi-dev libfl-dev \
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libreadline-dev pkg-config tcl-dev zlib1g-dev \
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graphviz xdot
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The environment variable `CXX` can be used to control the C++ compiler used, or
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run one of the following to override it:
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$ make config-clang
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$ make config-gcc
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The Makefile has many variables influencing the build process. These can be
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adjusted by modifying the Makefile.conf file which is created at the `make
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config-...` step (see above), or they can be set by passing an option to the
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make command directly:
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$ make CXX=$CXX
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For other compilers and build configurations it might be necessary to make some
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changes to the config section of the Makefile. It's also an alternative way to
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set the make variables mentioned above.
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$ vi Makefile # ..or..
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$ vi Makefile.conf
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To build Yosys simply type 'make' in this directory.
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$ make
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$ sudo make install
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Tests are located in the tests subdirectory and can be executed using the test
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target. Note that you need gawk as well as a recent version of iverilog (i.e.
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build from git). Then, execute tests via:
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$ make test
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To use a separate (out-of-tree) build directory, provide a path to the Makefile.
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$ mkdir build; cd build
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$ make -f ../Makefile
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Out-of-tree builds require a clean source tree.
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Getting Started
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===============
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Yosys can be used with the interactive command shell, with
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synthesis scripts or with command line arguments. Let's perform
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a simple synthesis job using the interactive command shell:
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$ ./yosys
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yosys>
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the command ``help`` can be used to print a list of all available
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commands and ``help <command>`` to print details on the specified command:
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yosys> help help
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reading and elaborating the design using the Verilog frontend:
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yosys> read -sv tests/simple/fiedler-cooley.v
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yosys> hierarchy -top up3down5
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writing the design to the console in the RTLIL format used by Yosys
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internally:
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yosys> write_rtlil
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convert processes (``always`` blocks) to netlist elements and perform
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some simple optimizations:
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yosys> proc; opt
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display design netlist using ``xdot``:
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yosys> show
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the same thing using ``gv`` as postscript viewer:
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yosys> show -format ps -viewer gv
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translating netlist to gate logic and perform some simple optimizations:
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yosys> techmap; opt
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write design netlist to a new Verilog file:
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yosys> write_verilog synth.v
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or using a simple synthesis script:
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$ cat synth.ys
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read -sv tests/simple/fiedler-cooley.v
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hierarchy -top up3down5
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proc; opt; techmap; opt
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write_verilog synth.v
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$ ./yosys synth.ys
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If ABC is enabled in the Yosys build configuration and a cell library is given
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in the liberty file ``mycells.lib``, the following synthesis script will
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synthesize for the given cell library:
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# read design
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read -sv tests/simple/fiedler-cooley.v
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hierarchy -top up3down5
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# the high-level stuff
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proc; fsm; opt; memory; opt
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# mapping to internal cell library
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techmap; opt
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# mapping flip-flops to mycells.lib
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dfflibmap -liberty mycells.lib
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# mapping logic to mycells.lib
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abc -liberty mycells.lib
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# cleanup
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clean
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If you do not have a liberty file but want to test this synthesis script,
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you can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources
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as simple example.
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Liberty file downloads for and information about free and open ASIC standard
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cell libraries can be found here:
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- http://www.vlsitechnology.org/html/libraries.html
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- http://www.vlsitechnology.org/synopsys/vsclib013.lib
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The command ``synth`` provides a good default synthesis script (see
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``help synth``):
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read -sv tests/simple/fiedler-cooley.v
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synth -top up3down5
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# mapping to target cells
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dfflibmap -liberty mycells.lib
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abc -liberty mycells.lib
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clean
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The command ``prep`` provides a good default word-level synthesis script, as
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used in SMT-based formal verification.
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Additional information
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======================
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The ``read_verilog`` command, used by default when calling ``read`` with Verilog
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source input, does not perform syntax checking. You should instead lint your
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source with another tool such as
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[Verilator](https://www.veripool.org/verilator/) first, e.g. by calling
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``verilator --lint-only``.
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Building the documentation
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==========================
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Note that there is no need to build the manual if you just want to read it.
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Simply visit https://yosys.readthedocs.io/en/latest/ instead.
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In addition to those packages listed above for building Yosys from source, the
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following are used for building the website:
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$ sudo apt install pdf2svg faketime
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Or for MacOS, using homebrew:
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$ brew install pdf2svg libfaketime
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PDFLaTeX, included with most LaTeX distributions, is also needed during the
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build process for the website. Or, run the following:
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$ sudo apt install texlive-latex-base texlive-latex-extra latexmk
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Or for MacOS, using homebrew:
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$ brew install basictex
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$ sudo tlmgr update --self
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$ sudo tlmgr install collection-latexextra latexmk tex-gyre
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The Python package, Sphinx, is needed along with those listed in
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`docs/source/requirements.txt`:
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$ pip install -U sphinx -r docs/source/requirements.txt
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From the root of the repository, run `make docs`. This will build/rebuild yosys
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as necessary before generating the website documentation from the yosys help
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commands. To build for pdf instead of html, call
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`make docs DOC_TARGET=latexpdf`.
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It is recommended to use the `ENABLE_HELP_SOURCE` make option for Yosys builds
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that will be used to build the documentation. This option enables source
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location tracking for passes and improves the command reference through grouping
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related commands and allowing for the documentation to link to the corresponding
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source files. Without this, a warning will be raised during the Sphinx build
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about `Found commands assigned to group unknown` and `make docs` is configured
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to fail on warnings by default.
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