3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-19 01:32:20 +00:00
yosys/tests/verific
2024-10-02 23:09:36 -07:00
..
.gitignore
bounds.vhd
bounds.ys.DISABLED
case.sv
case.ys
clocking.ys
enum_values.sv
enum_values.ys
memory_semantics.ys.DISABLED
range_case.sv
range_case.ys Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
README.md Update Verific 2024-10-02 23:09:36 -07:00
rom_case.ys.DISABLED
run-test.sh

Verific Test Cases

Disabled

  • bounds: checks top and bottom bound attributes, which are removed to avoid OpenSTA issues
  • memory_semantics: relies on initial values being retained, which we do not want
  • rom_case: relies on using Verific's VHDL frontend rather than GHDL