Emil J. Tywoniak 0c450ce8c8 WIP migration to twine		2026-06-18 19:27:41 +02:00
..
tests
abc9_model.v
arith_map.v
brams_defs.vh
brams_xc2v.txt
brams_xc2v_map.v
brams_xc3sda.txt
brams_xc3sda_map.v
brams_xc4v.txt
brams_xc4v_map.v
brams_xc5v_map.v
brams_xc6v_map.v	Fix RAMB36E1/E2 SDP parity port mapping typo	2026-04-18 19:10:18 +03:00
brams_xcu_map.v	Fix RAMB36E1/E2 SDP parity port mapping typo	2026-04-18 19:10:18 +03:00
brams_xcv.txt
brams_xcv_map.v
cells_map.v
cells_sim.v
cells_xtra.py
cells_xtra.v
ff_map.v
lut_map.v
lutrams_xc5v.txt
lutrams_xc5v_map.v
lutrams_xcu.txt
lutrams_xcv.txt
lutrams_xcv_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc	Add check before flatten in synth_*.	2026-05-05 14:06:58 +02:00
urams.txt
urams_map.v
xc3s_mult_map.v
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_dsp_map.v
xc7_dsp_map.v
xcu_dsp_map.v
xilinx_dffopt.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp48a.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp_cascade.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_dsp_CREG.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_srl.cc	WIP migration to twine	2026-06-18 19:27:41 +02:00
xilinx_srl.pmg	WIP migration to twine	2026-06-18 19:27:41 +02:00