Claire Wolf a7cc4673c3 Fix partsel expr bit width handling and add test case ... Signed-off-by: Claire Wolf <claire@symbioticeda.com>		2020-03-08 16:12:12 +01:00
..
.gitignore
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v
arrays01.v
arrays02.sv	Add proper test for SV-style arrays	2019-06-20 12:06:07 +02:00
attrib01_module.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib02_port_decl.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib03_parameter.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib04_net_var.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib05_port_conn.v.DISABLED	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib06_operator_suffix.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib07_func_call.v.DISABLED	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib08_mod_inst.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
attrib09_case.v	Added tests for attributes	2019-06-03 09:25:20 +02:00
carryadd.v
constmuldivmod.v
constpower.v
defvalue.sv	Add defvalue test, minor autotest fixes for .sv files	2019-06-19 12:12:08 +02:00
dff_different_styles.v
dff_init.v	Add test case from #997	2019-05-07 19:58:04 +02:00
fiedler-cooley.v
forgen01.v
forgen02.v
forloops.v
fsm.v
generate.v	Add test	2019-06-20 16:07:22 -07:00
graphtest.v
hierarchy.v
hierdefparam.v
i2c_master_tests.v
implicit_ports.v	Rename implicit_ports.sv test to implicit_ports.v	2019-06-07 13:12:25 +02:00
localparam_attr.v	Added tests for Verilog frontent for attributes on parameters and localparams	2019-05-16 12:53:43 +02:00
loops.v
macros.v
mem2reg.v	Add splitcmplxassign test case and silence splitcmplxassign warning	2019-05-01 10:01:54 +02:00
mem_arst.v	Make SV2017 compliant courtesy of @wsnyder	2019-12-12 07:34:07 -08:00
memory.v
multiplier.v
muxtree.v
omsp_dbg_uart.v
operators.v
param_attr.v	Added tests for Verilog frontent for attributes on parameters and localparams	2019-05-16 12:53:43 +02:00
paramods.v
partsel.v	Fix partsel expr bit width handling and add test case	2020-03-08 16:12:12 +01:00
process.v
realexpr.v	Add test case for real parameters	2019-08-20 11:38:21 +02:00
repwhile.v
retime.v
rotate.v
run-test.sh	Use command -v rather than which	2019-09-03 00:57:32 +01:00
scopes.v
signedexpr.v
sincos.v
specify.v
subbytes.v
task_func.v
undef_eqx_nex.v
usb_phy_tests.v
values.v
vloghammer.v
wandwor.v	Add actual wandwor test that is part of "make test"	2019-05-28 16:42:50 +02:00
wreduce.v
xfirrtl	Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.	2019-07-31 09:27:38 -07:00