mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-28 00:48:46 +00:00
14 lines
408 B
Text
14 lines
408 B
Text
read_verilog <<EOT
|
|
// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
|
|
// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
|
|
module top();
|
|
(* keep *) wire [31:0] \a[10] ;
|
|
(* keep *) wire b;
|
|
assign b = \a[10] [31];
|
|
endmodule
|
|
EOT
|
|
|
|
synth_intel_le -family cycloneiv -quartus
|
|
select -assert-none w:*[* w:*]*
|
|
|
|
design -reset
|