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21 lines
802 B
Text
21 lines
802 B
Text
read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/intel_le/common/le_sim.v -map +/intel_le/common/dff_sim.v synth_intel_le -family cycloneiv
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async2sync
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 6 t:MISTRAL_FF
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select -assert-max 1 t:MISTRAL_NOT
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select -assert-max 5 t:MISTRAL_ALUT2 #
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select -assert-max 1 t:MISTRAL_ALUT3
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select -assert-max 9 t:MISTRAL_ALUT4 #
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select -assert-none t:MISTRAL_FF t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
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design -reset
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