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29 lines
873 B
Text
29 lines
873 B
Text
read_verilog mult_unsigned.v
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hierarchy -top mult_unsigned
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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# TODO
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#equiv_opt -run prove: -assert null
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
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design -load postopt
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cd mult_unsigned
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#Vivado synthesizes 1 DSP48E1, 40 FDRE.
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select -assert-count 1 t:BUFG
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select -assert-count 20 t:FDRE
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select -assert-count 33 t:LUT2
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select -assert-count 1 t:LUT3
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select -assert-count 11 t:LUT4
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select -assert-count 4 t:LUT5
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select -assert-count 139 t:LUT6
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select -assert-count 19 t:MUXCY
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select -assert-count 35 t:MUXF7
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select -assert-count 20 t:SRL16E
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select -assert-count 20 t:XORCY
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select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:SRL16E t:XORCY %% t:* %D
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