read_verilog mult_unsigned.v
hierarchy -top mult_unsigned
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full

# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter

design -load postopt
cd mult_unsigned

#Vivado synthesizes 1 DSP48E1, 40 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 20 t:FDRE
select -assert-count 33 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 11 t:LUT4
select -assert-count 4 t:LUT5
select -assert-count 139 t:LUT6
select -assert-count 19 t:MUXCY
select -assert-count 35 t:MUXF7
select -assert-count 20 t:SRL16E
select -assert-count 20 t:XORCY
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:SRL16E t:XORCY %% t:* %D