mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-13 02:34:44 +00:00
Code Activity
yosys/tests/verific
History
Akash Levy 2d8588f15b Update Verific
2024-10-02 23:09:36 -07:00
..
.gitignore Add test example 2023-02-27 09:24:04 +01:00
bounds.vhd Add left and right bound properties to wire. Add test. Fix printing 2024-09-10 12:52:42 +02:00
bounds.ys.DISABLED Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
case.sv Add test example 2023-02-27 09:24:04 +01:00
case.ys Fixups 2024-09-23 04:25:10 -07:00
clocking.ys Clocking works with -formal flag 2024-09-22 08:01:16 -07:00
enum_values.sv verific: Fix enum_values support and signed attribute values 2023-03-15 09:51:36 +01:00
enum_values.ys verific: Fix enum_values support and signed attribute values 2023-03-15 09:51:36 +01:00
memory_semantics.ys.DISABLED Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
range_case.sv Added ranged case check 2023-02-27 09:24:04 +01:00
range_case.ys Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
README.md Update Verific 2024-10-02 23:09:36 -07:00
rom_case.ys.DISABLED Standardize convention, add back test, update README 2024-09-23 06:06:43 -07:00
run-test.sh Add test example 2023-02-27 09:24:04 +01:00

README.md

Verific Test Cases

Disabled

  • bounds: checks top and bottom bound attributes, which are removed to avoid OpenSTA issues
  • memory_semantics: relies on initial values being retained, which we do not want
  • rom_case: relies on using Verific's VHDL frontend rather than GHDL