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The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
20 lines
334 B
Verilog
20 lines
334 B
Verilog
module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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input CLK1;
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input [3:0] A1ADDR;
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output [3:0] A1DATA;
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input [3:0] B1ADDR;
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input [3:0] B1DATA;
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input B1EN;
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EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
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.di(B1DATA),
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.waddr(B1ADDR),
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.wclk(CLK1),
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.we(B1EN),
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.raddr(A1ADDR),
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.do(A1DATA)
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);
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endmodule
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