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yosys/techlibs/anlogic
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Icenowy Zheng c9513c695a Anlogic: let LUT5/6 have more cost than LUT4- 
According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.

So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.

Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-19 09:36:53 +08:00
..
anlogic_eqn.cc Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
arith_map.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
cells_map.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
cells_sim.v Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00
drams.txt anlogic: add support for Eagle Distributed RAM 2018-12-17 23:20:40 +08:00
drams_map.v anlogic: add support for Eagle Distributed RAM 2018-12-17 23:20:40 +08:00
eagle_bb.v Revert "Leave only real black box cells" 2018-12-17 23:20:40 +08:00
Makefile.inc anlogic: add support for Eagle Distributed RAM 2018-12-17 23:20:40 +08:00
synth_anlogic.cc Anlogic: let LUT5/6 have more cost than LUT4- 2018-12-19 09:36:53 +08:00