mirror of
https://github.com/YosysHQ/yosys
synced 2026-02-14 12:51:48 +00:00
1027 lines
32 KiB
C++
1027 lines
32 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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#include "kernel/ffinit.h"
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#include "kernel/threading.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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using RTLIL::id2cstr;
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struct keep_cache_t
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{
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dict<Module*, bool> keep_modules;
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bool purge_mode;
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keep_cache_t(bool purge_mode, ParallelDispatchThreadPool &thread_pool, const std::vector<RTLIL::Module *> &selected_modules)
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: purge_mode(purge_mode) {
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std::vector<RTLIL::Module *> scan_modules_worklist;
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dict<RTLIL::Module *, std::vector<RTLIL::Module*>> dependents;
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std::vector<RTLIL::Module *> propagate_kept_modules_worklist;
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for (RTLIL::Module *module : selected_modules) {
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if (keep_modules.count(module))
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continue;
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bool keep = scan_module(module, thread_pool, dependents, ALL_CELLS, scan_modules_worklist);
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keep_modules[module] = keep;
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if (keep)
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propagate_kept_modules_worklist.push_back(module);
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}
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while (!scan_modules_worklist.empty()) {
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RTLIL::Module *module = scan_modules_worklist.back();
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scan_modules_worklist.pop_back();
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if (keep_modules.count(module))
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continue;
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bool keep = scan_module(module, thread_pool, dependents, MINIMUM_CELLS, scan_modules_worklist);
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keep_modules[module] = keep;
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if (keep)
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propagate_kept_modules_worklist.push_back(module);
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}
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while (!propagate_kept_modules_worklist.empty()) {
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RTLIL::Module *module = propagate_kept_modules_worklist.back();
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propagate_kept_modules_worklist.pop_back();
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for (RTLIL::Module *dependent : dependents[module]) {
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if (keep_modules[dependent])
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continue;
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keep_modules[dependent] = true;
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propagate_kept_modules_worklist.push_back(dependent);
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}
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}
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}
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bool query(Cell *cell) const
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{
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if (keep_cell(cell, purge_mode))
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return true;
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if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
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return true;
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if (cell->module && cell->module->design) {
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RTLIL::Module *cell_module = cell->module->design->module(cell->type);
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return cell_module != nullptr && keep_modules.at(cell_module);
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}
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return false;
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}
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private:
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enum ScanCells {
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// Scan every cell to see if it uses a module that is kept.
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ALL_CELLS,
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// Stop scanning cells if we determine early that this module is kept.
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MINIMUM_CELLS,
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};
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bool scan_module(Module *module, ParallelDispatchThreadPool &thread_pool, dict<RTLIL::Module *, std::vector<RTLIL::Module*>> &dependents,
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ScanCells scan_cells, std::vector<Module*> &worklist) const
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{
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MonotonicFlag keep_module;
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if (module->get_bool_attribute(ID::keep)) {
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if (scan_cells == MINIMUM_CELLS)
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return true;
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keep_module.set();
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}
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ParallelDispatchThreadPool::Subpool subpool(thread_pool, ThreadPool::work_pool_size(0, module->cells_size(), 1000));
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ShardedVector<Module*> deps(subpool);
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const RTLIL::Module *const_module = module;
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bool purge_mode = this->purge_mode;
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subpool.run([purge_mode, const_module, scan_cells, &deps, &keep_module](const ParallelDispatchThreadPool::RunCtx &ctx) {
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bool keep = false;
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for (int i : ctx.item_range(const_module->cells_size())) {
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Cell *cell = const_module->cell_at(i);
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if (keep_cell(cell, purge_mode)) {
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if (scan_cells == MINIMUM_CELLS) {
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keep_module.set();
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return;
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}
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keep = true;
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}
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if (const_module->design) {
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RTLIL::Module *cell_module = const_module->design->module(cell->type);
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if (cell_module != nullptr)
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deps.insert(ctx, cell_module);
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}
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}
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if (keep) {
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keep_module.set();
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return;
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}
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for (int i : ctx.item_range(const_module->wires_size())) {
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Wire *wire = const_module->wire_at(i);
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if (wire->get_bool_attribute(ID::keep)) {
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keep_module.set();
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return;
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}
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}
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});
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if (scan_cells == MINIMUM_CELLS && keep_module.load())
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return true;
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for (Module *dep : deps) {
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dependents[dep].push_back(module);
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worklist.push_back(dep);
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}
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return keep_module.load();
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}
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static bool keep_cell(Cell *cell, bool purge_mode)
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{
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if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
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return true;
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if (cell->type.in(ID($overwrite_tag)))
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return true;
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if (cell->type == ID($print) || cell->type == ID($check))
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return true;
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if (cell->has_keep_attr())
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return true;
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if (!purge_mode && cell->type == ID($scopeinfo))
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return true;
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return false;
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}
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};
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CellTypes ct_reg, ct_all;
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struct RmStats {
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int count_rm_cells = 0;
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int count_rm_wires = 0;
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void log()
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{
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if (count_rm_cells > 0 || count_rm_wires > 0)
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YOSYS_NAMESPACE_PREFIX log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
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}
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};
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unsigned int hash_bit(const SigBit &bit) {
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return static_cast<unsigned int>(hash_ops<SigBit>::hash(bit).yield());
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}
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void rmunused_module_cells(Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose, RmStats &stats, keep_cache_t &keep_cache)
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{
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SigMap sigmap(module);
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FfInitVals ffinit;
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ffinit.set_parallel(&sigmap, subpool.thread_pool(), module);
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SigMap raw_sigmap;
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for (auto &it : module->connections_) {
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for (int i = 0; i < GetSize(it.second); i++) {
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if (it.second[i].wire != nullptr)
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raw_sigmap.add(it.first[i], it.second[i]);
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}
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}
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struct WireDrivers;
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struct WireDriver {
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using Accumulated = WireDrivers;
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SigBit bit;
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int driver_cell;
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};
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struct WireDrivers {
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WireDrivers() : driver_cell(0) {}
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WireDrivers(WireDriver driver) : bit(driver.bit), driver_cell(driver.driver_cell) {}
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WireDrivers(SigBit bit) : bit(bit), driver_cell(0) {}
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WireDrivers(WireDrivers &&other) = default;
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class const_iterator {
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public:
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const_iterator(const WireDrivers &drivers, bool end)
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: driver_cell(drivers.driver_cell), in_extra_cells(end) {
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if (drivers.extra_driver_cells) {
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if (end) {
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extra_it = drivers.extra_driver_cells->end();
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} else {
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extra_it = drivers.extra_driver_cells->begin();
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}
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}
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}
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int operator*() const {
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if (in_extra_cells)
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return **extra_it;
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return driver_cell;
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}
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const_iterator& operator++() {
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if (in_extra_cells)
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++*extra_it;
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else
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in_extra_cells = true;
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return *this;
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}
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bool operator!=(const const_iterator &other) const {
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return !(*this == other);
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}
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bool operator==(const const_iterator &other) const {
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return in_extra_cells == other.in_extra_cells &&
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extra_it == other.extra_it;
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}
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private:
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std::optional<pool<int>::iterator> extra_it;
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int driver_cell;
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bool in_extra_cells;
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};
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const_iterator begin() const { return const_iterator(*this, false); }
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const_iterator end() const { return const_iterator(*this, true); }
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SigBit bit;
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int driver_cell;
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std::unique_ptr<pool<int>> extra_driver_cells;
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};
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struct WireDriversKeyEquality {
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bool operator()(const WireDrivers &a, const WireDrivers &b) const {
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return a.bit == b.bit;
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}
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};
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struct WireDriversCollisionHandler {
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void operator()(WireDrivers &incumbent, WireDrivers &new_value) const {
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log_assert(new_value.extra_driver_cells == nullptr);
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if (!incumbent.extra_driver_cells)
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incumbent.extra_driver_cells.reset(new pool<int>());
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incumbent.extra_driver_cells->insert(new_value.driver_cell);
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}
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};
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using Wire2Drivers = ShardedHashSet<WireDriver, WireDriversKeyEquality, WireDriversCollisionHandler>;
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Wire2Drivers::Builder wire2driver_builder(subpool);
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ShardedVector<std::pair<std::string, int>> mem2cells_vector(subpool);
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ShardedVector<std::pair<SigBit, std::string>> driver_driver_logs(subpool);
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ShardedVector<Wire*> keep_wires(subpool);
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const RTLIL::Module *const_module = module;
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int num_threads = subpool.num_threads();
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ConcurrentWorkQueue<int> cell_queue(num_threads);
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std::vector<std::atomic<bool>> unused(const_module->cells_size());
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subpool.run([&sigmap, &raw_sigmap, &keep_cache, const_module, &mem2cells_vector, &driver_driver_logs, &keep_wires, &cell_queue, &wire2driver_builder, &unused](const ParallelDispatchThreadPool::RunCtx &ctx) {
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for (int i : ctx.item_range(const_module->cells_size())) {
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Cell *cell = const_module->cell_at(i);
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if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit), ID($meminit_v2)))
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mem2cells_vector.insert(ctx, {cell->getParam(ID::MEMID).decode_string(), i});
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for (auto &it2 : cell->connections()) {
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if (ct_all.cell_known(cell->type) && !ct_all.cell_output(cell->type, it2.first))
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continue;
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for (auto raw_bit : it2.second) {
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if (raw_bit.wire == nullptr)
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continue;
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auto bit = sigmap(raw_bit);
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if (bit.wire == nullptr && ct_all.cell_known(cell->type)) {
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std::string msg = stringf("Driver-driver conflict "
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"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
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log_signal(raw_bit), cell->name.unescape(), it2.first.unescape(), log_signal(bit), const_module->name.unescape());
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driver_driver_logs.insert(ctx, {raw_sigmap(raw_bit), msg});
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}
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if (bit.wire != nullptr)
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wire2driver_builder.insert(ctx, {{bit, i}, hash_bit(bit)});
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}
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}
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bool keep = keep_cache.query(cell);
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unused[i].store(!keep, std::memory_order_relaxed);
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if (keep)
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cell_queue.push(ctx, i);
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}
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for (int i : ctx.item_range(const_module->wires_size())) {
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Wire *wire = const_module->wire_at(i);
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if (wire->port_output || wire->get_bool_attribute(ID::keep))
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keep_wires.insert(ctx, wire);
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}
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});
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subpool.run([&wire2driver_builder](const ParallelDispatchThreadPool::RunCtx &ctx) {
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wire2driver_builder.process(ctx);
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});
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Wire2Drivers wire2driver(wire2driver_builder);
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dict<std::string, pool<int>> mem2cells;
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for (std::pair<std::string, int> &mem2cell : mem2cells_vector)
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mem2cells[mem2cell.first].insert(mem2cell.second);
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pool<SigBit> used_raw_bits;
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int i = 0;
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for (Wire *wire : keep_wires) {
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for (auto bit : sigmap(wire)) {
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const WireDrivers *drivers = wire2driver.find({{bit}, hash_bit(bit)});
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if (drivers != nullptr)
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for (int cell_index : *drivers)
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if (unused[cell_index].exchange(false, std::memory_order_relaxed)) {
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ThreadIndex fake_thread_index = {i++ % num_threads};
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cell_queue.push(fake_thread_index, cell_index);
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}
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}
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for (auto raw_bit : SigSpec(wire))
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used_raw_bits.insert(raw_sigmap(raw_bit));
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}
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std::vector<std::atomic<bool>> mem_unused(module->memories.size());
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dict<std::string, int> mem_indices;
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for (int i = 0; i < GetSize(module->memories); ++i) {
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mem_indices[module->memories.element(i)->first.str()] = i;
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mem_unused[i].store(true, std::memory_order_relaxed);
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}
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subpool.run([const_module, &sigmap, &wire2driver, &mem2cells, &unused, &cell_queue, &mem_indices, &mem_unused](const ParallelDispatchThreadPool::RunCtx &ctx) {
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pool<SigBit> bits;
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pool<std::string> mems;
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while (true) {
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std::vector<int> cell_indices = cell_queue.pop_batch(ctx);
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if (cell_indices.empty())
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return;
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for (auto cell_index : cell_indices) {
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Cell *cell = const_module->cell_at(cell_index);
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for (auto &it : cell->connections())
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if (!ct_all.cell_known(cell->type) || ct_all.cell_input(cell->type, it.first))
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for (auto bit : sigmap(it.second))
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bits.insert(bit);
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if (cell->type.in(ID($memrd), ID($memrd_v2))) {
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std::string mem_id = cell->getParam(ID::MEMID).decode_string();
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if (mem_indices.count(mem_id)) {
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int mem_index = mem_indices[mem_id];
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if (mem_unused[mem_index].exchange(false, std::memory_order_relaxed))
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mems.insert(mem_id);
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}
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}
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}
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for (auto bit : bits) {
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const WireDrivers *drivers = wire2driver.find({{bit}, hash_bit(bit)});
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if (drivers != nullptr)
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for (int cell_index : *drivers)
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if (unused[cell_index].exchange(false, std::memory_order_relaxed))
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cell_queue.push(ctx, cell_index);
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}
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bits.clear();
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for (auto mem : mems) {
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if (mem2cells.count(mem) == 0)
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continue;
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for (int cell_index : mem2cells.at(mem))
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if (unused[cell_index].exchange(false, std::memory_order_relaxed))
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cell_queue.push(ctx, cell_index);
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}
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mems.clear();
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}
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});
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ShardedVector<int> sharded_unused_cells(subpool);
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subpool.run([const_module, &unused, &sharded_unused_cells, &wire2driver](const ParallelDispatchThreadPool::RunCtx &ctx) {
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// Parallel destruction of `wire2driver`
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wire2driver.clear(ctx);
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for (int i : ctx.item_range(const_module->cells_size()))
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if (unused[i].load(std::memory_order_relaxed))
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sharded_unused_cells.insert(ctx, i);
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});
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pool<Cell*> unused_cells;
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for (int cell_index : sharded_unused_cells)
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unused_cells.insert(const_module->cell_at(cell_index));
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unused_cells.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
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for (auto cell : unused_cells) {
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if (verbose)
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log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
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module->design->scratchpad_set_bool("opt.did_something", true);
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if (cell->is_builtin_ff())
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ffinit.remove_init(cell->getPort(ID::Q));
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module->remove(cell);
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stats.count_rm_cells++;
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}
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for (const auto &it : mem_indices) {
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if (!mem_unused[it.second].load(std::memory_order_relaxed))
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continue;
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RTLIL::IdString id(it.first);
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if (verbose)
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log_debug(" removing unused memory `%s'.\n", id.unescape());
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delete module->memories.at(id);
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module->memories.erase(id);
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}
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if (!driver_driver_logs.empty()) {
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// We could do this in parallel but hopefully this is rare.
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for (auto &it : module->cells_) {
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Cell *cell = it.second;
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for (auto &it2 : cell->connections()) {
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if (ct_all.cell_known(cell->type) && !ct_all.cell_input(cell->type, it2.first))
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continue;
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for (auto raw_bit : raw_sigmap(it2.second))
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used_raw_bits.insert(raw_bit);
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}
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}
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for (std::pair<SigBit, std::string> &it : driver_driver_logs) {
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if (used_raw_bits.count(it.first))
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log_warning("%s\n", it.second);
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}
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}
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}
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int count_nontrivial_wire_attrs(RTLIL::Wire *w)
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{
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int count = w->attributes.size();
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count -= w->attributes.count(ID::src);
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count -= w->attributes.count(ID::hdlname);
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count -= w->attributes.count(ID(scopename));
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count -= w->attributes.count(ID::unused_bits);
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return count;
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}
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// Should we pick `s2` over `s1` to represent a signal?
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bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPool &conns, pool<RTLIL::Wire*> &direct_wires)
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{
|
|
RTLIL::Wire *w1 = s1.wire;
|
|
RTLIL::Wire *w2 = s2.wire;
|
|
|
|
if (w1 == NULL || w2 == NULL)
|
|
return w2 == NULL;
|
|
|
|
if (w1->port_input != w2->port_input)
|
|
return w2->port_input;
|
|
|
|
if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output))
|
|
return !(w2->port_input && w2->port_output);
|
|
|
|
if (w1->name.isPublic() && w2->name.isPublic()) {
|
|
if (regs.check(s1) != regs.check(s2))
|
|
return regs.check(s2);
|
|
if (direct_wires.count(w1) != direct_wires.count(w2))
|
|
return direct_wires.count(w2) != 0;
|
|
if (conns.check_any(s1) != conns.check_any(s2))
|
|
return conns.check_any(s2);
|
|
}
|
|
|
|
if (w1 == w2)
|
|
return s2.offset < s1.offset;
|
|
|
|
if (w1->port_output != w2->port_output)
|
|
return w2->port_output;
|
|
|
|
if (w1->name[0] != w2->name[0])
|
|
return w2->name.isPublic();
|
|
|
|
int attrs1 = count_nontrivial_wire_attrs(w1);
|
|
int attrs2 = count_nontrivial_wire_attrs(w2);
|
|
|
|
if (attrs1 != attrs2)
|
|
return attrs2 > attrs1;
|
|
|
|
return w2->name.lt_by_name(w1->name);
|
|
}
|
|
|
|
bool check_public_name(RTLIL::IdString id)
|
|
{
|
|
if (id.begins_with("$"))
|
|
return false;
|
|
const std::string &id_str = id.str();
|
|
if (id.begins_with("\\_") && (id.ends_with("_") || id_str.find("_[") != std::string::npos))
|
|
return false;
|
|
if (id_str.find(".$") != std::string::npos)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose, RmStats &stats)
|
|
{
|
|
// `register_signals` and `connected_signals` will help us decide later on
|
|
// on picking representatives out of groups of connected signals
|
|
SigPool register_signals;
|
|
SigPool connected_signals;
|
|
if (!purge_mode)
|
|
for (auto &it : module->cells_) {
|
|
RTLIL::Cell *cell = it.second;
|
|
if (ct_reg.cell_known(cell->type)) {
|
|
bool clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic));
|
|
for (auto &it2 : cell->connections())
|
|
if (clk2fflogic ? it2.first == ID::D : ct_reg.cell_output(cell->type, it2.first))
|
|
register_signals.add(it2.second);
|
|
}
|
|
for (auto &it2 : cell->connections())
|
|
connected_signals.add(it2.second);
|
|
}
|
|
|
|
SigMap assign_map(module);
|
|
|
|
// construct a pool of wires which are directly driven by a known celltype,
|
|
// this will influence our choice of representatives
|
|
pool<RTLIL::Wire*> direct_wires;
|
|
{
|
|
pool<RTLIL::SigSpec> direct_sigs;
|
|
for (auto &it : module->cells_) {
|
|
RTLIL::Cell *cell = it.second;
|
|
if (ct_all.cell_known(cell->type))
|
|
for (auto &it2 : cell->connections())
|
|
if (ct_all.cell_output(cell->type, it2.first))
|
|
direct_sigs.insert(assign_map(it2.second));
|
|
}
|
|
for (auto &it : module->wires_) {
|
|
if (direct_sigs.count(assign_map(it.second)) || it.second->port_input)
|
|
direct_wires.insert(it.second);
|
|
}
|
|
}
|
|
|
|
// weight all options for representatives with `compare_signals`,
|
|
// the one that wins will be what `assign_map` maps to
|
|
for (auto &it : module->wires_) {
|
|
RTLIL::Wire *wire = it.second;
|
|
for (int i = 0; i < wire->width; i++) {
|
|
RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1);
|
|
if (compare_signals(s2, s1, register_signals, connected_signals, direct_wires))
|
|
assign_map.add(s1);
|
|
}
|
|
}
|
|
|
|
// we are removing all connections
|
|
module->connections_.clear();
|
|
|
|
// used signals sigmapped
|
|
SigPool used_signals;
|
|
// used signals pre-sigmapped
|
|
SigPool raw_used_signals;
|
|
// used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`)
|
|
SigPool used_signals_nodrivers;
|
|
|
|
// gather the usage information for cells
|
|
for (auto &it : module->cells_) {
|
|
RTLIL::Cell *cell = it.second;
|
|
for (auto &it2 : cell->connections_) {
|
|
assign_map.apply(it2.second); // modify the cell connection in place
|
|
raw_used_signals.add(it2.second);
|
|
used_signals.add(it2.second);
|
|
if (!ct_all.cell_output(cell->type, it2.first))
|
|
used_signals_nodrivers.add(it2.second);
|
|
}
|
|
}
|
|
|
|
// gather the usage information for ports, wires with `keep`,
|
|
// also gather init bits
|
|
dict<RTLIL::SigBit, RTLIL::State> init_bits;
|
|
for (auto &it : module->wires_) {
|
|
RTLIL::Wire *wire = it.second;
|
|
if (wire->port_id > 0) {
|
|
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
|
|
raw_used_signals.add(sig);
|
|
assign_map.apply(sig);
|
|
used_signals.add(sig);
|
|
if (!wire->port_input)
|
|
used_signals_nodrivers.add(sig);
|
|
}
|
|
if (wire->get_bool_attribute(ID::keep)) {
|
|
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
|
|
assign_map.apply(sig);
|
|
used_signals.add(sig);
|
|
}
|
|
auto it2 = wire->attributes.find(ID::init);
|
|
if (it2 != wire->attributes.end()) {
|
|
RTLIL::Const &val = it2->second;
|
|
SigSpec sig = assign_map(wire);
|
|
for (int i = 0; i < GetSize(val) && i < GetSize(sig); i++)
|
|
if (val[i] != State::Sx)
|
|
init_bits[sig[i]] = val[i];
|
|
wire->attributes.erase(it2);
|
|
}
|
|
}
|
|
|
|
// set init attributes on all wires of a connected group
|
|
for (auto wire : module->wires()) {
|
|
bool found = false;
|
|
Const val(State::Sx, wire->width);
|
|
for (int i = 0; i < wire->width; i++) {
|
|
auto it = init_bits.find(RTLIL::SigBit(wire, i));
|
|
if (it != init_bits.end()) {
|
|
val.set(i, it->second);
|
|
found = true;
|
|
}
|
|
}
|
|
if (found)
|
|
wire->attributes[ID::init] = val;
|
|
}
|
|
|
|
// now decide for each wire if we should be deleting it
|
|
pool<RTLIL::Wire*> del_wires_queue;
|
|
for (auto wire : module->wires())
|
|
{
|
|
SigSpec s1 = SigSpec(wire), s2 = assign_map(s1);
|
|
log_assert(GetSize(s1) == GetSize(s2));
|
|
|
|
Const initval;
|
|
if (wire->attributes.count(ID::init))
|
|
initval = wire->attributes.at(ID::init);
|
|
if (GetSize(initval) != GetSize(wire))
|
|
initval.resize(GetSize(wire), State::Sx);
|
|
if (initval.is_fully_undef())
|
|
wire->attributes.erase(ID::init);
|
|
|
|
if (GetSize(wire) == 0) {
|
|
// delete zero-width wires, unless they are module ports
|
|
if (wire->port_id == 0)
|
|
goto delete_this_wire;
|
|
} else
|
|
if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
|
|
// do not delete anything with "keep" or module ports or initialized wires
|
|
} else
|
|
if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) {
|
|
// do not get rid of public names unless in purge mode or if the wire is entirely unused, not even aliased
|
|
} else
|
|
if (!raw_used_signals.check_any(s1)) {
|
|
// delete wires that aren't used by anything directly
|
|
goto delete_this_wire;
|
|
}
|
|
|
|
if (0)
|
|
{
|
|
delete_this_wire:
|
|
del_wires_queue.insert(wire);
|
|
}
|
|
else
|
|
{
|
|
RTLIL::SigSig new_conn;
|
|
for (int i = 0; i < GetSize(s1); i++)
|
|
if (s1[i] != s2[i]) {
|
|
if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
|
|
s2[i] = initval[i];
|
|
initval.set(i, State::Sx);
|
|
}
|
|
new_conn.first.append(s1[i]);
|
|
new_conn.second.append(s2[i]);
|
|
}
|
|
if (new_conn.first.size() > 0) {
|
|
if (initval.is_fully_undef())
|
|
wire->attributes.erase(ID::init);
|
|
else
|
|
wire->attributes.at(ID::init) = initval;
|
|
module->connect(new_conn);
|
|
}
|
|
|
|
if (!used_signals_nodrivers.check_all(s2)) {
|
|
std::string unused_bits;
|
|
for (int i = 0; i < GetSize(s2); i++) {
|
|
if (s2[i].wire == NULL)
|
|
continue;
|
|
if (!used_signals_nodrivers.check(s2[i])) {
|
|
if (!unused_bits.empty())
|
|
unused_bits += " ";
|
|
unused_bits += stringf("%d", i);
|
|
}
|
|
}
|
|
if (unused_bits.empty() || wire->port_id != 0)
|
|
wire->attributes.erase(ID::unused_bits);
|
|
else
|
|
wire->attributes[ID::unused_bits] = RTLIL::Const(unused_bits);
|
|
} else {
|
|
wire->attributes.erase(ID::unused_bits);
|
|
}
|
|
}
|
|
}
|
|
|
|
int del_temp_wires_count = 0;
|
|
for (auto wire : del_wires_queue) {
|
|
if (ys_debug() || (check_public_name(wire->name) && verbose))
|
|
log_debug(" removing unused non-port wire %s.\n", wire->name);
|
|
else
|
|
del_temp_wires_count++;
|
|
}
|
|
|
|
module->remove(del_wires_queue);
|
|
stats.count_rm_wires += GetSize(del_wires_queue);
|
|
|
|
if (verbose && del_temp_wires_count)
|
|
log_debug(" removed %d unused temporary wires.\n", del_temp_wires_count);
|
|
|
|
if (!del_wires_queue.empty())
|
|
module->design->scratchpad_set_bool("opt.did_something", true);
|
|
|
|
return !del_wires_queue.empty();
|
|
}
|
|
|
|
bool rmunused_module_init(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
|
|
{
|
|
CellTypes fftypes;
|
|
fftypes.setup_internals_mem();
|
|
|
|
SigMap sigmap(module);
|
|
|
|
const Module *const_module = module;
|
|
ShardedVector<std::pair<SigBit, State>> results(subpool);
|
|
subpool.run([const_module, &fftypes, &results](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
|
for (int i : ctx.item_range(const_module->cells_size())) {
|
|
RTLIL::Cell *cell = const_module->cell_at(i);
|
|
if (fftypes.cell_known(cell->type) && cell->hasPort(ID::Q))
|
|
{
|
|
SigSpec sig = cell->getPort(ID::Q);
|
|
|
|
for (int i = 0; i < GetSize(sig); i++)
|
|
{
|
|
SigBit bit = sig[i];
|
|
|
|
if (bit.wire == nullptr || bit.wire->attributes.count(ID::init) == 0)
|
|
continue;
|
|
|
|
Const init = bit.wire->attributes.at(ID::init);
|
|
|
|
if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz)
|
|
continue;
|
|
|
|
results.insert(ctx, {bit, init[i]});
|
|
}
|
|
}
|
|
}
|
|
});
|
|
dict<SigBit, State> qbits;
|
|
for (std::pair<SigBit, State> &p : results) {
|
|
sigmap.add(p.first);
|
|
qbits[p.first] = p.second;
|
|
}
|
|
|
|
ShardedVector<RTLIL::Wire*> wire_results(subpool);
|
|
subpool.run([const_module, &sigmap, &qbits, &wire_results](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
|
for (int j : ctx.item_range(const_module->wires_size())) {
|
|
RTLIL::Wire *wire = const_module->wire_at(j);
|
|
if (wire->attributes.count(ID::init) == 0)
|
|
continue;
|
|
Const init = wire->attributes.at(ID::init);
|
|
|
|
for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++)
|
|
{
|
|
if (init[i] == State::Sx || init[i] == State::Sz)
|
|
continue;
|
|
|
|
SigBit wire_bit = SigBit(wire, i);
|
|
SigBit mapped_wire_bit = sigmap(wire_bit);
|
|
|
|
if (wire_bit == mapped_wire_bit)
|
|
goto next_wire;
|
|
|
|
if (mapped_wire_bit.wire) {
|
|
if (qbits.count(mapped_wire_bit) == 0)
|
|
goto next_wire;
|
|
|
|
if (qbits.at(mapped_wire_bit) != init[i])
|
|
goto next_wire;
|
|
}
|
|
else {
|
|
if (mapped_wire_bit == State::Sx || mapped_wire_bit == State::Sz)
|
|
goto next_wire;
|
|
|
|
if (mapped_wire_bit != init[i]) {
|
|
log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i]));
|
|
goto next_wire;
|
|
}
|
|
}
|
|
}
|
|
wire_results.insert(ctx, wire);
|
|
|
|
next_wire:;
|
|
}
|
|
});
|
|
|
|
bool did_something = false;
|
|
for (RTLIL::Wire *wire : wire_results) {
|
|
if (verbose)
|
|
log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
|
|
wire->attributes.erase(ID::init);
|
|
did_something = true;
|
|
}
|
|
|
|
if (did_something)
|
|
module->design->scratchpad_set_bool("opt.did_something", true);
|
|
|
|
return did_something;
|
|
}
|
|
|
|
void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
|
|
{
|
|
ShardedVector<RTLIL::Cell*> delcells(subpool);
|
|
ShardedVector<RTLIL::SigSig> new_connections(subpool);
|
|
const RTLIL::Module *const_module = module;
|
|
subpool.run([const_module, &delcells, &new_connections](const ParallelDispatchThreadPool::RunCtx &ctx) {
|
|
for (int i : ctx.item_range(const_module->cells_size())) {
|
|
RTLIL::Cell *cell = const_module->cell_at(i);
|
|
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
|
|
bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
|
|
RTLIL::SigSpec a = cell->getPort(ID::A);
|
|
RTLIL::SigSpec y = cell->getPort(ID::Y);
|
|
a.extend_u0(GetSize(y), is_signed);
|
|
|
|
if (a.has_const(State::Sz)) {
|
|
RTLIL::SigSpec new_a;
|
|
RTLIL::SigSpec new_y;
|
|
for (int i = 0; i < GetSize(a); ++i) {
|
|
RTLIL::SigBit b = a[i];
|
|
if (b == State::Sz)
|
|
continue;
|
|
new_a.append(b);
|
|
new_y.append(y[i]);
|
|
}
|
|
a = std::move(new_a);
|
|
y = std::move(new_y);
|
|
}
|
|
if (!y.empty())
|
|
new_connections.insert(ctx, {y, a});
|
|
delcells.insert(ctx, cell);
|
|
} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
|
|
RTLIL::SigSpec a = cell->getPort(ID::A);
|
|
RTLIL::SigSpec b = cell->getPort(ID::B);
|
|
if (a.has_const() && !b.has_const())
|
|
std::swap(a, b);
|
|
new_connections.insert(ctx, {a, b});
|
|
delcells.insert(ctx, cell);
|
|
} else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) {
|
|
delcells.insert(ctx, cell);
|
|
}
|
|
}
|
|
});
|
|
bool did_something = false;
|
|
for (RTLIL::SigSig &connection : new_connections) {
|
|
module->connect(connection);
|
|
}
|
|
for (RTLIL::Cell *cell : delcells) {
|
|
if (verbose) {
|
|
if (cell->type == ID($connect))
|
|
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
|
|
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
|
|
else if (cell->type == ID($input_port))
|
|
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
|
|
log_signal(cell->getPort(ID::Y)));
|
|
else
|
|
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
|
|
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
|
|
}
|
|
module->remove(cell);
|
|
did_something = true;
|
|
}
|
|
if (did_something)
|
|
module->design->scratchpad_set_bool("opt.did_something", true);
|
|
}
|
|
|
|
void rmunused_module(RTLIL::Module *module, ParallelDispatchThreadPool &thread_pool, bool purge_mode, bool verbose, bool rminit, RmStats &stats, keep_cache_t &keep_cache)
|
|
{
|
|
if (verbose)
|
|
log("Finding unused cells or wires in module %s..\n", module->name);
|
|
|
|
// Use no more than one worker per thousand cells, rounded down, so
|
|
// we only start multithreading with at least 2000 cells.
|
|
int num_worker_threads = ThreadPool::work_pool_size(0, module->cells_size(), 1000);
|
|
ParallelDispatchThreadPool::Subpool subpool(thread_pool, num_worker_threads);
|
|
remove_temporary_cells(module, subpool, verbose);
|
|
rmunused_module_cells(module, subpool, verbose, stats, keep_cache);
|
|
while (rmunused_module_signals(module, purge_mode, verbose, stats)) { }
|
|
|
|
if (rminit && rmunused_module_init(module, subpool, verbose))
|
|
while (rmunused_module_signals(module, purge_mode, verbose, stats)) { }
|
|
}
|
|
|
|
struct OptCleanPass : public Pass {
|
|
OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" opt_clean [options] [selection]\n");
|
|
log("\n");
|
|
log("This pass identifies wires and cells that are unused and removes them. Other\n");
|
|
log("passes often remove cells but leave the wires in the design or reconnect the\n");
|
|
log("wires but leave the old cells in the design. This pass can be used to clean up\n");
|
|
log("after the passes that do the actual work.\n");
|
|
log("\n");
|
|
log("This pass only operates on completely selected modules without processes.\n");
|
|
log("\n");
|
|
log(" -purge\n");
|
|
log(" also remove internal nets if they have a public name\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
bool purge_mode = false;
|
|
|
|
log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
|
|
log_push();
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-purge") {
|
|
purge_mode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
std::vector<RTLIL::Module*> selected_modules;
|
|
for (auto module : design->selected_whole_modules_warn())
|
|
if (!module->has_processes_warn())
|
|
selected_modules.push_back(module);
|
|
int thread_pool_size = 0;
|
|
for (RTLIL::Module *m : selected_modules)
|
|
thread_pool_size = std::max(thread_pool_size, ThreadPool::work_pool_size(0, m->cells_size(), 1000));
|
|
ParallelDispatchThreadPool thread_pool(thread_pool_size);
|
|
keep_cache_t keep_cache(purge_mode, thread_pool, selected_modules);
|
|
|
|
ct_reg.setup_internals_mem();
|
|
ct_reg.setup_internals_anyinit();
|
|
ct_reg.setup_stdcells_mem();
|
|
|
|
ct_all.setup(design);
|
|
|
|
RmStats stats;
|
|
for (auto module : selected_modules)
|
|
rmunused_module(module, thread_pool, purge_mode, true, true, stats, keep_cache);
|
|
stats.log();
|
|
|
|
design->optimize();
|
|
design->check();
|
|
|
|
ct_reg.clear();
|
|
ct_all.clear();
|
|
log_pop();
|
|
|
|
request_garbage_collection();
|
|
}
|
|
} OptCleanPass;
|
|
|
|
struct CleanPass : public Pass {
|
|
CleanPass() : Pass("clean", "remove unused cells and wires") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" clean [options] [selection]\n");
|
|
log("\n");
|
|
log("This is identical to 'opt_clean', but less verbose.\n");
|
|
log("\n");
|
|
log("When commands are separated using the ';;' token, this command will be executed\n");
|
|
log("between the commands.\n");
|
|
log("\n");
|
|
log("When commands are separated using the ';;;' token, this command will be executed\n");
|
|
log("in -purge mode between the commands.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
bool purge_mode = false;
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-purge") {
|
|
purge_mode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
std::vector<RTLIL::Module*> selected_modules;
|
|
for (auto module : design->selected_unboxed_whole_modules())
|
|
if (!module->has_processes())
|
|
selected_modules.push_back(module);
|
|
int thread_pool_size = 0;
|
|
for (RTLIL::Module *m : selected_modules)
|
|
thread_pool_size = std::max(thread_pool_size, ThreadPool::work_pool_size(0, m->cells_size(), 1000));
|
|
ParallelDispatchThreadPool thread_pool(thread_pool_size);
|
|
keep_cache_t keep_cache(purge_mode, thread_pool, selected_modules);
|
|
|
|
ct_reg.setup_internals_mem();
|
|
ct_reg.setup_internals_anyinit();
|
|
ct_reg.setup_stdcells_mem();
|
|
|
|
ct_all.setup(design);
|
|
|
|
RmStats stats;
|
|
for (auto module : selected_modules)
|
|
rmunused_module(module, thread_pool, purge_mode, ys_debug(), true, stats, keep_cache);
|
|
|
|
log_suppressed();
|
|
stats.log();
|
|
|
|
design->optimize();
|
|
design->check();
|
|
|
|
ct_reg.clear();
|
|
ct_all.clear();
|
|
|
|
request_garbage_collection();
|
|
}
|
|
} CleanPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|