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2026-02-14 12:51:48 +00:00
Code
Activity
c742785b65
yosys
/
frontends
History
Robert O'Callahan
c742785b65
Merge
b438afc2d8
into
e2f0c4d9a0
2026-02-13 01:11:30 -05:00
..
aiger
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
aiger2
Enable xaiger2 pass when not in NDEBUG
2025-11-21 14:23:32 -08:00
ast
verilog: Do not set
module_not_derived
on internal cells
2026-01-19 16:48:13 -08:00
blif
Add gatesi_mode in BLIF format
2026-01-14 21:41:56 +01:00
json
Support param. default values in JSON FE and SV BE
2026-02-11 08:10:55 -08:00
liberty
read_liberty: support loopy retention cells
2025-11-20 13:21:32 +01:00
rpc
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
rtlil
Work around
std::reverse
miscompilation with empty range
2026-02-05 18:58:17 +00:00
verific
Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
2026-02-02 15:26:03 -08:00
verilog
read_verilog: remove log I left behind by accident
2026-01-13 18:47:23 +01:00