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yosys/tests
2026-05-20 12:14:50 -07:00
..
aiger Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order 2025-12-12 10:00:09 +01:00
alumacc
arch Merge from main 2026-02-13 04:14:08 -08:00
asicworld
bind
blif Merge from upstream 2026-01-26 22:16:11 -08:00
bram
bugpoint
cxxrtl
errors
fmt
fsm
functional Add test 2026-01-06 16:19:04 -08:00
hana
liberty
lut
memfile
memlib Fixups 2026-02-18 01:12:35 -08:00
memories
opt opt parallel prefix and priority encoders 2026-05-20 12:14:50 -07:00
opt_share
peepopt modshr onehot pass 2026-05-20 01:25:28 -07:00
proc Test empty switches 2026-01-07 13:21:33 +13:00
pyosys use run_pass in ecp5 add/sub test 2026-01-29 02:42:23 -08:00
realmath
rpc
rtlil
sat
sdc
select
share
silimate Improvements 2026-05-01 22:50:43 -07:00
sim
simple
simple_abc9
smv
sva
svinterfaces
svtypes
techmap Merge from main 2026-02-13 04:14:08 -08:00
tools Add AFL++ Grammar-Generator grammar for RTLIL fuzzing, and instructions for how to use it. 2025-12-22 21:56:26 +00:00
unit Fixups 2026-02-18 01:12:35 -08:00
various Fix offset in splitcells 2026-04-09 16:20:26 -07:00
verific No operator optimization, but it passes all tests 2026-04-22 03:12:26 -07:00
verilog Merge pull request #4235 from ylm/genblk_wire 2026-01-13 16:40:22 +01:00
vloghtb
xprop
.gitignore
common-env.sh
gen-tests-makefile.sh No operator optimization, but it passes all tests 2026-04-22 03:12:26 -07:00
pass-fuzzing.md Add AFL++ Grammar-Generator grammar for RTLIL fuzzing, and instructions for how to use it. 2025-12-22 21:56:26 +00:00