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yosys/backends/verilog
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Marcelina Kościelnicka 56e7791760 verilog backend: Emit a wire for ports as well. 
Fixes #3177.
2022-01-31 01:08:41 +01:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc verilog backend: Emit a wire for ports as well. 2022-01-31 01:08:41 +01:00