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yosys/tests/various/setundef_selection_ff.il

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module \test
wire input 1 \clk
wire output 2 \a
wire output 3 \b
cell $dff \myff_a
parameter \WIDTH 1
parameter \CLK_POLARITY 1'1
connect \D \a
connect \Q \a
connect \CLK \clk
end
cell $dff \myff_b
parameter \WIDTH 1
parameter \CLK_POLARITY 1'1
connect \D \b
connect \Q \b
connect \CLK \clk
end
end