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yosys/passes
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George Rennie bd2cdd31af proc_dff: refactor inference logic 
* Instead of an ad hoc mix of optimizations and inferences, this tries
  to make it more principled by first extracting a set of asynchronous
  update rules from the process, then optimizing them before lowering
  them to a concrete flip-flop type, preferring simpler ones
2024-11-28 19:03:33 +01:00
..
cmds portarcs: New command to derive propagation arcs 2024-11-13 16:20:35 +01:00
equiv equiv_simple: Take FFs into account for driver map 2024-02-21 12:05:52 +01:00
fsm rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
hierarchy Print a note about finding attribute (* top *) in hierarchy 2024-11-13 10:21:44 +01:00
memory rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
opt opt_dff: sigmap bits before looking up muxes 2024-11-28 19:03:33 +01:00
pmgen Merge pull request #4448 from georgerennie/shiftadd_gating 2024-11-20 13:34:09 +01:00
proc proc_dff: refactor inference logic 2024-11-28 19:03:33 +01:00
sat Merge pull request #4525 from georgerennie/peepopt_clock_gate 2024-11-11 14:49:09 +01:00
techmap clockgate: reduce errors to warnings 2024-11-18 18:32:18 +01:00
tests rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00