Miodrag Milanovic a689342207 Remove trailing whitespaces		2026-06-23 07:24:59 +02:00
..
tests	Remove trailing whitespaces	2026-06-23 07:24:59 +02:00
abc9_model.v
arith_map.v	End of file fix	2026-06-23 07:23:41 +02:00
brams_defs.vh
brams_xc2v.txt
brams_xc2v_map.v
brams_xc3sda.txt
brams_xc3sda_map.v
brams_xc4v.txt
brams_xc4v_map.v
brams_xc5v_map.v
brams_xc6v_map.v	Fix RAMB36E1/E2 SDP parity port mapping typo	2026-04-18 19:10:18 +03:00
brams_xcu_map.v	End of file fix	2026-06-23 07:23:41 +02:00
brams_xcv.txt
brams_xcv_map.v
cells_map.v
cells_sim.v
cells_xtra.py
cells_xtra.v	End of file fix	2026-06-23 07:23:41 +02:00
CMakeLists.txt	Migrate build system to CMake	2026-06-03 08:58:10 +00:00
ff_map.v	End of file fix	2026-06-23 07:23:41 +02:00
lut_map.v	End of file fix	2026-06-23 07:23:41 +02:00
lutrams_xc5v.txt
lutrams_xc5v_map.v
lutrams_xcu.txt
lutrams_xcv.txt
lutrams_xcv_map.v
mux_map.v
synth_xilinx.cc	Add check before flatten in synth_*.	2026-05-05 14:06:58 +02:00
urams.txt
urams_map.v
xc3s_mult_map.v	End of file fix	2026-06-23 07:23:41 +02:00
xc3sda_dsp_map.v	End of file fix	2026-06-23 07:23:41 +02:00
xc4v_dsp_map.v
xc5v_dsp_map.v	End of file fix	2026-06-23 07:23:41 +02:00
xc6s_dsp_map.v	End of file fix	2026-06-23 07:23:41 +02:00
xc7_dsp_map.v
xcu_dsp_map.v	End of file fix	2026-06-23 07:23:41 +02:00
xilinx_dffopt.cc	End of file fix	2026-06-23 07:23:41 +02:00
xilinx_dsp.cc	Remove pmgen related users of log_id	2026-05-14 17:28:10 +02:00
xilinx_dsp.pmg	Add support for subtraction in preadder	2026-02-03 08:31:01 -08:00
xilinx_dsp48a.pmg
xilinx_dsp_cascade.pmg	Refactor uses of log_id in pgm files	2026-05-14 12:21:32 +02:00
xilinx_dsp_CREG.pmg
xilinx_srl.cc	Refactored uses of log_id()	2026-05-08 20:59:24 -07:00
xilinx_srl.pmg