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yosys/tests/csa_tree/add_mixed_widths.v
2026-03-13 12:09:50 +01:00

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155 B
Verilog

module add_mixed_widths(
input [7:0] a,
input [3:0] b,
input [15:0] c,
input [7:0] d,
output [15:0] y
);
assign y = a + b + c + d;
endmodule