mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-23 04:49:15 +00:00
9 lines
114 B
Verilog
9 lines
114 B
Verilog
// Min chain len
|
|
|
|
module add_chain_3(
|
|
input [7:0] a, b, c,
|
|
output [7:0] y
|
|
);
|
|
assign y = a + b + c;
|
|
endmodule
|
|
|