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yosys/examples/cmos
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Uros Platise b34385ec92 Completed ngspice digital example with verilog tb
2016-03-05 08:34:05 +01:00
..
cmos_cells.lib Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
cmos_cells.sp Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
cmos_cells.v Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
cmos_cells_digital.sp Added digital (xspice) example code to examples/cmos/ 2016-03-02 12:07:57 +01:00
counter.v Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
counter.ys Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
counter_digital.ys Completed ngspice digital example with verilog tb 2016-03-05 08:34:05 +01:00
counter_tb.v Completed ngspice digital example with verilog tb 2016-03-05 08:34:05 +01:00
README Completed ngspice digital example with verilog tb 2016-03-05 08:34:05 +01:00
testbench.sh Added digital (xspice) example code to examples/cmos/ 2016-03-02 12:07:57 +01:00
testbench.sp Added digital (xspice) example code to examples/cmos/ 2016-03-02 12:07:57 +01:00
testbench_digital.sh Completed ngspice digital example with verilog tb 2016-03-05 08:34:05 +01:00
testbench_digital.sp Completed ngspice digital example with verilog tb 2016-03-05 08:34:05 +01:00

README 

In this directory you will find out, how to generate a spice output
operating in two modes, analog or event-driven mode supported by ngspice
xspice sub-module.

Each test bench can be run separately by either running:

- testbench.sh, to start analog simulation or
- testbench_digital.sh for mixed-signal digital simulation.

The later case also includes pure verilog simulation using the iverilog
and gtkwave to represent the results.