| .. |
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achronix
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End of file fix
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2026-06-23 07:23:41 +02:00 |
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analogdevices
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Remove trailing whitespaces
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2026-06-23 07:24:59 +02:00 |
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anlogic
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WIP migration to twine
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2026-07-20 12:27:18 +02:00 |
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common
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mul2dsp: declare $__mul and $__soft_mul so their ports have directions
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2026-07-22 01:28:24 +02:00 |
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coolrunner2
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coolrunner2: twines
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2026-07-20 15:01:30 +02:00 |
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easic
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Migrate build system to CMake
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2026-06-03 08:58:10 +00:00 |
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efinix
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WIP migration to twine
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2026-07-20 12:27:18 +02:00 |
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fabulous
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Remove old techmap.
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2026-07-08 12:07:58 +02:00 |
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gatemate
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WIP migration to twine
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2026-07-20 12:27:18 +02:00 |
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gowin
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gowin: replace positional arguments in cells_sim.v with named
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2026-07-17 23:33:02 +02:00 |
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greenpak4
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WIP migration to twine
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2026-07-20 12:27:18 +02:00 |
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ice40
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ice40_opt: retire the wrapper's ports before reinterpreting it as $lut
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2026-07-22 01:26:33 +02:00 |
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intel
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Revert "intel: register bram celltypes"
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2026-07-17 23:38:01 +02:00 |
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intel_alm
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Revert "intel: register bram celltypes"
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2026-07-17 23:38:01 +02:00 |
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lattice
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twines phase-3 build fix: post-fork main files broken by twine migration
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2026-07-20 15:01:30 +02:00 |
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microchip
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WIP migration to twine
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2026-07-20 12:27:18 +02:00 |
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nanoxplore
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techlibs: fix twines
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2026-07-20 13:57:10 +02:00 |
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quicklogic
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ql_bram_merge: declare the merged BRAM's ports before connecting them
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2026-07-22 01:29:55 +02:00 |
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sf2
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Remove trailing whitespaces
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2026-06-23 07:24:59 +02:00 |
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xilinx
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WIP migration to twine
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2026-07-20 12:27:18 +02:00 |
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CMakeLists.txt
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Migrate build system to CMake
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2026-06-03 08:58:10 +00:00 |
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fix_mod.py
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Remove trailing whitespaces
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2026-06-23 07:24:59 +02:00 |
