3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-08-07 14:41:26 +00:00
yosys/techlibs/common
2026-02-04 22:26:06 -08:00
..
choices
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc sdc_expand, opensta: start 2025-11-19 15:20:50 +01:00
mul2dsp.v
opensta.cc opensta, sdc_expand: mark as experimental 2025-11-19 15:31:17 +01:00
opensta.h opensta: refactor default command 2025-11-19 15:20:50 +01:00
pmux2mux.v
prep.cc Undo the terrible upstream changes that break everything... 2026-02-04 22:26:06 -08:00
sdc_expand.cc opensta, sdc_expand: mark as experimental 2025-11-19 15:31:17 +01:00
simcells.v
simlib.v added SIMLIB_VERILATOR_COMPAT 2025-10-01 10:19:25 -07:00
smtmap.v
synth.cc
techmap.v