mirror of
https://github.com/YosysHQ/yosys
synced 2026-02-04 00:06:18 +00:00
34829 lines
1.6 MiB
34829 lines
1.6 MiB
// Created by cells_xtra.py from Xilinx models
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module RAMB4_S1(DO, ADDR, DI, EN, CLK, WE, RST);
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [0:0] DO;
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input [11:0] ADDR;
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input [0:0] DI;
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input EN;
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(* clkbuf_sink *)
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input CLK;
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input WE;
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input RST;
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endmodule
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module RAMB4_S2(DO, ADDR, DI, EN, CLK, WE, RST);
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [1:0] DO;
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input [10:0] ADDR;
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input [1:0] DI;
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input EN;
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(* clkbuf_sink *)
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input CLK;
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input WE;
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input RST;
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endmodule
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module RAMB4_S4(DO, ADDR, DI, EN, CLK, WE, RST);
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [3:0] DO;
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input [9:0] ADDR;
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input [3:0] DI;
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input EN;
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(* clkbuf_sink *)
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input CLK;
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input WE;
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input RST;
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endmodule
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module RAMB4_S8(DO, ADDR, DI, EN, CLK, WE, RST);
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [7:0] DO;
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input [8:0] ADDR;
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input [7:0] DI;
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input EN;
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(* clkbuf_sink *)
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input CLK;
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input WE;
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input RST;
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endmodule
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module RAMB4_S16(DO, ADDR, DI, EN, CLK, WE, RST);
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [15:0] DO;
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input [7:0] ADDR;
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input [15:0] DI;
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input EN;
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(* clkbuf_sink *)
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input CLK;
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input WE;
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input RST;
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endmodule
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module RAMB4_S1_S1(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [0:0] DOA;
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input [11:0] ADDRA;
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input [0:0] DIA;
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input ENA;
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(* clkbuf_sink *)
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input CLKA;
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input WEA;
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input RSTA;
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output [0:0] DOB;
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input [11:0] ADDRB;
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input [0:0] DIB;
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input ENB;
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(* clkbuf_sink *)
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input CLKB;
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input WEB;
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input RSTB;
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endmodule
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module RAMB4_S1_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [0:0] DOA;
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input [11:0] ADDRA;
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input [0:0] DIA;
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input ENA;
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(* clkbuf_sink *)
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input CLKA;
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input WEA;
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input RSTA;
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output [1:0] DOB;
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input [10:0] ADDRB;
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input [1:0] DIB;
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input ENB;
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(* clkbuf_sink *)
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input CLKB;
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input WEB;
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input RSTB;
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endmodule
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module RAMB4_S1_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [0:0] DOA;
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input [11:0] ADDRA;
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input [0:0] DIA;
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input ENA;
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(* clkbuf_sink *)
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input CLKA;
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input WEA;
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input RSTA;
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output [3:0] DOB;
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input [9:0] ADDRB;
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input [3:0] DIB;
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input ENB;
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(* clkbuf_sink *)
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input CLKB;
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input WEB;
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input RSTB;
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endmodule
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module RAMB4_S1_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [0:0] DOA;
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input [11:0] ADDRA;
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input [0:0] DIA;
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input ENA;
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(* clkbuf_sink *)
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input CLKA;
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input WEA;
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input RSTA;
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output [7:0] DOB;
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input [8:0] ADDRB;
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input [7:0] DIB;
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input ENB;
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(* clkbuf_sink *)
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input CLKB;
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input WEB;
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input RSTB;
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endmodule
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module RAMB4_S1_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [0:0] DOA;
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input [11:0] ADDRA;
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input [0:0] DIA;
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input ENA;
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(* clkbuf_sink *)
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input CLKA;
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input WEA;
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input RSTA;
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output [15:0] DOB;
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input [7:0] ADDRB;
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input [15:0] DIB;
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input ENB;
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(* clkbuf_sink *)
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input CLKB;
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input WEB;
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input RSTB;
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endmodule
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module RAMB4_S2_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [1:0] DOA;
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input [10:0] ADDRA;
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input [1:0] DIA;
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input ENA;
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(* clkbuf_sink *)
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input CLKA;
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input WEA;
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input RSTA;
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output [1:0] DOB;
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input [10:0] ADDRB;
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input [1:0] DIB;
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input ENB;
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(* clkbuf_sink *)
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input CLKB;
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input WEB;
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input RSTB;
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endmodule
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module RAMB4_S2_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [1:0] DOA;
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input [10:0] ADDRA;
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input [1:0] DIA;
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input ENA;
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(* clkbuf_sink *)
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input CLKA;
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input WEA;
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input RSTA;
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output [3:0] DOB;
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input [9:0] ADDRB;
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input [3:0] DIB;
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input ENB;
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(* clkbuf_sink *)
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input CLKB;
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input WEB;
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input RSTB;
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endmodule
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module RAMB4_S2_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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output [1:0] DOA;
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input [10:0] ADDRA;
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input [1:0] DIA;
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input ENA;
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(* clkbuf_sink *)
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input CLKA;
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input WEA;
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input RSTA;
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output [7:0] DOB;
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input [8:0] ADDRB;
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input [7:0] DIB;
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input ENB;
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(* clkbuf_sink *)
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input CLKB;
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input WEB;
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input RSTB;
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endmodule
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module RAMB4_S2_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
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parameter SIM_COLLISION_CHECK = "ALL";
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parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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output [1:0] DOA;
|
|
input [10:0] ADDRA;
|
|
input [1:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input RSTA;
|
|
output [15:0] DOB;
|
|
input [7:0] ADDRB;
|
|
input [15:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input RSTB;
|
|
endmodule
|
|
|
|
module RAMB4_S4_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [3:0] DOA;
|
|
input [9:0] ADDRA;
|
|
input [3:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input RSTA;
|
|
output [3:0] DOB;
|
|
input [9:0] ADDRB;
|
|
input [3:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input RSTB;
|
|
endmodule
|
|
|
|
module RAMB4_S4_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [3:0] DOA;
|
|
input [9:0] ADDRA;
|
|
input [3:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input RSTA;
|
|
output [7:0] DOB;
|
|
input [8:0] ADDRB;
|
|
input [7:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input RSTB;
|
|
endmodule
|
|
|
|
module RAMB4_S4_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [3:0] DOA;
|
|
input [9:0] ADDRA;
|
|
input [3:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input RSTA;
|
|
output [15:0] DOB;
|
|
input [7:0] ADDRB;
|
|
input [15:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input RSTB;
|
|
endmodule
|
|
|
|
module RAMB4_S8_S8(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [7:0] DOA;
|
|
input [8:0] ADDRA;
|
|
input [7:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input RSTA;
|
|
output [7:0] DOB;
|
|
input [8:0] ADDRB;
|
|
input [7:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input RSTB;
|
|
endmodule
|
|
|
|
module RAMB4_S8_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [7:0] DOA;
|
|
input [8:0] ADDRA;
|
|
input [7:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input RSTA;
|
|
output [15:0] DOB;
|
|
input [7:0] ADDRB;
|
|
input [15:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input RSTB;
|
|
endmodule
|
|
|
|
module RAMB4_S16_S16(DOA, ADDRA, DIA, ENA, CLKA, WEA, RSTA, DOB, ADDRB, DIB, ENB, CLKB, WEB, RSTB);
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [15:0] DOA;
|
|
input [7:0] ADDRA;
|
|
input [15:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input RSTA;
|
|
output [15:0] DOB;
|
|
input [7:0] ADDRB;
|
|
input [15:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input RSTB;
|
|
endmodule
|
|
|
|
module RAMB16_S1(DO, ADDR, DI, EN, CLK, WE, SSR);
|
|
parameter [0:0] INIT = 1'h0;
|
|
parameter [0:0] SRVAL = 1'h0;
|
|
parameter WRITE_MODE = "WRITE_FIRST";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [0:0] DO;
|
|
input [13:0] ADDR;
|
|
input [0:0] DI;
|
|
input EN;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input WE;
|
|
input SSR;
|
|
endmodule
|
|
|
|
module RAMB16_S2(DO, ADDR, DI, EN, CLK, WE, SSR);
|
|
parameter [1:0] INIT = 2'h0;
|
|
parameter [1:0] SRVAL = 2'h0;
|
|
parameter WRITE_MODE = "WRITE_FIRST";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [1:0] DO;
|
|
input [12:0] ADDR;
|
|
input [1:0] DI;
|
|
input EN;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input WE;
|
|
input SSR;
|
|
endmodule
|
|
|
|
module RAMB16_S4(DO, ADDR, DI, EN, CLK, WE, SSR);
|
|
parameter [3:0] INIT = 4'h0;
|
|
parameter [3:0] SRVAL = 4'h0;
|
|
parameter WRITE_MODE = "WRITE_FIRST";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [3:0] DO;
|
|
input [11:0] ADDR;
|
|
input [3:0] DI;
|
|
input EN;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input WE;
|
|
input SSR;
|
|
endmodule
|
|
|
|
module RAMB16_S9(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR);
|
|
parameter [8:0] INIT = 9'h0;
|
|
parameter [8:0] SRVAL = 9'h0;
|
|
parameter WRITE_MODE = "WRITE_FIRST";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [7:0] DO;
|
|
output [0:0] DOP;
|
|
input [10:0] ADDR;
|
|
input [7:0] DI;
|
|
input [0:0] DIP;
|
|
input EN;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input WE;
|
|
input SSR;
|
|
endmodule
|
|
|
|
module RAMB16_S18(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR);
|
|
parameter [17:0] INIT = 18'h0;
|
|
parameter [17:0] SRVAL = 18'h0;
|
|
parameter WRITE_MODE = "WRITE_FIRST";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [15:0] DO;
|
|
output [1:0] DOP;
|
|
input [9:0] ADDR;
|
|
input [15:0] DI;
|
|
input [1:0] DIP;
|
|
input EN;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input WE;
|
|
input SSR;
|
|
endmodule
|
|
|
|
module RAMB16_S36(DO, DOP, ADDR, DI, DIP, EN, CLK, WE, SSR);
|
|
parameter [35:0] INIT = 36'h0;
|
|
parameter [35:0] SRVAL = 36'h0;
|
|
parameter WRITE_MODE = "WRITE_FIRST";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [31:0] DO;
|
|
output [3:0] DOP;
|
|
input [8:0] ADDR;
|
|
input [31:0] DI;
|
|
input [3:0] DIP;
|
|
input EN;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input WE;
|
|
input SSR;
|
|
endmodule
|
|
|
|
module RAMB16_S1_S1(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB);
|
|
parameter [0:0] INIT_A = 1'h0;
|
|
parameter [0:0] INIT_B = 1'h0;
|
|
parameter [0:0] SRVAL_A = 1'h0;
|
|
parameter [0:0] SRVAL_B = 1'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [0:0] DOA;
|
|
input [13:0] ADDRA;
|
|
input [0:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [0:0] DOB;
|
|
input [13:0] ADDRB;
|
|
input [0:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S1_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB);
|
|
parameter [0:0] INIT_A = 1'h0;
|
|
parameter [1:0] INIT_B = 2'h0;
|
|
parameter [0:0] SRVAL_A = 1'h0;
|
|
parameter [1:0] SRVAL_B = 2'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [0:0] DOA;
|
|
input [13:0] ADDRA;
|
|
input [0:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [1:0] DOB;
|
|
input [12:0] ADDRB;
|
|
input [1:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S1_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB);
|
|
parameter [0:0] INIT_A = 1'h0;
|
|
parameter [3:0] INIT_B = 4'h0;
|
|
parameter [0:0] SRVAL_A = 1'h0;
|
|
parameter [3:0] SRVAL_B = 4'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [0:0] DOA;
|
|
input [13:0] ADDRA;
|
|
input [0:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [3:0] DOB;
|
|
input [11:0] ADDRB;
|
|
input [3:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S1_S9(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [0:0] INIT_A = 1'h0;
|
|
parameter [8:0] INIT_B = 9'h0;
|
|
parameter [0:0] SRVAL_A = 1'h0;
|
|
parameter [8:0] SRVAL_B = 9'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [0:0] DOA;
|
|
input [13:0] ADDRA;
|
|
input [0:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [7:0] DOB;
|
|
output [0:0] DOPB;
|
|
input [10:0] ADDRB;
|
|
input [7:0] DIB;
|
|
input [0:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S1_S18(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [0:0] INIT_A = 1'h0;
|
|
parameter [17:0] INIT_B = 18'h0;
|
|
parameter [0:0] SRVAL_A = 1'h0;
|
|
parameter [17:0] SRVAL_B = 18'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [0:0] DOA;
|
|
input [13:0] ADDRA;
|
|
input [0:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [15:0] DOB;
|
|
output [1:0] DOPB;
|
|
input [9:0] ADDRB;
|
|
input [15:0] DIB;
|
|
input [1:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S1_S36(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [0:0] INIT_A = 1'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter [0:0] SRVAL_A = 1'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [0:0] DOA;
|
|
input [13:0] ADDRA;
|
|
input [0:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPB;
|
|
input [8:0] ADDRB;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S2_S2(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB);
|
|
parameter [1:0] INIT_A = 2'h0;
|
|
parameter [1:0] INIT_B = 2'h0;
|
|
parameter [1:0] SRVAL_A = 2'h0;
|
|
parameter [1:0] SRVAL_B = 2'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [1:0] DOA;
|
|
input [12:0] ADDRA;
|
|
input [1:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [1:0] DOB;
|
|
input [12:0] ADDRB;
|
|
input [1:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S2_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB);
|
|
parameter [1:0] INIT_A = 2'h0;
|
|
parameter [3:0] INIT_B = 4'h0;
|
|
parameter [1:0] SRVAL_A = 2'h0;
|
|
parameter [3:0] SRVAL_B = 4'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [1:0] DOA;
|
|
input [12:0] ADDRA;
|
|
input [1:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [3:0] DOB;
|
|
input [11:0] ADDRB;
|
|
input [3:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S2_S9(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [1:0] INIT_A = 2'h0;
|
|
parameter [8:0] INIT_B = 9'h0;
|
|
parameter [1:0] SRVAL_A = 2'h0;
|
|
parameter [8:0] SRVAL_B = 9'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [1:0] DOA;
|
|
input [12:0] ADDRA;
|
|
input [1:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [7:0] DOB;
|
|
output [0:0] DOPB;
|
|
input [10:0] ADDRB;
|
|
input [7:0] DIB;
|
|
input [0:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S2_S18(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [1:0] INIT_A = 2'h0;
|
|
parameter [17:0] INIT_B = 18'h0;
|
|
parameter [1:0] SRVAL_A = 2'h0;
|
|
parameter [17:0] SRVAL_B = 18'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [1:0] DOA;
|
|
input [12:0] ADDRA;
|
|
input [1:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [15:0] DOB;
|
|
output [1:0] DOPB;
|
|
input [9:0] ADDRB;
|
|
input [15:0] DIB;
|
|
input [1:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S2_S36(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [1:0] INIT_A = 2'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter [1:0] SRVAL_A = 2'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [1:0] DOA;
|
|
input [12:0] ADDRA;
|
|
input [1:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPB;
|
|
input [8:0] ADDRB;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S4_S4(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, ADDRB, DIB, ENB, CLKB, WEB, SSRB);
|
|
parameter [3:0] INIT_A = 4'h0;
|
|
parameter [3:0] INIT_B = 4'h0;
|
|
parameter [3:0] SRVAL_A = 4'h0;
|
|
parameter [3:0] SRVAL_B = 4'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [3:0] DOA;
|
|
input [11:0] ADDRA;
|
|
input [3:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [3:0] DOB;
|
|
input [11:0] ADDRB;
|
|
input [3:0] DIB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S4_S9(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [3:0] INIT_A = 4'h0;
|
|
parameter [8:0] INIT_B = 9'h0;
|
|
parameter [3:0] SRVAL_A = 4'h0;
|
|
parameter [8:0] SRVAL_B = 9'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [3:0] DOA;
|
|
input [11:0] ADDRA;
|
|
input [3:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [7:0] DOB;
|
|
output [0:0] DOPB;
|
|
input [10:0] ADDRB;
|
|
input [7:0] DIB;
|
|
input [0:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S4_S18(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [3:0] INIT_A = 4'h0;
|
|
parameter [17:0] INIT_B = 18'h0;
|
|
parameter [3:0] SRVAL_A = 4'h0;
|
|
parameter [17:0] SRVAL_B = 18'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [3:0] DOA;
|
|
input [11:0] ADDRA;
|
|
input [3:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [15:0] DOB;
|
|
output [1:0] DOPB;
|
|
input [9:0] ADDRB;
|
|
input [15:0] DIB;
|
|
input [1:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S4_S36(DOA, ADDRA, DIA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [3:0] INIT_A = 4'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter [3:0] SRVAL_A = 4'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [3:0] DOA;
|
|
input [11:0] ADDRA;
|
|
input [3:0] DIA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPB;
|
|
input [8:0] ADDRB;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S9_S9(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [8:0] INIT_A = 9'h0;
|
|
parameter [8:0] INIT_B = 9'h0;
|
|
parameter [8:0] SRVAL_A = 9'h0;
|
|
parameter [8:0] SRVAL_B = 9'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [7:0] DOA;
|
|
output [0:0] DOPA;
|
|
input [10:0] ADDRA;
|
|
input [7:0] DIA;
|
|
input [0:0] DIPA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [7:0] DOB;
|
|
output [0:0] DOPB;
|
|
input [10:0] ADDRB;
|
|
input [7:0] DIB;
|
|
input [0:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S9_S18(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [8:0] INIT_A = 9'h0;
|
|
parameter [17:0] INIT_B = 18'h0;
|
|
parameter [8:0] SRVAL_A = 9'h0;
|
|
parameter [17:0] SRVAL_B = 18'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [7:0] DOA;
|
|
output [0:0] DOPA;
|
|
input [10:0] ADDRA;
|
|
input [7:0] DIA;
|
|
input [0:0] DIPA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [15:0] DOB;
|
|
output [1:0] DOPB;
|
|
input [9:0] ADDRB;
|
|
input [15:0] DIB;
|
|
input [1:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S9_S36(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [8:0] INIT_A = 9'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter [8:0] SRVAL_A = 9'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [7:0] DOA;
|
|
output [0:0] DOPA;
|
|
input [10:0] ADDRA;
|
|
input [7:0] DIA;
|
|
input [0:0] DIPA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPB;
|
|
input [8:0] ADDRB;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S18_S18(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [17:0] INIT_A = 18'h0;
|
|
parameter [17:0] INIT_B = 18'h0;
|
|
parameter [17:0] SRVAL_A = 18'h0;
|
|
parameter [17:0] SRVAL_B = 18'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [15:0] DOA;
|
|
output [1:0] DOPA;
|
|
input [9:0] ADDRA;
|
|
input [15:0] DIA;
|
|
input [1:0] DIPA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [15:0] DOB;
|
|
output [1:0] DOPB;
|
|
input [9:0] ADDRB;
|
|
input [15:0] DIB;
|
|
input [1:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S18_S36(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [17:0] INIT_A = 18'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter [17:0] SRVAL_A = 18'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [15:0] DOA;
|
|
output [1:0] DOPA;
|
|
input [9:0] ADDRA;
|
|
input [15:0] DIA;
|
|
input [1:0] DIPA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPB;
|
|
input [8:0] ADDRB;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16_S36_S36(DOA, DOPA, ADDRA, DIA, DIPA, ENA, CLKA, WEA, SSRA, DOB, DOPB, ADDRB, DIB, DIPB, ENB, CLKB, WEB, SSRB);
|
|
parameter [35:0] INIT_A = 36'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter [35:0] SRVAL_A = 36'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
output [31:0] DOA;
|
|
output [3:0] DOPA;
|
|
input [8:0] ADDRA;
|
|
input [31:0] DIA;
|
|
input [3:0] DIPA;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input WEA;
|
|
input SSRA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPB;
|
|
input [8:0] ADDRB;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPB;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input WEB;
|
|
input SSRB;
|
|
endmodule
|
|
|
|
module RAMB16BWE_S18(DO, DOP, CLK, EN, SSR, WE, DI, DIP, ADDR);
|
|
parameter [17:0] INIT = 18'h0;
|
|
parameter [255:0] INITP_00 = 256'h0;
|
|
parameter [255:0] INITP_01 = 256'h0;
|
|
parameter [255:0] INITP_02 = 256'h0;
|
|
parameter [255:0] INITP_03 = 256'h0;
|
|
parameter [255:0] INITP_04 = 256'h0;
|
|
parameter [255:0] INITP_05 = 256'h0;
|
|
parameter [255:0] INITP_06 = 256'h0;
|
|
parameter [255:0] INITP_07 = 256'h0;
|
|
parameter [255:0] INIT_00 = 256'h0;
|
|
parameter [255:0] INIT_01 = 256'h0;
|
|
parameter [255:0] INIT_02 = 256'h0;
|
|
parameter [255:0] INIT_03 = 256'h0;
|
|
parameter [255:0] INIT_04 = 256'h0;
|
|
parameter [255:0] INIT_05 = 256'h0;
|
|
parameter [255:0] INIT_06 = 256'h0;
|
|
parameter [255:0] INIT_07 = 256'h0;
|
|
parameter [255:0] INIT_08 = 256'h0;
|
|
parameter [255:0] INIT_09 = 256'h0;
|
|
parameter [255:0] INIT_0A = 256'h0;
|
|
parameter [255:0] INIT_0B = 256'h0;
|
|
parameter [255:0] INIT_0C = 256'h0;
|
|
parameter [255:0] INIT_0D = 256'h0;
|
|
parameter [255:0] INIT_0E = 256'h0;
|
|
parameter [255:0] INIT_0F = 256'h0;
|
|
parameter [255:0] INIT_10 = 256'h0;
|
|
parameter [255:0] INIT_11 = 256'h0;
|
|
parameter [255:0] INIT_12 = 256'h0;
|
|
parameter [255:0] INIT_13 = 256'h0;
|
|
parameter [255:0] INIT_14 = 256'h0;
|
|
parameter [255:0] INIT_15 = 256'h0;
|
|
parameter [255:0] INIT_16 = 256'h0;
|
|
parameter [255:0] INIT_17 = 256'h0;
|
|
parameter [255:0] INIT_18 = 256'h0;
|
|
parameter [255:0] INIT_19 = 256'h0;
|
|
parameter [255:0] INIT_1A = 256'h0;
|
|
parameter [255:0] INIT_1B = 256'h0;
|
|
parameter [255:0] INIT_1C = 256'h0;
|
|
parameter [255:0] INIT_1D = 256'h0;
|
|
parameter [255:0] INIT_1E = 256'h0;
|
|
parameter [255:0] INIT_1F = 256'h0;
|
|
parameter [255:0] INIT_20 = 256'h0;
|
|
parameter [255:0] INIT_21 = 256'h0;
|
|
parameter [255:0] INIT_22 = 256'h0;
|
|
parameter [255:0] INIT_23 = 256'h0;
|
|
parameter [255:0] INIT_24 = 256'h0;
|
|
parameter [255:0] INIT_25 = 256'h0;
|
|
parameter [255:0] INIT_26 = 256'h0;
|
|
parameter [255:0] INIT_27 = 256'h0;
|
|
parameter [255:0] INIT_28 = 256'h0;
|
|
parameter [255:0] INIT_29 = 256'h0;
|
|
parameter [255:0] INIT_2A = 256'h0;
|
|
parameter [255:0] INIT_2B = 256'h0;
|
|
parameter [255:0] INIT_2C = 256'h0;
|
|
parameter [255:0] INIT_2D = 256'h0;
|
|
parameter [255:0] INIT_2E = 256'h0;
|
|
parameter [255:0] INIT_2F = 256'h0;
|
|
parameter [255:0] INIT_30 = 256'h0;
|
|
parameter [255:0] INIT_31 = 256'h0;
|
|
parameter [255:0] INIT_32 = 256'h0;
|
|
parameter [255:0] INIT_33 = 256'h0;
|
|
parameter [255:0] INIT_34 = 256'h0;
|
|
parameter [255:0] INIT_35 = 256'h0;
|
|
parameter [255:0] INIT_36 = 256'h0;
|
|
parameter [255:0] INIT_37 = 256'h0;
|
|
parameter [255:0] INIT_38 = 256'h0;
|
|
parameter [255:0] INIT_39 = 256'h0;
|
|
parameter [255:0] INIT_3A = 256'h0;
|
|
parameter [255:0] INIT_3B = 256'h0;
|
|
parameter [255:0] INIT_3C = 256'h0;
|
|
parameter [255:0] INIT_3D = 256'h0;
|
|
parameter [255:0] INIT_3E = 256'h0;
|
|
parameter [255:0] INIT_3F = 256'h0;
|
|
parameter [17:0] SRVAL = 18'h0;
|
|
parameter WRITE_MODE = "WRITE_FIRST";
|
|
output [15:0] DO;
|
|
output [1:0] DOP;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input EN;
|
|
input SSR;
|
|
input [1:0] WE;
|
|
input [15:0] DI;
|
|
input [1:0] DIP;
|
|
input [9:0] ADDR;
|
|
endmodule
|
|
|
|
module RAMB16BWE_S36(DO, DOP, CLK, EN, SSR, WE, DI, DIP, ADDR);
|
|
parameter [35:0] INIT = 36'h0;
|
|
parameter [255:0] INITP_00 = 256'h0;
|
|
parameter [255:0] INITP_01 = 256'h0;
|
|
parameter [255:0] INITP_02 = 256'h0;
|
|
parameter [255:0] INITP_03 = 256'h0;
|
|
parameter [255:0] INITP_04 = 256'h0;
|
|
parameter [255:0] INITP_05 = 256'h0;
|
|
parameter [255:0] INITP_06 = 256'h0;
|
|
parameter [255:0] INITP_07 = 256'h0;
|
|
parameter [255:0] INIT_00 = 256'h0;
|
|
parameter [255:0] INIT_01 = 256'h0;
|
|
parameter [255:0] INIT_02 = 256'h0;
|
|
parameter [255:0] INIT_03 = 256'h0;
|
|
parameter [255:0] INIT_04 = 256'h0;
|
|
parameter [255:0] INIT_05 = 256'h0;
|
|
parameter [255:0] INIT_06 = 256'h0;
|
|
parameter [255:0] INIT_07 = 256'h0;
|
|
parameter [255:0] INIT_08 = 256'h0;
|
|
parameter [255:0] INIT_09 = 256'h0;
|
|
parameter [255:0] INIT_0A = 256'h0;
|
|
parameter [255:0] INIT_0B = 256'h0;
|
|
parameter [255:0] INIT_0C = 256'h0;
|
|
parameter [255:0] INIT_0D = 256'h0;
|
|
parameter [255:0] INIT_0E = 256'h0;
|
|
parameter [255:0] INIT_0F = 256'h0;
|
|
parameter [255:0] INIT_10 = 256'h0;
|
|
parameter [255:0] INIT_11 = 256'h0;
|
|
parameter [255:0] INIT_12 = 256'h0;
|
|
parameter [255:0] INIT_13 = 256'h0;
|
|
parameter [255:0] INIT_14 = 256'h0;
|
|
parameter [255:0] INIT_15 = 256'h0;
|
|
parameter [255:0] INIT_16 = 256'h0;
|
|
parameter [255:0] INIT_17 = 256'h0;
|
|
parameter [255:0] INIT_18 = 256'h0;
|
|
parameter [255:0] INIT_19 = 256'h0;
|
|
parameter [255:0] INIT_1A = 256'h0;
|
|
parameter [255:0] INIT_1B = 256'h0;
|
|
parameter [255:0] INIT_1C = 256'h0;
|
|
parameter [255:0] INIT_1D = 256'h0;
|
|
parameter [255:0] INIT_1E = 256'h0;
|
|
parameter [255:0] INIT_1F = 256'h0;
|
|
parameter [255:0] INIT_20 = 256'h0;
|
|
parameter [255:0] INIT_21 = 256'h0;
|
|
parameter [255:0] INIT_22 = 256'h0;
|
|
parameter [255:0] INIT_23 = 256'h0;
|
|
parameter [255:0] INIT_24 = 256'h0;
|
|
parameter [255:0] INIT_25 = 256'h0;
|
|
parameter [255:0] INIT_26 = 256'h0;
|
|
parameter [255:0] INIT_27 = 256'h0;
|
|
parameter [255:0] INIT_28 = 256'h0;
|
|
parameter [255:0] INIT_29 = 256'h0;
|
|
parameter [255:0] INIT_2A = 256'h0;
|
|
parameter [255:0] INIT_2B = 256'h0;
|
|
parameter [255:0] INIT_2C = 256'h0;
|
|
parameter [255:0] INIT_2D = 256'h0;
|
|
parameter [255:0] INIT_2E = 256'h0;
|
|
parameter [255:0] INIT_2F = 256'h0;
|
|
parameter [255:0] INIT_30 = 256'h0;
|
|
parameter [255:0] INIT_31 = 256'h0;
|
|
parameter [255:0] INIT_32 = 256'h0;
|
|
parameter [255:0] INIT_33 = 256'h0;
|
|
parameter [255:0] INIT_34 = 256'h0;
|
|
parameter [255:0] INIT_35 = 256'h0;
|
|
parameter [255:0] INIT_36 = 256'h0;
|
|
parameter [255:0] INIT_37 = 256'h0;
|
|
parameter [255:0] INIT_38 = 256'h0;
|
|
parameter [255:0] INIT_39 = 256'h0;
|
|
parameter [255:0] INIT_3A = 256'h0;
|
|
parameter [255:0] INIT_3B = 256'h0;
|
|
parameter [255:0] INIT_3C = 256'h0;
|
|
parameter [255:0] INIT_3D = 256'h0;
|
|
parameter [255:0] INIT_3E = 256'h0;
|
|
parameter [255:0] INIT_3F = 256'h0;
|
|
parameter [35:0] SRVAL = 36'h0;
|
|
parameter WRITE_MODE = "WRITE_FIRST";
|
|
output [31:0] DO;
|
|
output [3:0] DOP;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input EN;
|
|
input SSR;
|
|
input [3:0] WE;
|
|
input [31:0] DI;
|
|
input [3:0] DIP;
|
|
input [8:0] ADDR;
|
|
endmodule
|
|
|
|
module RAMB16BWE_S18_S9(DOA, DOB, DOPA, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEB, WEA, DIA, DIB, DIPA, DIPB, ADDRA, ADDRB);
|
|
parameter [255:0] INITP_00 = 256'h0;
|
|
parameter [255:0] INITP_01 = 256'h0;
|
|
parameter [255:0] INITP_02 = 256'h0;
|
|
parameter [255:0] INITP_03 = 256'h0;
|
|
parameter [255:0] INITP_04 = 256'h0;
|
|
parameter [255:0] INITP_05 = 256'h0;
|
|
parameter [255:0] INITP_06 = 256'h0;
|
|
parameter [255:0] INITP_07 = 256'h0;
|
|
parameter [255:0] INIT_00 = 256'h0;
|
|
parameter [255:0] INIT_01 = 256'h0;
|
|
parameter [255:0] INIT_02 = 256'h0;
|
|
parameter [255:0] INIT_03 = 256'h0;
|
|
parameter [255:0] INIT_04 = 256'h0;
|
|
parameter [255:0] INIT_05 = 256'h0;
|
|
parameter [255:0] INIT_06 = 256'h0;
|
|
parameter [255:0] INIT_07 = 256'h0;
|
|
parameter [255:0] INIT_08 = 256'h0;
|
|
parameter [255:0] INIT_09 = 256'h0;
|
|
parameter [255:0] INIT_0A = 256'h0;
|
|
parameter [255:0] INIT_0B = 256'h0;
|
|
parameter [255:0] INIT_0C = 256'h0;
|
|
parameter [255:0] INIT_0D = 256'h0;
|
|
parameter [255:0] INIT_0E = 256'h0;
|
|
parameter [255:0] INIT_0F = 256'h0;
|
|
parameter [255:0] INIT_10 = 256'h0;
|
|
parameter [255:0] INIT_11 = 256'h0;
|
|
parameter [255:0] INIT_12 = 256'h0;
|
|
parameter [255:0] INIT_13 = 256'h0;
|
|
parameter [255:0] INIT_14 = 256'h0;
|
|
parameter [255:0] INIT_15 = 256'h0;
|
|
parameter [255:0] INIT_16 = 256'h0;
|
|
parameter [255:0] INIT_17 = 256'h0;
|
|
parameter [255:0] INIT_18 = 256'h0;
|
|
parameter [255:0] INIT_19 = 256'h0;
|
|
parameter [255:0] INIT_1A = 256'h0;
|
|
parameter [255:0] INIT_1B = 256'h0;
|
|
parameter [255:0] INIT_1C = 256'h0;
|
|
parameter [255:0] INIT_1D = 256'h0;
|
|
parameter [255:0] INIT_1E = 256'h0;
|
|
parameter [255:0] INIT_1F = 256'h0;
|
|
parameter [255:0] INIT_20 = 256'h0;
|
|
parameter [255:0] INIT_21 = 256'h0;
|
|
parameter [255:0] INIT_22 = 256'h0;
|
|
parameter [255:0] INIT_23 = 256'h0;
|
|
parameter [255:0] INIT_24 = 256'h0;
|
|
parameter [255:0] INIT_25 = 256'h0;
|
|
parameter [255:0] INIT_26 = 256'h0;
|
|
parameter [255:0] INIT_27 = 256'h0;
|
|
parameter [255:0] INIT_28 = 256'h0;
|
|
parameter [255:0] INIT_29 = 256'h0;
|
|
parameter [255:0] INIT_2A = 256'h0;
|
|
parameter [255:0] INIT_2B = 256'h0;
|
|
parameter [255:0] INIT_2C = 256'h0;
|
|
parameter [255:0] INIT_2D = 256'h0;
|
|
parameter [255:0] INIT_2E = 256'h0;
|
|
parameter [255:0] INIT_2F = 256'h0;
|
|
parameter [255:0] INIT_30 = 256'h0;
|
|
parameter [255:0] INIT_31 = 256'h0;
|
|
parameter [255:0] INIT_32 = 256'h0;
|
|
parameter [255:0] INIT_33 = 256'h0;
|
|
parameter [255:0] INIT_34 = 256'h0;
|
|
parameter [255:0] INIT_35 = 256'h0;
|
|
parameter [255:0] INIT_36 = 256'h0;
|
|
parameter [255:0] INIT_37 = 256'h0;
|
|
parameter [255:0] INIT_38 = 256'h0;
|
|
parameter [255:0] INIT_39 = 256'h0;
|
|
parameter [255:0] INIT_3A = 256'h0;
|
|
parameter [255:0] INIT_3B = 256'h0;
|
|
parameter [255:0] INIT_3C = 256'h0;
|
|
parameter [255:0] INIT_3D = 256'h0;
|
|
parameter [255:0] INIT_3E = 256'h0;
|
|
parameter [255:0] INIT_3F = 256'h0;
|
|
parameter [17:0] INIT_A = 18'h0;
|
|
parameter [8:0] INIT_B = 9'h0;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [17:0] SRVAL_A = 18'h0;
|
|
parameter [8:0] SRVAL_B = 9'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
output [15:0] DOA;
|
|
output [7:0] DOB;
|
|
output [1:0] DOPA;
|
|
output [0:0] DOPB;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input ENA;
|
|
input ENB;
|
|
input SSRA;
|
|
input SSRB;
|
|
input WEB;
|
|
input [1:0] WEA;
|
|
input [15:0] DIA;
|
|
input [7:0] DIB;
|
|
input [1:0] DIPA;
|
|
input [0:0] DIPB;
|
|
input [9:0] ADDRA;
|
|
input [10:0] ADDRB;
|
|
endmodule
|
|
|
|
module RAMB16BWE_S18_S18(DOA, DOB, DOPA, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEB, WEA, DIA, DIB, DIPA, DIPB, ADDRA, ADDRB);
|
|
parameter [255:0] INITP_00 = 256'h0;
|
|
parameter [255:0] INITP_01 = 256'h0;
|
|
parameter [255:0] INITP_02 = 256'h0;
|
|
parameter [255:0] INITP_03 = 256'h0;
|
|
parameter [255:0] INITP_04 = 256'h0;
|
|
parameter [255:0] INITP_05 = 256'h0;
|
|
parameter [255:0] INITP_06 = 256'h0;
|
|
parameter [255:0] INITP_07 = 256'h0;
|
|
parameter [255:0] INIT_00 = 256'h0;
|
|
parameter [255:0] INIT_01 = 256'h0;
|
|
parameter [255:0] INIT_02 = 256'h0;
|
|
parameter [255:0] INIT_03 = 256'h0;
|
|
parameter [255:0] INIT_04 = 256'h0;
|
|
parameter [255:0] INIT_05 = 256'h0;
|
|
parameter [255:0] INIT_06 = 256'h0;
|
|
parameter [255:0] INIT_07 = 256'h0;
|
|
parameter [255:0] INIT_08 = 256'h0;
|
|
parameter [255:0] INIT_09 = 256'h0;
|
|
parameter [255:0] INIT_0A = 256'h0;
|
|
parameter [255:0] INIT_0B = 256'h0;
|
|
parameter [255:0] INIT_0C = 256'h0;
|
|
parameter [255:0] INIT_0D = 256'h0;
|
|
parameter [255:0] INIT_0E = 256'h0;
|
|
parameter [255:0] INIT_0F = 256'h0;
|
|
parameter [255:0] INIT_10 = 256'h0;
|
|
parameter [255:0] INIT_11 = 256'h0;
|
|
parameter [255:0] INIT_12 = 256'h0;
|
|
parameter [255:0] INIT_13 = 256'h0;
|
|
parameter [255:0] INIT_14 = 256'h0;
|
|
parameter [255:0] INIT_15 = 256'h0;
|
|
parameter [255:0] INIT_16 = 256'h0;
|
|
parameter [255:0] INIT_17 = 256'h0;
|
|
parameter [255:0] INIT_18 = 256'h0;
|
|
parameter [255:0] INIT_19 = 256'h0;
|
|
parameter [255:0] INIT_1A = 256'h0;
|
|
parameter [255:0] INIT_1B = 256'h0;
|
|
parameter [255:0] INIT_1C = 256'h0;
|
|
parameter [255:0] INIT_1D = 256'h0;
|
|
parameter [255:0] INIT_1E = 256'h0;
|
|
parameter [255:0] INIT_1F = 256'h0;
|
|
parameter [255:0] INIT_20 = 256'h0;
|
|
parameter [255:0] INIT_21 = 256'h0;
|
|
parameter [255:0] INIT_22 = 256'h0;
|
|
parameter [255:0] INIT_23 = 256'h0;
|
|
parameter [255:0] INIT_24 = 256'h0;
|
|
parameter [255:0] INIT_25 = 256'h0;
|
|
parameter [255:0] INIT_26 = 256'h0;
|
|
parameter [255:0] INIT_27 = 256'h0;
|
|
parameter [255:0] INIT_28 = 256'h0;
|
|
parameter [255:0] INIT_29 = 256'h0;
|
|
parameter [255:0] INIT_2A = 256'h0;
|
|
parameter [255:0] INIT_2B = 256'h0;
|
|
parameter [255:0] INIT_2C = 256'h0;
|
|
parameter [255:0] INIT_2D = 256'h0;
|
|
parameter [255:0] INIT_2E = 256'h0;
|
|
parameter [255:0] INIT_2F = 256'h0;
|
|
parameter [255:0] INIT_30 = 256'h0;
|
|
parameter [255:0] INIT_31 = 256'h0;
|
|
parameter [255:0] INIT_32 = 256'h0;
|
|
parameter [255:0] INIT_33 = 256'h0;
|
|
parameter [255:0] INIT_34 = 256'h0;
|
|
parameter [255:0] INIT_35 = 256'h0;
|
|
parameter [255:0] INIT_36 = 256'h0;
|
|
parameter [255:0] INIT_37 = 256'h0;
|
|
parameter [255:0] INIT_38 = 256'h0;
|
|
parameter [255:0] INIT_39 = 256'h0;
|
|
parameter [255:0] INIT_3A = 256'h0;
|
|
parameter [255:0] INIT_3B = 256'h0;
|
|
parameter [255:0] INIT_3C = 256'h0;
|
|
parameter [255:0] INIT_3D = 256'h0;
|
|
parameter [255:0] INIT_3E = 256'h0;
|
|
parameter [255:0] INIT_3F = 256'h0;
|
|
parameter [17:0] INIT_A = 18'h0;
|
|
parameter [17:0] INIT_B = 18'h0;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [17:0] SRVAL_A = 18'h0;
|
|
parameter [17:0] SRVAL_B = 18'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
output [15:0] DOA;
|
|
output [15:0] DOB;
|
|
output [1:0] DOPA;
|
|
output [1:0] DOPB;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input ENA;
|
|
input ENB;
|
|
input SSRA;
|
|
input SSRB;
|
|
input [1:0] WEB;
|
|
input [1:0] WEA;
|
|
input [15:0] DIA;
|
|
input [15:0] DIB;
|
|
input [1:0] DIPA;
|
|
input [1:0] DIPB;
|
|
input [9:0] ADDRA;
|
|
input [9:0] ADDRB;
|
|
endmodule
|
|
|
|
module RAMB16BWE_S36_S9(DOA, DOPA, DOB, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEA, WEB, DIA, DIPA, DIB, DIPB, ADDRA, ADDRB);
|
|
parameter [255:0] INITP_00 = 256'h0;
|
|
parameter [255:0] INITP_01 = 256'h0;
|
|
parameter [255:0] INITP_02 = 256'h0;
|
|
parameter [255:0] INITP_03 = 256'h0;
|
|
parameter [255:0] INITP_04 = 256'h0;
|
|
parameter [255:0] INITP_05 = 256'h0;
|
|
parameter [255:0] INITP_06 = 256'h0;
|
|
parameter [255:0] INITP_07 = 256'h0;
|
|
parameter [255:0] INIT_00 = 256'h0;
|
|
parameter [255:0] INIT_01 = 256'h0;
|
|
parameter [255:0] INIT_02 = 256'h0;
|
|
parameter [255:0] INIT_03 = 256'h0;
|
|
parameter [255:0] INIT_04 = 256'h0;
|
|
parameter [255:0] INIT_05 = 256'h0;
|
|
parameter [255:0] INIT_06 = 256'h0;
|
|
parameter [255:0] INIT_07 = 256'h0;
|
|
parameter [255:0] INIT_08 = 256'h0;
|
|
parameter [255:0] INIT_09 = 256'h0;
|
|
parameter [255:0] INIT_0A = 256'h0;
|
|
parameter [255:0] INIT_0B = 256'h0;
|
|
parameter [255:0] INIT_0C = 256'h0;
|
|
parameter [255:0] INIT_0D = 256'h0;
|
|
parameter [255:0] INIT_0E = 256'h0;
|
|
parameter [255:0] INIT_0F = 256'h0;
|
|
parameter [255:0] INIT_10 = 256'h0;
|
|
parameter [255:0] INIT_11 = 256'h0;
|
|
parameter [255:0] INIT_12 = 256'h0;
|
|
parameter [255:0] INIT_13 = 256'h0;
|
|
parameter [255:0] INIT_14 = 256'h0;
|
|
parameter [255:0] INIT_15 = 256'h0;
|
|
parameter [255:0] INIT_16 = 256'h0;
|
|
parameter [255:0] INIT_17 = 256'h0;
|
|
parameter [255:0] INIT_18 = 256'h0;
|
|
parameter [255:0] INIT_19 = 256'h0;
|
|
parameter [255:0] INIT_1A = 256'h0;
|
|
parameter [255:0] INIT_1B = 256'h0;
|
|
parameter [255:0] INIT_1C = 256'h0;
|
|
parameter [255:0] INIT_1D = 256'h0;
|
|
parameter [255:0] INIT_1E = 256'h0;
|
|
parameter [255:0] INIT_1F = 256'h0;
|
|
parameter [255:0] INIT_20 = 256'h0;
|
|
parameter [255:0] INIT_21 = 256'h0;
|
|
parameter [255:0] INIT_22 = 256'h0;
|
|
parameter [255:0] INIT_23 = 256'h0;
|
|
parameter [255:0] INIT_24 = 256'h0;
|
|
parameter [255:0] INIT_25 = 256'h0;
|
|
parameter [255:0] INIT_26 = 256'h0;
|
|
parameter [255:0] INIT_27 = 256'h0;
|
|
parameter [255:0] INIT_28 = 256'h0;
|
|
parameter [255:0] INIT_29 = 256'h0;
|
|
parameter [255:0] INIT_2A = 256'h0;
|
|
parameter [255:0] INIT_2B = 256'h0;
|
|
parameter [255:0] INIT_2C = 256'h0;
|
|
parameter [255:0] INIT_2D = 256'h0;
|
|
parameter [255:0] INIT_2E = 256'h0;
|
|
parameter [255:0] INIT_2F = 256'h0;
|
|
parameter [255:0] INIT_30 = 256'h0;
|
|
parameter [255:0] INIT_31 = 256'h0;
|
|
parameter [255:0] INIT_32 = 256'h0;
|
|
parameter [255:0] INIT_33 = 256'h0;
|
|
parameter [255:0] INIT_34 = 256'h0;
|
|
parameter [255:0] INIT_35 = 256'h0;
|
|
parameter [255:0] INIT_36 = 256'h0;
|
|
parameter [255:0] INIT_37 = 256'h0;
|
|
parameter [255:0] INIT_38 = 256'h0;
|
|
parameter [255:0] INIT_39 = 256'h0;
|
|
parameter [255:0] INIT_3A = 256'h0;
|
|
parameter [255:0] INIT_3B = 256'h0;
|
|
parameter [255:0] INIT_3C = 256'h0;
|
|
parameter [255:0] INIT_3D = 256'h0;
|
|
parameter [255:0] INIT_3E = 256'h0;
|
|
parameter [255:0] INIT_3F = 256'h0;
|
|
parameter [35:0] INIT_A = 36'h0;
|
|
parameter [8:0] INIT_B = 9'h0;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [35:0] SRVAL_A = 36'h0;
|
|
parameter [8:0] SRVAL_B = 9'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
output [31:0] DOA;
|
|
output [3:0] DOPA;
|
|
output [7:0] DOB;
|
|
output [0:0] DOPB;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input ENA;
|
|
input ENB;
|
|
input SSRA;
|
|
input SSRB;
|
|
input [3:0] WEA;
|
|
input WEB;
|
|
input [31:0] DIA;
|
|
input [3:0] DIPA;
|
|
input [7:0] DIB;
|
|
input [0:0] DIPB;
|
|
input [8:0] ADDRA;
|
|
input [10:0] ADDRB;
|
|
endmodule
|
|
|
|
module RAMB16BWE_S36_S18(DOA, DOPA, DOB, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEA, WEB, DIA, DIPA, DIB, DIPB, ADDRA, ADDRB);
|
|
parameter [255:0] INITP_00 = 256'h0;
|
|
parameter [255:0] INITP_01 = 256'h0;
|
|
parameter [255:0] INITP_02 = 256'h0;
|
|
parameter [255:0] INITP_03 = 256'h0;
|
|
parameter [255:0] INITP_04 = 256'h0;
|
|
parameter [255:0] INITP_05 = 256'h0;
|
|
parameter [255:0] INITP_06 = 256'h0;
|
|
parameter [255:0] INITP_07 = 256'h0;
|
|
parameter [255:0] INIT_00 = 256'h0;
|
|
parameter [255:0] INIT_01 = 256'h0;
|
|
parameter [255:0] INIT_02 = 256'h0;
|
|
parameter [255:0] INIT_03 = 256'h0;
|
|
parameter [255:0] INIT_04 = 256'h0;
|
|
parameter [255:0] INIT_05 = 256'h0;
|
|
parameter [255:0] INIT_06 = 256'h0;
|
|
parameter [255:0] INIT_07 = 256'h0;
|
|
parameter [255:0] INIT_08 = 256'h0;
|
|
parameter [255:0] INIT_09 = 256'h0;
|
|
parameter [255:0] INIT_0A = 256'h0;
|
|
parameter [255:0] INIT_0B = 256'h0;
|
|
parameter [255:0] INIT_0C = 256'h0;
|
|
parameter [255:0] INIT_0D = 256'h0;
|
|
parameter [255:0] INIT_0E = 256'h0;
|
|
parameter [255:0] INIT_0F = 256'h0;
|
|
parameter [255:0] INIT_10 = 256'h0;
|
|
parameter [255:0] INIT_11 = 256'h0;
|
|
parameter [255:0] INIT_12 = 256'h0;
|
|
parameter [255:0] INIT_13 = 256'h0;
|
|
parameter [255:0] INIT_14 = 256'h0;
|
|
parameter [255:0] INIT_15 = 256'h0;
|
|
parameter [255:0] INIT_16 = 256'h0;
|
|
parameter [255:0] INIT_17 = 256'h0;
|
|
parameter [255:0] INIT_18 = 256'h0;
|
|
parameter [255:0] INIT_19 = 256'h0;
|
|
parameter [255:0] INIT_1A = 256'h0;
|
|
parameter [255:0] INIT_1B = 256'h0;
|
|
parameter [255:0] INIT_1C = 256'h0;
|
|
parameter [255:0] INIT_1D = 256'h0;
|
|
parameter [255:0] INIT_1E = 256'h0;
|
|
parameter [255:0] INIT_1F = 256'h0;
|
|
parameter [255:0] INIT_20 = 256'h0;
|
|
parameter [255:0] INIT_21 = 256'h0;
|
|
parameter [255:0] INIT_22 = 256'h0;
|
|
parameter [255:0] INIT_23 = 256'h0;
|
|
parameter [255:0] INIT_24 = 256'h0;
|
|
parameter [255:0] INIT_25 = 256'h0;
|
|
parameter [255:0] INIT_26 = 256'h0;
|
|
parameter [255:0] INIT_27 = 256'h0;
|
|
parameter [255:0] INIT_28 = 256'h0;
|
|
parameter [255:0] INIT_29 = 256'h0;
|
|
parameter [255:0] INIT_2A = 256'h0;
|
|
parameter [255:0] INIT_2B = 256'h0;
|
|
parameter [255:0] INIT_2C = 256'h0;
|
|
parameter [255:0] INIT_2D = 256'h0;
|
|
parameter [255:0] INIT_2E = 256'h0;
|
|
parameter [255:0] INIT_2F = 256'h0;
|
|
parameter [255:0] INIT_30 = 256'h0;
|
|
parameter [255:0] INIT_31 = 256'h0;
|
|
parameter [255:0] INIT_32 = 256'h0;
|
|
parameter [255:0] INIT_33 = 256'h0;
|
|
parameter [255:0] INIT_34 = 256'h0;
|
|
parameter [255:0] INIT_35 = 256'h0;
|
|
parameter [255:0] INIT_36 = 256'h0;
|
|
parameter [255:0] INIT_37 = 256'h0;
|
|
parameter [255:0] INIT_38 = 256'h0;
|
|
parameter [255:0] INIT_39 = 256'h0;
|
|
parameter [255:0] INIT_3A = 256'h0;
|
|
parameter [255:0] INIT_3B = 256'h0;
|
|
parameter [255:0] INIT_3C = 256'h0;
|
|
parameter [255:0] INIT_3D = 256'h0;
|
|
parameter [255:0] INIT_3E = 256'h0;
|
|
parameter [255:0] INIT_3F = 256'h0;
|
|
parameter [35:0] INIT_A = 36'h0;
|
|
parameter [17:0] INIT_B = 18'h0;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [35:0] SRVAL_A = 36'h0;
|
|
parameter [17:0] SRVAL_B = 18'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
output [31:0] DOA;
|
|
output [3:0] DOPA;
|
|
output [15:0] DOB;
|
|
output [1:0] DOPB;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input ENA;
|
|
input ENB;
|
|
input SSRA;
|
|
input SSRB;
|
|
input [3:0] WEA;
|
|
input [1:0] WEB;
|
|
input [31:0] DIA;
|
|
input [3:0] DIPA;
|
|
input [15:0] DIB;
|
|
input [1:0] DIPB;
|
|
input [8:0] ADDRA;
|
|
input [9:0] ADDRB;
|
|
endmodule
|
|
|
|
module RAMB16BWE_S36_S36(DOA, DOPA, DOB, DOPB, CLKA, CLKB, ENA, ENB, SSRA, SSRB, WEA, WEB, DIA, DIPA, DIB, DIPB, ADDRA, ADDRB);
|
|
parameter [255:0] INITP_00 = 256'h0;
|
|
parameter [255:0] INITP_01 = 256'h0;
|
|
parameter [255:0] INITP_02 = 256'h0;
|
|
parameter [255:0] INITP_03 = 256'h0;
|
|
parameter [255:0] INITP_04 = 256'h0;
|
|
parameter [255:0] INITP_05 = 256'h0;
|
|
parameter [255:0] INITP_06 = 256'h0;
|
|
parameter [255:0] INITP_07 = 256'h0;
|
|
parameter [255:0] INIT_00 = 256'h0;
|
|
parameter [255:0] INIT_01 = 256'h0;
|
|
parameter [255:0] INIT_02 = 256'h0;
|
|
parameter [255:0] INIT_03 = 256'h0;
|
|
parameter [255:0] INIT_04 = 256'h0;
|
|
parameter [255:0] INIT_05 = 256'h0;
|
|
parameter [255:0] INIT_06 = 256'h0;
|
|
parameter [255:0] INIT_07 = 256'h0;
|
|
parameter [255:0] INIT_08 = 256'h0;
|
|
parameter [255:0] INIT_09 = 256'h0;
|
|
parameter [255:0] INIT_0A = 256'h0;
|
|
parameter [255:0] INIT_0B = 256'h0;
|
|
parameter [255:0] INIT_0C = 256'h0;
|
|
parameter [255:0] INIT_0D = 256'h0;
|
|
parameter [255:0] INIT_0E = 256'h0;
|
|
parameter [255:0] INIT_0F = 256'h0;
|
|
parameter [255:0] INIT_10 = 256'h0;
|
|
parameter [255:0] INIT_11 = 256'h0;
|
|
parameter [255:0] INIT_12 = 256'h0;
|
|
parameter [255:0] INIT_13 = 256'h0;
|
|
parameter [255:0] INIT_14 = 256'h0;
|
|
parameter [255:0] INIT_15 = 256'h0;
|
|
parameter [255:0] INIT_16 = 256'h0;
|
|
parameter [255:0] INIT_17 = 256'h0;
|
|
parameter [255:0] INIT_18 = 256'h0;
|
|
parameter [255:0] INIT_19 = 256'h0;
|
|
parameter [255:0] INIT_1A = 256'h0;
|
|
parameter [255:0] INIT_1B = 256'h0;
|
|
parameter [255:0] INIT_1C = 256'h0;
|
|
parameter [255:0] INIT_1D = 256'h0;
|
|
parameter [255:0] INIT_1E = 256'h0;
|
|
parameter [255:0] INIT_1F = 256'h0;
|
|
parameter [255:0] INIT_20 = 256'h0;
|
|
parameter [255:0] INIT_21 = 256'h0;
|
|
parameter [255:0] INIT_22 = 256'h0;
|
|
parameter [255:0] INIT_23 = 256'h0;
|
|
parameter [255:0] INIT_24 = 256'h0;
|
|
parameter [255:0] INIT_25 = 256'h0;
|
|
parameter [255:0] INIT_26 = 256'h0;
|
|
parameter [255:0] INIT_27 = 256'h0;
|
|
parameter [255:0] INIT_28 = 256'h0;
|
|
parameter [255:0] INIT_29 = 256'h0;
|
|
parameter [255:0] INIT_2A = 256'h0;
|
|
parameter [255:0] INIT_2B = 256'h0;
|
|
parameter [255:0] INIT_2C = 256'h0;
|
|
parameter [255:0] INIT_2D = 256'h0;
|
|
parameter [255:0] INIT_2E = 256'h0;
|
|
parameter [255:0] INIT_2F = 256'h0;
|
|
parameter [255:0] INIT_30 = 256'h0;
|
|
parameter [255:0] INIT_31 = 256'h0;
|
|
parameter [255:0] INIT_32 = 256'h0;
|
|
parameter [255:0] INIT_33 = 256'h0;
|
|
parameter [255:0] INIT_34 = 256'h0;
|
|
parameter [255:0] INIT_35 = 256'h0;
|
|
parameter [255:0] INIT_36 = 256'h0;
|
|
parameter [255:0] INIT_37 = 256'h0;
|
|
parameter [255:0] INIT_38 = 256'h0;
|
|
parameter [255:0] INIT_39 = 256'h0;
|
|
parameter [255:0] INIT_3A = 256'h0;
|
|
parameter [255:0] INIT_3B = 256'h0;
|
|
parameter [255:0] INIT_3C = 256'h0;
|
|
parameter [255:0] INIT_3D = 256'h0;
|
|
parameter [255:0] INIT_3E = 256'h0;
|
|
parameter [255:0] INIT_3F = 256'h0;
|
|
parameter [35:0] INIT_A = 36'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [35:0] SRVAL_A = 36'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
output [31:0] DOA;
|
|
output [3:0] DOPA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPB;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input ENA;
|
|
input ENB;
|
|
input SSRA;
|
|
input SSRB;
|
|
input [3:0] WEA;
|
|
input [3:0] WEB;
|
|
input [31:0] DIA;
|
|
input [3:0] DIPA;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPB;
|
|
input [8:0] ADDRA;
|
|
input [8:0] ADDRB;
|
|
endmodule
|
|
|
|
module RAMB16BWER(DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, RSTA, RSTB, WEA, WEB);
|
|
parameter integer DATA_WIDTH_A = 0;
|
|
parameter integer DATA_WIDTH_B = 0;
|
|
parameter integer DOA_REG = 0;
|
|
parameter integer DOB_REG = 0;
|
|
parameter EN_RSTRAM_A = "TRUE";
|
|
parameter EN_RSTRAM_B = "TRUE";
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [35:0] INIT_A = 36'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter INIT_FILE = "NONE";
|
|
parameter RSTTYPE = "SYNC";
|
|
parameter RST_PRIORITY_A = "CE";
|
|
parameter RST_PRIORITY_B = "CE";
|
|
parameter SETUP_ALL = 1000;
|
|
parameter SETUP_READ_FIRST = 3000;
|
|
parameter SIM_DEVICE = "SPARTAN3ADSP";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [35:0] SRVAL_A = 36'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
output [31:0] DOA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPA;
|
|
output [3:0] DOPB;
|
|
input [13:0] ADDRA;
|
|
input [13:0] ADDRB;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input [31:0] DIA;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPA;
|
|
input [3:0] DIPB;
|
|
input ENA;
|
|
input ENB;
|
|
input REGCEA;
|
|
input REGCEB;
|
|
input RSTA;
|
|
input RSTB;
|
|
input [3:0] WEA;
|
|
input [3:0] WEB;
|
|
endmodule
|
|
|
|
module RAMB8BWER(DOADO, DOBDO, DOPADOP, DOPBDOP, ADDRAWRADDR, ADDRBRDADDR, CLKAWRCLK, CLKBRDCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENAWREN, ENBRDEN, REGCEA, REGCEBREGCE, RSTA, RSTBRST, WEAWEL, WEBWEU);
|
|
parameter integer DATA_WIDTH_A = 0;
|
|
parameter integer DATA_WIDTH_B = 0;
|
|
parameter integer DOA_REG = 0;
|
|
parameter integer DOB_REG = 0;
|
|
parameter EN_RSTRAM_A = "TRUE";
|
|
parameter EN_RSTRAM_B = "TRUE";
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [17:0] INIT_A = 18'h0;
|
|
parameter [17:0] INIT_B = 18'h0;
|
|
parameter INIT_FILE = "NONE";
|
|
parameter RAM_MODE = "TDP";
|
|
parameter RSTTYPE = "SYNC";
|
|
parameter RST_PRIORITY_A = "CE";
|
|
parameter RST_PRIORITY_B = "CE";
|
|
parameter SETUP_ALL = 1000;
|
|
parameter SETUP_READ_FIRST = 3000;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [17:0] SRVAL_A = 18'h0;
|
|
parameter [17:0] SRVAL_B = 18'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
output [15:0] DOADO;
|
|
output [15:0] DOBDO;
|
|
output [1:0] DOPADOP;
|
|
output [1:0] DOPBDOP;
|
|
input [12:0] ADDRAWRADDR;
|
|
input [12:0] ADDRBRDADDR;
|
|
(* clkbuf_sink *)
|
|
input CLKAWRCLK;
|
|
(* clkbuf_sink *)
|
|
input CLKBRDCLK;
|
|
input [15:0] DIADI;
|
|
input [15:0] DIBDI;
|
|
input [1:0] DIPADIP;
|
|
input [1:0] DIPBDIP;
|
|
input ENAWREN;
|
|
input ENBRDEN;
|
|
input REGCEA;
|
|
input REGCEBREGCE;
|
|
input RSTA;
|
|
input RSTBRST;
|
|
input [1:0] WEAWEL;
|
|
input [1:0] WEBWEU;
|
|
endmodule
|
|
|
|
module FIFO16(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
|
|
parameter [11:0] ALMOST_FULL_OFFSET = 12'h080;
|
|
parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080;
|
|
parameter integer DATA_WIDTH = 36;
|
|
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
|
|
output ALMOSTEMPTY;
|
|
output ALMOSTFULL;
|
|
output [31:0] DO;
|
|
output [3:0] DOP;
|
|
output EMPTY;
|
|
output FULL;
|
|
output [11:0] RDCOUNT;
|
|
output RDERR;
|
|
output [11:0] WRCOUNT;
|
|
output WRERR;
|
|
input [31:0] DI;
|
|
input [3:0] DIP;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input RST;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
endmodule
|
|
|
|
module RAMB16(CASCADEOUTA, CASCADEOUTB, DOA, DOB, DOPA, DOPB, ENA, CLKA, SSRA, CASCADEINA, REGCEA, ENB, CLKB, SSRB, CASCADEINB, REGCEB, ADDRA, ADDRB, DIA, DIB, DIPA
|
|
, DIPB, WEA, WEB);
|
|
parameter integer DOA_REG = 0;
|
|
parameter integer DOB_REG = 0;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [35:0] INIT_A = 36'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter INIT_FILE = "NONE";
|
|
parameter INVERT_CLK_DOA_REG = "FALSE";
|
|
parameter INVERT_CLK_DOB_REG = "FALSE";
|
|
parameter RAM_EXTENSION_A = "NONE";
|
|
parameter RAM_EXTENSION_B = "NONE";
|
|
parameter integer READ_WIDTH_A = 0;
|
|
parameter integer READ_WIDTH_B = 0;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter [35:0] SRVAL_A = 36'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter integer WRITE_WIDTH_A = 0;
|
|
parameter integer WRITE_WIDTH_B = 0;
|
|
output CASCADEOUTA;
|
|
output CASCADEOUTB;
|
|
output [31:0] DOA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPA;
|
|
output [3:0] DOPB;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input SSRA;
|
|
input CASCADEINA;
|
|
input REGCEA;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input SSRB;
|
|
input CASCADEINB;
|
|
input REGCEB;
|
|
input [14:0] ADDRA;
|
|
input [14:0] ADDRB;
|
|
input [31:0] DIA;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPA;
|
|
input [3:0] DIPB;
|
|
input [3:0] WEA;
|
|
input [3:0] WEB;
|
|
endmodule
|
|
|
|
module RAMB32_S64_ECC(STATUS, DO, RDCLK, RDEN, SSR, WRCLK, WREN, DI, RDADDR, WRADDR);
|
|
parameter DO_REG = 0;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
output [1:0] STATUS;
|
|
output [63:0] DO;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input SSR;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
input [63:0] DI;
|
|
input [8:0] RDADDR;
|
|
input [8:0] WRADDR;
|
|
endmodule
|
|
|
|
module FIFO18(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
|
|
parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080;
|
|
parameter [11:0] ALMOST_FULL_OFFSET = 12'h080;
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter integer DO_REG = 1;
|
|
parameter EN_SYN = "FALSE";
|
|
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
|
|
parameter SIM_MODE = "SAFE";
|
|
output ALMOSTEMPTY;
|
|
output ALMOSTFULL;
|
|
output [15:0] DO;
|
|
output [1:0] DOP;
|
|
output EMPTY;
|
|
output FULL;
|
|
output [11:0] RDCOUNT;
|
|
output RDERR;
|
|
output [11:0] WRCOUNT;
|
|
output WRERR;
|
|
input [15:0] DI;
|
|
input [1:0] DIP;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input RST;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
endmodule
|
|
|
|
module FIFO18_36(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
|
|
parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080;
|
|
parameter [8:0] ALMOST_FULL_OFFSET = 9'h080;
|
|
parameter integer DO_REG = 1;
|
|
parameter EN_SYN = "FALSE";
|
|
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
|
|
parameter SIM_MODE = "SAFE";
|
|
output ALMOSTEMPTY;
|
|
output ALMOSTFULL;
|
|
output [31:0] DO;
|
|
output [3:0] DOP;
|
|
output EMPTY;
|
|
output FULL;
|
|
output [8:0] RDCOUNT;
|
|
output RDERR;
|
|
output [8:0] WRCOUNT;
|
|
output WRERR;
|
|
input [31:0] DI;
|
|
input [3:0] DIP;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input RST;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
endmodule
|
|
|
|
module FIFO36(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
|
|
parameter [12:0] ALMOST_EMPTY_OFFSET = 13'h080;
|
|
parameter [12:0] ALMOST_FULL_OFFSET = 13'h080;
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter integer DO_REG = 1;
|
|
parameter EN_SYN = "FALSE";
|
|
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
|
|
parameter SIM_MODE = "SAFE";
|
|
output ALMOSTEMPTY;
|
|
output ALMOSTFULL;
|
|
output [31:0] DO;
|
|
output [3:0] DOP;
|
|
output EMPTY;
|
|
output FULL;
|
|
output [12:0] RDCOUNT;
|
|
output RDERR;
|
|
output [12:0] WRCOUNT;
|
|
output WRERR;
|
|
input [31:0] DI;
|
|
input [3:0] DIP;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input RST;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
endmodule
|
|
|
|
module FIFO36_72(ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN);
|
|
parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080;
|
|
parameter [8:0] ALMOST_FULL_OFFSET = 9'h080;
|
|
parameter integer DO_REG = 1;
|
|
parameter EN_ECC_WRITE = "FALSE";
|
|
parameter EN_ECC_READ = "FALSE";
|
|
parameter EN_SYN = "FALSE";
|
|
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
|
|
parameter SIM_MODE = "SAFE";
|
|
output ALMOSTEMPTY;
|
|
output ALMOSTFULL;
|
|
output DBITERR;
|
|
output [63:0] DO;
|
|
output [7:0] DOP;
|
|
output [7:0] ECCPARITY;
|
|
output EMPTY;
|
|
output FULL;
|
|
output [8:0] RDCOUNT;
|
|
output RDERR;
|
|
output SBITERR;
|
|
output [8:0] WRCOUNT;
|
|
output WRERR;
|
|
input [63:0] DI;
|
|
input [7:0] DIP;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input RST;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
endmodule
|
|
|
|
module RAMB18(DOA, DOB, DOPA, DOPB, ENA, CLKA, SSRA, REGCEA, ENB, CLKB, SSRB, REGCEB, ADDRA, ADDRB, DIA, DIB, DIPA, DIPB, WEA, WEB);
|
|
parameter integer DOA_REG = 0;
|
|
parameter integer DOB_REG = 0;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [17:0] INIT_A = 18'h0;
|
|
parameter [17:0] INIT_B = 18'h0;
|
|
parameter INIT_FILE = "NONE";
|
|
parameter integer READ_WIDTH_A = 0;
|
|
parameter integer READ_WIDTH_B = 0;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter SIM_MODE = "SAFE";
|
|
parameter [17:0] SRVAL_A = 18'h0;
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parameter [17:0] SRVAL_B = 18'h0;
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|
parameter WRITE_MODE_A = "WRITE_FIRST";
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|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
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parameter integer WRITE_WIDTH_A = 0;
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|
parameter integer WRITE_WIDTH_B = 0;
|
|
output [15:0] DOA;
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|
output [15:0] DOB;
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|
output [1:0] DOPA;
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|
output [1:0] DOPB;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input SSRA;
|
|
input REGCEA;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input SSRB;
|
|
input REGCEB;
|
|
input [13:0] ADDRA;
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|
input [13:0] ADDRB;
|
|
input [15:0] DIA;
|
|
input [15:0] DIB;
|
|
input [1:0] DIPA;
|
|
input [1:0] DIPB;
|
|
input [1:0] WEA;
|
|
input [1:0] WEB;
|
|
endmodule
|
|
|
|
module RAMB36(CASCADEOUTLATA, CASCADEOUTREGA, CASCADEOUTLATB, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, ENA, CLKA, SSRA, CASCADEINLATA, CASCADEINREGA, REGCEA, ENB, CLKB, SSRB, CASCADEINLATB, CASCADEINREGB, REGCEB, ADDRA
|
|
, ADDRB, DIA, DIB, DIPA, DIPB, WEA, WEB);
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|
parameter integer DOA_REG = 0;
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|
parameter integer DOB_REG = 0;
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|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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|
parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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|
parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [35:0] INIT_A = 36'h0;
|
|
parameter [35:0] INIT_B = 36'h0;
|
|
parameter INIT_FILE = "NONE";
|
|
parameter RAM_EXTENSION_A = "NONE";
|
|
parameter RAM_EXTENSION_B = "NONE";
|
|
parameter integer READ_WIDTH_A = 0;
|
|
parameter integer READ_WIDTH_B = 0;
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter SIM_MODE = "SAFE";
|
|
parameter [35:0] SRVAL_A = 36'h0;
|
|
parameter [35:0] SRVAL_B = 36'h0;
|
|
parameter WRITE_MODE_A = "WRITE_FIRST";
|
|
parameter WRITE_MODE_B = "WRITE_FIRST";
|
|
parameter integer WRITE_WIDTH_A = 0;
|
|
parameter integer WRITE_WIDTH_B = 0;
|
|
output CASCADEOUTLATA;
|
|
output CASCADEOUTREGA;
|
|
output CASCADEOUTLATB;
|
|
output CASCADEOUTREGB;
|
|
output [31:0] DOA;
|
|
output [31:0] DOB;
|
|
output [3:0] DOPA;
|
|
output [3:0] DOPB;
|
|
input ENA;
|
|
(* clkbuf_sink *)
|
|
input CLKA;
|
|
input SSRA;
|
|
input CASCADEINLATA;
|
|
input CASCADEINREGA;
|
|
input REGCEA;
|
|
input ENB;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
input SSRB;
|
|
input CASCADEINLATB;
|
|
input CASCADEINREGB;
|
|
input REGCEB;
|
|
input [15:0] ADDRA;
|
|
input [15:0] ADDRB;
|
|
input [31:0] DIA;
|
|
input [31:0] DIB;
|
|
input [3:0] DIPA;
|
|
input [3:0] DIPB;
|
|
input [3:0] WEA;
|
|
input [3:0] WEB;
|
|
endmodule
|
|
|
|
module RAMB18SDP(DO, DOP, RDCLK, RDEN, REGCE, SSR, WRCLK, WREN, WRADDR, RDADDR, DI, DIP, WE);
|
|
parameter integer DO_REG = 0;
|
|
parameter [35:0] INIT = 36'h0;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_FILE = "NONE";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter SIM_MODE = "SAFE";
|
|
parameter [35:0] SRVAL = 36'h0;
|
|
output [31:0] DO;
|
|
output [3:0] DOP;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input REGCE;
|
|
input SSR;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
input [8:0] WRADDR;
|
|
input [8:0] RDADDR;
|
|
input [31:0] DI;
|
|
input [3:0] DIP;
|
|
input [3:0] WE;
|
|
endmodule
|
|
|
|
module RAMB36SDP(DBITERR, SBITERR, DO, DOP, ECCPARITY, RDCLK, RDEN, REGCE, SSR, WRCLK, WREN, WRADDR, RDADDR, DI, DIP, WE);
|
|
parameter integer DO_REG = 0;
|
|
parameter EN_ECC_READ = "FALSE";
|
|
parameter EN_ECC_SCRUB = "FALSE";
|
|
parameter EN_ECC_WRITE = "FALSE";
|
|
parameter [71:0] INIT = 72'h0;
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter INIT_FILE = "NONE";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter SIM_MODE = "SAFE";
|
|
parameter [71:0] SRVAL = 72'h0;
|
|
output DBITERR;
|
|
output SBITERR;
|
|
output [63:0] DO;
|
|
output [7:0] DOP;
|
|
output [7:0] ECCPARITY;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input REGCE;
|
|
input SSR;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
input [8:0] WRADDR;
|
|
input [8:0] RDADDR;
|
|
input [63:0] DI;
|
|
input [7:0] DIP;
|
|
input [7:0] WE;
|
|
endmodule
|
|
|
|
module FIFO18E1(ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN);
|
|
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
|
|
parameter ALMOST_FULL_OFFSET = 13'h0080;
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter integer DO_REG = 1;
|
|
parameter EN_SYN = "FALSE";
|
|
parameter FIFO_MODE = "FIFO18";
|
|
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
|
|
parameter INIT = 36'h0;
|
|
parameter SIM_DEVICE = "VIRTEX6";
|
|
parameter SRVAL = 36'h0;
|
|
parameter IS_RDCLK_INVERTED = 1'b0;
|
|
parameter IS_RDEN_INVERTED = 1'b0;
|
|
parameter IS_RSTREG_INVERTED = 1'b0;
|
|
parameter IS_RST_INVERTED = 1'b0;
|
|
parameter IS_WRCLK_INVERTED = 1'b0;
|
|
parameter IS_WREN_INVERTED = 1'b0;
|
|
output ALMOSTEMPTY;
|
|
output ALMOSTFULL;
|
|
output [31:0] DO;
|
|
output [3:0] DOP;
|
|
output EMPTY;
|
|
output FULL;
|
|
output [11:0] RDCOUNT;
|
|
output RDERR;
|
|
output [11:0] WRCOUNT;
|
|
output WRERR;
|
|
input [31:0] DI;
|
|
input [3:0] DIP;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_RDCLK_INVERTED" *)
|
|
input RDCLK;
|
|
(* invertible_pin = "IS_RDEN_INVERTED" *)
|
|
input RDEN;
|
|
input REGCE;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
(* invertible_pin = "IS_RSTREG_INVERTED" *)
|
|
input RSTREG;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_WRCLK_INVERTED" *)
|
|
input WRCLK;
|
|
(* invertible_pin = "IS_WREN_INVERTED" *)
|
|
input WREN;
|
|
endmodule
|
|
|
|
module FIFO36E1(ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, DI, DIP, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST
|
|
, RSTREG, WRCLK, WREN);
|
|
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
|
|
parameter ALMOST_FULL_OFFSET = 13'h0080;
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter integer DO_REG = 1;
|
|
parameter EN_ECC_READ = "FALSE";
|
|
parameter EN_ECC_WRITE = "FALSE";
|
|
parameter EN_SYN = "FALSE";
|
|
parameter FIFO_MODE = "FIFO36";
|
|
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
|
|
parameter INIT = 72'h0;
|
|
parameter SIM_DEVICE = "VIRTEX6";
|
|
parameter SRVAL = 72'h0;
|
|
parameter IS_RDCLK_INVERTED = 1'b0;
|
|
parameter IS_RDEN_INVERTED = 1'b0;
|
|
parameter IS_RSTREG_INVERTED = 1'b0;
|
|
parameter IS_RST_INVERTED = 1'b0;
|
|
parameter IS_WRCLK_INVERTED = 1'b0;
|
|
parameter IS_WREN_INVERTED = 1'b0;
|
|
output ALMOSTEMPTY;
|
|
output ALMOSTFULL;
|
|
output DBITERR;
|
|
output [63:0] DO;
|
|
output [7:0] DOP;
|
|
output [7:0] ECCPARITY;
|
|
output EMPTY;
|
|
output FULL;
|
|
output [12:0] RDCOUNT;
|
|
output RDERR;
|
|
output SBITERR;
|
|
output [12:0] WRCOUNT;
|
|
output WRERR;
|
|
input [63:0] DI;
|
|
input [7:0] DIP;
|
|
input INJECTDBITERR;
|
|
input INJECTSBITERR;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_RDCLK_INVERTED" *)
|
|
input RDCLK;
|
|
(* invertible_pin = "IS_RDEN_INVERTED" *)
|
|
input RDEN;
|
|
input REGCE;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
(* invertible_pin = "IS_RSTREG_INVERTED" *)
|
|
input RSTREG;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_WRCLK_INVERTED" *)
|
|
input WRCLK;
|
|
(* invertible_pin = "IS_WREN_INVERTED" *)
|
|
input WREN;
|
|
endmodule
|
|
|
|
module FIFO18E2(CASDOUT, CASDOUTP, CASNXTEMPTY, CASPRVRDEN, DOUT, DOUTP, EMPTY, FULL, PROGEMPTY, PROGFULL, RDCOUNT, RDERR, RDRSTBUSY, WRCOUNT, WRERR, WRRSTBUSY, CASDIN, CASDINP, CASDOMUX, CASDOMUXEN, CASNXTRDEN
|
|
, CASOREGIMUX, CASOREGIMUXEN, CASPRVEMPTY, DIN, DINP, RDCLK, RDEN, REGCE, RST, RSTREG, SLEEP, WRCLK, WREN);
|
|
parameter CASCADE_ORDER = "NONE";
|
|
parameter CLOCK_DOMAINS = "INDEPENDENT";
|
|
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
|
|
parameter [35:0] INIT = 36'h000000000;
|
|
parameter [0:0] IS_RDCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RDEN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTREG_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter [0:0] IS_WRCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_WREN_INVERTED = 1'b0;
|
|
parameter integer PROG_EMPTY_THRESH = 256;
|
|
parameter integer PROG_FULL_THRESH = 256;
|
|
parameter RDCOUNT_TYPE = "RAW_PNTR";
|
|
parameter integer READ_WIDTH = 4;
|
|
parameter REGISTER_MODE = "UNREGISTERED";
|
|
parameter RSTREG_PRIORITY = "RSTREG";
|
|
parameter SLEEP_ASYNC = "FALSE";
|
|
parameter [35:0] SRVAL = 36'h000000000;
|
|
parameter WRCOUNT_TYPE = "RAW_PNTR";
|
|
parameter integer WRITE_WIDTH = 4;
|
|
output [31:0] CASDOUT;
|
|
output [3:0] CASDOUTP;
|
|
output CASNXTEMPTY;
|
|
output CASPRVRDEN;
|
|
output [31:0] DOUT;
|
|
output [3:0] DOUTP;
|
|
output EMPTY;
|
|
output FULL;
|
|
output PROGEMPTY;
|
|
output PROGFULL;
|
|
output [12:0] RDCOUNT;
|
|
output RDERR;
|
|
output RDRSTBUSY;
|
|
output [12:0] WRCOUNT;
|
|
output WRERR;
|
|
output WRRSTBUSY;
|
|
input [31:0] CASDIN;
|
|
input [3:0] CASDINP;
|
|
input CASDOMUX;
|
|
input CASDOMUXEN;
|
|
input CASNXTRDEN;
|
|
input CASOREGIMUX;
|
|
input CASOREGIMUXEN;
|
|
input CASPRVEMPTY;
|
|
input [31:0] DIN;
|
|
input [3:0] DINP;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_RDCLK_INVERTED" *)
|
|
input RDCLK;
|
|
(* invertible_pin = "IS_RDEN_INVERTED" *)
|
|
input RDEN;
|
|
input REGCE;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
(* invertible_pin = "IS_RSTREG_INVERTED" *)
|
|
input RSTREG;
|
|
input SLEEP;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_WRCLK_INVERTED" *)
|
|
input WRCLK;
|
|
(* invertible_pin = "IS_WREN_INVERTED" *)
|
|
input WREN;
|
|
endmodule
|
|
|
|
module FIFO36E2(CASDOUT, CASDOUTP, CASNXTEMPTY, CASPRVRDEN, DBITERR, DOUT, DOUTP, ECCPARITY, EMPTY, FULL, PROGEMPTY, PROGFULL, RDCOUNT, RDERR, RDRSTBUSY, SBITERR, WRCOUNT, WRERR, WRRSTBUSY, CASDIN, CASDINP
|
|
, CASDOMUX, CASDOMUXEN, CASNXTRDEN, CASOREGIMUX, CASOREGIMUXEN, CASPRVEMPTY, DIN, DINP, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, SLEEP, WRCLK, WREN);
|
|
parameter CASCADE_ORDER = "NONE";
|
|
parameter CLOCK_DOMAINS = "INDEPENDENT";
|
|
parameter EN_ECC_PIPE = "FALSE";
|
|
parameter EN_ECC_READ = "FALSE";
|
|
parameter EN_ECC_WRITE = "FALSE";
|
|
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
|
|
parameter [71:0] INIT = 72'h000000000000000000;
|
|
parameter [0:0] IS_RDCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RDEN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTREG_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter [0:0] IS_WRCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_WREN_INVERTED = 1'b0;
|
|
parameter integer PROG_EMPTY_THRESH = 256;
|
|
parameter integer PROG_FULL_THRESH = 256;
|
|
parameter RDCOUNT_TYPE = "RAW_PNTR";
|
|
parameter integer READ_WIDTH = 4;
|
|
parameter REGISTER_MODE = "UNREGISTERED";
|
|
parameter RSTREG_PRIORITY = "RSTREG";
|
|
parameter SLEEP_ASYNC = "FALSE";
|
|
parameter [71:0] SRVAL = 72'h000000000000000000;
|
|
parameter WRCOUNT_TYPE = "RAW_PNTR";
|
|
parameter integer WRITE_WIDTH = 4;
|
|
output [63:0] CASDOUT;
|
|
output [7:0] CASDOUTP;
|
|
output CASNXTEMPTY;
|
|
output CASPRVRDEN;
|
|
output DBITERR;
|
|
output [63:0] DOUT;
|
|
output [7:0] DOUTP;
|
|
output [7:0] ECCPARITY;
|
|
output EMPTY;
|
|
output FULL;
|
|
output PROGEMPTY;
|
|
output PROGFULL;
|
|
output [13:0] RDCOUNT;
|
|
output RDERR;
|
|
output RDRSTBUSY;
|
|
output SBITERR;
|
|
output [13:0] WRCOUNT;
|
|
output WRERR;
|
|
output WRRSTBUSY;
|
|
input [63:0] CASDIN;
|
|
input [7:0] CASDINP;
|
|
input CASDOMUX;
|
|
input CASDOMUXEN;
|
|
input CASNXTRDEN;
|
|
input CASOREGIMUX;
|
|
input CASOREGIMUXEN;
|
|
input CASPRVEMPTY;
|
|
input [63:0] DIN;
|
|
input [7:0] DINP;
|
|
input INJECTDBITERR;
|
|
input INJECTSBITERR;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_RDCLK_INVERTED" *)
|
|
input RDCLK;
|
|
(* invertible_pin = "IS_RDEN_INVERTED" *)
|
|
input RDEN;
|
|
input REGCE;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
(* invertible_pin = "IS_RSTREG_INVERTED" *)
|
|
input RSTREG;
|
|
input SLEEP;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_WRCLK_INVERTED" *)
|
|
input WRCLK;
|
|
(* invertible_pin = "IS_WREN_INVERTED" *)
|
|
input WREN;
|
|
endmodule
|
|
|
|
module RAMB18E2(CASDOUTA, CASDOUTB, CASDOUTPA, CASDOUTPB, DOUTADOUT, DOUTBDOUT, DOUTPADOUTP, DOUTPBDOUTP, ADDRARDADDR, ADDRBWRADDR, ADDRENA, ADDRENB, CASDIMUXA, CASDIMUXB, CASDINA, CASDINB, CASDINPA, CASDINPB, CASDOMUXA, CASDOMUXB, CASDOMUXEN_A
|
|
, CASDOMUXEN_B, CASOREGIMUXA, CASOREGIMUXB, CASOREGIMUXEN_A, CASOREGIMUXEN_B, CLKARDCLK, CLKBWRCLK, DINADIN, DINBDIN, DINPADINP, DINPBDINP, ENARDEN, ENBWREN, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, SLEEP, WEA
|
|
, WEBWE);
|
|
parameter CASCADE_ORDER_A = "NONE";
|
|
parameter CASCADE_ORDER_B = "NONE";
|
|
parameter CLOCK_DOMAINS = "INDEPENDENT";
|
|
parameter integer DOA_REG = 1;
|
|
parameter integer DOB_REG = 1;
|
|
parameter ENADDRENA = "FALSE";
|
|
parameter ENADDRENB = "FALSE";
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [17:0] INIT_A = 18'h00000;
|
|
parameter [17:0] INIT_B = 18'h00000;
|
|
parameter INIT_FILE = "NONE";
|
|
parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_ENARDEN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_ENBWREN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTREGB_INVERTED = 1'b0;
|
|
parameter RDADDRCHANGEA = "FALSE";
|
|
parameter RDADDRCHANGEB = "FALSE";
|
|
parameter integer READ_WIDTH_A = 0;
|
|
parameter integer READ_WIDTH_B = 0;
|
|
parameter RSTREG_PRIORITY_A = "RSTREG";
|
|
parameter RSTREG_PRIORITY_B = "RSTREG";
|
|
parameter SIM_COLLISION_CHECK = "ALL";
|
|
parameter SLEEP_ASYNC = "FALSE";
|
|
parameter [17:0] SRVAL_A = 18'h00000;
|
|
parameter [17:0] SRVAL_B = 18'h00000;
|
|
parameter WRITE_MODE_A = "NO_CHANGE";
|
|
parameter WRITE_MODE_B = "NO_CHANGE";
|
|
parameter integer WRITE_WIDTH_A = 0;
|
|
parameter integer WRITE_WIDTH_B = 0;
|
|
output [15:0] CASDOUTA;
|
|
output [15:0] CASDOUTB;
|
|
output [1:0] CASDOUTPA;
|
|
output [1:0] CASDOUTPB;
|
|
output [15:0] DOUTADOUT;
|
|
output [15:0] DOUTBDOUT;
|
|
output [1:0] DOUTPADOUTP;
|
|
output [1:0] DOUTPBDOUTP;
|
|
input [13:0] ADDRARDADDR;
|
|
input [13:0] ADDRBWRADDR;
|
|
input ADDRENA;
|
|
input ADDRENB;
|
|
input CASDIMUXA;
|
|
input CASDIMUXB;
|
|
input [15:0] CASDINA;
|
|
input [15:0] CASDINB;
|
|
input [1:0] CASDINPA;
|
|
input [1:0] CASDINPB;
|
|
input CASDOMUXA;
|
|
input CASDOMUXB;
|
|
input CASDOMUXEN_A;
|
|
input CASDOMUXEN_B;
|
|
input CASOREGIMUXA;
|
|
input CASOREGIMUXB;
|
|
input CASOREGIMUXEN_A;
|
|
input CASOREGIMUXEN_B;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
|
input CLKARDCLK;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
|
input CLKBWRCLK;
|
|
input [15:0] DINADIN;
|
|
input [15:0] DINBDIN;
|
|
input [1:0] DINPADINP;
|
|
input [1:0] DINPBDINP;
|
|
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
|
input ENARDEN;
|
|
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
|
input ENBWREN;
|
|
input REGCEAREGCE;
|
|
input REGCEB;
|
|
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
|
input RSTRAMARSTRAM;
|
|
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
|
input RSTRAMB;
|
|
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
|
input RSTREGARSTREG;
|
|
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
|
input RSTREGB;
|
|
input SLEEP;
|
|
input [1:0] WEA;
|
|
input [3:0] WEBWE;
|
|
endmodule
|
|
|
|
module RAMB36E2(CASDOUTA, CASDOUTB, CASDOUTPA, CASDOUTPB, CASOUTDBITERR, CASOUTSBITERR, DBITERR, DOUTADOUT, DOUTBDOUT, DOUTPADOUTP, DOUTPBDOUTP, ECCPARITY, RDADDRECC, SBITERR, ADDRARDADDR, ADDRBWRADDR, ADDRENA, ADDRENB, CASDIMUXA, CASDIMUXB, CASDINA
|
|
, CASDINB, CASDINPA, CASDINPB, CASDOMUXA, CASDOMUXB, CASDOMUXEN_A, CASDOMUXEN_B, CASINDBITERR, CASINSBITERR, CASOREGIMUXA, CASOREGIMUXB, CASOREGIMUXEN_A, CASOREGIMUXEN_B, CLKARDCLK, CLKBWRCLK, DINADIN, DINBDIN, DINPADINP, DINPBDINP, ECCPIPECE, ENARDEN
|
|
, ENBWREN, INJECTDBITERR, INJECTSBITERR, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, SLEEP, WEA, WEBWE);
|
|
parameter CASCADE_ORDER_A = "NONE";
|
|
parameter CASCADE_ORDER_B = "NONE";
|
|
parameter CLOCK_DOMAINS = "INDEPENDENT";
|
|
parameter integer DOA_REG = 1;
|
|
parameter integer DOB_REG = 1;
|
|
parameter ENADDRENA = "FALSE";
|
|
parameter ENADDRENB = "FALSE";
|
|
parameter EN_ECC_PIPE = "FALSE";
|
|
parameter EN_ECC_READ = "FALSE";
|
|
parameter EN_ECC_WRITE = "FALSE";
|
|
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
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parameter [35:0] INIT_A = 36'h000000000;
|
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parameter [35:0] INIT_B = 36'h000000000;
|
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parameter INIT_FILE = "NONE";
|
|
parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0;
|
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parameter [0:0] IS_ENARDEN_INVERTED = 1'b0;
|
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parameter [0:0] IS_ENBWREN_INVERTED = 1'b0;
|
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parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0;
|
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parameter [0:0] IS_RSTREGB_INVERTED = 1'b0;
|
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parameter RDADDRCHANGEA = "FALSE";
|
|
parameter RDADDRCHANGEB = "FALSE";
|
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parameter integer READ_WIDTH_A = 0;
|
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parameter integer READ_WIDTH_B = 0;
|
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parameter RSTREG_PRIORITY_A = "RSTREG";
|
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parameter RSTREG_PRIORITY_B = "RSTREG";
|
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parameter SIM_COLLISION_CHECK = "ALL";
|
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parameter SLEEP_ASYNC = "FALSE";
|
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parameter [35:0] SRVAL_A = 36'h000000000;
|
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parameter [35:0] SRVAL_B = 36'h000000000;
|
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parameter WRITE_MODE_A = "NO_CHANGE";
|
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parameter WRITE_MODE_B = "NO_CHANGE";
|
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parameter integer WRITE_WIDTH_A = 0;
|
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parameter integer WRITE_WIDTH_B = 0;
|
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output [31:0] CASDOUTA;
|
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output [31:0] CASDOUTB;
|
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output [3:0] CASDOUTPA;
|
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output [3:0] CASDOUTPB;
|
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output CASOUTDBITERR;
|
|
output CASOUTSBITERR;
|
|
output DBITERR;
|
|
output [31:0] DOUTADOUT;
|
|
output [31:0] DOUTBDOUT;
|
|
output [3:0] DOUTPADOUTP;
|
|
output [3:0] DOUTPBDOUTP;
|
|
output [7:0] ECCPARITY;
|
|
output [8:0] RDADDRECC;
|
|
output SBITERR;
|
|
input [14:0] ADDRARDADDR;
|
|
input [14:0] ADDRBWRADDR;
|
|
input ADDRENA;
|
|
input ADDRENB;
|
|
input CASDIMUXA;
|
|
input CASDIMUXB;
|
|
input [31:0] CASDINA;
|
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input [31:0] CASDINB;
|
|
input [3:0] CASDINPA;
|
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input [3:0] CASDINPB;
|
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input CASDOMUXA;
|
|
input CASDOMUXB;
|
|
input CASDOMUXEN_A;
|
|
input CASDOMUXEN_B;
|
|
input CASINDBITERR;
|
|
input CASINSBITERR;
|
|
input CASOREGIMUXA;
|
|
input CASOREGIMUXB;
|
|
input CASOREGIMUXEN_A;
|
|
input CASOREGIMUXEN_B;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
|
|
input CLKARDCLK;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
|
|
input CLKBWRCLK;
|
|
input [31:0] DINADIN;
|
|
input [31:0] DINBDIN;
|
|
input [3:0] DINPADINP;
|
|
input [3:0] DINPBDINP;
|
|
input ECCPIPECE;
|
|
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
|
|
input ENARDEN;
|
|
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
|
|
input ENBWREN;
|
|
input INJECTDBITERR;
|
|
input INJECTSBITERR;
|
|
input REGCEAREGCE;
|
|
input REGCEB;
|
|
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
|
|
input RSTRAMARSTRAM;
|
|
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
|
|
input RSTRAMB;
|
|
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
|
|
input RSTREGARSTREG;
|
|
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
|
|
input RSTREGB;
|
|
input SLEEP;
|
|
input [3:0] WEA;
|
|
input [7:0] WEBWE;
|
|
endmodule
|
|
|
|
module URAM288(CAS_OUT_ADDR_A, CAS_OUT_ADDR_B, CAS_OUT_BWE_A, CAS_OUT_BWE_B, CAS_OUT_DBITERR_A, CAS_OUT_DBITERR_B, CAS_OUT_DIN_A, CAS_OUT_DIN_B, CAS_OUT_DOUT_A, CAS_OUT_DOUT_B, CAS_OUT_EN_A, CAS_OUT_EN_B, CAS_OUT_RDACCESS_A, CAS_OUT_RDACCESS_B, CAS_OUT_RDB_WR_A, CAS_OUT_RDB_WR_B, CAS_OUT_SBITERR_A, CAS_OUT_SBITERR_B, DBITERR_A, DBITERR_B, DOUT_A
|
|
, DOUT_B, RDACCESS_A, RDACCESS_B, SBITERR_A, SBITERR_B, ADDR_A, ADDR_B, BWE_A, BWE_B, CAS_IN_ADDR_A, CAS_IN_ADDR_B, CAS_IN_BWE_A, CAS_IN_BWE_B, CAS_IN_DBITERR_A, CAS_IN_DBITERR_B, CAS_IN_DIN_A, CAS_IN_DIN_B, CAS_IN_DOUT_A, CAS_IN_DOUT_B, CAS_IN_EN_A, CAS_IN_EN_B
|
|
, CAS_IN_RDACCESS_A, CAS_IN_RDACCESS_B, CAS_IN_RDB_WR_A, CAS_IN_RDB_WR_B, CAS_IN_SBITERR_A, CAS_IN_SBITERR_B, CLK, DIN_A, DIN_B, EN_A, EN_B, INJECT_DBITERR_A, INJECT_DBITERR_B, INJECT_SBITERR_A, INJECT_SBITERR_B, OREG_CE_A, OREG_CE_B, OREG_ECC_CE_A, OREG_ECC_CE_B, RDB_WR_A, RDB_WR_B
|
|
, RST_A, RST_B, SLEEP);
|
|
parameter integer AUTO_SLEEP_LATENCY = 8;
|
|
parameter integer AVG_CONS_INACTIVE_CYCLES = 10;
|
|
parameter BWE_MODE_A = "PARITY_INTERLEAVED";
|
|
parameter BWE_MODE_B = "PARITY_INTERLEAVED";
|
|
parameter CASCADE_ORDER_A = "NONE";
|
|
parameter CASCADE_ORDER_B = "NONE";
|
|
parameter EN_AUTO_SLEEP_MODE = "FALSE";
|
|
parameter EN_ECC_RD_A = "FALSE";
|
|
parameter EN_ECC_RD_B = "FALSE";
|
|
parameter EN_ECC_WR_A = "FALSE";
|
|
parameter EN_ECC_WR_B = "FALSE";
|
|
parameter IREG_PRE_A = "FALSE";
|
|
parameter IREG_PRE_B = "FALSE";
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_EN_A_INVERTED = 1'b0;
|
|
parameter [0:0] IS_EN_B_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_A_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_B_INVERTED = 1'b0;
|
|
parameter MATRIX_ID = "NONE";
|
|
parameter integer NUM_UNIQUE_SELF_ADDR_A = 1;
|
|
parameter integer NUM_UNIQUE_SELF_ADDR_B = 1;
|
|
parameter integer NUM_URAM_IN_MATRIX = 1;
|
|
parameter OREG_A = "FALSE";
|
|
parameter OREG_B = "FALSE";
|
|
parameter OREG_ECC_A = "FALSE";
|
|
parameter OREG_ECC_B = "FALSE";
|
|
parameter REG_CAS_A = "FALSE";
|
|
parameter REG_CAS_B = "FALSE";
|
|
parameter RST_MODE_A = "SYNC";
|
|
parameter RST_MODE_B = "SYNC";
|
|
parameter [10:0] SELF_ADDR_A = 11'h000;
|
|
parameter [10:0] SELF_ADDR_B = 11'h000;
|
|
parameter [10:0] SELF_MASK_A = 11'h7FF;
|
|
parameter [10:0] SELF_MASK_B = 11'h7FF;
|
|
parameter USE_EXT_CE_A = "FALSE";
|
|
parameter USE_EXT_CE_B = "FALSE";
|
|
output [22:0] CAS_OUT_ADDR_A;
|
|
output [22:0] CAS_OUT_ADDR_B;
|
|
output [8:0] CAS_OUT_BWE_A;
|
|
output [8:0] CAS_OUT_BWE_B;
|
|
output CAS_OUT_DBITERR_A;
|
|
output CAS_OUT_DBITERR_B;
|
|
output [71:0] CAS_OUT_DIN_A;
|
|
output [71:0] CAS_OUT_DIN_B;
|
|
output [71:0] CAS_OUT_DOUT_A;
|
|
output [71:0] CAS_OUT_DOUT_B;
|
|
output CAS_OUT_EN_A;
|
|
output CAS_OUT_EN_B;
|
|
output CAS_OUT_RDACCESS_A;
|
|
output CAS_OUT_RDACCESS_B;
|
|
output CAS_OUT_RDB_WR_A;
|
|
output CAS_OUT_RDB_WR_B;
|
|
output CAS_OUT_SBITERR_A;
|
|
output CAS_OUT_SBITERR_B;
|
|
output DBITERR_A;
|
|
output DBITERR_B;
|
|
output [71:0] DOUT_A;
|
|
output [71:0] DOUT_B;
|
|
output RDACCESS_A;
|
|
output RDACCESS_B;
|
|
output SBITERR_A;
|
|
output SBITERR_B;
|
|
input [22:0] ADDR_A;
|
|
input [22:0] ADDR_B;
|
|
input [8:0] BWE_A;
|
|
input [8:0] BWE_B;
|
|
input [22:0] CAS_IN_ADDR_A;
|
|
input [22:0] CAS_IN_ADDR_B;
|
|
input [8:0] CAS_IN_BWE_A;
|
|
input [8:0] CAS_IN_BWE_B;
|
|
input CAS_IN_DBITERR_A;
|
|
input CAS_IN_DBITERR_B;
|
|
input [71:0] CAS_IN_DIN_A;
|
|
input [71:0] CAS_IN_DIN_B;
|
|
input [71:0] CAS_IN_DOUT_A;
|
|
input [71:0] CAS_IN_DOUT_B;
|
|
input CAS_IN_EN_A;
|
|
input CAS_IN_EN_B;
|
|
input CAS_IN_RDACCESS_A;
|
|
input CAS_IN_RDACCESS_B;
|
|
input CAS_IN_RDB_WR_A;
|
|
input CAS_IN_RDB_WR_B;
|
|
input CAS_IN_SBITERR_A;
|
|
input CAS_IN_SBITERR_B;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
input [71:0] DIN_A;
|
|
input [71:0] DIN_B;
|
|
(* invertible_pin = "IS_EN_A_INVERTED" *)
|
|
input EN_A;
|
|
(* invertible_pin = "IS_EN_B_INVERTED" *)
|
|
input EN_B;
|
|
input INJECT_DBITERR_A;
|
|
input INJECT_DBITERR_B;
|
|
input INJECT_SBITERR_A;
|
|
input INJECT_SBITERR_B;
|
|
input OREG_CE_A;
|
|
input OREG_CE_B;
|
|
input OREG_ECC_CE_A;
|
|
input OREG_ECC_CE_B;
|
|
(* invertible_pin = "IS_RDB_WR_A_INVERTED" *)
|
|
input RDB_WR_A;
|
|
(* invertible_pin = "IS_RDB_WR_B_INVERTED" *)
|
|
input RDB_WR_B;
|
|
(* invertible_pin = "IS_RST_A_INVERTED" *)
|
|
input RST_A;
|
|
(* invertible_pin = "IS_RST_B_INVERTED" *)
|
|
input RST_B;
|
|
input SLEEP;
|
|
endmodule
|
|
|
|
module URAM288_BASE(DBITERR_A, DBITERR_B, DOUT_A, DOUT_B, SBITERR_A, SBITERR_B, ADDR_A, ADDR_B, BWE_A, BWE_B, CLK, DIN_A, DIN_B, EN_A, EN_B, INJECT_DBITERR_A, INJECT_DBITERR_B, INJECT_SBITERR_A, INJECT_SBITERR_B, OREG_CE_A, OREG_CE_B
|
|
, OREG_ECC_CE_A, OREG_ECC_CE_B, RDB_WR_A, RDB_WR_B, RST_A, RST_B, SLEEP);
|
|
parameter integer AUTO_SLEEP_LATENCY = 8;
|
|
parameter integer AVG_CONS_INACTIVE_CYCLES = 10;
|
|
parameter BWE_MODE_A = "PARITY_INTERLEAVED";
|
|
parameter BWE_MODE_B = "PARITY_INTERLEAVED";
|
|
parameter EN_AUTO_SLEEP_MODE = "FALSE";
|
|
parameter EN_ECC_RD_A = "FALSE";
|
|
parameter EN_ECC_RD_B = "FALSE";
|
|
parameter EN_ECC_WR_A = "FALSE";
|
|
parameter EN_ECC_WR_B = "FALSE";
|
|
parameter IREG_PRE_A = "FALSE";
|
|
parameter IREG_PRE_B = "FALSE";
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_EN_A_INVERTED = 1'b0;
|
|
parameter [0:0] IS_EN_B_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_A_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_B_INVERTED = 1'b0;
|
|
parameter OREG_A = "FALSE";
|
|
parameter OREG_B = "FALSE";
|
|
parameter OREG_ECC_A = "FALSE";
|
|
parameter OREG_ECC_B = "FALSE";
|
|
parameter RST_MODE_A = "SYNC";
|
|
parameter RST_MODE_B = "SYNC";
|
|
parameter USE_EXT_CE_A = "FALSE";
|
|
parameter USE_EXT_CE_B = "FALSE";
|
|
output DBITERR_A;
|
|
output DBITERR_B;
|
|
output [71:0] DOUT_A;
|
|
output [71:0] DOUT_B;
|
|
output SBITERR_A;
|
|
output SBITERR_B;
|
|
input [22:0] ADDR_A;
|
|
input [22:0] ADDR_B;
|
|
input [8:0] BWE_A;
|
|
input [8:0] BWE_B;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
input [71:0] DIN_A;
|
|
input [71:0] DIN_B;
|
|
(* invertible_pin = "IS_EN_A_INVERTED" *)
|
|
input EN_A;
|
|
(* invertible_pin = "IS_EN_B_INVERTED" *)
|
|
input EN_B;
|
|
input INJECT_DBITERR_A;
|
|
input INJECT_DBITERR_B;
|
|
input INJECT_SBITERR_A;
|
|
input INJECT_SBITERR_B;
|
|
input OREG_CE_A;
|
|
input OREG_CE_B;
|
|
input OREG_ECC_CE_A;
|
|
input OREG_ECC_CE_B;
|
|
(* invertible_pin = "IS_RDB_WR_A_INVERTED" *)
|
|
input RDB_WR_A;
|
|
(* invertible_pin = "IS_RDB_WR_B_INVERTED" *)
|
|
input RDB_WR_B;
|
|
(* invertible_pin = "IS_RST_A_INVERTED" *)
|
|
input RST_A;
|
|
(* invertible_pin = "IS_RST_B_INVERTED" *)
|
|
input RST_B;
|
|
input SLEEP;
|
|
endmodule
|
|
|
|
module DSP48E(ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL, CEA1
|
|
, CEA2, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CEM, CEMULTCARRYIN, CEP, CLK, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTM
|
|
, RSTP);
|
|
parameter SIM_MODE = "SAFE";
|
|
parameter integer ACASCREG = 1;
|
|
parameter integer ALUMODEREG = 1;
|
|
parameter integer AREG = 1;
|
|
parameter AUTORESET_PATTERN_DETECT = "FALSE";
|
|
parameter AUTORESET_PATTERN_DETECT_OPTINV = "MATCH";
|
|
parameter A_INPUT = "DIRECT";
|
|
parameter integer BCASCREG = 1;
|
|
parameter integer BREG = 1;
|
|
parameter B_INPUT = "DIRECT";
|
|
parameter integer CARRYINREG = 1;
|
|
parameter integer CARRYINSELREG = 1;
|
|
parameter integer CREG = 1;
|
|
parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
|
|
parameter integer MREG = 1;
|
|
parameter integer MULTCARRYINREG = 1;
|
|
parameter integer OPMODEREG = 1;
|
|
parameter [47:0] PATTERN = 48'h000000000000;
|
|
parameter integer PREG = 1;
|
|
parameter SEL_MASK = "MASK";
|
|
parameter SEL_PATTERN = "PATTERN";
|
|
parameter SEL_ROUNDING_MASK = "SEL_MASK";
|
|
parameter USE_MULT = "MULT_S";
|
|
parameter USE_PATTERN_DETECT = "NO_PATDET";
|
|
parameter USE_SIMD = "ONE48";
|
|
output [29:0] ACOUT;
|
|
output [17:0] BCOUT;
|
|
output CARRYCASCOUT;
|
|
output [3:0] CARRYOUT;
|
|
output MULTSIGNOUT;
|
|
output OVERFLOW;
|
|
output [47:0] P;
|
|
output PATTERNBDETECT;
|
|
output PATTERNDETECT;
|
|
output [47:0] PCOUT;
|
|
output UNDERFLOW;
|
|
input [29:0] A;
|
|
input [29:0] ACIN;
|
|
input [3:0] ALUMODE;
|
|
input [17:0] B;
|
|
input [17:0] BCIN;
|
|
input [47:0] C;
|
|
input CARRYCASCIN;
|
|
input CARRYIN;
|
|
input [2:0] CARRYINSEL;
|
|
input CEA1;
|
|
input CEA2;
|
|
input CEALUMODE;
|
|
input CEB1;
|
|
input CEB2;
|
|
input CEC;
|
|
input CECARRYIN;
|
|
input CECTRL;
|
|
input CEM;
|
|
input CEMULTCARRYIN;
|
|
input CEP;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input MULTSIGNIN;
|
|
input [6:0] OPMODE;
|
|
input [47:0] PCIN;
|
|
input RSTA;
|
|
input RSTALLCARRYIN;
|
|
input RSTALUMODE;
|
|
input RSTB;
|
|
input RSTC;
|
|
input RSTCTRL;
|
|
input RSTM;
|
|
input RSTP;
|
|
endmodule
|
|
|
|
module DSP48E2(ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, XOROUT, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL
|
|
, CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CED, CEINMODE, CEM, CEP, CLK, D, INMODE, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN
|
|
, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP);
|
|
parameter integer ACASCREG = 1;
|
|
parameter integer ADREG = 1;
|
|
parameter integer ALUMODEREG = 1;
|
|
parameter AMULTSEL = "A";
|
|
parameter integer AREG = 1;
|
|
parameter AUTORESET_PATDET = "NO_RESET";
|
|
parameter AUTORESET_PRIORITY = "RESET";
|
|
parameter A_INPUT = "DIRECT";
|
|
parameter integer BCASCREG = 1;
|
|
parameter BMULTSEL = "B";
|
|
parameter integer BREG = 1;
|
|
parameter B_INPUT = "DIRECT";
|
|
parameter integer CARRYINREG = 1;
|
|
parameter integer CARRYINSELREG = 1;
|
|
parameter integer CREG = 1;
|
|
parameter integer DREG = 1;
|
|
parameter integer INMODEREG = 1;
|
|
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000;
|
|
parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [4:0] IS_INMODE_INVERTED = 5'b00000;
|
|
parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000;
|
|
parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTA_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTB_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTC_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTD_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTM_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RSTP_INVERTED = 1'b0;
|
|
parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
|
|
parameter integer MREG = 1;
|
|
parameter integer OPMODEREG = 1;
|
|
parameter [47:0] PATTERN = 48'h000000000000;
|
|
parameter PREADDINSEL = "A";
|
|
parameter integer PREG = 1;
|
|
parameter [47:0] RND = 48'h000000000000;
|
|
parameter SEL_MASK = "MASK";
|
|
parameter SEL_PATTERN = "PATTERN";
|
|
parameter USE_MULT = "MULTIPLY";
|
|
parameter USE_PATTERN_DETECT = "NO_PATDET";
|
|
parameter USE_SIMD = "ONE48";
|
|
parameter USE_WIDEXOR = "FALSE";
|
|
parameter XORSIMD = "XOR24_48_96";
|
|
output [29:0] ACOUT;
|
|
output [17:0] BCOUT;
|
|
output CARRYCASCOUT;
|
|
output [3:0] CARRYOUT;
|
|
output MULTSIGNOUT;
|
|
output OVERFLOW;
|
|
output [47:0] P;
|
|
output PATTERNBDETECT;
|
|
output PATTERNDETECT;
|
|
output [47:0] PCOUT;
|
|
output UNDERFLOW;
|
|
output [7:0] XOROUT;
|
|
input [29:0] A;
|
|
input [29:0] ACIN;
|
|
(* invertible_pin = "IS_ALUMODE_INVERTED" *)
|
|
input [3:0] ALUMODE;
|
|
input [17:0] B;
|
|
input [17:0] BCIN;
|
|
input [47:0] C;
|
|
input CARRYCASCIN;
|
|
(* invertible_pin = "IS_CARRYIN_INVERTED" *)
|
|
input CARRYIN;
|
|
input [2:0] CARRYINSEL;
|
|
input CEA1;
|
|
input CEA2;
|
|
input CEAD;
|
|
input CEALUMODE;
|
|
input CEB1;
|
|
input CEB2;
|
|
input CEC;
|
|
input CECARRYIN;
|
|
input CECTRL;
|
|
input CED;
|
|
input CEINMODE;
|
|
input CEM;
|
|
input CEP;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
input [26:0] D;
|
|
(* invertible_pin = "IS_INMODE_INVERTED" *)
|
|
input [4:0] INMODE;
|
|
input MULTSIGNIN;
|
|
(* invertible_pin = "IS_OPMODE_INVERTED" *)
|
|
input [8:0] OPMODE;
|
|
input [47:0] PCIN;
|
|
(* invertible_pin = "IS_RSTA_INVERTED" *)
|
|
input RSTA;
|
|
(* invertible_pin = "IS_RSTALLCARRYIN_INVERTED" *)
|
|
input RSTALLCARRYIN;
|
|
(* invertible_pin = "IS_RSTALUMODE_INVERTED" *)
|
|
input RSTALUMODE;
|
|
(* invertible_pin = "IS_RSTB_INVERTED" *)
|
|
input RSTB;
|
|
(* invertible_pin = "IS_RSTC_INVERTED" *)
|
|
input RSTC;
|
|
(* invertible_pin = "IS_RSTCTRL_INVERTED" *)
|
|
input RSTCTRL;
|
|
(* invertible_pin = "IS_RSTD_INVERTED" *)
|
|
input RSTD;
|
|
(* invertible_pin = "IS_RSTINMODE_INVERTED" *)
|
|
input RSTINMODE;
|
|
(* invertible_pin = "IS_RSTM_INVERTED" *)
|
|
input RSTM;
|
|
(* invertible_pin = "IS_RSTP_INVERTED" *)
|
|
input RSTP;
|
|
endmodule
|
|
|
|
module FDDRCPE(C0, C1, CE, D0, D1, CLR, PRE, Q);
|
|
parameter INIT = 1'b0;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
input D0;
|
|
input D1;
|
|
input CLR;
|
|
input PRE;
|
|
output Q;
|
|
endmodule
|
|
|
|
module FDDRRSE(Q, C0, C1, CE, D0, D1, R, S);
|
|
parameter INIT = 1'b0;
|
|
output Q;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
input D0;
|
|
input D1;
|
|
input R;
|
|
input S;
|
|
endmodule
|
|
|
|
module IFDDRCPE(Q0, Q1, C0, C1, CE, CLR, D, PRE);
|
|
output Q0;
|
|
output Q1;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
input CLR;
|
|
(* iopad_external_pin *)
|
|
input D;
|
|
input PRE;
|
|
endmodule
|
|
|
|
module IFDDRRSE(Q0, Q1, C0, C1, CE, D, R, S);
|
|
output Q0;
|
|
output Q1;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
(* iopad_external_pin *)
|
|
input D;
|
|
input R;
|
|
input S;
|
|
endmodule
|
|
|
|
module OFDDRCPE(Q, C0, C1, CE, CLR, D0, D1, PRE);
|
|
(* iopad_external_pin *)
|
|
output Q;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
input CLR;
|
|
input D0;
|
|
input D1;
|
|
input PRE;
|
|
endmodule
|
|
|
|
module OFDDRRSE(Q, C0, C1, CE, D0, D1, R, S);
|
|
(* iopad_external_pin *)
|
|
output Q;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
input D0;
|
|
input D1;
|
|
input R;
|
|
input S;
|
|
endmodule
|
|
|
|
module OFDDRTCPE(O, C0, C1, CE, CLR, D0, D1, PRE, T);
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
input CLR;
|
|
input D0;
|
|
input D1;
|
|
input PRE;
|
|
input T;
|
|
endmodule
|
|
|
|
module OFDDRTRSE(O, C0, C1, CE, D0, D1, R, S, T);
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
input D0;
|
|
input D1;
|
|
input R;
|
|
input S;
|
|
input T;
|
|
endmodule
|
|
|
|
module IDDR2(Q0, Q1, C0, C1, CE, D, R, S);
|
|
parameter DDR_ALIGNMENT = "NONE";
|
|
parameter [0:0] INIT_Q0 = 1'b0;
|
|
parameter [0:0] INIT_Q1 = 1'b0;
|
|
parameter SRTYPE = "SYNC";
|
|
output Q0;
|
|
output Q1;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
input D;
|
|
input R;
|
|
input S;
|
|
endmodule
|
|
|
|
module ODDR2(Q, C0, C1, CE, D0, D1, R, S);
|
|
parameter DDR_ALIGNMENT = "NONE";
|
|
parameter [0:0] INIT = 1'b0;
|
|
parameter SRTYPE = "SYNC";
|
|
output Q;
|
|
(* clkbuf_sink *)
|
|
input C0;
|
|
(* clkbuf_sink *)
|
|
input C1;
|
|
input CE;
|
|
input D0;
|
|
input D1;
|
|
input R;
|
|
input S;
|
|
endmodule
|
|
|
|
module IDDR(Q1, Q2, C, CE, D, R, S);
|
|
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
|
|
parameter INIT_Q1 = 1'b0;
|
|
parameter INIT_Q2 = 1'b0;
|
|
parameter [0:0] IS_C_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D_INVERTED = 1'b0;
|
|
parameter SRTYPE = "SYNC";
|
|
parameter MSGON = "TRUE";
|
|
parameter XON = "TRUE";
|
|
output Q1;
|
|
output Q2;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_C_INVERTED" *)
|
|
input C;
|
|
input CE;
|
|
(* invertible_pin = "IS_D_INVERTED" *)
|
|
input D;
|
|
input R;
|
|
input S;
|
|
endmodule
|
|
|
|
module IDDR_2CLK(Q1, Q2, C, CB, CE, D, R, S);
|
|
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
|
|
parameter INIT_Q1 = 1'b0;
|
|
parameter INIT_Q2 = 1'b0;
|
|
parameter [0:0] IS_CB_INVERTED = 1'b0;
|
|
parameter [0:0] IS_C_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D_INVERTED = 1'b0;
|
|
parameter SRTYPE = "SYNC";
|
|
output Q1;
|
|
output Q2;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_C_INVERTED" *)
|
|
input C;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CB_INVERTED" *)
|
|
input CB;
|
|
input CE;
|
|
(* invertible_pin = "IS_D_INVERTED" *)
|
|
input D;
|
|
input R;
|
|
input S;
|
|
endmodule
|
|
|
|
module ODDR(Q, C, CE, D1, D2, R, S);
|
|
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
|
|
parameter INIT = 1'b0;
|
|
parameter [0:0] IS_C_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D2_INVERTED = 1'b0;
|
|
parameter SRTYPE = "SYNC";
|
|
parameter MSGON = "TRUE";
|
|
parameter XON = "TRUE";
|
|
output Q;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_C_INVERTED" *)
|
|
input C;
|
|
input CE;
|
|
(* invertible_pin = "IS_D1_INVERTED" *)
|
|
input D1;
|
|
(* invertible_pin = "IS_D2_INVERTED" *)
|
|
input D2;
|
|
input R;
|
|
input S;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module IDELAYCTRL(RDY, REFCLK, RST);
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
output RDY;
|
|
(* clkbuf_sink *)
|
|
input REFCLK;
|
|
input RST;
|
|
endmodule
|
|
|
|
module IDELAY(O, C, CE, I, INC, RST);
|
|
parameter IOBDELAY_TYPE = "DEFAULT";
|
|
parameter integer IOBDELAY_VALUE = 0;
|
|
output O;
|
|
(* clkbuf_sink *)
|
|
input C;
|
|
input CE;
|
|
input I;
|
|
input INC;
|
|
input RST;
|
|
endmodule
|
|
|
|
module ISERDES(O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKDIV, D, DLYCE, DLYINC, DLYRST, OCLK, REV, SHIFTIN1
|
|
, SHIFTIN2, SR);
|
|
parameter BITSLIP_ENABLE = "FALSE";
|
|
parameter DATA_RATE = "DDR";
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter [0:0] INIT_Q1 = 1'b0;
|
|
parameter [0:0] INIT_Q2 = 1'b0;
|
|
parameter [0:0] INIT_Q3 = 1'b0;
|
|
parameter [0:0] INIT_Q4 = 1'b0;
|
|
parameter INTERFACE_TYPE = "MEMORY";
|
|
parameter IOBDELAY = "NONE";
|
|
parameter IOBDELAY_TYPE = "DEFAULT";
|
|
parameter integer IOBDELAY_VALUE = 0;
|
|
parameter integer NUM_CE = 2;
|
|
parameter SERDES_MODE = "MASTER";
|
|
parameter integer SIM_DELAY_D = 0;
|
|
parameter integer SIM_SETUP_D_CLK = 0;
|
|
parameter integer SIM_HOLD_D_CLK = 0;
|
|
parameter [0:0] SRVAL_Q1 = 1'b0;
|
|
parameter [0:0] SRVAL_Q2 = 1'b0;
|
|
parameter [0:0] SRVAL_Q3 = 1'b0;
|
|
parameter [0:0] SRVAL_Q4 = 1'b0;
|
|
output O;
|
|
output Q1;
|
|
output Q2;
|
|
output Q3;
|
|
output Q4;
|
|
output Q5;
|
|
output Q6;
|
|
output SHIFTOUT1;
|
|
output SHIFTOUT2;
|
|
input BITSLIP;
|
|
input CE1;
|
|
input CE2;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
(* clkbuf_sink *)
|
|
input CLKDIV;
|
|
input D;
|
|
input DLYCE;
|
|
input DLYINC;
|
|
input DLYRST;
|
|
(* clkbuf_sink *)
|
|
input OCLK;
|
|
input REV;
|
|
input SHIFTIN1;
|
|
input SHIFTIN2;
|
|
input SR;
|
|
endmodule
|
|
|
|
module OSERDES(OQ, SHIFTOUT1, SHIFTOUT2, TQ, CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4
|
|
, TCE);
|
|
parameter DATA_RATE_OQ = "DDR";
|
|
parameter DATA_RATE_TQ = "DDR";
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter [0:0] INIT_OQ = 1'b0;
|
|
parameter [0:0] INIT_TQ = 1'b0;
|
|
parameter SERDES_MODE = "MASTER";
|
|
parameter [0:0] SRVAL_OQ = 1'b0;
|
|
parameter [0:0] SRVAL_TQ = 1'b0;
|
|
parameter integer TRISTATE_WIDTH = 4;
|
|
output OQ;
|
|
output SHIFTOUT1;
|
|
output SHIFTOUT2;
|
|
output TQ;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
(* clkbuf_sink *)
|
|
input CLKDIV;
|
|
input D1;
|
|
input D2;
|
|
input D3;
|
|
input D4;
|
|
input D5;
|
|
input D6;
|
|
input OCE;
|
|
input REV;
|
|
input SHIFTIN1;
|
|
input SHIFTIN2;
|
|
input SR;
|
|
input T1;
|
|
input T2;
|
|
input T3;
|
|
input T4;
|
|
input TCE;
|
|
endmodule
|
|
|
|
module IODELAY(DATAOUT, C, CE, DATAIN, IDATAIN, INC, ODATAIN, RST, T);
|
|
parameter DELAY_SRC = "I";
|
|
parameter HIGH_PERFORMANCE_MODE = "TRUE";
|
|
parameter IDELAY_TYPE = "DEFAULT";
|
|
parameter integer IDELAY_VALUE = 0;
|
|
parameter integer ODELAY_VALUE = 0;
|
|
parameter real REFCLK_FREQUENCY = 200.0;
|
|
parameter SIGNAL_PATTERN = "DATA";
|
|
output DATAOUT;
|
|
(* clkbuf_sink *)
|
|
input C;
|
|
input CE;
|
|
input DATAIN;
|
|
input IDATAIN;
|
|
input INC;
|
|
input ODATAIN;
|
|
input RST;
|
|
input T;
|
|
endmodule
|
|
|
|
module ISERDES_NODELAY(Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2);
|
|
parameter BITSLIP_ENABLE = "FALSE";
|
|
parameter DATA_RATE = "DDR";
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter INIT_Q1 = 1'b0;
|
|
parameter INIT_Q2 = 1'b0;
|
|
parameter INIT_Q3 = 1'b0;
|
|
parameter INIT_Q4 = 1'b0;
|
|
parameter INTERFACE_TYPE = "MEMORY";
|
|
parameter integer NUM_CE = 2;
|
|
parameter SERDES_MODE = "MASTER";
|
|
output Q1;
|
|
output Q2;
|
|
output Q3;
|
|
output Q4;
|
|
output Q5;
|
|
output Q6;
|
|
output SHIFTOUT1;
|
|
output SHIFTOUT2;
|
|
input BITSLIP;
|
|
input CE1;
|
|
input CE2;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
(* clkbuf_sink *)
|
|
input CLKDIV;
|
|
input D;
|
|
(* clkbuf_sink *)
|
|
input OCLK;
|
|
input RST;
|
|
input SHIFTIN1;
|
|
input SHIFTIN2;
|
|
endmodule
|
|
|
|
module IODELAYE1(CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CLKIN, CNTVALUEIN, DATAIN, IDATAIN, INC, ODATAIN, RST, T);
|
|
parameter CINVCTRL_SEL = "FALSE";
|
|
parameter DELAY_SRC = "I";
|
|
parameter HIGH_PERFORMANCE_MODE = "FALSE";
|
|
parameter IDELAY_TYPE = "DEFAULT";
|
|
parameter integer IDELAY_VALUE = 0;
|
|
parameter ODELAY_TYPE = "FIXED";
|
|
parameter integer ODELAY_VALUE = 0;
|
|
parameter real REFCLK_FREQUENCY = 200.0;
|
|
parameter SIGNAL_PATTERN = "DATA";
|
|
output [4:0] CNTVALUEOUT;
|
|
output DATAOUT;
|
|
(* clkbuf_sink *)
|
|
input C;
|
|
input CE;
|
|
input CINVCTRL;
|
|
input CLKIN;
|
|
input [4:0] CNTVALUEIN;
|
|
input DATAIN;
|
|
input IDATAIN;
|
|
input INC;
|
|
input ODATAIN;
|
|
input RST;
|
|
input T;
|
|
endmodule
|
|
|
|
module ISERDESE1(O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, DDLY, DYNCLKDIVSEL, DYNCLKSEL, OCLK, OFB
|
|
, RST, SHIFTIN1, SHIFTIN2);
|
|
parameter DATA_RATE = "DDR";
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter DYN_CLKDIV_INV_EN = "FALSE";
|
|
parameter DYN_CLK_INV_EN = "FALSE";
|
|
parameter [0:0] INIT_Q1 = 1'b0;
|
|
parameter [0:0] INIT_Q2 = 1'b0;
|
|
parameter [0:0] INIT_Q3 = 1'b0;
|
|
parameter [0:0] INIT_Q4 = 1'b0;
|
|
parameter INTERFACE_TYPE = "MEMORY";
|
|
parameter integer NUM_CE = 2;
|
|
parameter IOBDELAY = "NONE";
|
|
parameter OFB_USED = "FALSE";
|
|
parameter SERDES_MODE = "MASTER";
|
|
parameter [0:0] SRVAL_Q1 = 1'b0;
|
|
parameter [0:0] SRVAL_Q2 = 1'b0;
|
|
parameter [0:0] SRVAL_Q3 = 1'b0;
|
|
parameter [0:0] SRVAL_Q4 = 1'b0;
|
|
output O;
|
|
output Q1;
|
|
output Q2;
|
|
output Q3;
|
|
output Q4;
|
|
output Q5;
|
|
output Q6;
|
|
output SHIFTOUT1;
|
|
output SHIFTOUT2;
|
|
input BITSLIP;
|
|
input CE1;
|
|
input CE2;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
(* clkbuf_sink *)
|
|
input CLKB;
|
|
(* clkbuf_sink *)
|
|
input CLKDIV;
|
|
input D;
|
|
input DDLY;
|
|
input DYNCLKDIVSEL;
|
|
input DYNCLKSEL;
|
|
(* clkbuf_sink *)
|
|
input OCLK;
|
|
input OFB;
|
|
input RST;
|
|
input SHIFTIN1;
|
|
input SHIFTIN2;
|
|
endmodule
|
|
|
|
module OSERDESE1(OCBEXTEND, OFB, OQ, SHIFTOUT1, SHIFTOUT2, TFB, TQ, CLK, CLKDIV, CLKPERF, CLKPERFDELAY, D1, D2, D3, D4, D5, D6, OCE, ODV, RST, SHIFTIN1
|
|
, SHIFTIN2, T1, T2, T3, T4, TCE, WC);
|
|
parameter DATA_RATE_OQ = "DDR";
|
|
parameter DATA_RATE_TQ = "DDR";
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter integer DDR3_DATA = 1;
|
|
parameter [0:0] INIT_OQ = 1'b0;
|
|
parameter [0:0] INIT_TQ = 1'b0;
|
|
parameter INTERFACE_TYPE = "DEFAULT";
|
|
parameter integer ODELAY_USED = 0;
|
|
parameter SERDES_MODE = "MASTER";
|
|
parameter [0:0] SRVAL_OQ = 1'b0;
|
|
parameter [0:0] SRVAL_TQ = 1'b0;
|
|
parameter integer TRISTATE_WIDTH = 4;
|
|
output OCBEXTEND;
|
|
output OFB;
|
|
output OQ;
|
|
output SHIFTOUT1;
|
|
output SHIFTOUT2;
|
|
output TFB;
|
|
output TQ;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
(* clkbuf_sink *)
|
|
input CLKDIV;
|
|
input CLKPERF;
|
|
input CLKPERFDELAY;
|
|
input D1;
|
|
input D2;
|
|
input D3;
|
|
input D4;
|
|
input D5;
|
|
input D6;
|
|
input OCE;
|
|
input ODV;
|
|
input RST;
|
|
input SHIFTIN1;
|
|
input SHIFTIN2;
|
|
input T1;
|
|
input T2;
|
|
input T3;
|
|
input T4;
|
|
input TCE;
|
|
input WC;
|
|
endmodule
|
|
|
|
module IDELAYE2(CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN, REGRST);
|
|
parameter CINVCTRL_SEL = "FALSE";
|
|
parameter DELAY_SRC = "IDATAIN";
|
|
parameter HIGH_PERFORMANCE_MODE = "FALSE";
|
|
parameter IDELAY_TYPE = "FIXED";
|
|
parameter integer IDELAY_VALUE = 0;
|
|
parameter [0:0] IS_C_INVERTED = 1'b0;
|
|
parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
|
|
parameter PIPE_SEL = "FALSE";
|
|
parameter real REFCLK_FREQUENCY = 200.0;
|
|
parameter SIGNAL_PATTERN = "DATA";
|
|
parameter integer SIM_DELAY_D = 0;
|
|
output [4:0] CNTVALUEOUT;
|
|
output DATAOUT;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_C_INVERTED" *)
|
|
input C;
|
|
input CE;
|
|
input CINVCTRL;
|
|
input [4:0] CNTVALUEIN;
|
|
(* invertible_pin = "IS_DATAIN_INVERTED" *)
|
|
input DATAIN;
|
|
(* invertible_pin = "IS_IDATAIN_INVERTED" *)
|
|
input IDATAIN;
|
|
input INC;
|
|
input LD;
|
|
input LDPIPEEN;
|
|
input REGRST;
|
|
endmodule
|
|
|
|
module ODELAYE2(CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN, REGRST);
|
|
parameter CINVCTRL_SEL = "FALSE";
|
|
parameter DELAY_SRC = "ODATAIN";
|
|
parameter HIGH_PERFORMANCE_MODE = "FALSE";
|
|
parameter [0:0] IS_C_INVERTED = 1'b0;
|
|
parameter [0:0] IS_ODATAIN_INVERTED = 1'b0;
|
|
parameter ODELAY_TYPE = "FIXED";
|
|
parameter integer ODELAY_VALUE = 0;
|
|
parameter PIPE_SEL = "FALSE";
|
|
parameter real REFCLK_FREQUENCY = 200.0;
|
|
parameter SIGNAL_PATTERN = "DATA";
|
|
parameter integer SIM_DELAY_D = 0;
|
|
output [4:0] CNTVALUEOUT;
|
|
output DATAOUT;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_C_INVERTED" *)
|
|
input C;
|
|
input CE;
|
|
input CINVCTRL;
|
|
input CLKIN;
|
|
input [4:0] CNTVALUEIN;
|
|
input INC;
|
|
input LD;
|
|
input LDPIPEEN;
|
|
(* invertible_pin = "IS_ODATAIN_INVERTED" *)
|
|
input ODATAIN;
|
|
input REGRST;
|
|
endmodule
|
|
|
|
module ISERDESE2(O, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, SHIFTOUT1, SHIFTOUT2, BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, CLKDIVP, D, DDLY, DYNCLKDIVSEL
|
|
, DYNCLKSEL, OCLK, OCLKB, OFB, RST, SHIFTIN1, SHIFTIN2);
|
|
parameter DATA_RATE = "DDR";
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter DYN_CLKDIV_INV_EN = "FALSE";
|
|
parameter DYN_CLK_INV_EN = "FALSE";
|
|
parameter [0:0] INIT_Q1 = 1'b0;
|
|
parameter [0:0] INIT_Q2 = 1'b0;
|
|
parameter [0:0] INIT_Q3 = 1'b0;
|
|
parameter [0:0] INIT_Q4 = 1'b0;
|
|
parameter INTERFACE_TYPE = "MEMORY";
|
|
parameter IOBDELAY = "NONE";
|
|
parameter [0:0] IS_CLKB_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D_INVERTED = 1'b0;
|
|
parameter [0:0] IS_OCLKB_INVERTED = 1'b0;
|
|
parameter [0:0] IS_OCLK_INVERTED = 1'b0;
|
|
parameter integer NUM_CE = 2;
|
|
parameter OFB_USED = "FALSE";
|
|
parameter SERDES_MODE = "MASTER";
|
|
parameter [0:0] SRVAL_Q1 = 1'b0;
|
|
parameter [0:0] SRVAL_Q2 = 1'b0;
|
|
parameter [0:0] SRVAL_Q3 = 1'b0;
|
|
parameter [0:0] SRVAL_Q4 = 1'b0;
|
|
output O;
|
|
output Q1;
|
|
output Q2;
|
|
output Q3;
|
|
output Q4;
|
|
output Q5;
|
|
output Q6;
|
|
output Q7;
|
|
output Q8;
|
|
output SHIFTOUT1;
|
|
output SHIFTOUT2;
|
|
input BITSLIP;
|
|
input CE1;
|
|
input CE2;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLKB_INVERTED" *)
|
|
input CLKB;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLKDIV_INVERTED" *)
|
|
input CLKDIV;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLKDIVP_INVERTED" *)
|
|
input CLKDIVP;
|
|
(* invertible_pin = "IS_D_INVERTED" *)
|
|
input D;
|
|
input DDLY;
|
|
input DYNCLKDIVSEL;
|
|
input DYNCLKSEL;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_OCLK_INVERTED" *)
|
|
input OCLK;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_OCLKB_INVERTED" *)
|
|
input OCLKB;
|
|
input OFB;
|
|
input RST;
|
|
input SHIFTIN1;
|
|
input SHIFTIN2;
|
|
endmodule
|
|
|
|
module OSERDESE2(OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ, CLK, CLKDIV, D1, D2, D3, D4, D5, D6, D7, D8, OCE, RST, SHIFTIN1, SHIFTIN2
|
|
, T1, T2, T3, T4, TBYTEIN, TCE);
|
|
parameter DATA_RATE_OQ = "DDR";
|
|
parameter DATA_RATE_TQ = "DDR";
|
|
parameter integer DATA_WIDTH = 4;
|
|
parameter [0:0] INIT_OQ = 1'b0;
|
|
parameter [0:0] INIT_TQ = 1'b0;
|
|
parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D3_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D4_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D5_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D6_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D7_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D8_INVERTED = 1'b0;
|
|
parameter [0:0] IS_T1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_T2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_T3_INVERTED = 1'b0;
|
|
parameter [0:0] IS_T4_INVERTED = 1'b0;
|
|
parameter SERDES_MODE = "MASTER";
|
|
parameter [0:0] SRVAL_OQ = 1'b0;
|
|
parameter [0:0] SRVAL_TQ = 1'b0;
|
|
parameter TBYTE_CTL = "FALSE";
|
|
parameter TBYTE_SRC = "FALSE";
|
|
parameter integer TRISTATE_WIDTH = 4;
|
|
output OFB;
|
|
output OQ;
|
|
output SHIFTOUT1;
|
|
output SHIFTOUT2;
|
|
output TBYTEOUT;
|
|
output TFB;
|
|
output TQ;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLKDIV_INVERTED" *)
|
|
input CLKDIV;
|
|
(* invertible_pin = "IS_D1_INVERTED" *)
|
|
input D1;
|
|
(* invertible_pin = "IS_D2_INVERTED" *)
|
|
input D2;
|
|
(* invertible_pin = "IS_D3_INVERTED" *)
|
|
input D3;
|
|
(* invertible_pin = "IS_D4_INVERTED" *)
|
|
input D4;
|
|
(* invertible_pin = "IS_D5_INVERTED" *)
|
|
input D5;
|
|
(* invertible_pin = "IS_D6_INVERTED" *)
|
|
input D6;
|
|
(* invertible_pin = "IS_D7_INVERTED" *)
|
|
input D7;
|
|
(* invertible_pin = "IS_D8_INVERTED" *)
|
|
input D8;
|
|
input OCE;
|
|
input RST;
|
|
input SHIFTIN1;
|
|
input SHIFTIN2;
|
|
(* invertible_pin = "IS_T1_INVERTED" *)
|
|
input T1;
|
|
(* invertible_pin = "IS_T2_INVERTED" *)
|
|
input T2;
|
|
(* invertible_pin = "IS_T3_INVERTED" *)
|
|
input T3;
|
|
(* invertible_pin = "IS_T4_INVERTED" *)
|
|
input T4;
|
|
input TBYTEIN;
|
|
input TCE;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module PHASER_IN(FINEOVERFLOW, ICLK, ICLKDIV, ISERDESRST, RCLK, COUNTERREADVAL, COUNTERLOADEN, COUNTERREADEN, DIVIDERST, EDGEADV, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK, RST, SYNCIN, SYSCLK, RANKSEL, COUNTERLOADVAL);
|
|
parameter integer CLKOUT_DIV = 4;
|
|
parameter DQS_BIAS_MODE = "FALSE";
|
|
parameter EN_ISERDES_RST = "FALSE";
|
|
parameter integer FINE_DELAY = 0;
|
|
parameter FREQ_REF_DIV = "NONE";
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real MEMREFCLK_PERIOD = 0.000;
|
|
parameter OUTPUT_CLK_SRC = "PHASE_REF";
|
|
parameter real PHASEREFCLK_PERIOD = 0.000;
|
|
parameter real REFCLK_PERIOD = 0.000;
|
|
parameter integer SEL_CLK_OFFSET = 5;
|
|
parameter SYNC_IN_DIV_RST = "FALSE";
|
|
output FINEOVERFLOW;
|
|
output ICLK;
|
|
output ICLKDIV;
|
|
output ISERDESRST;
|
|
output RCLK;
|
|
output [5:0] COUNTERREADVAL;
|
|
input COUNTERLOADEN;
|
|
input COUNTERREADEN;
|
|
input DIVIDERST;
|
|
input EDGEADV;
|
|
input FINEENABLE;
|
|
input FINEINC;
|
|
input FREQREFCLK;
|
|
input MEMREFCLK;
|
|
input PHASEREFCLK;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
input SYNCIN;
|
|
input SYSCLK;
|
|
input [1:0] RANKSEL;
|
|
input [5:0] COUNTERLOADVAL;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module PHASER_IN_PHY(DQSFOUND, DQSOUTOFRANGE, FINEOVERFLOW, ICLK, ICLKDIV, ISERDESRST, PHASELOCKED, RCLK, WRENABLE, COUNTERREADVAL, BURSTPENDINGPHY, COUNTERLOADEN, COUNTERREADEN, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK, RST, RSTDQSFIND, SYNCIN
|
|
, SYSCLK, ENCALIBPHY, RANKSELPHY, COUNTERLOADVAL);
|
|
parameter BURST_MODE = "FALSE";
|
|
parameter integer CLKOUT_DIV = 4;
|
|
parameter [0:0] DQS_AUTO_RECAL = 1'b1;
|
|
parameter DQS_BIAS_MODE = "FALSE";
|
|
parameter [2:0] DQS_FIND_PATTERN = 3'b001;
|
|
parameter integer FINE_DELAY = 0;
|
|
parameter FREQ_REF_DIV = "NONE";
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real MEMREFCLK_PERIOD = 0.000;
|
|
parameter OUTPUT_CLK_SRC = "PHASE_REF";
|
|
parameter real PHASEREFCLK_PERIOD = 0.000;
|
|
parameter real REFCLK_PERIOD = 0.000;
|
|
parameter integer SEL_CLK_OFFSET = 5;
|
|
parameter SYNC_IN_DIV_RST = "FALSE";
|
|
parameter WR_CYCLES = "FALSE";
|
|
output DQSFOUND;
|
|
output DQSOUTOFRANGE;
|
|
output FINEOVERFLOW;
|
|
output ICLK;
|
|
output ICLKDIV;
|
|
output ISERDESRST;
|
|
output PHASELOCKED;
|
|
output RCLK;
|
|
output WRENABLE;
|
|
output [5:0] COUNTERREADVAL;
|
|
input BURSTPENDINGPHY;
|
|
input COUNTERLOADEN;
|
|
input COUNTERREADEN;
|
|
input FINEENABLE;
|
|
input FINEINC;
|
|
input FREQREFCLK;
|
|
input MEMREFCLK;
|
|
input PHASEREFCLK;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
input RSTDQSFIND;
|
|
input SYNCIN;
|
|
input SYSCLK;
|
|
input [1:0] ENCALIBPHY;
|
|
input [1:0] RANKSELPHY;
|
|
input [5:0] COUNTERLOADVAL;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module PHASER_OUT(COARSEOVERFLOW, FINEOVERFLOW, OCLK, OCLKDELAYED, OCLKDIV, OSERDESRST, COUNTERREADVAL, COARSEENABLE, COARSEINC, COUNTERLOADEN, COUNTERREADEN, DIVIDERST, EDGEADV, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK, RST, SELFINEOCLKDELAY, SYNCIN
|
|
, SYSCLK, COUNTERLOADVAL);
|
|
parameter integer CLKOUT_DIV = 4;
|
|
parameter COARSE_BYPASS = "FALSE";
|
|
parameter integer COARSE_DELAY = 0;
|
|
parameter EN_OSERDES_RST = "FALSE";
|
|
parameter integer FINE_DELAY = 0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real MEMREFCLK_PERIOD = 0.000;
|
|
parameter OCLKDELAY_INV = "FALSE";
|
|
parameter integer OCLK_DELAY = 0;
|
|
parameter OUTPUT_CLK_SRC = "PHASE_REF";
|
|
parameter real PHASEREFCLK_PERIOD = 0.000;
|
|
parameter [2:0] PO = 3'b000;
|
|
parameter real REFCLK_PERIOD = 0.000;
|
|
parameter SYNC_IN_DIV_RST = "FALSE";
|
|
output COARSEOVERFLOW;
|
|
output FINEOVERFLOW;
|
|
output OCLK;
|
|
output OCLKDELAYED;
|
|
output OCLKDIV;
|
|
output OSERDESRST;
|
|
output [8:0] COUNTERREADVAL;
|
|
input COARSEENABLE;
|
|
input COARSEINC;
|
|
input COUNTERLOADEN;
|
|
input COUNTERREADEN;
|
|
input DIVIDERST;
|
|
input EDGEADV;
|
|
input FINEENABLE;
|
|
input FINEINC;
|
|
input FREQREFCLK;
|
|
input MEMREFCLK;
|
|
input PHASEREFCLK;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
input SELFINEOCLKDELAY;
|
|
input SYNCIN;
|
|
input SYSCLK;
|
|
input [8:0] COUNTERLOADVAL;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module PHASER_OUT_PHY(COARSEOVERFLOW, FINEOVERFLOW, OCLK, OCLKDELAYED, OCLKDIV, OSERDESRST, RDENABLE, CTSBUS, DQSBUS, DTSBUS, COUNTERREADVAL, BURSTPENDINGPHY, COARSEENABLE, COARSEINC, COUNTERLOADEN, COUNTERREADEN, FINEENABLE, FINEINC, FREQREFCLK, MEMREFCLK, PHASEREFCLK
|
|
, RST, SELFINEOCLKDELAY, SYNCIN, SYSCLK, ENCALIBPHY, COUNTERLOADVAL);
|
|
parameter integer CLKOUT_DIV = 4;
|
|
parameter COARSE_BYPASS = "FALSE";
|
|
parameter integer COARSE_DELAY = 0;
|
|
parameter DATA_CTL_N = "FALSE";
|
|
parameter DATA_RD_CYCLES = "FALSE";
|
|
parameter integer FINE_DELAY = 0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real MEMREFCLK_PERIOD = 0.000;
|
|
parameter OCLKDELAY_INV = "FALSE";
|
|
parameter integer OCLK_DELAY = 0;
|
|
parameter OUTPUT_CLK_SRC = "PHASE_REF";
|
|
parameter real PHASEREFCLK_PERIOD = 0.000;
|
|
parameter [2:0] PO = 3'b000;
|
|
parameter real REFCLK_PERIOD = 0.000;
|
|
parameter SYNC_IN_DIV_RST = "FALSE";
|
|
output COARSEOVERFLOW;
|
|
output FINEOVERFLOW;
|
|
output OCLK;
|
|
output OCLKDELAYED;
|
|
output OCLKDIV;
|
|
output OSERDESRST;
|
|
output RDENABLE;
|
|
output [1:0] CTSBUS;
|
|
output [1:0] DQSBUS;
|
|
output [1:0] DTSBUS;
|
|
output [8:0] COUNTERREADVAL;
|
|
input BURSTPENDINGPHY;
|
|
input COARSEENABLE;
|
|
input COARSEINC;
|
|
input COUNTERLOADEN;
|
|
input COUNTERREADEN;
|
|
input FINEENABLE;
|
|
input FINEINC;
|
|
input FREQREFCLK;
|
|
input MEMREFCLK;
|
|
input PHASEREFCLK;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
input SELFINEOCLKDELAY;
|
|
input SYNCIN;
|
|
input SYSCLK;
|
|
input [1:0] ENCALIBPHY;
|
|
input [8:0] COUNTERLOADVAL;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module PHASER_REF(LOCKED, CLKIN, PWRDWN, RST);
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
output LOCKED;
|
|
input CLKIN;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module PHY_CONTROL(PHYCTLALMOSTFULL, PHYCTLEMPTY, PHYCTLFULL, PHYCTLREADY, INRANKA, INRANKB, INRANKC, INRANKD, PCENABLECALIB, AUXOUTPUT, INBURSTPENDING, OUTBURSTPENDING, MEMREFCLK, PHYCLK, PHYCTLMSTREMPTY, PHYCTLWRENABLE, PLLLOCK, READCALIBENABLE, REFDLLLOCK, RESET, SYNCIN
|
|
, WRITECALIBENABLE, PHYCTLWD);
|
|
parameter integer AO_TOGGLE = 0;
|
|
parameter [3:0] AO_WRLVL_EN = 4'b0000;
|
|
parameter BURST_MODE = "FALSE";
|
|
parameter integer CLK_RATIO = 1;
|
|
parameter integer CMD_OFFSET = 0;
|
|
parameter integer CO_DURATION = 0;
|
|
parameter DATA_CTL_A_N = "FALSE";
|
|
parameter DATA_CTL_B_N = "FALSE";
|
|
parameter DATA_CTL_C_N = "FALSE";
|
|
parameter DATA_CTL_D_N = "FALSE";
|
|
parameter DISABLE_SEQ_MATCH = "TRUE";
|
|
parameter integer DI_DURATION = 0;
|
|
parameter integer DO_DURATION = 0;
|
|
parameter integer EVENTS_DELAY = 63;
|
|
parameter integer FOUR_WINDOW_CLOCKS = 63;
|
|
parameter MULTI_REGION = "FALSE";
|
|
parameter PHY_COUNT_ENABLE = "FALSE";
|
|
parameter integer RD_CMD_OFFSET_0 = 0;
|
|
parameter integer RD_CMD_OFFSET_1 = 00;
|
|
parameter integer RD_CMD_OFFSET_2 = 0;
|
|
parameter integer RD_CMD_OFFSET_3 = 0;
|
|
parameter integer RD_DURATION_0 = 0;
|
|
parameter integer RD_DURATION_1 = 0;
|
|
parameter integer RD_DURATION_2 = 0;
|
|
parameter integer RD_DURATION_3 = 0;
|
|
parameter SYNC_MODE = "FALSE";
|
|
parameter integer WR_CMD_OFFSET_0 = 0;
|
|
parameter integer WR_CMD_OFFSET_1 = 0;
|
|
parameter integer WR_CMD_OFFSET_2 = 0;
|
|
parameter integer WR_CMD_OFFSET_3 = 0;
|
|
parameter integer WR_DURATION_0 = 0;
|
|
parameter integer WR_DURATION_1 = 0;
|
|
parameter integer WR_DURATION_2 = 0;
|
|
parameter integer WR_DURATION_3 = 0;
|
|
output PHYCTLALMOSTFULL;
|
|
output PHYCTLEMPTY;
|
|
output PHYCTLFULL;
|
|
output PHYCTLREADY;
|
|
output [1:0] INRANKA;
|
|
output [1:0] INRANKB;
|
|
output [1:0] INRANKC;
|
|
output [1:0] INRANKD;
|
|
output [1:0] PCENABLECALIB;
|
|
output [3:0] AUXOUTPUT;
|
|
output [3:0] INBURSTPENDING;
|
|
output [3:0] OUTBURSTPENDING;
|
|
input MEMREFCLK;
|
|
input PHYCLK;
|
|
input PHYCTLMSTREMPTY;
|
|
input PHYCTLWRENABLE;
|
|
input PLLLOCK;
|
|
input READCALIBENABLE;
|
|
input REFDLLLOCK;
|
|
input RESET;
|
|
input SYNCIN;
|
|
input WRITECALIBENABLE;
|
|
input [31:0] PHYCTLWD;
|
|
endmodule
|
|
|
|
module IDDRE1(Q1, Q2, C, CB, D, R);
|
|
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
|
|
parameter [0:0] IS_CB_INVERTED = 1'b0;
|
|
parameter [0:0] IS_C_INVERTED = 1'b0;
|
|
output Q1;
|
|
output Q2;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_C_INVERTED" *)
|
|
input C;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CB_INVERTED" *)
|
|
input CB;
|
|
input D;
|
|
input R;
|
|
endmodule
|
|
|
|
module ODDRE1(Q, C, D1, D2, SR);
|
|
parameter [0:0] IS_C_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_D2_INVERTED = 1'b0;
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter [0:0] SRVAL = 1'b0;
|
|
output Q;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_C_INVERTED" *)
|
|
input C;
|
|
(* invertible_pin = "IS_D1_INVERTED" *)
|
|
input D1;
|
|
(* invertible_pin = "IS_D2_INVERTED" *)
|
|
input D2;
|
|
input SR;
|
|
endmodule
|
|
|
|
module IDELAYE3(CASC_OUT, CNTVALUEOUT, DATAOUT, CASC_IN, CASC_RETURN, CE, CLK, CNTVALUEIN, DATAIN, EN_VTC, IDATAIN, INC, LOAD, RST);
|
|
parameter CASCADE = "NONE";
|
|
parameter DELAY_FORMAT = "TIME";
|
|
parameter DELAY_SRC = "IDATAIN";
|
|
parameter DELAY_TYPE = "FIXED";
|
|
parameter integer DELAY_VALUE = 0;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter LOOPBACK = "FALSE";
|
|
parameter real REFCLK_FREQUENCY = 300.0;
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter real SIM_VERSION = 2.0;
|
|
parameter UPDATE_MODE = "ASYNC";
|
|
output CASC_OUT;
|
|
output [8:0] CNTVALUEOUT;
|
|
output DATAOUT;
|
|
input CASC_IN;
|
|
input CASC_RETURN;
|
|
input CE;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
input [8:0] CNTVALUEIN;
|
|
input DATAIN;
|
|
input EN_VTC;
|
|
input IDATAIN;
|
|
input INC;
|
|
input LOAD;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module ODELAYE3(CASC_OUT, CNTVALUEOUT, DATAOUT, CASC_IN, CASC_RETURN, CE, CLK, CNTVALUEIN, EN_VTC, INC, LOAD, ODATAIN, RST);
|
|
parameter CASCADE = "NONE";
|
|
parameter DELAY_FORMAT = "TIME";
|
|
parameter DELAY_TYPE = "FIXED";
|
|
parameter integer DELAY_VALUE = 0;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REFCLK_FREQUENCY = 300.0;
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter real SIM_VERSION = 2.0;
|
|
parameter UPDATE_MODE = "ASYNC";
|
|
output CASC_OUT;
|
|
output [8:0] CNTVALUEOUT;
|
|
output DATAOUT;
|
|
input CASC_IN;
|
|
input CASC_RETURN;
|
|
input CE;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
input [8:0] CNTVALUEIN;
|
|
input EN_VTC;
|
|
input INC;
|
|
input LOAD;
|
|
input ODATAIN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module ISERDESE3(FIFO_EMPTY, INTERNAL_DIVCLK, Q, CLK, CLKDIV, CLK_B, D, FIFO_RD_CLK, FIFO_RD_EN, RST);
|
|
parameter integer DATA_WIDTH = 8;
|
|
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
|
|
parameter FIFO_ENABLE = "FALSE";
|
|
parameter FIFO_SYNC_MODE = "FALSE";
|
|
parameter IDDR_MODE = "FALSE";
|
|
parameter [0:0] IS_CLK_B_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter real SIM_VERSION = 2.0;
|
|
output FIFO_EMPTY;
|
|
output INTERNAL_DIVCLK;
|
|
output [7:0] Q;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
(* clkbuf_sink *)
|
|
input CLKDIV;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_B_INVERTED" *)
|
|
input CLK_B;
|
|
input D;
|
|
(* clkbuf_sink *)
|
|
input FIFO_RD_CLK;
|
|
input FIFO_RD_EN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module OSERDESE3(OQ, T_OUT, CLK, CLKDIV, D, RST, T);
|
|
parameter integer DATA_WIDTH = 8;
|
|
parameter [0:0] INIT = 1'b0;
|
|
parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter ODDR_MODE = "FALSE";
|
|
parameter OSERDES_D_BYPASS = "FALSE";
|
|
parameter OSERDES_T_BYPASS = "FALSE";
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter real SIM_VERSION = 2.0;
|
|
output OQ;
|
|
output T_OUT;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLKDIV_INVERTED" *)
|
|
input CLKDIV;
|
|
input [7:0] D;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
input T;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module BITSLICE_CONTROL(CLK_TO_EXT_NORTH, CLK_TO_EXT_SOUTH, DLY_RDY, DYN_DCI, NCLK_NIBBLE_OUT, PCLK_NIBBLE_OUT, RIU_RD_DATA, RIU_VALID, RX_BIT_CTRL_OUT0, RX_BIT_CTRL_OUT1, RX_BIT_CTRL_OUT2, RX_BIT_CTRL_OUT3, RX_BIT_CTRL_OUT4, RX_BIT_CTRL_OUT5, RX_BIT_CTRL_OUT6, TX_BIT_CTRL_OUT0, TX_BIT_CTRL_OUT1, TX_BIT_CTRL_OUT2, TX_BIT_CTRL_OUT3, TX_BIT_CTRL_OUT4, TX_BIT_CTRL_OUT5
|
|
, TX_BIT_CTRL_OUT6, TX_BIT_CTRL_OUT_TRI, VTC_RDY, CLK_FROM_EXT, EN_VTC, NCLK_NIBBLE_IN, PCLK_NIBBLE_IN, PHY_RDCS0, PHY_RDCS1, PHY_RDEN, PHY_WRCS0, PHY_WRCS1, PLL_CLK, REFCLK, RIU_ADDR, RIU_CLK, RIU_NIBBLE_SEL, RIU_WR_DATA, RIU_WR_EN, RST, RX_BIT_CTRL_IN0
|
|
, RX_BIT_CTRL_IN1, RX_BIT_CTRL_IN2, RX_BIT_CTRL_IN3, RX_BIT_CTRL_IN4, RX_BIT_CTRL_IN5, RX_BIT_CTRL_IN6, TBYTE_IN, TX_BIT_CTRL_IN0, TX_BIT_CTRL_IN1, TX_BIT_CTRL_IN2, TX_BIT_CTRL_IN3, TX_BIT_CTRL_IN4, TX_BIT_CTRL_IN5, TX_BIT_CTRL_IN6, TX_BIT_CTRL_IN_TRI);
|
|
parameter CTRL_CLK = "EXTERNAL";
|
|
parameter DIV_MODE = "DIV2";
|
|
parameter EN_CLK_TO_EXT_NORTH = "DISABLE";
|
|
parameter EN_CLK_TO_EXT_SOUTH = "DISABLE";
|
|
parameter EN_DYN_ODLY_MODE = "FALSE";
|
|
parameter EN_OTHER_NCLK = "FALSE";
|
|
parameter EN_OTHER_PCLK = "FALSE";
|
|
parameter IDLY_VT_TRACK = "TRUE";
|
|
parameter INV_RXCLK = "FALSE";
|
|
parameter ODLY_VT_TRACK = "TRUE";
|
|
parameter QDLY_VT_TRACK = "TRUE";
|
|
parameter [5:0] READ_IDLE_COUNT = 6'h00;
|
|
parameter REFCLK_SRC = "PLLCLK";
|
|
parameter integer ROUNDING_FACTOR = 16;
|
|
parameter RXGATE_EXTEND = "FALSE";
|
|
parameter RX_CLK_PHASE_N = "SHIFT_0";
|
|
parameter RX_CLK_PHASE_P = "SHIFT_0";
|
|
parameter RX_GATING = "DISABLE";
|
|
parameter SELF_CALIBRATE = "ENABLE";
|
|
parameter SERIAL_MODE = "FALSE";
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter SIM_SPEEDUP = "FAST";
|
|
parameter real SIM_VERSION = 2.0;
|
|
parameter TX_GATING = "DISABLE";
|
|
output CLK_TO_EXT_NORTH;
|
|
output CLK_TO_EXT_SOUTH;
|
|
output DLY_RDY;
|
|
output [6:0] DYN_DCI;
|
|
output NCLK_NIBBLE_OUT;
|
|
output PCLK_NIBBLE_OUT;
|
|
output [15:0] RIU_RD_DATA;
|
|
output RIU_VALID;
|
|
output [39:0] RX_BIT_CTRL_OUT0;
|
|
output [39:0] RX_BIT_CTRL_OUT1;
|
|
output [39:0] RX_BIT_CTRL_OUT2;
|
|
output [39:0] RX_BIT_CTRL_OUT3;
|
|
output [39:0] RX_BIT_CTRL_OUT4;
|
|
output [39:0] RX_BIT_CTRL_OUT5;
|
|
output [39:0] RX_BIT_CTRL_OUT6;
|
|
output [39:0] TX_BIT_CTRL_OUT0;
|
|
output [39:0] TX_BIT_CTRL_OUT1;
|
|
output [39:0] TX_BIT_CTRL_OUT2;
|
|
output [39:0] TX_BIT_CTRL_OUT3;
|
|
output [39:0] TX_BIT_CTRL_OUT4;
|
|
output [39:0] TX_BIT_CTRL_OUT5;
|
|
output [39:0] TX_BIT_CTRL_OUT6;
|
|
output [39:0] TX_BIT_CTRL_OUT_TRI;
|
|
output VTC_RDY;
|
|
input CLK_FROM_EXT;
|
|
input EN_VTC;
|
|
input NCLK_NIBBLE_IN;
|
|
input PCLK_NIBBLE_IN;
|
|
input [3:0] PHY_RDCS0;
|
|
input [3:0] PHY_RDCS1;
|
|
input [3:0] PHY_RDEN;
|
|
input [3:0] PHY_WRCS0;
|
|
input [3:0] PHY_WRCS1;
|
|
input PLL_CLK;
|
|
input REFCLK;
|
|
input [5:0] RIU_ADDR;
|
|
input RIU_CLK;
|
|
input RIU_NIBBLE_SEL;
|
|
input [15:0] RIU_WR_DATA;
|
|
input RIU_WR_EN;
|
|
input RST;
|
|
input [39:0] RX_BIT_CTRL_IN0;
|
|
input [39:0] RX_BIT_CTRL_IN1;
|
|
input [39:0] RX_BIT_CTRL_IN2;
|
|
input [39:0] RX_BIT_CTRL_IN3;
|
|
input [39:0] RX_BIT_CTRL_IN4;
|
|
input [39:0] RX_BIT_CTRL_IN5;
|
|
input [39:0] RX_BIT_CTRL_IN6;
|
|
input [3:0] TBYTE_IN;
|
|
input [39:0] TX_BIT_CTRL_IN0;
|
|
input [39:0] TX_BIT_CTRL_IN1;
|
|
input [39:0] TX_BIT_CTRL_IN2;
|
|
input [39:0] TX_BIT_CTRL_IN3;
|
|
input [39:0] TX_BIT_CTRL_IN4;
|
|
input [39:0] TX_BIT_CTRL_IN5;
|
|
input [39:0] TX_BIT_CTRL_IN6;
|
|
input [39:0] TX_BIT_CTRL_IN_TRI;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module RIU_OR(RIU_RD_DATA, RIU_RD_VALID, RIU_RD_DATA_LOW, RIU_RD_DATA_UPP, RIU_RD_VALID_LOW, RIU_RD_VALID_UPP);
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter real SIM_VERSION = 2.0;
|
|
output [15:0] RIU_RD_DATA;
|
|
output RIU_RD_VALID;
|
|
input [15:0] RIU_RD_DATA_LOW;
|
|
input [15:0] RIU_RD_DATA_UPP;
|
|
input RIU_RD_VALID_LOW;
|
|
input RIU_RD_VALID_UPP;
|
|
endmodule
|
|
|
|
module RX_BITSLICE(CNTVALUEOUT, CNTVALUEOUT_EXT, FIFO_EMPTY, FIFO_WRCLK_OUT, Q, RX_BIT_CTRL_OUT, TX_BIT_CTRL_OUT, CE, CE_EXT, CLK, CLK_EXT, CNTVALUEIN, CNTVALUEIN_EXT, DATAIN, EN_VTC, EN_VTC_EXT, FIFO_RD_CLK, FIFO_RD_EN, INC, INC_EXT, LOAD
|
|
, LOAD_EXT, RST, RST_DLY, RST_DLY_EXT, RX_BIT_CTRL_IN, TX_BIT_CTRL_IN);
|
|
parameter CASCADE = "TRUE";
|
|
parameter DATA_TYPE = "NONE";
|
|
parameter integer DATA_WIDTH = 8;
|
|
parameter DELAY_FORMAT = "TIME";
|
|
parameter DELAY_TYPE = "FIXED";
|
|
parameter integer DELAY_VALUE = 0;
|
|
parameter integer DELAY_VALUE_EXT = 0;
|
|
parameter FIFO_SYNC_MODE = "FALSE";
|
|
parameter [0:0] IS_CLK_EXT_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_DLY_EXT_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_DLY_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REFCLK_FREQUENCY = 300.0;
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter real SIM_VERSION = 2.0;
|
|
parameter UPDATE_MODE = "ASYNC";
|
|
parameter UPDATE_MODE_EXT = "ASYNC";
|
|
output [8:0] CNTVALUEOUT;
|
|
output [8:0] CNTVALUEOUT_EXT;
|
|
output FIFO_EMPTY;
|
|
output FIFO_WRCLK_OUT;
|
|
output [7:0] Q;
|
|
output [39:0] RX_BIT_CTRL_OUT;
|
|
output [39:0] TX_BIT_CTRL_OUT;
|
|
input CE;
|
|
input CE_EXT;
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
(* invertible_pin = "IS_CLK_EXT_INVERTED" *)
|
|
input CLK_EXT;
|
|
input [8:0] CNTVALUEIN;
|
|
input [8:0] CNTVALUEIN_EXT;
|
|
input DATAIN;
|
|
input EN_VTC;
|
|
input EN_VTC_EXT;
|
|
input FIFO_RD_CLK;
|
|
input FIFO_RD_EN;
|
|
input INC;
|
|
input INC_EXT;
|
|
input LOAD;
|
|
input LOAD_EXT;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
(* invertible_pin = "IS_RST_DLY_INVERTED" *)
|
|
input RST_DLY;
|
|
(* invertible_pin = "IS_RST_DLY_EXT_INVERTED" *)
|
|
input RST_DLY_EXT;
|
|
input [39:0] RX_BIT_CTRL_IN;
|
|
input [39:0] TX_BIT_CTRL_IN;
|
|
endmodule
|
|
|
|
module RXTX_BITSLICE(FIFO_EMPTY, FIFO_WRCLK_OUT, O, Q, RX_BIT_CTRL_OUT, RX_CNTVALUEOUT, TX_BIT_CTRL_OUT, TX_CNTVALUEOUT, T_OUT, D, DATAIN, FIFO_RD_CLK, FIFO_RD_EN, RX_BIT_CTRL_IN, RX_CE, RX_CLK, RX_CNTVALUEIN, RX_EN_VTC, RX_INC, RX_LOAD, RX_RST
|
|
, RX_RST_DLY, T, TBYTE_IN, TX_BIT_CTRL_IN, TX_CE, TX_CLK, TX_CNTVALUEIN, TX_EN_VTC, TX_INC, TX_LOAD, TX_RST, TX_RST_DLY);
|
|
parameter FIFO_SYNC_MODE = "FALSE";
|
|
parameter [0:0] INIT = 1'b1;
|
|
parameter [0:0] IS_RX_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RX_RST_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TX_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TX_RST_INVERTED = 1'b0;
|
|
parameter LOOPBACK = "FALSE";
|
|
parameter NATIVE_ODELAY_BYPASS = "FALSE";
|
|
parameter ENABLE_PRE_EMPHASIS = "FALSE";
|
|
parameter RX_DATA_TYPE = "NONE";
|
|
parameter integer RX_DATA_WIDTH = 8;
|
|
parameter RX_DELAY_FORMAT = "TIME";
|
|
parameter RX_DELAY_TYPE = "FIXED";
|
|
parameter integer RX_DELAY_VALUE = 0;
|
|
parameter real RX_REFCLK_FREQUENCY = 300.0;
|
|
parameter RX_UPDATE_MODE = "ASYNC";
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter real SIM_VERSION = 2.0;
|
|
parameter TBYTE_CTL = "TBYTE_IN";
|
|
parameter integer TX_DATA_WIDTH = 8;
|
|
parameter TX_DELAY_FORMAT = "TIME";
|
|
parameter TX_DELAY_TYPE = "FIXED";
|
|
parameter integer TX_DELAY_VALUE = 0;
|
|
parameter TX_OUTPUT_PHASE_90 = "FALSE";
|
|
parameter real TX_REFCLK_FREQUENCY = 300.0;
|
|
parameter TX_UPDATE_MODE = "ASYNC";
|
|
output FIFO_EMPTY;
|
|
output FIFO_WRCLK_OUT;
|
|
output O;
|
|
output [7:0] Q;
|
|
output [39:0] RX_BIT_CTRL_OUT;
|
|
output [8:0] RX_CNTVALUEOUT;
|
|
output [39:0] TX_BIT_CTRL_OUT;
|
|
output [8:0] TX_CNTVALUEOUT;
|
|
output T_OUT;
|
|
input [7:0] D;
|
|
input DATAIN;
|
|
input FIFO_RD_CLK;
|
|
input FIFO_RD_EN;
|
|
input [39:0] RX_BIT_CTRL_IN;
|
|
input RX_CE;
|
|
(* invertible_pin = "IS_RX_CLK_INVERTED" *)
|
|
input RX_CLK;
|
|
input [8:0] RX_CNTVALUEIN;
|
|
input RX_EN_VTC;
|
|
input RX_INC;
|
|
input RX_LOAD;
|
|
(* invertible_pin = "IS_RX_RST_INVERTED" *)
|
|
input RX_RST;
|
|
(* invertible_pin = "IS_RX_RST_DLY_INVERTED" *)
|
|
input RX_RST_DLY;
|
|
input T;
|
|
input TBYTE_IN;
|
|
input [39:0] TX_BIT_CTRL_IN;
|
|
input TX_CE;
|
|
(* invertible_pin = "IS_TX_CLK_INVERTED" *)
|
|
input TX_CLK;
|
|
input [8:0] TX_CNTVALUEIN;
|
|
input TX_EN_VTC;
|
|
input TX_INC;
|
|
input TX_LOAD;
|
|
(* invertible_pin = "IS_TX_RST_INVERTED" *)
|
|
input TX_RST;
|
|
(* invertible_pin = "IS_TX_RST_DLY_INVERTED" *)
|
|
input TX_RST_DLY;
|
|
endmodule
|
|
|
|
module TX_BITSLICE(CNTVALUEOUT, O, RX_BIT_CTRL_OUT, TX_BIT_CTRL_OUT, T_OUT, CE, CLK, CNTVALUEIN, D, EN_VTC, INC, LOAD, RST, RST_DLY, RX_BIT_CTRL_IN, T, TBYTE_IN, TX_BIT_CTRL_IN);
|
|
parameter integer DATA_WIDTH = 8;
|
|
parameter DELAY_FORMAT = "TIME";
|
|
parameter DELAY_TYPE = "FIXED";
|
|
parameter integer DELAY_VALUE = 0;
|
|
parameter ENABLE_PRE_EMPHASIS = "FALSE";
|
|
parameter [0:0] INIT = 1'b1;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_DLY_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter NATIVE_ODELAY_BYPASS = "FALSE";
|
|
parameter OUTPUT_PHASE_90 = "FALSE";
|
|
parameter real REFCLK_FREQUENCY = 300.0;
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter real SIM_VERSION = 2.0;
|
|
parameter TBYTE_CTL = "TBYTE_IN";
|
|
parameter UPDATE_MODE = "ASYNC";
|
|
output [8:0] CNTVALUEOUT;
|
|
output O;
|
|
output [39:0] RX_BIT_CTRL_OUT;
|
|
output [39:0] TX_BIT_CTRL_OUT;
|
|
output T_OUT;
|
|
input CE;
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
input [8:0] CNTVALUEIN;
|
|
input [7:0] D;
|
|
input EN_VTC;
|
|
input INC;
|
|
input LOAD;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
(* invertible_pin = "IS_RST_DLY_INVERTED" *)
|
|
input RST_DLY;
|
|
input [39:0] RX_BIT_CTRL_IN;
|
|
input T;
|
|
input TBYTE_IN;
|
|
input [39:0] TX_BIT_CTRL_IN;
|
|
endmodule
|
|
|
|
module TX_BITSLICE_TRI(BIT_CTRL_OUT, CNTVALUEOUT, TRI_OUT, BIT_CTRL_IN, CE, CLK, CNTVALUEIN, EN_VTC, INC, LOAD, RST, RST_DLY);
|
|
parameter integer DATA_WIDTH = 8;
|
|
parameter DELAY_FORMAT = "TIME";
|
|
parameter DELAY_TYPE = "FIXED";
|
|
parameter integer DELAY_VALUE = 0;
|
|
parameter [0:0] INIT = 1'b1;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_DLY_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter NATIVE_ODELAY_BYPASS = "FALSE";
|
|
parameter OUTPUT_PHASE_90 = "FALSE";
|
|
parameter real REFCLK_FREQUENCY = 300.0;
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter real SIM_VERSION = 2.0;
|
|
parameter UPDATE_MODE = "ASYNC";
|
|
output [39:0] BIT_CTRL_OUT;
|
|
output [8:0] CNTVALUEOUT;
|
|
output TRI_OUT;
|
|
input [39:0] BIT_CTRL_IN;
|
|
input CE;
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
input [8:0] CNTVALUEIN;
|
|
input EN_VTC;
|
|
input INC;
|
|
input LOAD;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
(* invertible_pin = "IS_RST_DLY_INVERTED" *)
|
|
input RST_DLY;
|
|
endmodule
|
|
|
|
module IODELAY2(BUSY, DATAOUT2, DATAOUT, DOUT, TOUT, CAL, CE, CLK, IDATAIN, INC, IOCLK0, IOCLK1, ODATAIN, RST, T);
|
|
parameter COUNTER_WRAPAROUND = "WRAPAROUND";
|
|
parameter DATA_RATE = "SDR";
|
|
parameter DELAY_SRC = "IO";
|
|
parameter integer IDELAY2_VALUE = 0;
|
|
parameter IDELAY_MODE = "NORMAL";
|
|
parameter IDELAY_TYPE = "DEFAULT";
|
|
parameter integer IDELAY_VALUE = 0;
|
|
parameter integer ODELAY_VALUE = 0;
|
|
parameter SERDES_MODE = "NONE";
|
|
parameter integer SIM_TAPDELAY_VALUE = 75;
|
|
output BUSY;
|
|
output DATAOUT2;
|
|
output DATAOUT;
|
|
output DOUT;
|
|
output TOUT;
|
|
input CAL;
|
|
input CE;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input IDATAIN;
|
|
input INC;
|
|
(* clkbuf_sink *)
|
|
input IOCLK0;
|
|
(* clkbuf_sink *)
|
|
input IOCLK1;
|
|
input ODATAIN;
|
|
input RST;
|
|
input T;
|
|
endmodule
|
|
|
|
module IODRP2(DATAOUT2, DATAOUT, DOUT, SDO, TOUT, ADD, BKST, CLK, CS, IDATAIN, IOCLK0, IOCLK1, ODATAIN, SDI, T);
|
|
parameter DATA_RATE = "SDR";
|
|
parameter integer SIM_TAPDELAY_VALUE = 75;
|
|
output DATAOUT2;
|
|
output DATAOUT;
|
|
output DOUT;
|
|
output SDO;
|
|
output TOUT;
|
|
input ADD;
|
|
input BKST;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input CS;
|
|
input IDATAIN;
|
|
(* clkbuf_sink *)
|
|
input IOCLK0;
|
|
(* clkbuf_sink *)
|
|
input IOCLK1;
|
|
input ODATAIN;
|
|
input SDI;
|
|
input T;
|
|
endmodule
|
|
|
|
module IODRP2_MCB(AUXSDO, DATAOUT2, DATAOUT, DOUT, DQSOUTN, DQSOUTP, SDO, TOUT, ADD, AUXSDOIN, BKST, CLK, CS, IDATAIN, IOCLK0, IOCLK1, MEMUPDATE, ODATAIN, SDI, T, AUXADDR
|
|
);
|
|
parameter DATA_RATE = "SDR";
|
|
parameter integer IDELAY_VALUE = 0;
|
|
parameter integer MCB_ADDRESS = 0;
|
|
parameter integer ODELAY_VALUE = 0;
|
|
parameter SERDES_MODE = "NONE";
|
|
parameter integer SIM_TAPDELAY_VALUE = 75;
|
|
output AUXSDO;
|
|
output DATAOUT2;
|
|
output DATAOUT;
|
|
output DOUT;
|
|
output DQSOUTN;
|
|
output DQSOUTP;
|
|
output SDO;
|
|
output TOUT;
|
|
input ADD;
|
|
input AUXSDOIN;
|
|
input BKST;
|
|
(* clkbuf_sink *)
|
|
input CLK;
|
|
input CS;
|
|
input IDATAIN;
|
|
(* clkbuf_sink *)
|
|
input IOCLK0;
|
|
(* clkbuf_sink *)
|
|
input IOCLK1;
|
|
input MEMUPDATE;
|
|
input ODATAIN;
|
|
input SDI;
|
|
input T;
|
|
input [4:0] AUXADDR;
|
|
endmodule
|
|
|
|
module ISERDES2(CFB0, CFB1, DFB, FABRICOUT, INCDEC, Q1, Q2, Q3, Q4, SHIFTOUT, VALID, BITSLIP, CE0, CLK0, CLK1, CLKDIV, D, IOCE, RST, SHIFTIN);
|
|
parameter BITSLIP_ENABLE = "FALSE";
|
|
parameter DATA_RATE = "SDR";
|
|
parameter integer DATA_WIDTH = 1;
|
|
parameter INTERFACE_TYPE = "NETWORKING";
|
|
parameter SERDES_MODE = "NONE";
|
|
output CFB0;
|
|
output CFB1;
|
|
output DFB;
|
|
output FABRICOUT;
|
|
output INCDEC;
|
|
output Q1;
|
|
output Q2;
|
|
output Q3;
|
|
output Q4;
|
|
output SHIFTOUT;
|
|
output VALID;
|
|
input BITSLIP;
|
|
input CE0;
|
|
(* clkbuf_sink *)
|
|
input CLK0;
|
|
(* clkbuf_sink *)
|
|
input CLK1;
|
|
(* clkbuf_sink *)
|
|
input CLKDIV;
|
|
input D;
|
|
input IOCE;
|
|
input RST;
|
|
input SHIFTIN;
|
|
endmodule
|
|
|
|
module OSERDES2(OQ, SHIFTOUT1, SHIFTOUT2, SHIFTOUT3, SHIFTOUT4, TQ, CLK0, CLK1, CLKDIV, D1, D2, D3, D4, IOCE, OCE, RST, SHIFTIN1, SHIFTIN2, SHIFTIN3, SHIFTIN4, T1
|
|
, T2, T3, T4, TCE, TRAIN);
|
|
parameter BYPASS_GCLK_FF = "FALSE";
|
|
parameter DATA_RATE_OQ = "DDR";
|
|
parameter DATA_RATE_OT = "DDR";
|
|
parameter integer DATA_WIDTH = 2;
|
|
parameter OUTPUT_MODE = "SINGLE_ENDED";
|
|
parameter SERDES_MODE = "NONE";
|
|
parameter integer TRAIN_PATTERN = 0;
|
|
output OQ;
|
|
output SHIFTOUT1;
|
|
output SHIFTOUT2;
|
|
output SHIFTOUT3;
|
|
output SHIFTOUT4;
|
|
output TQ;
|
|
(* clkbuf_sink *)
|
|
input CLK0;
|
|
(* clkbuf_sink *)
|
|
input CLK1;
|
|
(* clkbuf_sink *)
|
|
input CLKDIV;
|
|
input D1;
|
|
input D2;
|
|
input D3;
|
|
input D4;
|
|
input IOCE;
|
|
input OCE;
|
|
input RST;
|
|
input SHIFTIN1;
|
|
input SHIFTIN2;
|
|
input SHIFTIN3;
|
|
input SHIFTIN4;
|
|
input T1;
|
|
input T2;
|
|
input T3;
|
|
input T4;
|
|
input TCE;
|
|
input TRAIN;
|
|
endmodule
|
|
|
|
module IBUF_DLY_ADJ(O, I, S);
|
|
parameter DELAY_OFFSET = "OFF";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
input [2:0] S;
|
|
endmodule
|
|
|
|
module IBUF_IBUFDISABLE(O, I, IBUFDISABLE);
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
input IBUFDISABLE;
|
|
endmodule
|
|
|
|
module IBUF_INTERMDISABLE(O, I, IBUFDISABLE, INTERMDISABLE);
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input INTERMDISABLE;
|
|
endmodule
|
|
|
|
module IBUF_ANALOG(O, I);
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
endmodule
|
|
|
|
module IBUFE3(O, I, IBUFDISABLE, OSC, OSC_EN, VREF);
|
|
parameter CCIO_EN = "TRUE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
|
|
parameter USE_IBUFDISABLE = "FALSE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input [3:0] OSC;
|
|
input OSC_EN;
|
|
input VREF;
|
|
endmodule
|
|
|
|
module IBUFDS(O, I, IB);
|
|
parameter CAPACITANCE = "DONT_CARE";
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_DELAY_VALUE = "0";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IFD_DELAY_VALUE = "AUTO";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module IBUFDS_DLY_ADJ(O, I, IB, S);
|
|
parameter DELAY_OFFSET = "OFF";
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
input [2:0] S;
|
|
endmodule
|
|
|
|
module IBUFDS_IBUFDISABLE(O, I, IB, IBUFDISABLE);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
input IBUFDISABLE;
|
|
endmodule
|
|
|
|
module IBUFDS_INTERMDISABLE(O, I, IB, IBUFDISABLE, INTERMDISABLE);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
input IBUFDISABLE;
|
|
input INTERMDISABLE;
|
|
endmodule
|
|
|
|
module IBUFDS_DIFF_OUT(O, OB, I, IB);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
output O;
|
|
output OB;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module IBUFDS_DIFF_OUT_IBUFDISABLE(O, OB, I, IB, IBUFDISABLE);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
output OB;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
input IBUFDISABLE;
|
|
endmodule
|
|
|
|
module IBUFDS_DIFF_OUT_INTERMDISABLE(O, OB, I, IB, IBUFDISABLE, INTERMDISABLE);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
output OB;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
input IBUFDISABLE;
|
|
input INTERMDISABLE;
|
|
endmodule
|
|
|
|
module IBUFDSE3(O, I, IB, IBUFDISABLE, OSC, OSC_EN);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter USE_IBUFDISABLE = "FALSE";
|
|
parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
input IBUFDISABLE;
|
|
input [3:0] OSC;
|
|
input [1:0] OSC_EN;
|
|
endmodule
|
|
|
|
module IBUFDS_DPHY(HSRX_O, LPRX_O_N, LPRX_O_P, HSRX_DISABLE, I, IB, LPRX_DISABLE);
|
|
parameter DIFF_TERM = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
output HSRX_O;
|
|
output LPRX_O_N;
|
|
output LPRX_O_P;
|
|
input HSRX_DISABLE;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
input LPRX_DISABLE;
|
|
endmodule
|
|
|
|
module IBUFGDS(O, I, IB);
|
|
parameter CAPACITANCE = "DONT_CARE";
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter IBUF_DELAY_VALUE = "0";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module IBUFGDS_DIFF_OUT(O, OB, I, IB);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
output O;
|
|
output OB;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module IOBUF_DCIEN(O, IO, DCITERMDISABLE, I, IBUFDISABLE, T);
|
|
parameter integer DRIVE = 12;
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter SLEW = "SLOW";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
input DCITERMDISABLE;
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input T;
|
|
endmodule
|
|
|
|
module IOBUF_INTERMDISABLE(O, IO, I, IBUFDISABLE, INTERMDISABLE, T);
|
|
parameter integer DRIVE = 12;
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter SLEW = "SLOW";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input INTERMDISABLE;
|
|
input T;
|
|
endmodule
|
|
|
|
module IOBUFE3(O, IO, DCITERMDISABLE, I, IBUFDISABLE, OSC, OSC_EN, T, VREF);
|
|
parameter integer DRIVE = 12;
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
|
|
parameter USE_IBUFDISABLE = "FALSE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
input DCITERMDISABLE;
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input [3:0] OSC;
|
|
input OSC_EN;
|
|
input T;
|
|
input VREF;
|
|
endmodule
|
|
|
|
module IOBUFDS(O, IO, IOB, I, T);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SLEW = "SLOW";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
(* iopad_external_pin *)
|
|
inout IOB;
|
|
input I;
|
|
input T;
|
|
endmodule
|
|
|
|
module IOBUFDS_DCIEN(O, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, T);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter SLEW = "SLOW";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
(* iopad_external_pin *)
|
|
inout IOB;
|
|
input DCITERMDISABLE;
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input T;
|
|
endmodule
|
|
|
|
module IOBUFDS_INTERMDISABLE(O, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, T);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter SLEW = "SLOW";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
(* iopad_external_pin *)
|
|
inout IOB;
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input INTERMDISABLE;
|
|
input T;
|
|
endmodule
|
|
|
|
module IOBUFDS_DIFF_OUT(O, OB, IO, IOB, I, TM, TS);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
output O;
|
|
output OB;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
(* iopad_external_pin *)
|
|
inout IOB;
|
|
input I;
|
|
input TM;
|
|
input TS;
|
|
endmodule
|
|
|
|
module IOBUFDS_DIFF_OUT_DCIEN(O, OB, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, TM, TS);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
output OB;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
(* iopad_external_pin *)
|
|
inout IOB;
|
|
input DCITERMDISABLE;
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input TM;
|
|
input TS;
|
|
endmodule
|
|
|
|
module IOBUFDS_DIFF_OUT_INTERMDISABLE(O, OB, IO, IOB, I, IBUFDISABLE, INTERMDISABLE, TM, TS);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter USE_IBUFDISABLE = "TRUE";
|
|
output O;
|
|
output OB;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
(* iopad_external_pin *)
|
|
inout IOB;
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input INTERMDISABLE;
|
|
input TM;
|
|
input TS;
|
|
endmodule
|
|
|
|
module IOBUFDSE3(O, IO, IOB, DCITERMDISABLE, I, IBUFDISABLE, OSC, OSC_EN, T);
|
|
parameter DIFF_TERM = "FALSE";
|
|
parameter DQS_BIAS = "FALSE";
|
|
parameter IBUF_LOW_PWR = "TRUE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter integer SIM_INPUT_BUFFER_OFFSET = 0;
|
|
parameter USE_IBUFDISABLE = "FALSE";
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
inout IO;
|
|
(* iopad_external_pin *)
|
|
inout IOB;
|
|
input DCITERMDISABLE;
|
|
input I;
|
|
input IBUFDISABLE;
|
|
input [3:0] OSC;
|
|
input [1:0] OSC_EN;
|
|
input T;
|
|
endmodule
|
|
|
|
module OBUFDS(O, OB, I);
|
|
parameter CAPACITANCE = "DONT_CARE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SLEW = "SLOW";
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
output OB;
|
|
input I;
|
|
endmodule
|
|
|
|
module OBUFDS_DPHY(O, OB, HSTX_I, HSTX_T, LPTX_I_N, LPTX_I_P, LPTX_T);
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
output OB;
|
|
input HSTX_I;
|
|
input HSTX_T;
|
|
input LPTX_I_N;
|
|
input LPTX_I_P;
|
|
input LPTX_T;
|
|
endmodule
|
|
|
|
module OBUFTDS(O, OB, I, T);
|
|
parameter CAPACITANCE = "DONT_CARE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SLEW = "SLOW";
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
output OB;
|
|
input I;
|
|
input T;
|
|
endmodule
|
|
|
|
module KEEPER(O);
|
|
inout O;
|
|
endmodule
|
|
|
|
module PULLDOWN(O);
|
|
output O;
|
|
endmodule
|
|
|
|
module PULLUP(O);
|
|
output O;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module DCIRESET(LOCKED, RST);
|
|
output LOCKED;
|
|
input RST;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module HPIO_VREF(VREF, FABRIC_VREF_TUNE);
|
|
parameter VREF_CNTR = "OFF";
|
|
output VREF;
|
|
input [6:0] FABRIC_VREF_TUNE;
|
|
endmodule
|
|
|
|
module BUFGCE(O, CE, I);
|
|
parameter CE_TYPE = "SYNC";
|
|
parameter [0:0] IS_CE_INVERTED = 1'b0;
|
|
parameter [0:0] IS_I_INVERTED = 1'b0;
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter STARTUP_SYNC = "FALSE";
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
(* invertible_pin = "IS_CE_INVERTED" *)
|
|
input CE;
|
|
(* invertible_pin = "IS_I_INVERTED" *)
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFGCE_1(O, CE, I);
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input CE;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFGMUX(O, I0, I1, S);
|
|
parameter CLK_SEL_TYPE = "SYNC";
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input I0;
|
|
input I1;
|
|
input S;
|
|
endmodule
|
|
|
|
module BUFGMUX_1(O, I0, I1, S);
|
|
parameter CLK_SEL_TYPE = "SYNC";
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input I0;
|
|
input I1;
|
|
input S;
|
|
endmodule
|
|
|
|
module BUFGMUX_CTRL(O, I0, I1, S);
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input I0;
|
|
input I1;
|
|
input S;
|
|
endmodule
|
|
|
|
module BUFGMUX_VIRTEX4(O, I0, I1, S);
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input I0;
|
|
input I1;
|
|
input S;
|
|
endmodule
|
|
|
|
module BUFG_GT(O, CE, CEMASK, CLR, CLRMASK, DIV, I);
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter STARTUP_SYNC = "FALSE";
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input CE;
|
|
input CEMASK;
|
|
input CLR;
|
|
input CLRMASK;
|
|
input [2:0] DIV;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFG_GT_SYNC(CESYNC, CLRSYNC, CE, CLK, CLR);
|
|
output CESYNC;
|
|
output CLRSYNC;
|
|
input CE;
|
|
input CLK;
|
|
input CLR;
|
|
endmodule
|
|
|
|
module BUFG_PS(O, I);
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter STARTUP_SYNC = "FALSE";
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFGCE_DIV(O, CE, CLR, I);
|
|
parameter integer BUFGCE_DIVIDE = 1;
|
|
parameter CE_TYPE = "SYNC";
|
|
parameter HARDSYNC_CLR = "FALSE";
|
|
parameter [0:0] IS_CE_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLR_INVERTED = 1'b0;
|
|
parameter [0:0] IS_I_INVERTED = 1'b0;
|
|
parameter SIM_DEVICE = "ULTRASCALE";
|
|
parameter STARTUP_SYNC = "FALSE";
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
(* invertible_pin = "IS_CE_INVERTED" *)
|
|
input CE;
|
|
(* invertible_pin = "IS_CLR_INVERTED" *)
|
|
input CLR;
|
|
(* invertible_pin = "IS_I_INVERTED" *)
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFH(O, I);
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFIO2(DIVCLK, IOCLK, SERDESSTROBE, I);
|
|
parameter DIVIDE_BYPASS = "TRUE";
|
|
parameter integer DIVIDE = 1;
|
|
parameter I_INVERT = "FALSE";
|
|
parameter USE_DOUBLER = "FALSE";
|
|
(* clkbuf_driver *)
|
|
output DIVCLK;
|
|
(* clkbuf_driver *)
|
|
output IOCLK;
|
|
output SERDESSTROBE;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFIO2_2CLK(DIVCLK, IOCLK, SERDESSTROBE, I, IB);
|
|
parameter integer DIVIDE = 2;
|
|
(* clkbuf_driver *)
|
|
output DIVCLK;
|
|
(* clkbuf_driver *)
|
|
output IOCLK;
|
|
output SERDESSTROBE;
|
|
input I;
|
|
input IB;
|
|
endmodule
|
|
|
|
module BUFIO2FB(O, I);
|
|
parameter DIVIDE_BYPASS = "TRUE";
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFPLL(IOCLK, LOCK, SERDESSTROBE, GCLK, LOCKED, PLLIN);
|
|
parameter integer DIVIDE = 1;
|
|
parameter ENABLE_SYNC = "TRUE";
|
|
(* clkbuf_driver *)
|
|
output IOCLK;
|
|
output LOCK;
|
|
output SERDESSTROBE;
|
|
input GCLK;
|
|
input LOCKED;
|
|
input PLLIN;
|
|
endmodule
|
|
|
|
module BUFPLL_MCB(IOCLK0, IOCLK1, LOCK, SERDESSTROBE0, SERDESSTROBE1, GCLK, LOCKED, PLLIN0, PLLIN1);
|
|
parameter integer DIVIDE = 2;
|
|
parameter LOCK_SRC = "LOCK_TO_0";
|
|
(* clkbuf_driver *)
|
|
output IOCLK0;
|
|
(* clkbuf_driver *)
|
|
output IOCLK1;
|
|
output LOCK;
|
|
output SERDESSTROBE0;
|
|
output SERDESSTROBE1;
|
|
input GCLK;
|
|
input LOCKED;
|
|
input PLLIN0;
|
|
input PLLIN1;
|
|
endmodule
|
|
|
|
module BUFIO(O, I);
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFIODQS(O, DQSMASK, I);
|
|
parameter DQSMASK_ENABLE = "FALSE";
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input DQSMASK;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFR(O, CE, CLR, I);
|
|
parameter BUFR_DIVIDE = "BYPASS";
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input CE;
|
|
input CLR;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFMR(O, I);
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
input I;
|
|
endmodule
|
|
|
|
module BUFMRCE(O, CE, I);
|
|
parameter CE_TYPE = "SYNC";
|
|
parameter integer INIT_OUT = 0;
|
|
parameter [0:0] IS_CE_INVERTED = 1'b0;
|
|
(* clkbuf_driver *)
|
|
output O;
|
|
(* invertible_pin = "IS_CE_INVERTED" *)
|
|
input CE;
|
|
input I;
|
|
endmodule
|
|
|
|
module DCM(CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST, CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS);
|
|
parameter real CLKDV_DIVIDE = 2.0;
|
|
parameter integer CLKFX_DIVIDE = 1;
|
|
parameter integer CLKFX_MULTIPLY = 4;
|
|
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
|
|
parameter real CLKIN_PERIOD = 10.0;
|
|
parameter CLKOUT_PHASE_SHIFT = "NONE";
|
|
parameter CLK_FEEDBACK = "1X";
|
|
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
|
|
parameter DFS_FREQUENCY_MODE = "LOW";
|
|
parameter DLL_FREQUENCY_MODE = "LOW";
|
|
parameter DSS_MODE = "NONE";
|
|
parameter DUTY_CYCLE_CORRECTION = "TRUE";
|
|
parameter [15:0] FACTORY_JF = 16'hC080;
|
|
parameter integer PHASE_SHIFT = 0;
|
|
parameter SIM_MODE = "SAFE";
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
input CLKFB;
|
|
input CLKIN;
|
|
input DSSEN;
|
|
input PSCLK;
|
|
input PSEN;
|
|
input PSINCDEC;
|
|
input RST;
|
|
output CLK0;
|
|
output CLK180;
|
|
output CLK270;
|
|
output CLK2X;
|
|
output CLK2X180;
|
|
output CLK90;
|
|
output CLKDV;
|
|
output CLKFX;
|
|
output CLKFX180;
|
|
output LOCKED;
|
|
output PSDONE;
|
|
output [7:0] STATUS;
|
|
endmodule
|
|
|
|
module DCM_SP(CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST, CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS);
|
|
parameter real CLKDV_DIVIDE = 2.0;
|
|
parameter integer CLKFX_DIVIDE = 1;
|
|
parameter integer CLKFX_MULTIPLY = 4;
|
|
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
|
|
parameter real CLKIN_PERIOD = 10.0;
|
|
parameter CLKOUT_PHASE_SHIFT = "NONE";
|
|
parameter CLK_FEEDBACK = "1X";
|
|
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
|
|
parameter DFS_FREQUENCY_MODE = "LOW";
|
|
parameter DLL_FREQUENCY_MODE = "LOW";
|
|
parameter DSS_MODE = "NONE";
|
|
parameter DUTY_CYCLE_CORRECTION = "TRUE";
|
|
parameter FACTORY_JF = 16'hC080;
|
|
parameter integer PHASE_SHIFT = 0;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
input CLKFB;
|
|
input CLKIN;
|
|
input DSSEN;
|
|
input PSCLK;
|
|
input PSEN;
|
|
input PSINCDEC;
|
|
input RST;
|
|
output CLK0;
|
|
output CLK180;
|
|
output CLK270;
|
|
output CLK2X;
|
|
output CLK2X180;
|
|
output CLK90;
|
|
output CLKDV;
|
|
output CLKFX;
|
|
output CLKFX180;
|
|
output LOCKED;
|
|
output PSDONE;
|
|
output [7:0] STATUS;
|
|
endmodule
|
|
|
|
module DCM_CLKGEN(CLKFX180, CLKFX, CLKFXDV, LOCKED, PROGDONE, STATUS, CLKIN, FREEZEDCM, PROGCLK, PROGDATA, PROGEN, RST);
|
|
parameter SPREAD_SPECTRUM = "NONE";
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
parameter integer CLKFXDV_DIVIDE = 2;
|
|
parameter integer CLKFX_DIVIDE = 1;
|
|
parameter integer CLKFX_MULTIPLY = 4;
|
|
parameter real CLKFX_MD_MAX = 0.0;
|
|
parameter real CLKIN_PERIOD = 0.0;
|
|
output CLKFX180;
|
|
output CLKFX;
|
|
output CLKFXDV;
|
|
output LOCKED;
|
|
output PROGDONE;
|
|
output [2:1] STATUS;
|
|
input CLKIN;
|
|
input FREEZEDCM;
|
|
input PROGCLK;
|
|
input PROGDATA;
|
|
input PROGEN;
|
|
input RST;
|
|
endmodule
|
|
|
|
module DCM_ADV(CLK0, CLK180, CLK270, CLK2X180, CLK2X, CLK90, CLKDV, CLKFX180, CLKFX, DRDY, LOCKED, PSDONE, DO, CLKFB, CLKIN, DCLK, DEN, DWE, PSCLK, PSEN, PSINCDEC
|
|
, RST, DI, DADDR);
|
|
parameter real CLKDV_DIVIDE = 2.0;
|
|
parameter integer CLKFX_DIVIDE = 1;
|
|
parameter integer CLKFX_MULTIPLY = 4;
|
|
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
|
|
parameter real CLKIN_PERIOD = 10.0;
|
|
parameter CLKOUT_PHASE_SHIFT = "NONE";
|
|
parameter CLK_FEEDBACK = "1X";
|
|
parameter DCM_AUTOCALIBRATION = "TRUE";
|
|
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
|
|
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
|
|
parameter DFS_FREQUENCY_MODE = "LOW";
|
|
parameter DLL_FREQUENCY_MODE = "LOW";
|
|
parameter DUTY_CYCLE_CORRECTION = "TRUE";
|
|
parameter FACTORY_JF = 16'hF0F0;
|
|
parameter integer PHASE_SHIFT = 0;
|
|
parameter SIM_DEVICE ="VIRTEX4";
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLK0;
|
|
output CLK180;
|
|
output CLK270;
|
|
output CLK2X180;
|
|
output CLK2X;
|
|
output CLK90;
|
|
output CLKDV;
|
|
output CLKFX180;
|
|
output CLKFX;
|
|
output DRDY;
|
|
output LOCKED;
|
|
output PSDONE;
|
|
output [15:0] DO;
|
|
input CLKFB;
|
|
input CLKIN;
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
input PSCLK;
|
|
input PSEN;
|
|
input PSINCDEC;
|
|
input RST;
|
|
input [15:0] DI;
|
|
input [6:0] DADDR;
|
|
endmodule
|
|
|
|
module DCM_BASE(CLK0, CLK180, CLK270, CLK2X180, CLK2X, CLK90, CLKDV, CLKFX180, CLKFX, LOCKED, CLKFB, CLKIN, RST);
|
|
parameter real CLKDV_DIVIDE = 2.0;
|
|
parameter integer CLKFX_DIVIDE = 1;
|
|
parameter integer CLKFX_MULTIPLY = 4;
|
|
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
|
|
parameter real CLKIN_PERIOD = 10.0;
|
|
parameter CLKOUT_PHASE_SHIFT = "NONE";
|
|
parameter CLK_FEEDBACK = "1X";
|
|
parameter DCM_AUTOCALIBRATION = "TRUE";
|
|
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
|
|
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
|
|
parameter DFS_FREQUENCY_MODE = "LOW";
|
|
parameter DLL_FREQUENCY_MODE = "LOW";
|
|
parameter DUTY_CYCLE_CORRECTION = "TRUE";
|
|
parameter [15:0] FACTORY_JF = 16'hF0F0;
|
|
parameter integer PHASE_SHIFT = 0;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLK0;
|
|
output CLK180;
|
|
output CLK270;
|
|
output CLK2X180;
|
|
output CLK2X;
|
|
output CLK90;
|
|
output CLKDV;
|
|
output CLKFX180;
|
|
output CLKFX;
|
|
output LOCKED;
|
|
input CLKFB;
|
|
input CLKIN;
|
|
input RST;
|
|
endmodule
|
|
|
|
module DCM_PS(CLK0, CLK180, CLK270, CLK2X180, CLK2X, CLK90, CLKDV, CLKFX180, CLKFX, LOCKED, PSDONE, DO, CLKFB, CLKIN, PSCLK, PSEN, PSINCDEC, RST);
|
|
parameter real CLKDV_DIVIDE = 2.0;
|
|
parameter integer CLKFX_DIVIDE = 1;
|
|
parameter integer CLKFX_MULTIPLY = 4;
|
|
parameter CLKIN_DIVIDE_BY_2 = "FALSE";
|
|
parameter real CLKIN_PERIOD = 10.0;
|
|
parameter CLKOUT_PHASE_SHIFT = "NONE";
|
|
parameter CLK_FEEDBACK = "1X";
|
|
parameter DCM_AUTOCALIBRATION = "TRUE";
|
|
parameter DCM_PERFORMANCE_MODE = "MAX_SPEED";
|
|
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
|
|
parameter DFS_FREQUENCY_MODE = "LOW";
|
|
parameter DLL_FREQUENCY_MODE = "LOW";
|
|
parameter DUTY_CYCLE_CORRECTION = "TRUE";
|
|
parameter [15:0] FACTORY_JF = 16'hF0F0;
|
|
parameter integer PHASE_SHIFT = 0;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLK0;
|
|
output CLK180;
|
|
output CLK270;
|
|
output CLK2X180;
|
|
output CLK2X;
|
|
output CLK90;
|
|
output CLKDV;
|
|
output CLKFX180;
|
|
output CLKFX;
|
|
output LOCKED;
|
|
output PSDONE;
|
|
output [15:0] DO;
|
|
input CLKFB;
|
|
input CLKIN;
|
|
input PSCLK;
|
|
input PSEN;
|
|
input PSINCDEC;
|
|
input RST;
|
|
endmodule
|
|
|
|
module PMCD(CLKA1, CLKA1D2, CLKA1D4, CLKA1D8, CLKB1, CLKC1, CLKD1, CLKA, CLKB, CLKC, CLKD, REL, RST);
|
|
parameter EN_REL = "FALSE";
|
|
parameter RST_DEASSERT_CLK = "CLKA";
|
|
output CLKA1;
|
|
output CLKA1D2;
|
|
output CLKA1D4;
|
|
output CLKA1D8;
|
|
output CLKB1;
|
|
output CLKC1;
|
|
output CLKD1;
|
|
input CLKA;
|
|
input CLKB;
|
|
input CLKC;
|
|
input CLKD;
|
|
input REL;
|
|
input RST;
|
|
endmodule
|
|
|
|
module PLL_ADV(CLKFBDCM, CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUTDCM0, CLKOUTDCM1, CLKOUTDCM2, CLKOUTDCM3, CLKOUTDCM4, CLKOUTDCM5, DRDY, LOCKED, DO, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL
|
|
, DCLK, DEN, DWE, REL, RST, DI, DADDR);
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter CLK_FEEDBACK = "CLKFBOUT";
|
|
parameter CLKFBOUT_DESKEW_ADJUST = "NONE";
|
|
parameter CLKOUT0_DESKEW_ADJUST = "NONE";
|
|
parameter CLKOUT1_DESKEW_ADJUST = "NONE";
|
|
parameter CLKOUT2_DESKEW_ADJUST = "NONE";
|
|
parameter CLKOUT3_DESKEW_ADJUST = "NONE";
|
|
parameter CLKOUT4_DESKEW_ADJUST = "NONE";
|
|
parameter CLKOUT5_DESKEW_ADJUST = "NONE";
|
|
parameter integer CLKFBOUT_MULT = 1;
|
|
parameter real CLKFBOUT_PHASE = 0.0;
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKIN2_PERIOD = 0.000;
|
|
parameter integer CLKOUT0_DIVIDE = 1;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT0_PHASE = 0.0;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT1_PHASE = 0.0;
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT2_PHASE = 0.0;
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT3_PHASE = 0.0;
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT4_PHASE = 0.0;
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT5_PHASE = 0.0;
|
|
parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter EN_REL = "FALSE";
|
|
parameter PLL_PMCD_MODE = "FALSE";
|
|
parameter real REF_JITTER = 0.100;
|
|
parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
|
|
parameter RST_DEASSERT_CLK = "CLKIN1";
|
|
parameter SIM_DEVICE = "VIRTEX5";
|
|
parameter real VCOCLK_FREQ_MAX = 1440.0;
|
|
parameter real VCOCLK_FREQ_MIN = 400.0;
|
|
parameter real CLKIN_FREQ_MAX = 710.0;
|
|
parameter real CLKIN_FREQ_MIN = 19.0;
|
|
parameter real CLKPFD_FREQ_MAX = 550.0;
|
|
parameter real CLKPFD_FREQ_MIN = 19.0;
|
|
output CLKFBDCM;
|
|
output CLKFBOUT;
|
|
output CLKOUT0;
|
|
output CLKOUT1;
|
|
output CLKOUT2;
|
|
output CLKOUT3;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output CLKOUTDCM0;
|
|
output CLKOUTDCM1;
|
|
output CLKOUTDCM2;
|
|
output CLKOUTDCM3;
|
|
output CLKOUTDCM4;
|
|
output CLKOUTDCM5;
|
|
output DRDY;
|
|
output LOCKED;
|
|
output [15:0] DO;
|
|
input CLKFBIN;
|
|
input CLKIN1;
|
|
input CLKIN2;
|
|
input CLKINSEL;
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
input REL;
|
|
input RST;
|
|
input [15:0] DI;
|
|
input [4:0] DADDR;
|
|
endmodule
|
|
|
|
module PLL_BASE(CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, LOCKED, CLKFBIN, CLKIN, RST);
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter integer CLKFBOUT_MULT = 1;
|
|
parameter real CLKFBOUT_PHASE = 0.0;
|
|
parameter real CLKIN_PERIOD = 0.000;
|
|
parameter integer CLKOUT0_DIVIDE = 1;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT0_PHASE = 0.0;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT1_PHASE = 0.0;
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT2_PHASE = 0.0;
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT3_PHASE = 0.0;
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT4_PHASE = 0.0;
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.5;
|
|
parameter real CLKOUT5_PHASE = 0.0;
|
|
parameter CLK_FEEDBACK = "CLKFBOUT";
|
|
parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter real REF_JITTER = 0.100;
|
|
parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKOUT0;
|
|
output CLKOUT1;
|
|
output CLKOUT2;
|
|
output CLKOUT3;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output LOCKED;
|
|
input CLKFBIN;
|
|
input CLKIN;
|
|
input RST;
|
|
endmodule
|
|
|
|
module MMCM_ADV(CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DRDY, LOCKED, PSDONE, DO, CLKFBIN, CLKIN1
|
|
, CLKIN2, CLKINSEL, DCLK, DEN, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST, DI, DADDR);
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter CLKFBOUT_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT0_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT1_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT2_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT3_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT4_CASCADE = "FALSE";
|
|
parameter CLKOUT4_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT5_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT6_USE_FINE_PS = "FALSE";
|
|
parameter CLOCK_HOLD = "FALSE";
|
|
parameter COMPENSATION = "ZHOLD";
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter integer CLKOUT6_DIVIDE = 1;
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter real CLKFBOUT_MULT_F = 5.000;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKIN2_PERIOD = 0.000;
|
|
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT6_PHASE = 0.000;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter real REF_JITTER2 = 0.010;
|
|
parameter real VCOCLK_FREQ_MAX = 1600.0;
|
|
parameter real VCOCLK_FREQ_MIN = 600.0;
|
|
parameter real CLKIN_FREQ_MAX = 800.0;
|
|
parameter real CLKIN_FREQ_MIN = 10.0;
|
|
parameter real CLKPFD_FREQ_MAX = 550.0;
|
|
parameter real CLKPFD_FREQ_MIN = 10.0;
|
|
output CLKFBOUT;
|
|
output CLKFBOUTB;
|
|
output CLKFBSTOPPED;
|
|
output CLKINSTOPPED;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUT2;
|
|
output CLKOUT2B;
|
|
output CLKOUT3;
|
|
output CLKOUT3B;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output CLKOUT6;
|
|
output DRDY;
|
|
output LOCKED;
|
|
output PSDONE;
|
|
output [15:0] DO;
|
|
input CLKFBIN;
|
|
input CLKIN1;
|
|
input CLKIN2;
|
|
input CLKINSEL;
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
input PSCLK;
|
|
input PSEN;
|
|
input PSINCDEC;
|
|
input PWRDWN;
|
|
input RST;
|
|
input [15:0] DI;
|
|
input [6:0] DADDR;
|
|
endmodule
|
|
|
|
module MMCM_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST);
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter real CLKFBOUT_MULT_F = 5.000;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter CLKOUT4_CASCADE = "FALSE";
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter integer CLKOUT6_DIVIDE = 1;
|
|
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT6_PHASE = 0.000;
|
|
parameter CLOCK_HOLD = "FALSE";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKFBOUTB;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUT2;
|
|
output CLKOUT2B;
|
|
output CLKOUT3;
|
|
output CLKOUT3B;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output CLKOUT6;
|
|
output LOCKED;
|
|
input CLKFBIN;
|
|
input CLKIN1;
|
|
input PWRDWN;
|
|
input RST;
|
|
endmodule
|
|
|
|
module MMCME2_ADV(CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DO, DRDY, LOCKED, PSDONE, CLKFBIN, CLKIN1
|
|
, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST);
|
|
parameter real CLKIN_FREQ_MAX = 1066.000;
|
|
parameter real CLKIN_FREQ_MIN = 10.000;
|
|
parameter real CLKPFD_FREQ_MAX = 550.000;
|
|
parameter real CLKPFD_FREQ_MIN = 10.000;
|
|
parameter real VCOCLK_FREQ_MAX = 1600.000;
|
|
parameter real VCOCLK_FREQ_MIN = 600.000;
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter real CLKFBOUT_MULT_F = 5.000;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter CLKFBOUT_USE_FINE_PS = "FALSE";
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKIN2_PERIOD = 0.000;
|
|
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter CLKOUT0_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter CLKOUT1_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter CLKOUT2_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter CLKOUT3_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT4_CASCADE = "FALSE";
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter CLKOUT4_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter CLKOUT5_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT6_DIVIDE = 1;
|
|
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT6_PHASE = 0.000;
|
|
parameter CLKOUT6_USE_FINE_PS = "FALSE";
|
|
parameter COMPENSATION = "ZHOLD";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PSEN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter real REF_JITTER2 = 0.010;
|
|
parameter SS_EN = "FALSE";
|
|
parameter SS_MODE = "CENTER_HIGH";
|
|
parameter integer SS_MOD_PERIOD = 10000;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKFBOUTB;
|
|
output CLKFBSTOPPED;
|
|
output CLKINSTOPPED;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUT2;
|
|
output CLKOUT2B;
|
|
output CLKOUT3;
|
|
output CLKOUT3B;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output CLKOUT6;
|
|
output [15:0] DO;
|
|
output DRDY;
|
|
output LOCKED;
|
|
output PSDONE;
|
|
input CLKFBIN;
|
|
input CLKIN1;
|
|
input CLKIN2;
|
|
(* invertible_pin = "IS_CLKINSEL_INVERTED" *)
|
|
input CLKINSEL;
|
|
input [6:0] DADDR;
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
input PSCLK;
|
|
(* invertible_pin = "IS_PSEN_INVERTED" *)
|
|
input PSEN;
|
|
(* invertible_pin = "IS_PSINCDEC_INVERTED" *)
|
|
input PSINCDEC;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module MMCME2_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST);
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter real CLKFBOUT_MULT_F = 5.000;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter CLKOUT4_CASCADE = "FALSE";
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter integer CLKOUT6_DIVIDE = 1;
|
|
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT6_PHASE = 0.000;
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKFBOUTB;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUT2;
|
|
output CLKOUT2B;
|
|
output CLKOUT3;
|
|
output CLKOUT3B;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output CLKOUT6;
|
|
output LOCKED;
|
|
input CLKFBIN;
|
|
input CLKIN1;
|
|
input PWRDWN;
|
|
input RST;
|
|
endmodule
|
|
|
|
module PLLE2_ADV(CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, DRDY, LOCKED, DO, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DCLK, DEN, DWE, PWRDWN, RST, DI, DADDR
|
|
);
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter COMPENSATION = "ZHOLD";
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
parameter integer CLKOUT0_DIVIDE = 1;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter integer CLKFBOUT_MULT = 5;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKIN2_PERIOD = 0.000;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter real REF_JITTER2 = 0.010;
|
|
parameter real VCOCLK_FREQ_MAX = 2133.000;
|
|
parameter real VCOCLK_FREQ_MIN = 800.000;
|
|
parameter real CLKIN_FREQ_MAX = 1066.000;
|
|
parameter real CLKIN_FREQ_MIN = 19.000;
|
|
parameter real CLKPFD_FREQ_MAX = 550.0;
|
|
parameter real CLKPFD_FREQ_MIN = 19.0;
|
|
output CLKFBOUT;
|
|
output CLKOUT0;
|
|
output CLKOUT1;
|
|
output CLKOUT2;
|
|
output CLKOUT3;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output DRDY;
|
|
output LOCKED;
|
|
output [15:0] DO;
|
|
input CLKFBIN;
|
|
input CLKIN1;
|
|
input CLKIN2;
|
|
(* invertible_pin = "IS_CLKINSEL_INVERTED" *)
|
|
input CLKINSEL;
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
input [15:0] DI;
|
|
input [6:0] DADDR;
|
|
endmodule
|
|
|
|
module PLLE2_BASE(CLKFBOUT, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST);
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter integer CLKFBOUT_MULT = 5;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter integer CLKOUT0_DIVIDE = 1;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKOUT0;
|
|
output CLKOUT1;
|
|
output CLKOUT2;
|
|
output CLKOUT3;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output LOCKED;
|
|
input CLKFBIN;
|
|
input CLKIN1;
|
|
input PWRDWN;
|
|
input RST;
|
|
endmodule
|
|
|
|
module MMCME3_ADV(CDDCDONE, CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DO, DRDY, LOCKED, PSDONE, CDDCREQ
|
|
, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST);
|
|
parameter real CLKIN_FREQ_MAX = 1066.000;
|
|
parameter real CLKIN_FREQ_MIN = 10.000;
|
|
parameter real CLKPFD_FREQ_MAX = 550.000;
|
|
parameter real CLKPFD_FREQ_MIN = 10.000;
|
|
parameter real VCOCLK_FREQ_MAX = 1600.000;
|
|
parameter real VCOCLK_FREQ_MIN = 600.000;
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter real CLKFBOUT_MULT_F = 5.000;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter CLKFBOUT_USE_FINE_PS = "FALSE";
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKIN2_PERIOD = 0.000;
|
|
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter CLKOUT0_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter CLKOUT1_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter CLKOUT2_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter CLKOUT3_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT4_CASCADE = "FALSE";
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter CLKOUT4_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter CLKOUT5_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT6_DIVIDE = 1;
|
|
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT6_PHASE = 0.000;
|
|
parameter CLKOUT6_USE_FINE_PS = "FALSE";
|
|
parameter COMPENSATION = "AUTO";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PSEN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter real REF_JITTER2 = 0.010;
|
|
parameter SS_EN = "FALSE";
|
|
parameter SS_MODE = "CENTER_HIGH";
|
|
parameter integer SS_MOD_PERIOD = 10000;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CDDCDONE;
|
|
output CLKFBOUT;
|
|
output CLKFBOUTB;
|
|
output CLKFBSTOPPED;
|
|
output CLKINSTOPPED;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUT2;
|
|
output CLKOUT2B;
|
|
output CLKOUT3;
|
|
output CLKOUT3B;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output CLKOUT6;
|
|
output [15:0] DO;
|
|
output DRDY;
|
|
output LOCKED;
|
|
output PSDONE;
|
|
input CDDCREQ;
|
|
(* invertible_pin = "IS_CLKFBIN_INVERTED" *)
|
|
input CLKFBIN;
|
|
(* invertible_pin = "IS_CLKIN1_INVERTED" *)
|
|
input CLKIN1;
|
|
(* invertible_pin = "IS_CLKIN2_INVERTED" *)
|
|
input CLKIN2;
|
|
(* invertible_pin = "IS_CLKINSEL_INVERTED" *)
|
|
input CLKINSEL;
|
|
input [6:0] DADDR;
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
input PSCLK;
|
|
(* invertible_pin = "IS_PSEN_INVERTED" *)
|
|
input PSEN;
|
|
(* invertible_pin = "IS_PSINCDEC_INVERTED" *)
|
|
input PSINCDEC;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module MMCME3_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST);
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter real CLKFBOUT_MULT_F = 5.000;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter CLKOUT4_CASCADE = "FALSE";
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter integer CLKOUT6_DIVIDE = 1;
|
|
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT6_PHASE = 0.000;
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKFBOUTB;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUT2;
|
|
output CLKOUT2B;
|
|
output CLKOUT3;
|
|
output CLKOUT3B;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output CLKOUT6;
|
|
output LOCKED;
|
|
(* invertible_pin = "IS_CLKFBIN_INVERTED" *)
|
|
input CLKFBIN;
|
|
(* invertible_pin = "IS_CLKIN1_INVERTED" *)
|
|
input CLKIN1;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module PLLE3_ADV(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, DO, DRDY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, DADDR, DCLK, DEN, DI, DWE, PWRDWN, RST);
|
|
parameter real CLKIN_FREQ_MAX = 1066.000;
|
|
parameter real CLKIN_FREQ_MIN = 70.000;
|
|
parameter real CLKPFD_FREQ_MAX = 667.500;
|
|
parameter real CLKPFD_FREQ_MIN = 70.000;
|
|
parameter real VCOCLK_FREQ_MAX = 1335.000;
|
|
parameter real VCOCLK_FREQ_MIN = 600.000;
|
|
parameter integer CLKFBOUT_MULT = 5;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN_PERIOD = 0.000;
|
|
parameter integer CLKOUT0_DIVIDE = 1;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter CLKOUTPHY_MODE = "VCO_2X";
|
|
parameter COMPENSATION = "AUTO";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER = 0.010;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUTPHY;
|
|
output [15:0] DO;
|
|
output DRDY;
|
|
output LOCKED;
|
|
(* invertible_pin = "IS_CLKFBIN_INVERTED" *)
|
|
input CLKFBIN;
|
|
(* invertible_pin = "IS_CLKIN_INVERTED" *)
|
|
input CLKIN;
|
|
input CLKOUTPHYEN;
|
|
input [6:0] DADDR;
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module PLLE3_BASE(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, PWRDWN, RST);
|
|
parameter integer CLKFBOUT_MULT = 5;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN_PERIOD = 0.000;
|
|
parameter integer CLKOUT0_DIVIDE = 1;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter CLKOUTPHY_MODE = "VCO_2X";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER = 0.010;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUTPHY;
|
|
output LOCKED;
|
|
(* invertible_pin = "IS_CLKFBIN_INVERTED" *)
|
|
input CLKFBIN;
|
|
(* invertible_pin = "IS_CLKIN_INVERTED" *)
|
|
input CLKIN;
|
|
input CLKOUTPHYEN;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module MMCME4_ADV(CDDCDONE, CLKFBOUT, CLKFBOUTB, CLKFBSTOPPED, CLKINSTOPPED, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, DO, DRDY, LOCKED, PSDONE, CDDCREQ
|
|
, CLKFBIN, CLKIN1, CLKIN2, CLKINSEL, DADDR, DCLK, DEN, DI, DWE, PSCLK, PSEN, PSINCDEC, PWRDWN, RST);
|
|
parameter real CLKIN_FREQ_MAX = 1066.000;
|
|
parameter real CLKIN_FREQ_MIN = 10.000;
|
|
parameter real CLKPFD_FREQ_MAX = 550.000;
|
|
parameter real CLKPFD_FREQ_MIN = 10.000;
|
|
parameter real VCOCLK_FREQ_MAX = 1600.000;
|
|
parameter real VCOCLK_FREQ_MIN = 800.000;
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter real CLKFBOUT_MULT_F = 5.000;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter CLKFBOUT_USE_FINE_PS = "FALSE";
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKIN2_PERIOD = 0.000;
|
|
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter CLKOUT0_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter CLKOUT1_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter CLKOUT2_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter CLKOUT3_USE_FINE_PS = "FALSE";
|
|
parameter CLKOUT4_CASCADE = "FALSE";
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter CLKOUT4_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter CLKOUT5_USE_FINE_PS = "FALSE";
|
|
parameter integer CLKOUT6_DIVIDE = 1;
|
|
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT6_PHASE = 0.000;
|
|
parameter CLKOUT6_USE_FINE_PS = "FALSE";
|
|
parameter COMPENSATION = "AUTO";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PSEN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter real REF_JITTER2 = 0.010;
|
|
parameter SS_EN = "FALSE";
|
|
parameter SS_MODE = "CENTER_HIGH";
|
|
parameter integer SS_MOD_PERIOD = 10000;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CDDCDONE;
|
|
output CLKFBOUT;
|
|
output CLKFBOUTB;
|
|
output CLKFBSTOPPED;
|
|
output CLKINSTOPPED;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUT2;
|
|
output CLKOUT2B;
|
|
output CLKOUT3;
|
|
output CLKOUT3B;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output CLKOUT6;
|
|
output [15:0] DO;
|
|
output DRDY;
|
|
output LOCKED;
|
|
output PSDONE;
|
|
input CDDCREQ;
|
|
(* invertible_pin = "IS_CLKFBIN_INVERTED" *)
|
|
input CLKFBIN;
|
|
(* invertible_pin = "IS_CLKIN1_INVERTED" *)
|
|
input CLKIN1;
|
|
(* invertible_pin = "IS_CLKIN2_INVERTED" *)
|
|
input CLKIN2;
|
|
(* invertible_pin = "IS_CLKINSEL_INVERTED" *)
|
|
input CLKINSEL;
|
|
input [6:0] DADDR;
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
input PSCLK;
|
|
(* invertible_pin = "IS_PSEN_INVERTED" *)
|
|
input PSEN;
|
|
(* invertible_pin = "IS_PSINCDEC_INVERTED" *)
|
|
input PSINCDEC;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module MMCME4_BASE(CLKFBOUT, CLKFBOUTB, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUT2, CLKOUT2B, CLKOUT3, CLKOUT3B, CLKOUT4, CLKOUT5, CLKOUT6, LOCKED, CLKFBIN, CLKIN1, PWRDWN, RST);
|
|
parameter BANDWIDTH = "OPTIMIZED";
|
|
parameter real CLKFBOUT_MULT_F = 5.000;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN1_PERIOD = 0.000;
|
|
parameter real CLKOUT0_DIVIDE_F = 1.000;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter integer CLKOUT2_DIVIDE = 1;
|
|
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT2_PHASE = 0.000;
|
|
parameter integer CLKOUT3_DIVIDE = 1;
|
|
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT3_PHASE = 0.000;
|
|
parameter CLKOUT4_CASCADE = "FALSE";
|
|
parameter integer CLKOUT4_DIVIDE = 1;
|
|
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT4_PHASE = 0.000;
|
|
parameter integer CLKOUT5_DIVIDE = 1;
|
|
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT5_PHASE = 0.000;
|
|
parameter integer CLKOUT6_DIVIDE = 1;
|
|
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT6_PHASE = 0.000;
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER1 = 0.010;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKFBOUTB;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUT2;
|
|
output CLKOUT2B;
|
|
output CLKOUT3;
|
|
output CLKOUT3B;
|
|
output CLKOUT4;
|
|
output CLKOUT5;
|
|
output CLKOUT6;
|
|
output LOCKED;
|
|
(* invertible_pin = "IS_CLKFBIN_INVERTED" *)
|
|
input CLKFBIN;
|
|
(* invertible_pin = "IS_CLKIN1_INVERTED" *)
|
|
input CLKIN1;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module PLLE4_ADV(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, DO, DRDY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, DADDR, DCLK, DEN, DI, DWE, PWRDWN, RST);
|
|
parameter real CLKIN_FREQ_MAX = 1066.000;
|
|
parameter real CLKIN_FREQ_MIN = 70.000;
|
|
parameter real CLKPFD_FREQ_MAX = 667.500;
|
|
parameter real CLKPFD_FREQ_MIN = 70.000;
|
|
parameter real VCOCLK_FREQ_MAX = 1500.000;
|
|
parameter real VCOCLK_FREQ_MIN = 750.000;
|
|
parameter integer CLKFBOUT_MULT = 5;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN_PERIOD = 0.000;
|
|
parameter integer CLKOUT0_DIVIDE = 1;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter CLKOUTPHY_MODE = "VCO_2X";
|
|
parameter COMPENSATION = "AUTO";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER = 0.010;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUTPHY;
|
|
output [15:0] DO;
|
|
output DRDY;
|
|
output LOCKED;
|
|
(* invertible_pin = "IS_CLKFBIN_INVERTED" *)
|
|
input CLKFBIN;
|
|
(* invertible_pin = "IS_CLKIN_INVERTED" *)
|
|
input CLKIN;
|
|
input CLKOUTPHYEN;
|
|
input [6:0] DADDR;
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module PLLE4_BASE(CLKFBOUT, CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B, CLKOUTPHY, LOCKED, CLKFBIN, CLKIN, CLKOUTPHYEN, PWRDWN, RST);
|
|
parameter integer CLKFBOUT_MULT = 5;
|
|
parameter real CLKFBOUT_PHASE = 0.000;
|
|
parameter real CLKIN_PERIOD = 0.000;
|
|
parameter integer CLKOUT0_DIVIDE = 1;
|
|
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT0_PHASE = 0.000;
|
|
parameter integer CLKOUT1_DIVIDE = 1;
|
|
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
|
|
parameter real CLKOUT1_PHASE = 0.000;
|
|
parameter CLKOUTPHY_MODE = "VCO_2X";
|
|
parameter integer DIVCLK_DIVIDE = 1;
|
|
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKIN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0;
|
|
parameter real REF_JITTER = 0.010;
|
|
parameter STARTUP_WAIT = "FALSE";
|
|
output CLKFBOUT;
|
|
output CLKOUT0;
|
|
output CLKOUT0B;
|
|
output CLKOUT1;
|
|
output CLKOUT1B;
|
|
output CLKOUTPHY;
|
|
output LOCKED;
|
|
(* invertible_pin = "IS_CLKFBIN_INVERTED" *)
|
|
input CLKFBIN;
|
|
(* invertible_pin = "IS_CLKIN_INVERTED" *)
|
|
input CLKIN;
|
|
input CLKOUTPHYEN;
|
|
(* invertible_pin = "IS_PWRDWN_INVERTED" *)
|
|
input PWRDWN;
|
|
(* invertible_pin = "IS_RST_INVERTED" *)
|
|
input RST;
|
|
endmodule
|
|
|
|
module BUFT(O, I, T);
|
|
output O;
|
|
input I;
|
|
input T;
|
|
endmodule
|
|
|
|
module IN_FIFO(ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, RDCLK, RDEN, RESET, WRCLK, WREN, D0, D1
|
|
, D2, D3, D4, D7, D8, D9, D5, D6);
|
|
parameter integer ALMOST_EMPTY_VALUE = 1;
|
|
parameter integer ALMOST_FULL_VALUE = 1;
|
|
parameter ARRAY_MODE = "ARRAY_MODE_4_X_8";
|
|
parameter SYNCHRONOUS_MODE = "FALSE";
|
|
output ALMOSTEMPTY;
|
|
output ALMOSTFULL;
|
|
output EMPTY;
|
|
output FULL;
|
|
output [7:0] Q0;
|
|
output [7:0] Q1;
|
|
output [7:0] Q2;
|
|
output [7:0] Q3;
|
|
output [7:0] Q4;
|
|
output [7:0] Q5;
|
|
output [7:0] Q6;
|
|
output [7:0] Q7;
|
|
output [7:0] Q8;
|
|
output [7:0] Q9;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input RESET;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
input [3:0] D0;
|
|
input [3:0] D1;
|
|
input [3:0] D2;
|
|
input [3:0] D3;
|
|
input [3:0] D4;
|
|
input [3:0] D7;
|
|
input [3:0] D8;
|
|
input [3:0] D9;
|
|
input [7:0] D5;
|
|
input [7:0] D6;
|
|
endmodule
|
|
|
|
module OUT_FIFO(ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL, Q0, Q1, Q2, Q3, Q4, Q7, Q8, Q9, Q5, Q6, RDCLK, RDEN, RESET, WRCLK, WREN, D0, D1
|
|
, D2, D3, D4, D5, D6, D7, D8, D9);
|
|
parameter integer ALMOST_EMPTY_VALUE = 1;
|
|
parameter integer ALMOST_FULL_VALUE = 1;
|
|
parameter ARRAY_MODE = "ARRAY_MODE_8_X_4";
|
|
parameter OUTPUT_DISABLE = "FALSE";
|
|
parameter SYNCHRONOUS_MODE = "FALSE";
|
|
output ALMOSTEMPTY;
|
|
output ALMOSTFULL;
|
|
output EMPTY;
|
|
output FULL;
|
|
output [3:0] Q0;
|
|
output [3:0] Q1;
|
|
output [3:0] Q2;
|
|
output [3:0] Q3;
|
|
output [3:0] Q4;
|
|
output [3:0] Q7;
|
|
output [3:0] Q8;
|
|
output [3:0] Q9;
|
|
output [7:0] Q5;
|
|
output [7:0] Q6;
|
|
(* clkbuf_sink *)
|
|
input RDCLK;
|
|
input RDEN;
|
|
input RESET;
|
|
(* clkbuf_sink *)
|
|
input WRCLK;
|
|
input WREN;
|
|
input [7:0] D0;
|
|
input [7:0] D1;
|
|
input [7:0] D2;
|
|
input [7:0] D3;
|
|
input [7:0] D4;
|
|
input [7:0] D5;
|
|
input [7:0] D6;
|
|
input [7:0] D7;
|
|
input [7:0] D8;
|
|
input [7:0] D9;
|
|
endmodule
|
|
|
|
module HARD_SYNC(DOUT, CLK, DIN);
|
|
parameter [0:0] INIT = 1'b0;
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0;
|
|
parameter integer LATENCY = 2;
|
|
output DOUT;
|
|
(* clkbuf_sink *)
|
|
(* invertible_pin = "IS_CLK_INVERTED" *)
|
|
input CLK;
|
|
input DIN;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module STARTUP_SPARTAN3(CLK, GSR, GTS);
|
|
input CLK;
|
|
input GSR;
|
|
input GTS;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module STARTUP_SPARTAN3E(CLK, GSR, GTS, MBT);
|
|
input CLK;
|
|
input GSR;
|
|
input GTS;
|
|
input MBT;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module STARTUP_SPARTAN3A(CLK, GSR, GTS);
|
|
input CLK;
|
|
input GSR;
|
|
input GTS;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module STARTUP_SPARTAN6(CFGCLK, CFGMCLK, EOS, CLK, GSR, GTS, KEYCLEARB);
|
|
output CFGCLK;
|
|
output CFGMCLK;
|
|
output EOS;
|
|
input CLK;
|
|
input GSR;
|
|
input GTS;
|
|
input KEYCLEARB;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module STARTUP_VIRTEX4(EOS, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS);
|
|
output EOS;
|
|
input CLK;
|
|
input GSR;
|
|
input GTS;
|
|
input USRCCLKO;
|
|
input USRCCLKTS;
|
|
input USRDONEO;
|
|
input USRDONETS;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module STARTUP_VIRTEX5(CFGCLK, CFGMCLK, DINSPI, EOS, TCKSPI, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS);
|
|
output CFGCLK;
|
|
output CFGMCLK;
|
|
output DINSPI;
|
|
output EOS;
|
|
output TCKSPI;
|
|
input CLK;
|
|
input GSR;
|
|
input GTS;
|
|
input USRCCLKO;
|
|
input USRCCLKTS;
|
|
input USRDONEO;
|
|
input USRDONETS;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module STARTUP_VIRTEX6(CFGCLK, CFGMCLK, DINSPI, EOS, PREQ, TCKSPI, CLK, GSR, GTS, KEYCLEARB, PACK, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS);
|
|
parameter PROG_USR = "FALSE";
|
|
output CFGCLK;
|
|
output CFGMCLK;
|
|
output DINSPI;
|
|
output EOS;
|
|
output PREQ;
|
|
output TCKSPI;
|
|
input CLK;
|
|
input GSR;
|
|
input GTS;
|
|
input KEYCLEARB;
|
|
input PACK;
|
|
input USRCCLKO;
|
|
input USRCCLKTS;
|
|
input USRDONEO;
|
|
input USRDONETS;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module STARTUPE2(CFGCLK, CFGMCLK, EOS, PREQ, CLK, GSR, GTS, KEYCLEARB, PACK, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS);
|
|
parameter PROG_USR = "FALSE";
|
|
parameter real SIM_CCLK_FREQ = 0.0;
|
|
output CFGCLK;
|
|
output CFGMCLK;
|
|
output EOS;
|
|
output PREQ;
|
|
input CLK;
|
|
input GSR;
|
|
input GTS;
|
|
input KEYCLEARB;
|
|
input PACK;
|
|
input USRCCLKO;
|
|
input USRCCLKTS;
|
|
input USRDONEO;
|
|
input USRDONETS;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module STARTUPE3(CFGCLK, CFGMCLK, DI, EOS, PREQ, DO, DTS, FCSBO, FCSBTS, GSR, GTS, KEYCLEARB, PACK, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS);
|
|
parameter PROG_USR = "FALSE";
|
|
parameter real SIM_CCLK_FREQ = 0.0;
|
|
output CFGCLK;
|
|
output CFGMCLK;
|
|
output [3:0] DI;
|
|
output EOS;
|
|
output PREQ;
|
|
input [3:0] DO;
|
|
input [3:0] DTS;
|
|
input FCSBO;
|
|
input FCSBTS;
|
|
input GSR;
|
|
input GTS;
|
|
input KEYCLEARB;
|
|
input PACK;
|
|
input USRCCLKO;
|
|
input USRCCLKTS;
|
|
input USRDONEO;
|
|
input USRDONETS;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module CAPTURE_SPARTAN3(CAP, CLK);
|
|
parameter ONESHOT = "FALSE";
|
|
input CAP;
|
|
input CLK;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module CAPTURE_SPARTAN3A(CAP, CLK);
|
|
parameter ONESHOT = "TRUE";
|
|
input CAP;
|
|
input CLK;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module CAPTURE_VIRTEX4(CAP, CLK);
|
|
parameter ONESHOT = "TRUE";
|
|
input CAP;
|
|
input CLK;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module CAPTURE_VIRTEX5(CAP, CLK);
|
|
parameter ONESHOT = "TRUE";
|
|
input CAP;
|
|
input CLK;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module CAPTURE_VIRTEX6(CAP, CLK);
|
|
parameter ONESHOT = "TRUE";
|
|
input CAP;
|
|
input CLK;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module CAPTUREE2(CAP, CLK);
|
|
parameter ONESHOT = "TRUE";
|
|
input CAP;
|
|
input CLK;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module ICAP_SPARTAN3A(BUSY, O, CE, CLK, WRITE, I);
|
|
output BUSY;
|
|
output [7:0] O;
|
|
input CE;
|
|
input CLK;
|
|
input WRITE;
|
|
input [7:0] I;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module ICAP_SPARTAN6(BUSY, O, CLK, CE, WRITE, I);
|
|
parameter DEVICE_ID = 32'h04000093;
|
|
parameter SIM_CFG_FILE_NAME = "NONE";
|
|
output BUSY;
|
|
output [15:0] O;
|
|
input CLK;
|
|
input CE;
|
|
input WRITE;
|
|
input [15:0] I;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module ICAP_VIRTEX4(BUSY, O, CE, CLK, WRITE, I);
|
|
parameter ICAP_WIDTH = "X8";
|
|
output BUSY;
|
|
output [31:0] O;
|
|
input CE;
|
|
input CLK;
|
|
input WRITE;
|
|
input [31:0] I;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module ICAP_VIRTEX5(BUSY, O, CE, CLK, WRITE, I);
|
|
parameter ICAP_WIDTH = "X8";
|
|
output BUSY;
|
|
output [31:0] O;
|
|
input CE;
|
|
input CLK;
|
|
input WRITE;
|
|
input [31:0] I;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module ICAP_VIRTEX6(BUSY, O, CLK, CSB, RDWRB, I);
|
|
parameter [31:0] DEVICE_ID = 32'h04244093;
|
|
parameter ICAP_WIDTH = "X8";
|
|
parameter SIM_CFG_FILE_NAME = "NONE";
|
|
output BUSY;
|
|
output [31:0] O;
|
|
input CLK;
|
|
input CSB;
|
|
input RDWRB;
|
|
input [31:0] I;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module ICAPE2(O, CLK, CSIB, RDWRB, I);
|
|
parameter [31:0] DEVICE_ID = 32'h04244093;
|
|
parameter ICAP_WIDTH = "X32";
|
|
parameter SIM_CFG_FILE_NAME = "NONE";
|
|
output [31:0] O;
|
|
input CLK;
|
|
input CSIB;
|
|
input RDWRB;
|
|
input [31:0] I;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module ICAPE3(AVAIL, O, PRDONE, PRERROR, CLK, CSIB, RDWRB, I);
|
|
parameter [31:0] DEVICE_ID = 32'h03628093;
|
|
parameter ICAP_AUTO_SWITCH = "DISABLE";
|
|
parameter SIM_CFG_FILE_NAME = "NONE";
|
|
output AVAIL;
|
|
output [31:0] O;
|
|
output PRDONE;
|
|
output PRERROR;
|
|
input CLK;
|
|
input CSIB;
|
|
input RDWRB;
|
|
input [31:0] I;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module BSCAN_SPARTAN3(CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2);
|
|
output CAPTURE;
|
|
output DRCK1;
|
|
output DRCK2;
|
|
output RESET;
|
|
output SEL1;
|
|
output SEL2;
|
|
output SHIFT;
|
|
output TDI;
|
|
output UPDATE;
|
|
input TDO1;
|
|
input TDO2;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module BSCAN_SPARTAN3A(CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TCK, TDI, TMS, UPDATE, TDO1, TDO2);
|
|
output CAPTURE;
|
|
output DRCK1;
|
|
output DRCK2;
|
|
output RESET;
|
|
output SEL1;
|
|
output SEL2;
|
|
output SHIFT;
|
|
output TCK;
|
|
output TDI;
|
|
output TMS;
|
|
output UPDATE;
|
|
input TDO1;
|
|
input TDO2;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module BSCAN_SPARTAN6(CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO);
|
|
parameter integer JTAG_CHAIN = 1;
|
|
output CAPTURE;
|
|
output DRCK;
|
|
output RESET;
|
|
output RUNTEST;
|
|
output SEL;
|
|
output SHIFT;
|
|
output TCK;
|
|
output TDI;
|
|
output TMS;
|
|
output UPDATE;
|
|
input TDO;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module BSCAN_VIRTEX4(CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO);
|
|
parameter integer JTAG_CHAIN = 1;
|
|
output CAPTURE;
|
|
output DRCK;
|
|
output RESET;
|
|
output SEL;
|
|
output SHIFT;
|
|
output TDI;
|
|
output UPDATE;
|
|
input TDO;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module BSCAN_VIRTEX5(CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO);
|
|
parameter integer JTAG_CHAIN = 1;
|
|
output CAPTURE;
|
|
output DRCK;
|
|
output RESET;
|
|
output SEL;
|
|
output SHIFT;
|
|
output TDI;
|
|
output UPDATE;
|
|
input TDO;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module BSCAN_VIRTEX6(CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO);
|
|
parameter DISABLE_JTAG = "FALSE";
|
|
parameter integer JTAG_CHAIN = 1;
|
|
output CAPTURE;
|
|
output DRCK;
|
|
output RESET;
|
|
output RUNTEST;
|
|
output SEL;
|
|
output SHIFT;
|
|
output TCK;
|
|
output TDI;
|
|
output TMS;
|
|
output UPDATE;
|
|
input TDO;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module BSCANE2(CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO);
|
|
parameter DISABLE_JTAG = "FALSE";
|
|
parameter integer JTAG_CHAIN = 1;
|
|
output CAPTURE;
|
|
output DRCK;
|
|
output RESET;
|
|
output RUNTEST;
|
|
output SEL;
|
|
output SHIFT;
|
|
output TCK;
|
|
output TDI;
|
|
output TMS;
|
|
output UPDATE;
|
|
input TDO;
|
|
endmodule
|
|
|
|
module DNA_PORT(DOUT, CLK, DIN, READ, SHIFT);
|
|
parameter [56:0] SIM_DNA_VALUE = 57'h0;
|
|
output DOUT;
|
|
input CLK;
|
|
input DIN;
|
|
input READ;
|
|
input SHIFT;
|
|
endmodule
|
|
|
|
module DNA_PORTE2(DOUT, CLK, DIN, READ, SHIFT);
|
|
parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000;
|
|
output DOUT;
|
|
input CLK;
|
|
input DIN;
|
|
input READ;
|
|
input SHIFT;
|
|
endmodule
|
|
|
|
module FRAME_ECC_VIRTEX4(ERROR, SYNDROME, SYNDROMEVALID);
|
|
output ERROR;
|
|
output [11:0] SYNDROME;
|
|
output SYNDROMEVALID;
|
|
endmodule
|
|
|
|
module FRAME_ECC_VIRTEX5(CRCERROR, ECCERROR, SYNDROMEVALID, SYNDROME);
|
|
output CRCERROR;
|
|
output ECCERROR;
|
|
output SYNDROMEVALID;
|
|
output [11:0] SYNDROME;
|
|
endmodule
|
|
|
|
module FRAME_ECC_VIRTEX6(CRCERROR, ECCERROR, ECCERRORSINGLE, SYNDROMEVALID, SYNDROME, FAR, SYNBIT, SYNWORD);
|
|
parameter FARSRC = "EFAR";
|
|
parameter FRAME_RBT_IN_FILENAME = "NONE";
|
|
output CRCERROR;
|
|
output ECCERROR;
|
|
output ECCERRORSINGLE;
|
|
output SYNDROMEVALID;
|
|
output [12:0] SYNDROME;
|
|
output [23:0] FAR;
|
|
output [4:0] SYNBIT;
|
|
output [6:0] SYNWORD;
|
|
endmodule
|
|
|
|
module FRAME_ECCE2(CRCERROR, ECCERROR, ECCERRORSINGLE, SYNDROMEVALID, SYNDROME, FAR, SYNBIT, SYNWORD);
|
|
parameter FARSRC = "EFAR";
|
|
parameter FRAME_RBT_IN_FILENAME = "NONE";
|
|
output CRCERROR;
|
|
output ECCERROR;
|
|
output ECCERRORSINGLE;
|
|
output SYNDROMEVALID;
|
|
output [12:0] SYNDROME;
|
|
output [25:0] FAR;
|
|
output [4:0] SYNBIT;
|
|
output [6:0] SYNWORD;
|
|
endmodule
|
|
|
|
module FRAME_ECCE3(CRCERROR, ECCERRORNOTSINGLE, ECCERRORSINGLE, ENDOFFRAME, ENDOFSCAN, FAR, FARSEL, ICAPBOTCLK, ICAPTOPCLK);
|
|
output CRCERROR;
|
|
output ECCERRORNOTSINGLE;
|
|
output ECCERRORSINGLE;
|
|
output ENDOFFRAME;
|
|
output ENDOFSCAN;
|
|
output [25:0] FAR;
|
|
input [1:0] FARSEL;
|
|
input ICAPBOTCLK;
|
|
input ICAPTOPCLK;
|
|
endmodule
|
|
|
|
module FRAME_ECCE4(CRCERROR, ECCERRORNOTSINGLE, ECCERRORSINGLE, ENDOFFRAME, ENDOFSCAN, FAR, FARSEL, ICAPBOTCLK, ICAPTOPCLK);
|
|
output CRCERROR;
|
|
output ECCERRORNOTSINGLE;
|
|
output ECCERRORSINGLE;
|
|
output ENDOFFRAME;
|
|
output ENDOFSCAN;
|
|
output [26:0] FAR;
|
|
input [1:0] FARSEL;
|
|
input ICAPBOTCLK;
|
|
input ICAPTOPCLK;
|
|
endmodule
|
|
|
|
module USR_ACCESS_VIRTEX4(DATA, DATAVALID);
|
|
output [31:0] DATA;
|
|
output DATAVALID;
|
|
endmodule
|
|
|
|
module USR_ACCESS_VIRTEX5(CFGCLK, DATA, DATAVALID);
|
|
output CFGCLK;
|
|
output [31:0] DATA;
|
|
output DATAVALID;
|
|
endmodule
|
|
|
|
module USR_ACCESS_VIRTEX6(CFGCLK, DATA, DATAVALID);
|
|
output CFGCLK;
|
|
output [31:0] DATA;
|
|
output DATAVALID;
|
|
endmodule
|
|
|
|
module USR_ACCESSE2(CFGCLK, DATAVALID, DATA);
|
|
output CFGCLK;
|
|
output DATAVALID;
|
|
output [31:0] DATA;
|
|
endmodule
|
|
|
|
module POST_CRC_INTERNAL(CRCERROR);
|
|
output CRCERROR;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module SUSPEND_SYNC(SREQ, CLK, SACK);
|
|
output SREQ;
|
|
input CLK;
|
|
input SACK;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module KEY_CLEAR(KEYCLEARB);
|
|
input KEYCLEARB;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module MASTER_JTAG(TDO, TCK, TDI, TMS);
|
|
output TDO;
|
|
input TCK;
|
|
input TDI;
|
|
input TMS;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module SPI_ACCESS(MISO, CLK, CSB, MOSI);
|
|
parameter SIM_DELAY_TYPE = "SCALED";
|
|
parameter SIM_DEVICE = "3S1400AN";
|
|
parameter SIM_FACTORY_ID = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
parameter SIM_MEM_FILE = "NONE";
|
|
parameter SIM_USER_ID = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
|
|
output MISO;
|
|
input CLK;
|
|
input CSB;
|
|
input MOSI;
|
|
endmodule
|
|
|
|
module EFUSE_USR(EFUSEUSR);
|
|
parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000;
|
|
output [31:0] EFUSEUSR;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module SYSMON(BUSY, DRDY, EOC, EOS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, OT, DO, ALM, CHANNEL, CONVST, CONVSTCLK, DCLK, DEN, DWE, RESET, VN, VP, DI, VAUXN
|
|
, VAUXP, DADDR);
|
|
parameter [15:0] INIT_40 = 16'h0;
|
|
parameter [15:0] INIT_41 = 16'h0;
|
|
parameter [15:0] INIT_42 = 16'h0800;
|
|
parameter [15:0] INIT_43 = 16'h0;
|
|
parameter [15:0] INIT_44 = 16'h0;
|
|
parameter [15:0] INIT_45 = 16'h0;
|
|
parameter [15:0] INIT_46 = 16'h0;
|
|
parameter [15:0] INIT_47 = 16'h0;
|
|
parameter [15:0] INIT_48 = 16'h0;
|
|
parameter [15:0] INIT_49 = 16'h0;
|
|
parameter [15:0] INIT_4A = 16'h0;
|
|
parameter [15:0] INIT_4B = 16'h0;
|
|
parameter [15:0] INIT_4C = 16'h0;
|
|
parameter [15:0] INIT_4D = 16'h0;
|
|
parameter [15:0] INIT_4E = 16'h0;
|
|
parameter [15:0] INIT_4F = 16'h0;
|
|
parameter [15:0] INIT_50 = 16'h0;
|
|
parameter [15:0] INIT_51 = 16'h0;
|
|
parameter [15:0] INIT_52 = 16'h0;
|
|
parameter [15:0] INIT_53 = 16'h0;
|
|
parameter [15:0] INIT_54 = 16'h0;
|
|
parameter [15:0] INIT_55 = 16'h0;
|
|
parameter [15:0] INIT_56 = 16'h0;
|
|
parameter [15:0] INIT_57 = 16'h0;
|
|
parameter SIM_DEVICE = "VIRTEX5";
|
|
parameter SIM_MONITOR_FILE = "design.txt";
|
|
output BUSY;
|
|
output DRDY;
|
|
output EOC;
|
|
output EOS;
|
|
output JTAGBUSY;
|
|
output JTAGLOCKED;
|
|
output JTAGMODIFIED;
|
|
output OT;
|
|
output [15:0] DO;
|
|
output [2:0] ALM;
|
|
output [4:0] CHANNEL;
|
|
input CONVST;
|
|
input CONVSTCLK;
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
input RESET;
|
|
input VN;
|
|
input VP;
|
|
input [15:0] DI;
|
|
input [15:0] VAUXN;
|
|
input [15:0] VAUXP;
|
|
input [6:0] DADDR;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module XADC(BUSY, DRDY, EOC, EOS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, OT, DO, ALM, CHANNEL, MUXADDR, CONVST, CONVSTCLK, DCLK, DEN, DWE, RESET, VN, VP, DI
|
|
, VAUXN, VAUXP, DADDR);
|
|
parameter [15:0] INIT_40 = 16'h0;
|
|
parameter [15:0] INIT_41 = 16'h0;
|
|
parameter [15:0] INIT_42 = 16'h0800;
|
|
parameter [15:0] INIT_43 = 16'h0;
|
|
parameter [15:0] INIT_44 = 16'h0;
|
|
parameter [15:0] INIT_45 = 16'h0;
|
|
parameter [15:0] INIT_46 = 16'h0;
|
|
parameter [15:0] INIT_47 = 16'h0;
|
|
parameter [15:0] INIT_48 = 16'h0;
|
|
parameter [15:0] INIT_49 = 16'h0;
|
|
parameter [15:0] INIT_4A = 16'h0;
|
|
parameter [15:0] INIT_4B = 16'h0;
|
|
parameter [15:0] INIT_4C = 16'h0;
|
|
parameter [15:0] INIT_4D = 16'h0;
|
|
parameter [15:0] INIT_4E = 16'h0;
|
|
parameter [15:0] INIT_4F = 16'h0;
|
|
parameter [15:0] INIT_50 = 16'h0;
|
|
parameter [15:0] INIT_51 = 16'h0;
|
|
parameter [15:0] INIT_52 = 16'h0;
|
|
parameter [15:0] INIT_53 = 16'h0;
|
|
parameter [15:0] INIT_54 = 16'h0;
|
|
parameter [15:0] INIT_55 = 16'h0;
|
|
parameter [15:0] INIT_56 = 16'h0;
|
|
parameter [15:0] INIT_57 = 16'h0;
|
|
parameter [15:0] INIT_58 = 16'h0;
|
|
parameter [15:0] INIT_59 = 16'h0;
|
|
parameter [15:0] INIT_5A = 16'h0;
|
|
parameter [15:0] INIT_5B = 16'h0;
|
|
parameter [15:0] INIT_5C = 16'h0;
|
|
parameter [15:0] INIT_5D = 16'h0;
|
|
parameter [15:0] INIT_5E = 16'h0;
|
|
parameter [15:0] INIT_5F = 16'h0;
|
|
parameter IS_CONVSTCLK_INVERTED = 1'b0;
|
|
parameter IS_DCLK_INVERTED = 1'b0;
|
|
parameter SIM_DEVICE = "7SERIES";
|
|
parameter SIM_MONITOR_FILE = "design.txt";
|
|
output BUSY;
|
|
output DRDY;
|
|
output EOC;
|
|
output EOS;
|
|
output JTAGBUSY;
|
|
output JTAGLOCKED;
|
|
output JTAGMODIFIED;
|
|
output OT;
|
|
output [15:0] DO;
|
|
output [7:0] ALM;
|
|
output [4:0] CHANNEL;
|
|
output [4:0] MUXADDR;
|
|
input CONVST;
|
|
(* invertible_pin = "IS_CONVSTCLK_INVERTED" *)
|
|
input CONVSTCLK;
|
|
(* invertible_pin = "IS_DCLK_INVERTED" *)
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
input RESET;
|
|
input VN;
|
|
input VP;
|
|
input [15:0] DI;
|
|
input [15:0] VAUXN;
|
|
input [15:0] VAUXP;
|
|
input [6:0] DADDR;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module SYSMONE1(ALM, BUSY, CHANNEL, DO, DRDY, EOC, EOS, I2C_SCLK_TS, I2C_SDA_TS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, MUXADDR, OT, CONVST, CONVSTCLK, DADDR, DCLK, DEN, DI, DWE
|
|
, I2C_SCLK, I2C_SDA, RESET, VAUXN, VAUXP, VN, VP);
|
|
parameter [15:0] INIT_40 = 16'h0;
|
|
parameter [15:0] INIT_41 = 16'h0;
|
|
parameter [15:0] INIT_42 = 16'h0;
|
|
parameter [15:0] INIT_43 = 16'h0;
|
|
parameter [15:0] INIT_44 = 16'h0;
|
|
parameter [15:0] INIT_45 = 16'h0;
|
|
parameter [15:0] INIT_46 = 16'h0;
|
|
parameter [15:0] INIT_47 = 16'h0;
|
|
parameter [15:0] INIT_48 = 16'h0;
|
|
parameter [15:0] INIT_49 = 16'h0;
|
|
parameter [15:0] INIT_4A = 16'h0;
|
|
parameter [15:0] INIT_4B = 16'h0;
|
|
parameter [15:0] INIT_4C = 16'h0;
|
|
parameter [15:0] INIT_4D = 16'h0;
|
|
parameter [15:0] INIT_4E = 16'h0;
|
|
parameter [15:0] INIT_4F = 16'h0;
|
|
parameter [15:0] INIT_50 = 16'h0;
|
|
parameter [15:0] INIT_51 = 16'h0;
|
|
parameter [15:0] INIT_52 = 16'h0;
|
|
parameter [15:0] INIT_53 = 16'h0;
|
|
parameter [15:0] INIT_54 = 16'h0;
|
|
parameter [15:0] INIT_55 = 16'h0;
|
|
parameter [15:0] INIT_56 = 16'h0;
|
|
parameter [15:0] INIT_57 = 16'h0;
|
|
parameter [15:0] INIT_58 = 16'h0;
|
|
parameter [15:0] INIT_59 = 16'h0;
|
|
parameter [15:0] INIT_5A = 16'h0;
|
|
parameter [15:0] INIT_5B = 16'h0;
|
|
parameter [15:0] INIT_5C = 16'h0;
|
|
parameter [15:0] INIT_5D = 16'h0;
|
|
parameter [15:0] INIT_5E = 16'h0;
|
|
parameter [15:0] INIT_5F = 16'h0;
|
|
parameter [15:0] INIT_60 = 16'h0;
|
|
parameter [15:0] INIT_61 = 16'h0;
|
|
parameter [15:0] INIT_62 = 16'h0;
|
|
parameter [15:0] INIT_63 = 16'h0;
|
|
parameter [15:0] INIT_64 = 16'h0;
|
|
parameter [15:0] INIT_65 = 16'h0;
|
|
parameter [15:0] INIT_66 = 16'h0;
|
|
parameter [15:0] INIT_67 = 16'h0;
|
|
parameter [15:0] INIT_68 = 16'h0;
|
|
parameter [15:0] INIT_69 = 16'h0;
|
|
parameter [15:0] INIT_6A = 16'h0;
|
|
parameter [15:0] INIT_6B = 16'h0;
|
|
parameter [15:0] INIT_6C = 16'h0;
|
|
parameter [15:0] INIT_6D = 16'h0;
|
|
parameter [15:0] INIT_6E = 16'h0;
|
|
parameter [15:0] INIT_6F = 16'h0;
|
|
parameter [15:0] INIT_70 = 16'h0;
|
|
parameter [15:0] INIT_71 = 16'h0;
|
|
parameter [15:0] INIT_72 = 16'h0;
|
|
parameter [15:0] INIT_73 = 16'h0;
|
|
parameter [15:0] INIT_74 = 16'h0;
|
|
parameter [15:0] INIT_75 = 16'h0;
|
|
parameter [15:0] INIT_76 = 16'h0;
|
|
parameter [15:0] INIT_77 = 16'h0;
|
|
parameter [15:0] INIT_78 = 16'h0;
|
|
parameter [15:0] INIT_79 = 16'h0;
|
|
parameter [15:0] INIT_7A = 16'h0;
|
|
parameter [15:0] INIT_7B = 16'h0;
|
|
parameter [15:0] INIT_7C = 16'h0;
|
|
parameter [15:0] INIT_7D = 16'h0;
|
|
parameter [15:0] INIT_7E = 16'h0;
|
|
parameter [15:0] INIT_7F = 16'h0;
|
|
parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_DCLK_INVERTED = 1'b0;
|
|
parameter SIM_MONITOR_FILE = "design.txt";
|
|
parameter integer SYSMON_VUSER0_BANK = 0;
|
|
parameter SYSMON_VUSER0_MONITOR = "NONE";
|
|
parameter integer SYSMON_VUSER1_BANK = 0;
|
|
parameter SYSMON_VUSER1_MONITOR = "NONE";
|
|
parameter integer SYSMON_VUSER2_BANK = 0;
|
|
parameter SYSMON_VUSER2_MONITOR = "NONE";
|
|
parameter integer SYSMON_VUSER3_BANK = 0;
|
|
parameter SYSMON_VUSER3_MONITOR = "NONE";
|
|
output [15:0] ALM;
|
|
output BUSY;
|
|
output [5:0] CHANNEL;
|
|
output [15:0] DO;
|
|
output DRDY;
|
|
output EOC;
|
|
output EOS;
|
|
output I2C_SCLK_TS;
|
|
output I2C_SDA_TS;
|
|
output JTAGBUSY;
|
|
output JTAGLOCKED;
|
|
output JTAGMODIFIED;
|
|
output [4:0] MUXADDR;
|
|
output OT;
|
|
input CONVST;
|
|
(* invertible_pin = "IS_CONVSTCLK_INVERTED" *)
|
|
input CONVSTCLK;
|
|
input [7:0] DADDR;
|
|
(* invertible_pin = "IS_DCLK_INVERTED" *)
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
input I2C_SCLK;
|
|
input I2C_SDA;
|
|
input RESET;
|
|
input [15:0] VAUXN;
|
|
input [15:0] VAUXP;
|
|
input VN;
|
|
input VP;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module SYSMONE4(ADC_DATA, ALM, BUSY, CHANNEL, DO, DRDY, EOC, EOS, I2C_SCLK_TS, I2C_SDA_TS, JTAGBUSY, JTAGLOCKED, JTAGMODIFIED, MUXADDR, OT, SMBALERT_TS, CONVST, CONVSTCLK, DADDR, DCLK, DEN
|
|
, DI, DWE, I2C_SCLK, I2C_SDA, RESET, VAUXN, VAUXP, VN, VP);
|
|
parameter [15:0] COMMON_N_SOURCE = 16'hFFFF;
|
|
parameter [15:0] INIT_40 = 16'h0000;
|
|
parameter [15:0] INIT_41 = 16'h0000;
|
|
parameter [15:0] INIT_42 = 16'h0000;
|
|
parameter [15:0] INIT_43 = 16'h0000;
|
|
parameter [15:0] INIT_44 = 16'h0000;
|
|
parameter [15:0] INIT_45 = 16'h0000;
|
|
parameter [15:0] INIT_46 = 16'h0000;
|
|
parameter [15:0] INIT_47 = 16'h0000;
|
|
parameter [15:0] INIT_48 = 16'h0000;
|
|
parameter [15:0] INIT_49 = 16'h0000;
|
|
parameter [15:0] INIT_4A = 16'h0000;
|
|
parameter [15:0] INIT_4B = 16'h0000;
|
|
parameter [15:0] INIT_4C = 16'h0000;
|
|
parameter [15:0] INIT_4D = 16'h0000;
|
|
parameter [15:0] INIT_4E = 16'h0000;
|
|
parameter [15:0] INIT_4F = 16'h0000;
|
|
parameter [15:0] INIT_50 = 16'h0000;
|
|
parameter [15:0] INIT_51 = 16'h0000;
|
|
parameter [15:0] INIT_52 = 16'h0000;
|
|
parameter [15:0] INIT_53 = 16'h0000;
|
|
parameter [15:0] INIT_54 = 16'h0000;
|
|
parameter [15:0] INIT_55 = 16'h0000;
|
|
parameter [15:0] INIT_56 = 16'h0000;
|
|
parameter [15:0] INIT_57 = 16'h0000;
|
|
parameter [15:0] INIT_58 = 16'h0000;
|
|
parameter [15:0] INIT_59 = 16'h0000;
|
|
parameter [15:0] INIT_5A = 16'h0000;
|
|
parameter [15:0] INIT_5B = 16'h0000;
|
|
parameter [15:0] INIT_5C = 16'h0000;
|
|
parameter [15:0] INIT_5D = 16'h0000;
|
|
parameter [15:0] INIT_5E = 16'h0000;
|
|
parameter [15:0] INIT_5F = 16'h0000;
|
|
parameter [15:0] INIT_60 = 16'h0000;
|
|
parameter [15:0] INIT_61 = 16'h0000;
|
|
parameter [15:0] INIT_62 = 16'h0000;
|
|
parameter [15:0] INIT_63 = 16'h0000;
|
|
parameter [15:0] INIT_64 = 16'h0000;
|
|
parameter [15:0] INIT_65 = 16'h0000;
|
|
parameter [15:0] INIT_66 = 16'h0000;
|
|
parameter [15:0] INIT_67 = 16'h0000;
|
|
parameter [15:0] INIT_68 = 16'h0000;
|
|
parameter [15:0] INIT_69 = 16'h0000;
|
|
parameter [15:0] INIT_6A = 16'h0000;
|
|
parameter [15:0] INIT_6B = 16'h0000;
|
|
parameter [15:0] INIT_6C = 16'h0000;
|
|
parameter [15:0] INIT_6D = 16'h0000;
|
|
parameter [15:0] INIT_6E = 16'h0000;
|
|
parameter [15:0] INIT_6F = 16'h0000;
|
|
parameter [15:0] INIT_70 = 16'h0000;
|
|
parameter [15:0] INIT_71 = 16'h0000;
|
|
parameter [15:0] INIT_72 = 16'h0000;
|
|
parameter [15:0] INIT_73 = 16'h0000;
|
|
parameter [15:0] INIT_74 = 16'h0000;
|
|
parameter [15:0] INIT_75 = 16'h0000;
|
|
parameter [15:0] INIT_76 = 16'h0000;
|
|
parameter [15:0] INIT_77 = 16'h0000;
|
|
parameter [15:0] INIT_78 = 16'h0000;
|
|
parameter [15:0] INIT_79 = 16'h0000;
|
|
parameter [15:0] INIT_7A = 16'h0000;
|
|
parameter [15:0] INIT_7B = 16'h0000;
|
|
parameter [15:0] INIT_7C = 16'h0000;
|
|
parameter [15:0] INIT_7D = 16'h0000;
|
|
parameter [15:0] INIT_7E = 16'h0000;
|
|
parameter [15:0] INIT_7F = 16'h0000;
|
|
parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_DCLK_INVERTED = 1'b0;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter SIM_MONITOR_FILE = "design.txt";
|
|
parameter integer SYSMON_VUSER0_BANK = 0;
|
|
parameter SYSMON_VUSER0_MONITOR = "NONE";
|
|
parameter integer SYSMON_VUSER1_BANK = 0;
|
|
parameter SYSMON_VUSER1_MONITOR = "NONE";
|
|
parameter integer SYSMON_VUSER2_BANK = 0;
|
|
parameter SYSMON_VUSER2_MONITOR = "NONE";
|
|
parameter integer SYSMON_VUSER3_BANK = 0;
|
|
parameter SYSMON_VUSER3_MONITOR = "NONE";
|
|
output [15:0] ADC_DATA;
|
|
output [15:0] ALM;
|
|
output BUSY;
|
|
output [5:0] CHANNEL;
|
|
output [15:0] DO;
|
|
output DRDY;
|
|
output EOC;
|
|
output EOS;
|
|
output I2C_SCLK_TS;
|
|
output I2C_SDA_TS;
|
|
output JTAGBUSY;
|
|
output JTAGLOCKED;
|
|
output JTAGMODIFIED;
|
|
output [4:0] MUXADDR;
|
|
output OT;
|
|
output SMBALERT_TS;
|
|
input CONVST;
|
|
(* invertible_pin = "IS_CONVSTCLK_INVERTED" *)
|
|
input CONVSTCLK;
|
|
input [7:0] DADDR;
|
|
(* invertible_pin = "IS_DCLK_INVERTED" *)
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
input I2C_SCLK;
|
|
input I2C_SDA;
|
|
input RESET;
|
|
input [15:0] VAUXN;
|
|
input [15:0] VAUXP;
|
|
input VN;
|
|
input VP;
|
|
endmodule
|
|
|
|
module GTPA1_DUAL(DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET0, PLLLKDET1, REFCLKOUT0, REFCLKOUT1, REFCLKPLL0, REFCLKPLL1, RESETDONE0, RESETDONE1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1
|
|
, RXCOMMADET0, RXCOMMADET1, RXELECIDLE0, RXELECIDLE1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXVALID0, RXVALID1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, DRPDO, GTPCLKFBEAST, GTPCLKFBWEST, GTPCLKOUT0, GTPCLKOUT1
|
|
, RXLOSSOFSYNC0, RXLOSSOFSYNC1, TXBUFSTATUS0, TXBUFSTATUS1, RXBUFSTATUS0, RXBUFSTATUS1, RXCHBONDO, RXCLKCORCNT0, RXCLKCORCNT1, RXSTATUS0, RXSTATUS1, RXDATA0, RXDATA1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXDISPERR0, RXDISPERR1, RXNOTINTABLE0, RXNOTINTABLE1
|
|
, RXRUNDISP0, RXRUNDISP1, TXKERR0, TXKERR1, TXRUNDISP0, TXRUNDISP1, RCALOUTEAST, RCALOUTWEST, TSTOUT0, TSTOUT1, CLK00, CLK01, CLK10, CLK11, CLKINEAST0, CLKINEAST1, CLKINWEST0, CLKINWEST1, DCLK, DEN, DWE
|
|
, GATERXELECIDLE0, GATERXELECIDLE1, GCLK00, GCLK01, GCLK10, GCLK11, GTPRESET0, GTPRESET1, IGNORESIGDET0, IGNORESIGDET1, INTDATAWIDTH0, INTDATAWIDTH1, PLLCLK00, PLLCLK01, PLLCLK10, PLLCLK11, PLLLKDETEN0, PLLLKDETEN1, PLLPOWERDOWN0, PLLPOWERDOWN1, PRBSCNTRESET0
|
|
, PRBSCNTRESET1, REFCLKPWRDNB0, REFCLKPWRDNB1, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCHBONDMASTER0, RXCHBONDMASTER1, RXCHBONDSLAVE0, RXCHBONDSLAVE1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXENCHANSYNC0, RXENCHANSYNC1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1
|
|
, RXENPMAPHASEALIGN0, RXENPMAPHASEALIGN1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TSTCLK0, TSTCLK1, TXCOMSTART0
|
|
, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDETECTRX0, TXDETECTRX1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1, TXENPMAPHASEALIGN0, TXENPMAPHASEALIGN1, TXINHIBIT0, TXINHIBIT1, TXPDOWNASYNCH0, TXPDOWNASYNCH1, TXPMASETPHASE0, TXPMASETPHASE1, TXPOLARITY0, TXPOLARITY1, TXPRBSFORCEERR0, TXPRBSFORCEERR1
|
|
, TXRESET0, TXRESET1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21, USRCODEERR0, USRCODEERR1, TSTIN0, TSTIN1, DI, GTPCLKFBSEL0EAST, GTPCLKFBSEL0WEST, GTPCLKFBSEL1EAST, GTPCLKFBSEL1WEST, RXDATAWIDTH0, RXDATAWIDTH1, RXEQMIX0, RXEQMIX1, RXPOWERDOWN0, RXPOWERDOWN1
|
|
, TXDATAWIDTH0, TXDATAWIDTH1, TXPOWERDOWN0, TXPOWERDOWN1, LOOPBACK0, LOOPBACK1, REFSELDYPLL0, REFSELDYPLL1, RXCHBONDI, RXENPRBSTST0, RXENPRBSTST1, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXENPRBSTST0, TXENPRBSTST1, TXPREEMPHASIS0, TXPREEMPHASIS1, TXDATA0, TXDATA1, TXBYPASS8B10B0, TXBYPASS8B10B1
|
|
, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXDIFFCTRL0, TXDIFFCTRL1, RCALINEAST, RCALINWEST, DADDR, GTPTEST0, GTPTEST1);
|
|
parameter AC_CAP_DIS_0 = "TRUE";
|
|
parameter AC_CAP_DIS_1 = "TRUE";
|
|
parameter integer ALIGN_COMMA_WORD_0 = 1;
|
|
parameter integer ALIGN_COMMA_WORD_1 = 1;
|
|
parameter integer CB2_INH_CC_PERIOD_0 = 8;
|
|
parameter integer CB2_INH_CC_PERIOD_1 = 8;
|
|
parameter [4:0] CDR_PH_ADJ_TIME_0 = 5'b01010;
|
|
parameter [4:0] CDR_PH_ADJ_TIME_1 = 5'b01010;
|
|
parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7;
|
|
parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7;
|
|
parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1;
|
|
parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1;
|
|
parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE";
|
|
parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE";
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111;
|
|
parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE";
|
|
parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE";
|
|
parameter integer CHAN_BOND_SEQ_LEN_0 = 1;
|
|
parameter integer CHAN_BOND_SEQ_LEN_1 = 1;
|
|
parameter integer CLK25_DIVIDER_0 = 4;
|
|
parameter integer CLK25_DIVIDER_1 = 4;
|
|
parameter CLKINDC_B_0 = "TRUE";
|
|
parameter CLKINDC_B_1 = "TRUE";
|
|
parameter CLKRCV_TRST_0 = "TRUE";
|
|
parameter CLKRCV_TRST_1 = "TRUE";
|
|
parameter CLK_CORRECT_USE_0 = "TRUE";
|
|
parameter CLK_CORRECT_USE_1 = "TRUE";
|
|
parameter integer CLK_COR_ADJ_LEN_0 = 1;
|
|
parameter integer CLK_COR_ADJ_LEN_1 = 1;
|
|
parameter integer CLK_COR_DET_LEN_0 = 1;
|
|
parameter integer CLK_COR_DET_LEN_1 = 1;
|
|
parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
|
|
parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
|
|
parameter CLK_COR_KEEP_IDLE_0 = "FALSE";
|
|
parameter CLK_COR_KEEP_IDLE_1 = "FALSE";
|
|
parameter integer CLK_COR_MAX_LAT_0 = 20;
|
|
parameter integer CLK_COR_MAX_LAT_1 = 20;
|
|
parameter integer CLK_COR_MIN_LAT_0 = 18;
|
|
parameter integer CLK_COR_MIN_LAT_1 = 18;
|
|
parameter CLK_COR_PRECEDENCE_0 = "TRUE";
|
|
parameter CLK_COR_PRECEDENCE_1 = "TRUE";
|
|
parameter integer CLK_COR_REPEAT_WAIT_0 = 0;
|
|
parameter integer CLK_COR_REPEAT_WAIT_1 = 0;
|
|
parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111;
|
|
parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111;
|
|
parameter CLK_COR_SEQ_2_USE_0 = "FALSE";
|
|
parameter CLK_COR_SEQ_2_USE_1 = "FALSE";
|
|
parameter CLK_OUT_GTP_SEL_0 = "REFCLKPLL0";
|
|
parameter CLK_OUT_GTP_SEL_1 = "REFCLKPLL1";
|
|
parameter [1:0] CM_TRIM_0 = 2'b00;
|
|
parameter [1:0] CM_TRIM_1 = 2'b00;
|
|
parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111;
|
|
parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111;
|
|
parameter [3:0] COM_BURST_VAL_0 = 4'b1111;
|
|
parameter [3:0] COM_BURST_VAL_1 = 4'b1111;
|
|
parameter DEC_MCOMMA_DETECT_0 = "TRUE";
|
|
parameter DEC_MCOMMA_DETECT_1 = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT_0 = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT_1 = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY_0 = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY_1 = "TRUE";
|
|
parameter GTP_CFG_PWRUP_0 = "TRUE";
|
|
parameter GTP_CFG_PWRUP_1 = "TRUE";
|
|
parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011;
|
|
parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011;
|
|
parameter MCOMMA_DETECT_0 = "TRUE";
|
|
parameter MCOMMA_DETECT_1 = "TRUE";
|
|
parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110;
|
|
parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110;
|
|
parameter integer OOB_CLK_DIVIDER_0 = 4;
|
|
parameter integer OOB_CLK_DIVIDER_1 = 4;
|
|
parameter PCI_EXPRESS_MODE_0 = "FALSE";
|
|
parameter PCI_EXPRESS_MODE_1 = "FALSE";
|
|
parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100;
|
|
parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100;
|
|
parameter PCOMMA_DETECT_0 = "TRUE";
|
|
parameter PCOMMA_DETECT_1 = "TRUE";
|
|
parameter [2:0] PLLLKDET_CFG_0 = 3'b101;
|
|
parameter [2:0] PLLLKDET_CFG_1 = 3'b101;
|
|
parameter [23:0] PLL_COM_CFG_0 = 24'h21680A;
|
|
parameter [23:0] PLL_COM_CFG_1 = 24'h21680A;
|
|
parameter [7:0] PLL_CP_CFG_0 = 8'h00;
|
|
parameter [7:0] PLL_CP_CFG_1 = 8'h00;
|
|
parameter integer PLL_DIVSEL_FB_0 = 5;
|
|
parameter integer PLL_DIVSEL_FB_1 = 5;
|
|
parameter integer PLL_DIVSEL_REF_0 = 2;
|
|
parameter integer PLL_DIVSEL_REF_1 = 2;
|
|
parameter integer PLL_RXDIVSEL_OUT_0 = 1;
|
|
parameter integer PLL_RXDIVSEL_OUT_1 = 1;
|
|
parameter PLL_SATA_0 = "FALSE";
|
|
parameter PLL_SATA_1 = "FALSE";
|
|
parameter PLL_SOURCE_0 = "PLL0";
|
|
parameter PLL_SOURCE_1 = "PLL0";
|
|
parameter integer PLL_TXDIVSEL_OUT_0 = 1;
|
|
parameter integer PLL_TXDIVSEL_OUT_1 = 1;
|
|
parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404040;
|
|
parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404040;
|
|
parameter [35:0] PMA_COM_CFG_EAST = 36'h000008000;
|
|
parameter [35:0] PMA_COM_CFG_WEST = 36'h00000A000;
|
|
parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h00;
|
|
parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h00;
|
|
parameter [24:0] PMA_RX_CFG_0 = 25'h05CE048;
|
|
parameter [24:0] PMA_RX_CFG_1 = 25'h05CE048;
|
|
parameter [19:0] PMA_TX_CFG_0 = 20'h00082;
|
|
parameter [19:0] PMA_TX_CFG_1 = 20'h00082;
|
|
parameter RCV_TERM_GND_0 = "FALSE";
|
|
parameter RCV_TERM_GND_1 = "FALSE";
|
|
parameter RCV_TERM_VTTRX_0 = "TRUE";
|
|
parameter RCV_TERM_VTTRX_1 = "TRUE";
|
|
parameter [7:0] RXEQ_CFG_0 = 8'b01111011;
|
|
parameter [7:0] RXEQ_CFG_1 = 8'b01111011;
|
|
parameter [0:0] RXPRBSERR_LOOPBACK_0 = 1'b0;
|
|
parameter [0:0] RXPRBSERR_LOOPBACK_1 = 1'b0;
|
|
parameter RX_BUFFER_USE_0 = "TRUE";
|
|
parameter RX_BUFFER_USE_1 = "TRUE";
|
|
parameter RX_DECODE_SEQ_MATCH_0 = "TRUE";
|
|
parameter RX_DECODE_SEQ_MATCH_1 = "TRUE";
|
|
parameter RX_EN_IDLE_HOLD_CDR_0 = "FALSE";
|
|
parameter RX_EN_IDLE_HOLD_CDR_1 = "FALSE";
|
|
parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_FR_0 = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_FR_1 = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_PH_0 = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_PH_1 = "TRUE";
|
|
parameter RX_EN_MODE_RESET_BUF_0 = "TRUE";
|
|
parameter RX_EN_MODE_RESET_BUF_1 = "TRUE";
|
|
parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000;
|
|
parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000;
|
|
parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000;
|
|
parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000;
|
|
parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE";
|
|
parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE";
|
|
parameter integer RX_LOS_INVALID_INCR_0 = 1;
|
|
parameter integer RX_LOS_INVALID_INCR_1 = 1;
|
|
parameter integer RX_LOS_THRESHOLD_0 = 4;
|
|
parameter integer RX_LOS_THRESHOLD_1 = 4;
|
|
parameter RX_SLIDE_MODE_0 = "PCS";
|
|
parameter RX_SLIDE_MODE_1 = "PCS";
|
|
parameter RX_STATUS_FMT_0 = "PCIE";
|
|
parameter RX_STATUS_FMT_1 = "PCIE";
|
|
parameter RX_XCLK_SEL_0 = "RXREC";
|
|
parameter RX_XCLK_SEL_1 = "RXREC";
|
|
parameter [2:0] SATA_BURST_VAL_0 = 3'b100;
|
|
parameter [2:0] SATA_BURST_VAL_1 = 3'b100;
|
|
parameter [2:0] SATA_IDLE_VAL_0 = 3'b011;
|
|
parameter [2:0] SATA_IDLE_VAL_1 = 3'b011;
|
|
parameter integer SATA_MAX_BURST_0 = 7;
|
|
parameter integer SATA_MAX_BURST_1 = 7;
|
|
parameter integer SATA_MAX_INIT_0 = 22;
|
|
parameter integer SATA_MAX_INIT_1 = 22;
|
|
parameter integer SATA_MAX_WAKE_0 = 7;
|
|
parameter integer SATA_MAX_WAKE_1 = 7;
|
|
parameter integer SATA_MIN_BURST_0 = 4;
|
|
parameter integer SATA_MIN_BURST_1 = 4;
|
|
parameter integer SATA_MIN_INIT_0 = 12;
|
|
parameter integer SATA_MIN_INIT_1 = 12;
|
|
parameter integer SATA_MIN_WAKE_0 = 4;
|
|
parameter integer SATA_MIN_WAKE_1 = 4;
|
|
parameter integer SIM_GTPRESET_SPEEDUP = 0;
|
|
parameter SIM_RECEIVER_DETECT_PASS = "FALSE";
|
|
parameter [2:0] SIM_REFCLK0_SOURCE = 3'b000;
|
|
parameter [2:0] SIM_REFCLK1_SOURCE = 3'b000;
|
|
parameter SIM_TX_ELEC_IDLE_LEVEL = "X";
|
|
parameter SIM_VERSION = "2.0";
|
|
parameter [4:0] TERMINATION_CTRL_0 = 5'b10100;
|
|
parameter [4:0] TERMINATION_CTRL_1 = 5'b10100;
|
|
parameter TERMINATION_OVRD_0 = "FALSE";
|
|
parameter TERMINATION_OVRD_1 = "FALSE";
|
|
parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03C;
|
|
parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03C;
|
|
parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19;
|
|
parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19;
|
|
parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064;
|
|
parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064;
|
|
parameter [31:0] TST_ATTR_0 = 32'h00000000;
|
|
parameter [31:0] TST_ATTR_1 = 32'h00000000;
|
|
parameter [2:0] TXRX_INVERT_0 = 3'b011;
|
|
parameter [2:0] TXRX_INVERT_1 = 3'b011;
|
|
parameter TX_BUFFER_USE_0 = "FALSE";
|
|
parameter TX_BUFFER_USE_1 = "FALSE";
|
|
parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832;
|
|
parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832;
|
|
parameter [2:0] TX_IDLE_DELAY_0 = 3'b011;
|
|
parameter [2:0] TX_IDLE_DELAY_1 = 3'b011;
|
|
parameter [1:0] TX_TDCC_CFG_0 = 2'b00;
|
|
parameter [1:0] TX_TDCC_CFG_1 = 2'b00;
|
|
parameter TX_XCLK_SEL_0 = "TXUSR";
|
|
parameter TX_XCLK_SEL_1 = "TXUSR";
|
|
output DRDY;
|
|
output PHYSTATUS0;
|
|
output PHYSTATUS1;
|
|
output PLLLKDET0;
|
|
output PLLLKDET1;
|
|
output REFCLKOUT0;
|
|
output REFCLKOUT1;
|
|
output REFCLKPLL0;
|
|
output REFCLKPLL1;
|
|
output RESETDONE0;
|
|
output RESETDONE1;
|
|
output RXBYTEISALIGNED0;
|
|
output RXBYTEISALIGNED1;
|
|
output RXBYTEREALIGN0;
|
|
output RXBYTEREALIGN1;
|
|
output RXCHANBONDSEQ0;
|
|
output RXCHANBONDSEQ1;
|
|
output RXCHANISALIGNED0;
|
|
output RXCHANISALIGNED1;
|
|
output RXCHANREALIGN0;
|
|
output RXCHANREALIGN1;
|
|
output RXCOMMADET0;
|
|
output RXCOMMADET1;
|
|
output RXELECIDLE0;
|
|
output RXELECIDLE1;
|
|
output RXPRBSERR0;
|
|
output RXPRBSERR1;
|
|
output RXRECCLK0;
|
|
output RXRECCLK1;
|
|
output RXVALID0;
|
|
output RXVALID1;
|
|
output TXN0;
|
|
output TXN1;
|
|
output TXOUTCLK0;
|
|
output TXOUTCLK1;
|
|
output TXP0;
|
|
output TXP1;
|
|
output [15:0] DRPDO;
|
|
output [1:0] GTPCLKFBEAST;
|
|
output [1:0] GTPCLKFBWEST;
|
|
output [1:0] GTPCLKOUT0;
|
|
output [1:0] GTPCLKOUT1;
|
|
output [1:0] RXLOSSOFSYNC0;
|
|
output [1:0] RXLOSSOFSYNC1;
|
|
output [1:0] TXBUFSTATUS0;
|
|
output [1:0] TXBUFSTATUS1;
|
|
output [2:0] RXBUFSTATUS0;
|
|
output [2:0] RXBUFSTATUS1;
|
|
output [2:0] RXCHBONDO;
|
|
output [2:0] RXCLKCORCNT0;
|
|
output [2:0] RXCLKCORCNT1;
|
|
output [2:0] RXSTATUS0;
|
|
output [2:0] RXSTATUS1;
|
|
output [31:0] RXDATA0;
|
|
output [31:0] RXDATA1;
|
|
output [3:0] RXCHARISCOMMA0;
|
|
output [3:0] RXCHARISCOMMA1;
|
|
output [3:0] RXCHARISK0;
|
|
output [3:0] RXCHARISK1;
|
|
output [3:0] RXDISPERR0;
|
|
output [3:0] RXDISPERR1;
|
|
output [3:0] RXNOTINTABLE0;
|
|
output [3:0] RXNOTINTABLE1;
|
|
output [3:0] RXRUNDISP0;
|
|
output [3:0] RXRUNDISP1;
|
|
output [3:0] TXKERR0;
|
|
output [3:0] TXKERR1;
|
|
output [3:0] TXRUNDISP0;
|
|
output [3:0] TXRUNDISP1;
|
|
output [4:0] RCALOUTEAST;
|
|
output [4:0] RCALOUTWEST;
|
|
output [4:0] TSTOUT0;
|
|
output [4:0] TSTOUT1;
|
|
input CLK00;
|
|
input CLK01;
|
|
input CLK10;
|
|
input CLK11;
|
|
input CLKINEAST0;
|
|
input CLKINEAST1;
|
|
input CLKINWEST0;
|
|
input CLKINWEST1;
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
input GATERXELECIDLE0;
|
|
input GATERXELECIDLE1;
|
|
input GCLK00;
|
|
input GCLK01;
|
|
input GCLK10;
|
|
input GCLK11;
|
|
input GTPRESET0;
|
|
input GTPRESET1;
|
|
input IGNORESIGDET0;
|
|
input IGNORESIGDET1;
|
|
input INTDATAWIDTH0;
|
|
input INTDATAWIDTH1;
|
|
input PLLCLK00;
|
|
input PLLCLK01;
|
|
input PLLCLK10;
|
|
input PLLCLK11;
|
|
input PLLLKDETEN0;
|
|
input PLLLKDETEN1;
|
|
input PLLPOWERDOWN0;
|
|
input PLLPOWERDOWN1;
|
|
input PRBSCNTRESET0;
|
|
input PRBSCNTRESET1;
|
|
input REFCLKPWRDNB0;
|
|
input REFCLKPWRDNB1;
|
|
input RXBUFRESET0;
|
|
input RXBUFRESET1;
|
|
input RXCDRRESET0;
|
|
input RXCDRRESET1;
|
|
input RXCHBONDMASTER0;
|
|
input RXCHBONDMASTER1;
|
|
input RXCHBONDSLAVE0;
|
|
input RXCHBONDSLAVE1;
|
|
input RXCOMMADETUSE0;
|
|
input RXCOMMADETUSE1;
|
|
input RXDEC8B10BUSE0;
|
|
input RXDEC8B10BUSE1;
|
|
input RXENCHANSYNC0;
|
|
input RXENCHANSYNC1;
|
|
input RXENMCOMMAALIGN0;
|
|
input RXENMCOMMAALIGN1;
|
|
input RXENPCOMMAALIGN0;
|
|
input RXENPCOMMAALIGN1;
|
|
input RXENPMAPHASEALIGN0;
|
|
input RXENPMAPHASEALIGN1;
|
|
input RXN0;
|
|
input RXN1;
|
|
input RXP0;
|
|
input RXP1;
|
|
input RXPMASETPHASE0;
|
|
input RXPMASETPHASE1;
|
|
input RXPOLARITY0;
|
|
input RXPOLARITY1;
|
|
input RXRESET0;
|
|
input RXRESET1;
|
|
input RXSLIDE0;
|
|
input RXSLIDE1;
|
|
input RXUSRCLK0;
|
|
input RXUSRCLK1;
|
|
input RXUSRCLK20;
|
|
input RXUSRCLK21;
|
|
input TSTCLK0;
|
|
input TSTCLK1;
|
|
input TXCOMSTART0;
|
|
input TXCOMSTART1;
|
|
input TXCOMTYPE0;
|
|
input TXCOMTYPE1;
|
|
input TXDETECTRX0;
|
|
input TXDETECTRX1;
|
|
input TXELECIDLE0;
|
|
input TXELECIDLE1;
|
|
input TXENC8B10BUSE0;
|
|
input TXENC8B10BUSE1;
|
|
input TXENPMAPHASEALIGN0;
|
|
input TXENPMAPHASEALIGN1;
|
|
input TXINHIBIT0;
|
|
input TXINHIBIT1;
|
|
input TXPDOWNASYNCH0;
|
|
input TXPDOWNASYNCH1;
|
|
input TXPMASETPHASE0;
|
|
input TXPMASETPHASE1;
|
|
input TXPOLARITY0;
|
|
input TXPOLARITY1;
|
|
input TXPRBSFORCEERR0;
|
|
input TXPRBSFORCEERR1;
|
|
input TXRESET0;
|
|
input TXRESET1;
|
|
input TXUSRCLK0;
|
|
input TXUSRCLK1;
|
|
input TXUSRCLK20;
|
|
input TXUSRCLK21;
|
|
input USRCODEERR0;
|
|
input USRCODEERR1;
|
|
input [11:0] TSTIN0;
|
|
input [11:0] TSTIN1;
|
|
input [15:0] DI;
|
|
input [1:0] GTPCLKFBSEL0EAST;
|
|
input [1:0] GTPCLKFBSEL0WEST;
|
|
input [1:0] GTPCLKFBSEL1EAST;
|
|
input [1:0] GTPCLKFBSEL1WEST;
|
|
input [1:0] RXDATAWIDTH0;
|
|
input [1:0] RXDATAWIDTH1;
|
|
input [1:0] RXEQMIX0;
|
|
input [1:0] RXEQMIX1;
|
|
input [1:0] RXPOWERDOWN0;
|
|
input [1:0] RXPOWERDOWN1;
|
|
input [1:0] TXDATAWIDTH0;
|
|
input [1:0] TXDATAWIDTH1;
|
|
input [1:0] TXPOWERDOWN0;
|
|
input [1:0] TXPOWERDOWN1;
|
|
input [2:0] LOOPBACK0;
|
|
input [2:0] LOOPBACK1;
|
|
input [2:0] REFSELDYPLL0;
|
|
input [2:0] REFSELDYPLL1;
|
|
input [2:0] RXCHBONDI;
|
|
input [2:0] RXENPRBSTST0;
|
|
input [2:0] RXENPRBSTST1;
|
|
input [2:0] TXBUFDIFFCTRL0;
|
|
input [2:0] TXBUFDIFFCTRL1;
|
|
input [2:0] TXENPRBSTST0;
|
|
input [2:0] TXENPRBSTST1;
|
|
input [2:0] TXPREEMPHASIS0;
|
|
input [2:0] TXPREEMPHASIS1;
|
|
input [31:0] TXDATA0;
|
|
input [31:0] TXDATA1;
|
|
input [3:0] TXBYPASS8B10B0;
|
|
input [3:0] TXBYPASS8B10B1;
|
|
input [3:0] TXCHARDISPMODE0;
|
|
input [3:0] TXCHARDISPMODE1;
|
|
input [3:0] TXCHARDISPVAL0;
|
|
input [3:0] TXCHARDISPVAL1;
|
|
input [3:0] TXCHARISK0;
|
|
input [3:0] TXCHARISK1;
|
|
input [3:0] TXDIFFCTRL0;
|
|
input [3:0] TXDIFFCTRL1;
|
|
input [4:0] RCALINEAST;
|
|
input [4:0] RCALINWEST;
|
|
input [7:0] DADDR;
|
|
input [7:0] GTPTEST0;
|
|
input [7:0] GTPTEST1;
|
|
endmodule
|
|
|
|
module GT11_CUSTOM(DRDY, RXBUFERR, RXCALFAIL, RXCOMMADET, RXCYCLELIMIT, RXLOCK, RXMCLK, RXPCSHCLKOUT, RXREALIGN, RXRECCLK1, RXRECCLK2, RXSIGDET, TX1N, TX1P, TXBUFERR, TXCALFAIL, TXCYCLELIMIT, TXLOCK, TXOUTCLK1, TXOUTCLK2, TXPCSHCLKOUT
|
|
, DO, RXLOSSOFSYNC, RXCRCOUT, TXCRCOUT, CHBONDO, RXSTATUS, RXDATA, RXCHARISCOMMA, RXCHARISK, RXDISPERR, RXNOTINTABLE, RXRUNDISP, TXKERR, TXRUNDISP, DCLK, DEN, DWE, ENCHANSYNC, ENMCOMMAALIGN, ENPCOMMAALIGN, GREFCLK
|
|
, POWERDOWN, REFCLK1, REFCLK2, RX1N, RX1P, RXBLOCKSYNC64B66BUSE, RXCLKSTABLE, RXCOMMADETUSE, RXCRCCLK, RXCRCDATAVALID, RXCRCINIT, RXCRCINTCLK, RXCRCPD, RXCRCRESET, RXDEC64B66BUSE, RXDEC8B10BUSE, RXDESCRAM64B66BUSE, RXIGNOREBTF, RXPMARESET, RXPOLARITY, RXRESET
|
|
, RXSLIDE, RXSYNC, RXUSRCLK2, RXUSRCLK, TXCLKSTABLE, TXCRCCLK, TXCRCDATAVALID, TXCRCINIT, TXCRCINTCLK, TXCRCPD, TXCRCRESET, TXENC64B66BUSE, TXENC8B10BUSE, TXENOOB, TXGEARBOX64B66BUSE, TXINHIBIT, TXPMARESET, TXPOLARITY, TXRESET, TXSCRAM64B66BUSE, TXSYNC
|
|
, TXUSRCLK2, TXUSRCLK, DI, LOOPBACK, RXDATAWIDTH, RXINTDATAWIDTH, TXDATAWIDTH, TXINTDATAWIDTH, RXCRCDATAWIDTH, TXCRCDATAWIDTH, CHBONDI, RXCRCIN, TXCRCIN, TXDATA, DADDR, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK);
|
|
parameter ALIGN_COMMA_WORD = 1;
|
|
parameter BANDGAPSEL = "FALSE";
|
|
parameter BIASRESSEL = "TRUE";
|
|
parameter CCCB_ARBITRATOR_DISABLE = "FALSE";
|
|
parameter CHAN_BOND_LIMIT = 16;
|
|
parameter CHAN_BOND_MODE = "NONE";
|
|
parameter CHAN_BOND_ONE_SHOT = "FALSE";
|
|
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_MASK = 4'b0000;
|
|
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_MASK = 4'b0000;
|
|
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
|
|
parameter CHAN_BOND_SEQ_LEN = 1;
|
|
parameter CLK_CORRECT_USE = "TRUE";
|
|
parameter CLK_COR_8B10B_DE = "FALSE";
|
|
parameter CLK_COR_MAX_LAT = 36;
|
|
parameter CLK_COR_MIN_LAT = 28;
|
|
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_MASK = 4'b0000;
|
|
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_MASK = 4'b0000;
|
|
parameter CLK_COR_SEQ_2_USE = "FALSE";
|
|
parameter CLK_COR_SEQ_DROP = "FALSE";
|
|
parameter CLK_COR_SEQ_LEN = 1;
|
|
parameter COMMA32 = "FALSE";
|
|
parameter COMMA_10B_MASK = 10'h3FF;
|
|
parameter CYCLE_LIMIT_SEL = 2'b00;
|
|
parameter DCDR_FILTER = 3'b010;
|
|
parameter DEC_MCOMMA_DETECT = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY = "TRUE";
|
|
parameter DIGRX_FWDCLK = 2'b00;
|
|
parameter DIGRX_SYNC_MODE = "FALSE";
|
|
parameter ENABLE_DCDR = "FALSE";
|
|
parameter FDET_HYS_CAL = 3'b110;
|
|
parameter FDET_HYS_SEL = 3'b110;
|
|
parameter FDET_LCK_CAL = 3'b101;
|
|
parameter FDET_LCK_SEL = 3'b101;
|
|
parameter GT11_MODE = "SINGLE";
|
|
parameter IREFBIASMODE = 2'b11;
|
|
parameter LOOPCAL_WAIT = 2'b00;
|
|
parameter MCOMMA_32B_VALUE = 32'h000000F6;
|
|
parameter MCOMMA_DETECT = "TRUE";
|
|
parameter OPPOSITE_SELECT = "FALSE";
|
|
parameter PCOMMA_32B_VALUE = 32'hF6F62828;
|
|
parameter PCOMMA_DETECT = "TRUE";
|
|
parameter PCS_BIT_SLIP = "FALSE";
|
|
parameter PMACLKENABLE = "TRUE";
|
|
parameter PMACOREPWRENABLE = "TRUE";
|
|
parameter PMAIREFTRIM = 4'b0111;
|
|
parameter PMAVBGCTRL = 5'b00000;
|
|
parameter PMAVREFTRIM = 4'b0111;
|
|
parameter PMA_BIT_SLIP = "FALSE";
|
|
parameter REPEATER = "FALSE";
|
|
parameter RXACTST = "FALSE";
|
|
parameter RXAFEEQ = 9'b000000000;
|
|
parameter RXAFEPD = "FALSE";
|
|
parameter RXAFETST = "FALSE";
|
|
parameter RXAPD = "FALSE";
|
|
parameter RXASYNCDIVIDE = 2'b11;
|
|
parameter RXBY_32 = "TRUE";
|
|
parameter RXCDRLOS = 6'b000000;
|
|
parameter RXCLK0_FORCE_PMACLK = "FALSE";
|
|
parameter RXCLKMODE = 6'b110001;
|
|
parameter RXCMADJ = 2'b10;
|
|
parameter RXCPSEL = "TRUE";
|
|
parameter RXCPTST = "FALSE";
|
|
parameter RXCRCCLOCKDOUBLE = "FALSE";
|
|
parameter RXCRCENABLE = "FALSE";
|
|
parameter RXCRCINITVAL = 32'h00000000;
|
|
parameter RXCRCINVERTGEN = "FALSE";
|
|
parameter RXCRCSAMECLOCK = "FALSE";
|
|
parameter RXCTRL1 = 10'h200;
|
|
parameter RXCYCLE_LIMIT_SEL = 2'b00;
|
|
parameter RXDATA_SEL = 2'b00;
|
|
parameter RXDCCOUPLE = "FALSE";
|
|
parameter RXDIGRESET = "FALSE";
|
|
parameter RXDIGRX = "FALSE";
|
|
parameter RXEQ = 64'h4000000000000000;
|
|
parameter RXFDCAL_CLOCK_DIVIDE = "NONE";
|
|
parameter RXFDET_HYS_CAL = 3'b110;
|
|
parameter RXFDET_HYS_SEL = 3'b110;
|
|
parameter RXFDET_LCK_CAL = 3'b101;
|
|
parameter RXFDET_LCK_SEL = 3'b101;
|
|
parameter RXFECONTROL1 = 2'b00;
|
|
parameter RXFECONTROL2 = 3'b000;
|
|
parameter RXFETUNE = 2'b01;
|
|
parameter RXLB = "FALSE";
|
|
parameter RXLKADJ = 5'b00000;
|
|
parameter RXLKAPD = "FALSE";
|
|
parameter RXLOOPCAL_WAIT = 2'b00;
|
|
parameter RXLOOPFILT = 4'b0111;
|
|
parameter RXOUTDIV2SEL = 1;
|
|
parameter RXPD = "FALSE";
|
|
parameter RXPDDTST = "FALSE";
|
|
parameter RXPLLNDIVSEL = 8;
|
|
parameter RXPMACLKSEL = "REFCLK1";
|
|
parameter RXRCPADJ = 3'b011;
|
|
parameter RXRCPPD = "FALSE";
|
|
parameter RXRECCLK1_USE_SYNC = "FALSE";
|
|
parameter RXRIBADJ = 2'b11;
|
|
parameter RXRPDPD = "FALSE";
|
|
parameter RXRSDPD = "FALSE";
|
|
parameter RXSLOWDOWN_CAL = 2'b00;
|
|
parameter RXUSRDIVISOR = 1;
|
|
parameter RXVCODAC_INIT = 10'b1010000000;
|
|
parameter RXVCO_CTRL_ENABLE = "TRUE";
|
|
parameter RX_BUFFER_USE = "TRUE";
|
|
parameter RX_CLOCK_DIVIDER = 2'b00;
|
|
parameter RX_LOS_INVALID_INCR = 1;
|
|
parameter RX_LOS_THRESHOLD = 4;
|
|
parameter SAMPLE_8X = "FALSE";
|
|
parameter SH_CNT_MAX = 64;
|
|
parameter SH_INVALID_CNT_MAX = 16;
|
|
parameter SLOWDOWN_CAL = 2'b00;
|
|
parameter TXABPMACLKSEL = "REFCLK1";
|
|
parameter TXAPD = "FALSE";
|
|
parameter TXAREFBIASSEL = "FALSE";
|
|
parameter TXASYNCDIVIDE = 2'b11;
|
|
parameter TXCLK0_FORCE_PMACLK = "FALSE";
|
|
parameter TXCLKMODE = 4'b1001;
|
|
parameter TXCPSEL = "TRUE";
|
|
parameter TXCRCCLOCKDOUBLE = "FALSE";
|
|
parameter TXCRCENABLE = "FALSE";
|
|
parameter TXCRCINITVAL = 32'h00000000;
|
|
parameter TXCRCINVERTGEN = "FALSE";
|
|
parameter TXCRCSAMECLOCK = "FALSE";
|
|
parameter TXCTRL1 = 10'h200;
|
|
parameter TXDATA_SEL = 2'b00;
|
|
parameter TXDAT_PRDRV_DAC = 3'b111;
|
|
parameter TXDAT_TAP_DAC = 5'b10110;
|
|
parameter TXDIGPD = "FALSE";
|
|
parameter TXFDCAL_CLOCK_DIVIDE = "NONE";
|
|
parameter TXHIGHSIGNALEN = "TRUE";
|
|
parameter TXLOOPFILT = 4'b0111;
|
|
parameter TXLVLSHFTPD = "FALSE";
|
|
parameter TXOUTCLK1_USE_SYNC = "FALSE";
|
|
parameter TXOUTDIV2SEL = 1;
|
|
parameter TXPD = "FALSE";
|
|
parameter TXPHASESEL = "FALSE";
|
|
parameter TXPLLNDIVSEL = 8;
|
|
parameter TXPOST_PRDRV_DAC = 3'b111;
|
|
parameter TXPOST_TAP_DAC = 5'b01110;
|
|
parameter TXPOST_TAP_PD = "TRUE";
|
|
parameter TXPRE_PRDRV_DAC = 3'b111;
|
|
parameter TXPRE_TAP_DAC = 5'b00000;
|
|
parameter TXPRE_TAP_PD = "TRUE";
|
|
parameter TXSLEWRATE = "FALSE";
|
|
parameter TXTERMTRIM = 4'b1100;
|
|
parameter TX_BUFFER_USE = "TRUE";
|
|
parameter TX_CLOCK_DIVIDER = 2'b00;
|
|
parameter VCODAC_INIT = 10'b1010000000;
|
|
parameter VCO_CTRL_ENABLE = "TRUE";
|
|
parameter VREFBIASMODE = 2'b11;
|
|
output DRDY;
|
|
output RXBUFERR;
|
|
output RXCALFAIL;
|
|
output RXCOMMADET;
|
|
output RXCYCLELIMIT;
|
|
output RXLOCK;
|
|
output RXMCLK;
|
|
output RXPCSHCLKOUT;
|
|
output RXREALIGN;
|
|
output RXRECCLK1;
|
|
output RXRECCLK2;
|
|
output RXSIGDET;
|
|
output TX1N;
|
|
output TX1P;
|
|
output TXBUFERR;
|
|
output TXCALFAIL;
|
|
output TXCYCLELIMIT;
|
|
output TXLOCK;
|
|
output TXOUTCLK1;
|
|
output TXOUTCLK2;
|
|
output TXPCSHCLKOUT;
|
|
output [15:0] DO;
|
|
output [1:0] RXLOSSOFSYNC;
|
|
output [31:0] RXCRCOUT;
|
|
output [31:0] TXCRCOUT;
|
|
output [4:0] CHBONDO;
|
|
output [5:0] RXSTATUS;
|
|
output [63:0] RXDATA;
|
|
output [7:0] RXCHARISCOMMA;
|
|
output [7:0] RXCHARISK;
|
|
output [7:0] RXDISPERR;
|
|
output [7:0] RXNOTINTABLE;
|
|
output [7:0] RXRUNDISP;
|
|
output [7:0] TXKERR;
|
|
output [7:0] TXRUNDISP;
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
input ENCHANSYNC;
|
|
input ENMCOMMAALIGN;
|
|
input ENPCOMMAALIGN;
|
|
input GREFCLK;
|
|
input POWERDOWN;
|
|
input REFCLK1;
|
|
input REFCLK2;
|
|
input RX1N;
|
|
input RX1P;
|
|
input RXBLOCKSYNC64B66BUSE;
|
|
input RXCLKSTABLE;
|
|
input RXCOMMADETUSE;
|
|
input RXCRCCLK;
|
|
input RXCRCDATAVALID;
|
|
input RXCRCINIT;
|
|
input RXCRCINTCLK;
|
|
input RXCRCPD;
|
|
input RXCRCRESET;
|
|
input RXDEC64B66BUSE;
|
|
input RXDEC8B10BUSE;
|
|
input RXDESCRAM64B66BUSE;
|
|
input RXIGNOREBTF;
|
|
input RXPMARESET;
|
|
input RXPOLARITY;
|
|
input RXRESET;
|
|
input RXSLIDE;
|
|
input RXSYNC;
|
|
input RXUSRCLK2;
|
|
input RXUSRCLK;
|
|
input TXCLKSTABLE;
|
|
input TXCRCCLK;
|
|
input TXCRCDATAVALID;
|
|
input TXCRCINIT;
|
|
input TXCRCINTCLK;
|
|
input TXCRCPD;
|
|
input TXCRCRESET;
|
|
input TXENC64B66BUSE;
|
|
input TXENC8B10BUSE;
|
|
input TXENOOB;
|
|
input TXGEARBOX64B66BUSE;
|
|
input TXINHIBIT;
|
|
input TXPMARESET;
|
|
input TXPOLARITY;
|
|
input TXRESET;
|
|
input TXSCRAM64B66BUSE;
|
|
input TXSYNC;
|
|
input TXUSRCLK2;
|
|
input TXUSRCLK;
|
|
input [15:0] DI;
|
|
input [1:0] LOOPBACK;
|
|
input [1:0] RXDATAWIDTH;
|
|
input [1:0] RXINTDATAWIDTH;
|
|
input [1:0] TXDATAWIDTH;
|
|
input [1:0] TXINTDATAWIDTH;
|
|
input [2:0] RXCRCDATAWIDTH;
|
|
input [2:0] TXCRCDATAWIDTH;
|
|
input [4:0] CHBONDI;
|
|
input [63:0] RXCRCIN;
|
|
input [63:0] TXCRCIN;
|
|
input [63:0] TXDATA;
|
|
input [7:0] DADDR;
|
|
input [7:0] TXBYPASS8B10B;
|
|
input [7:0] TXCHARDISPMODE;
|
|
input [7:0] TXCHARDISPVAL;
|
|
input [7:0] TXCHARISK;
|
|
endmodule
|
|
|
|
module GT11_DUAL(DRDYA, DRDYB, RXBUFERRA, RXBUFERRB, RXCALFAILA, RXCALFAILB, RXCOMMADETA, RXCOMMADETB, RXCYCLELIMITA, RXCYCLELIMITB, RXLOCKA, RXLOCKB, RXMCLKA, RXMCLKB, RXPCSHCLKOUTA, RXPCSHCLKOUTB, RXREALIGNA, RXREALIGNB, RXRECCLK1A, RXRECCLK1B, RXRECCLK2A
|
|
, RXRECCLK2B, RXSIGDETA, RXSIGDETB, TX1NA, TX1NB, TX1PA, TX1PB, TXBUFERRA, TXBUFERRB, TXCALFAILA, TXCALFAILB, TXCYCLELIMITA, TXCYCLELIMITB, TXLOCKA, TXLOCKB, TXOUTCLK1A, TXOUTCLK1B, TXOUTCLK2A, TXOUTCLK2B, TXPCSHCLKOUTA, TXPCSHCLKOUTB
|
|
, DOA, DOB, RXLOSSOFSYNCA, RXLOSSOFSYNCB, RXCRCOUTA, RXCRCOUTB, TXCRCOUTA, TXCRCOUTB, CHBONDOA, CHBONDOB, RXSTATUSA, RXSTATUSB, RXDATAA, RXDATAB, RXCHARISCOMMAA, RXCHARISCOMMAB, RXCHARISKA, RXCHARISKB, RXDISPERRA, RXDISPERRB, RXNOTINTABLEA
|
|
, RXNOTINTABLEB, RXRUNDISPA, RXRUNDISPB, TXKERRA, TXKERRB, TXRUNDISPA, TXRUNDISPB, DCLKA, DCLKB, DENA, DENB, DWEA, DWEB, ENCHANSYNCA, ENCHANSYNCB, ENMCOMMAALIGNA, ENMCOMMAALIGNB, ENPCOMMAALIGNA, ENPCOMMAALIGNB, GREFCLKA, GREFCLKB
|
|
, POWERDOWNA, POWERDOWNB, REFCLK1A, REFCLK1B, REFCLK2A, REFCLK2B, RX1NA, RX1NB, RX1PA, RX1PB, RXBLOCKSYNC64B66BUSEA, RXBLOCKSYNC64B66BUSEB, RXCLKSTABLEA, RXCLKSTABLEB, RXCOMMADETUSEA, RXCOMMADETUSEB, RXCRCCLKA, RXCRCCLKB, RXCRCDATAVALIDA, RXCRCDATAVALIDB, RXCRCINITA
|
|
, RXCRCINITB, RXCRCINTCLKA, RXCRCINTCLKB, RXCRCPDA, RXCRCPDB, RXCRCRESETA, RXCRCRESETB, RXDEC64B66BUSEA, RXDEC64B66BUSEB, RXDEC8B10BUSEA, RXDEC8B10BUSEB, RXDESCRAM64B66BUSEA, RXDESCRAM64B66BUSEB, RXIGNOREBTFA, RXIGNOREBTFB, RXPMARESETA, RXPMARESETB, RXPOLARITYA, RXPOLARITYB, RXRESETA, RXRESETB
|
|
, RXSLIDEA, RXSLIDEB, RXSYNCA, RXSYNCB, RXUSRCLK2A, RXUSRCLK2B, RXUSRCLKA, RXUSRCLKB, TXCLKSTABLEA, TXCLKSTABLEB, TXCRCCLKA, TXCRCCLKB, TXCRCDATAVALIDA, TXCRCDATAVALIDB, TXCRCINITA, TXCRCINITB, TXCRCINTCLKA, TXCRCINTCLKB, TXCRCPDA, TXCRCPDB, TXCRCRESETA
|
|
, TXCRCRESETB, TXENC64B66BUSEA, TXENC64B66BUSEB, TXENC8B10BUSEA, TXENC8B10BUSEB, TXENOOBA, TXENOOBB, TXGEARBOX64B66BUSEA, TXGEARBOX64B66BUSEB, TXINHIBITA, TXINHIBITB, TXPMARESETA, TXPMARESETB, TXPOLARITYA, TXPOLARITYB, TXRESETA, TXRESETB, TXSCRAM64B66BUSEA, TXSCRAM64B66BUSEB, TXSYNCA, TXSYNCB
|
|
, TXUSRCLK2A, TXUSRCLK2B, TXUSRCLKA, TXUSRCLKB, DIA, DIB, LOOPBACKA, LOOPBACKB, RXDATAWIDTHA, RXDATAWIDTHB, RXINTDATAWIDTHA, RXINTDATAWIDTHB, TXDATAWIDTHA, TXDATAWIDTHB, TXINTDATAWIDTHA, TXINTDATAWIDTHB, RXCRCDATAWIDTHA, RXCRCDATAWIDTHB, TXCRCDATAWIDTHA, TXCRCDATAWIDTHB, CHBONDIA
|
|
, CHBONDIB, RXCRCINA, RXCRCINB, TXCRCINA, TXCRCINB, TXDATAA, TXDATAB, DADDRA, DADDRB, TXBYPASS8B10BA, TXBYPASS8B10BB, TXCHARDISPMODEA, TXCHARDISPMODEB, TXCHARDISPVALA, TXCHARDISPVALB, TXCHARISKA, TXCHARISKB);
|
|
parameter ALIGN_COMMA_WORD_A = 1;
|
|
parameter ALIGN_COMMA_WORD_B = 1;
|
|
parameter BANDGAPSEL_A = "FALSE";
|
|
parameter BANDGAPSEL_B = "FALSE";
|
|
parameter BIASRESSEL_A = "TRUE";
|
|
parameter BIASRESSEL_B = "TRUE";
|
|
parameter CCCB_ARBITRATOR_DISABLE_A = "FALSE";
|
|
parameter CCCB_ARBITRATOR_DISABLE_B = "FALSE";
|
|
parameter CHAN_BOND_LIMIT_A = 16;
|
|
parameter CHAN_BOND_LIMIT_B = 16;
|
|
parameter CHAN_BOND_MODE_A = "NONE";
|
|
parameter CHAN_BOND_MODE_B = "NONE";
|
|
parameter CHAN_BOND_ONE_SHOT_A = "FALSE";
|
|
parameter CHAN_BOND_ONE_SHOT_B = "FALSE";
|
|
parameter CHAN_BOND_SEQ_1_1_A = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_1_B = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_2_A = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_2_B = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_3_A = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_3_B = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_4_A = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_4_B = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_1_MASK_A = 4'b0000;
|
|
parameter CHAN_BOND_SEQ_1_MASK_B = 4'b0000;
|
|
parameter CHAN_BOND_SEQ_2_1_A = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_1_B = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_2_A = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_2_B = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_3_A = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_3_B = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_4_A = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_4_B = 11'b00000000000;
|
|
parameter CHAN_BOND_SEQ_2_MASK_A = 4'b0000;
|
|
parameter CHAN_BOND_SEQ_2_MASK_B = 4'b0000;
|
|
parameter CHAN_BOND_SEQ_2_USE_A = "FALSE";
|
|
parameter CHAN_BOND_SEQ_2_USE_B = "FALSE";
|
|
parameter CHAN_BOND_SEQ_LEN_A = 1;
|
|
parameter CHAN_BOND_SEQ_LEN_B = 1;
|
|
parameter CLK_CORRECT_USE_A = "TRUE";
|
|
parameter CLK_CORRECT_USE_B = "TRUE";
|
|
parameter CLK_COR_8B10B_DE_A = "FALSE";
|
|
parameter CLK_COR_8B10B_DE_B = "FALSE";
|
|
parameter CLK_COR_MAX_LAT_A = 36;
|
|
parameter CLK_COR_MAX_LAT_B = 36;
|
|
parameter CLK_COR_MIN_LAT_A = 28;
|
|
parameter CLK_COR_MIN_LAT_B = 28;
|
|
parameter CLK_COR_SEQ_1_1_A = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_1_B = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_2_A = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_2_B = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_3_A = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_3_B = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_4_A = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_4_B = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_1_MASK_A = 4'b0000;
|
|
parameter CLK_COR_SEQ_1_MASK_B = 4'b0000;
|
|
parameter CLK_COR_SEQ_2_1_A = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_1_B = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_2_A = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_2_B = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_3_A = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_3_B = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_4_A = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_4_B = 11'b00000000000;
|
|
parameter CLK_COR_SEQ_2_MASK_A = 4'b0000;
|
|
parameter CLK_COR_SEQ_2_MASK_B = 4'b0000;
|
|
parameter CLK_COR_SEQ_2_USE_A = "FALSE";
|
|
parameter CLK_COR_SEQ_2_USE_B = "FALSE";
|
|
parameter CLK_COR_SEQ_DROP_A = "FALSE";
|
|
parameter CLK_COR_SEQ_DROP_B = "FALSE";
|
|
parameter CLK_COR_SEQ_LEN_A = 1;
|
|
parameter CLK_COR_SEQ_LEN_B = 1;
|
|
parameter COMMA32_A = "FALSE";
|
|
parameter COMMA32_B = "FALSE";
|
|
parameter COMMA_10B_MASK_A = 10'h3FF;
|
|
parameter COMMA_10B_MASK_B = 10'h3FF;
|
|
parameter CYCLE_LIMIT_SEL_A = 2'b00;
|
|
parameter CYCLE_LIMIT_SEL_B = 2'b00;
|
|
parameter DCDR_FILTER_A = 3'b010;
|
|
parameter DCDR_FILTER_B = 3'b010;
|
|
parameter DEC_MCOMMA_DETECT_A = "TRUE";
|
|
parameter DEC_MCOMMA_DETECT_B = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT_A = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT_B = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY_A = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY_B = "TRUE";
|
|
parameter DIGRX_FWDCLK_A = 2'b00;
|
|
parameter DIGRX_FWDCLK_B = 2'b00;
|
|
parameter DIGRX_SYNC_MODE_A = "FALSE";
|
|
parameter DIGRX_SYNC_MODE_B = "FALSE";
|
|
parameter ENABLE_DCDR_A = "FALSE";
|
|
parameter ENABLE_DCDR_B = "FALSE";
|
|
parameter FDET_HYS_CAL_A = 3'b110;
|
|
parameter FDET_HYS_CAL_B = 3'b110;
|
|
parameter FDET_HYS_SEL_A = 3'b110;
|
|
parameter FDET_HYS_SEL_B = 3'b110;
|
|
parameter FDET_LCK_CAL_A = 3'b101;
|
|
parameter FDET_LCK_CAL_B = 3'b101;
|
|
parameter FDET_LCK_SEL_A = 3'b101;
|
|
parameter FDET_LCK_SEL_B = 3'b101;
|
|
parameter IREFBIASMODE_A = 2'b11;
|
|
parameter IREFBIASMODE_B = 2'b11;
|
|
parameter LOOPCAL_WAIT_A = 2'b00;
|
|
parameter LOOPCAL_WAIT_B = 2'b00;
|
|
parameter MCOMMA_32B_VALUE_A = 32'hA1A1A2A2;
|
|
parameter MCOMMA_32B_VALUE_B = 32'hA1A1A2A2;
|
|
parameter MCOMMA_DETECT_A = "TRUE";
|
|
parameter MCOMMA_DETECT_B = "TRUE";
|
|
parameter OPPOSITE_SELECT_A = "FALSE";
|
|
parameter OPPOSITE_SELECT_B = "FALSE";
|
|
parameter PCOMMA_32B_VALUE_A = 32'hA1A1A2A2;
|
|
parameter PCOMMA_32B_VALUE_B = 32'hA1A1A2A2;
|
|
parameter PCOMMA_DETECT_A = "TRUE";
|
|
parameter PCOMMA_DETECT_B = "TRUE";
|
|
parameter PCS_BIT_SLIP_A = "FALSE";
|
|
parameter PCS_BIT_SLIP_B = "FALSE";
|
|
parameter PMACLKENABLE_A = "TRUE";
|
|
parameter PMACLKENABLE_B = "TRUE";
|
|
parameter PMACOREPWRENABLE_A = "TRUE";
|
|
parameter PMACOREPWRENABLE_B = "TRUE";
|
|
parameter PMAIREFTRIM_A = 4'b0111;
|
|
parameter PMAIREFTRIM_B = 4'b0111;
|
|
parameter PMAVBGCTRL_A = 5'b00000;
|
|
parameter PMAVBGCTRL_B = 5'b00000;
|
|
parameter PMAVREFTRIM_A = 4'b0111;
|
|
parameter PMAVREFTRIM_B = 4'b0111;
|
|
parameter PMA_BIT_SLIP_A = "FALSE";
|
|
parameter PMA_BIT_SLIP_B = "FALSE";
|
|
parameter POWER_ENABLE_A = "TRUE";
|
|
parameter POWER_ENABLE_B = "TRUE";
|
|
parameter REPEATER_A = "FALSE";
|
|
parameter REPEATER_B = "FALSE";
|
|
parameter RXACTST_A = "FALSE";
|
|
parameter RXACTST_B = "FALSE";
|
|
parameter RXAFEEQ_A = 9'b000000000;
|
|
parameter RXAFEEQ_B = 9'b000000000;
|
|
parameter RXAFEPD_A = "FALSE";
|
|
parameter RXAFEPD_B = "FALSE";
|
|
parameter RXAFETST_A = "FALSE";
|
|
parameter RXAFETST_B = "FALSE";
|
|
parameter RXAPD_A = "FALSE";
|
|
parameter RXAPD_B = "FALSE";
|
|
parameter RXASYNCDIVIDE_A = 2'b00;
|
|
parameter RXASYNCDIVIDE_B = 2'b00;
|
|
parameter RXBY_32_A = "TRUE";
|
|
parameter RXBY_32_B = "TRUE";
|
|
parameter RXCDRLOS_A = 6'b000000;
|
|
parameter RXCDRLOS_B = 6'b000000;
|
|
parameter RXCLK0_FORCE_PMACLK_A = "FALSE";
|
|
parameter RXCLK0_FORCE_PMACLK_B = "FALSE";
|
|
parameter RXCLKMODE_A = 6'b110001;
|
|
parameter RXCLKMODE_B = 6'b110001;
|
|
parameter RXCMADJ_A = 2'b10;
|
|
parameter RXCMADJ_B = 2'b10;
|
|
parameter RXCPSEL_A = "TRUE";
|
|
parameter RXCPSEL_B = "TRUE";
|
|
parameter RXCPTST_A = "FALSE";
|
|
parameter RXCPTST_B = "FALSE";
|
|
parameter RXCRCCLOCKDOUBLE_A = "FALSE";
|
|
parameter RXCRCCLOCKDOUBLE_B = "FALSE";
|
|
parameter RXCRCENABLE_A = "FALSE";
|
|
parameter RXCRCENABLE_B = "FALSE";
|
|
parameter RXCRCINITVAL_A = 32'h00000000;
|
|
parameter RXCRCINITVAL_B = 32'h00000000;
|
|
parameter RXCRCINVERTGEN_A = "FALSE";
|
|
parameter RXCRCINVERTGEN_B = "FALSE";
|
|
parameter RXCRCSAMECLOCK_A = "FALSE";
|
|
parameter RXCRCSAMECLOCK_B = "FALSE";
|
|
parameter RXCTRL1_A = 10'h006;
|
|
parameter RXCTRL1_B = 10'h006;
|
|
parameter RXCYCLE_LIMIT_SEL_A = 2'b00;
|
|
parameter RXCYCLE_LIMIT_SEL_B = 2'b00;
|
|
parameter RXDATA_SEL_A = 2'b00;
|
|
parameter RXDATA_SEL_B = 2'b00;
|
|
parameter RXDCCOUPLE_A = "FALSE";
|
|
parameter RXDCCOUPLE_B = "FALSE";
|
|
parameter RXDIGRESET_A = "FALSE";
|
|
parameter RXDIGRESET_B = "FALSE";
|
|
parameter RXDIGRX_A = "FALSE";
|
|
parameter RXDIGRX_B = "FALSE";
|
|
parameter RXEQ_A = 64'h4000000000000000;
|
|
parameter RXEQ_B = 64'h4000000000000000;
|
|
parameter RXFDCAL_CLOCK_DIVIDE_A = "NONE";
|
|
parameter RXFDCAL_CLOCK_DIVIDE_B = "NONE";
|
|
parameter RXFDET_HYS_CAL_A = 3'b110;
|
|
parameter RXFDET_HYS_CAL_B = 3'b110;
|
|
parameter RXFDET_HYS_SEL_A = 3'b110;
|
|
parameter RXFDET_HYS_SEL_B = 3'b110;
|
|
parameter RXFDET_LCK_CAL_A = 3'b101;
|
|
parameter RXFDET_LCK_CAL_B = 3'b101;
|
|
parameter RXFDET_LCK_SEL_A = 3'b101;
|
|
parameter RXFDET_LCK_SEL_B = 3'b101;
|
|
parameter RXFECONTROL1_A = 2'b00;
|
|
parameter RXFECONTROL1_B = 2'b00;
|
|
parameter RXFECONTROL2_A = 3'b000;
|
|
parameter RXFECONTROL2_B = 3'b000;
|
|
parameter RXFETUNE_A = 2'b01;
|
|
parameter RXFETUNE_B = 2'b01;
|
|
parameter RXLB_A = "FALSE";
|
|
parameter RXLB_B = "FALSE";
|
|
parameter RXLKADJ_A = 5'b00000;
|
|
parameter RXLKADJ_B = 5'b00000;
|
|
parameter RXLKAPD_A = "FALSE";
|
|
parameter RXLKAPD_B = "FALSE";
|
|
parameter RXLOOPCAL_WAIT_A = 2'b00;
|
|
parameter RXLOOPCAL_WAIT_B = 2'b00;
|
|
parameter RXLOOPFILT_A = 4'b0111;
|
|
parameter RXLOOPFILT_B = 4'b0111;
|
|
parameter RXOUTDIV2SEL_A = 1;
|
|
parameter RXOUTDIV2SEL_B = 1;
|
|
parameter RXPDDTST_A = "FALSE";
|
|
parameter RXPDDTST_B = "FALSE";
|
|
parameter RXPD_A = "FALSE";
|
|
parameter RXPD_B = "FALSE";
|
|
parameter RXPLLNDIVSEL_A = 8;
|
|
parameter RXPLLNDIVSEL_B = 8;
|
|
parameter RXPMACLKSEL_A = "REFCLK1";
|
|
parameter RXPMACLKSEL_B = "REFCLK1";
|
|
parameter RXRCPADJ_A = 3'b011;
|
|
parameter RXRCPADJ_B = 3'b011;
|
|
parameter RXRCPPD_A = "FALSE";
|
|
parameter RXRCPPD_B = "FALSE";
|
|
parameter RXRECCLK1_USE_SYNC_A = "FALSE";
|
|
parameter RXRECCLK1_USE_SYNC_B = "FALSE";
|
|
parameter RXRIBADJ_A = 2'b11;
|
|
parameter RXRIBADJ_B = 2'b11;
|
|
parameter RXRPDPD_A = "FALSE";
|
|
parameter RXRPDPD_B = "FALSE";
|
|
parameter RXRSDPD_A = "FALSE";
|
|
parameter RXRSDPD_B = "FALSE";
|
|
parameter RXSLOWDOWN_CAL_A = 2'b00;
|
|
parameter RXSLOWDOWN_CAL_B = 2'b00;
|
|
parameter RXUSRDIVISOR_A = 1;
|
|
parameter RXUSRDIVISOR_B = 1;
|
|
parameter RXVCODAC_INIT_A = 10'b1010000000;
|
|
parameter RXVCODAC_INIT_B = 10'b1010000000;
|
|
parameter RXVCO_CTRL_ENABLE_A = "TRUE";
|
|
parameter RXVCO_CTRL_ENABLE_B = "TRUE";
|
|
parameter RX_BUFFER_USE_A = "TRUE";
|
|
parameter RX_BUFFER_USE_B = "TRUE";
|
|
parameter RX_CLOCK_DIVIDER_A = 2'b00;
|
|
parameter RX_CLOCK_DIVIDER_B = 2'b00;
|
|
parameter RX_LOS_INVALID_INCR_A = 1;
|
|
parameter RX_LOS_INVALID_INCR_B = 1;
|
|
parameter RX_LOS_THRESHOLD_A = 4;
|
|
parameter RX_LOS_THRESHOLD_B = 4;
|
|
parameter SAMPLE_8X_A = "FALSE";
|
|
parameter SAMPLE_8X_B = "FALSE";
|
|
parameter SH_CNT_MAX_A = 64;
|
|
parameter SH_CNT_MAX_B = 64;
|
|
parameter SH_INVALID_CNT_MAX_A = 16;
|
|
parameter SH_INVALID_CNT_MAX_B = 16;
|
|
parameter SLOWDOWN_CAL_A = 2'b00;
|
|
parameter SLOWDOWN_CAL_B = 2'b00;
|
|
parameter TXABPMACLKSEL_A = "REFCLK1";
|
|
parameter TXABPMACLKSEL_B = "REFCLK1";
|
|
parameter TXAPD_A = "FALSE";
|
|
parameter TXAPD_B = "FALSE";
|
|
parameter TXAREFBIASSEL_A = "FALSE";
|
|
parameter TXAREFBIASSEL_B = "FALSE";
|
|
parameter TXASYNCDIVIDE_A = 2'b00;
|
|
parameter TXASYNCDIVIDE_B = 2'b00;
|
|
parameter TXCLK0_FORCE_PMACLK_A = "FALSE";
|
|
parameter TXCLK0_FORCE_PMACLK_B = "FALSE";
|
|
parameter TXCLKMODE_A = 4'b1001;
|
|
parameter TXCLKMODE_B = 4'b1001;
|
|
parameter TXCPSEL_A = "TRUE";
|
|
parameter TXCPSEL_B = "TRUE";
|
|
parameter TXCRCCLOCKDOUBLE_A = "FALSE";
|
|
parameter TXCRCCLOCKDOUBLE_B = "FALSE";
|
|
parameter TXCRCENABLE_A = "FALSE";
|
|
parameter TXCRCENABLE_B = "FALSE";
|
|
parameter TXCRCINITVAL_A = 32'h00000000;
|
|
parameter TXCRCINITVAL_B = 32'h00000000;
|
|
parameter TXCRCINVERTGEN_A = "FALSE";
|
|
parameter TXCRCINVERTGEN_B = "FALSE";
|
|
parameter TXCRCSAMECLOCK_A = "FALSE";
|
|
parameter TXCRCSAMECLOCK_B = "FALSE";
|
|
parameter TXCTRL1_A = 10'h006;
|
|
parameter TXCTRL1_B = 10'h006;
|
|
parameter TXDATA_SEL_A = 2'b00;
|
|
parameter TXDATA_SEL_B = 2'b00;
|
|
parameter TXDAT_PRDRV_DAC_A = 3'b111;
|
|
parameter TXDAT_PRDRV_DAC_B = 3'b111;
|
|
parameter TXDAT_TAP_DAC_A = 5'b10110;
|
|
parameter TXDAT_TAP_DAC_B = 5'b10110;
|
|
parameter TXDIGPD_A = "FALSE";
|
|
parameter TXDIGPD_B = "FALSE";
|
|
parameter TXFDCAL_CLOCK_DIVIDE_A = "NONE";
|
|
parameter TXFDCAL_CLOCK_DIVIDE_B = "NONE";
|
|
parameter TXHIGHSIGNALEN_A = "TRUE";
|
|
parameter TXHIGHSIGNALEN_B = "TRUE";
|
|
parameter TXLOOPFILT_A = 4'b0111;
|
|
parameter TXLOOPFILT_B = 4'b0111;
|
|
parameter TXLVLSHFTPD_A = "FALSE";
|
|
parameter TXLVLSHFTPD_B = "FALSE";
|
|
parameter TXOUTCLK1_USE_SYNC_A = "FALSE";
|
|
parameter TXOUTCLK1_USE_SYNC_B = "FALSE";
|
|
parameter TXOUTDIV2SEL_A = 1;
|
|
parameter TXOUTDIV2SEL_B = 1;
|
|
parameter TXPD_A = "FALSE";
|
|
parameter TXPD_B = "FALSE";
|
|
parameter TXPHASESEL_A = "FALSE";
|
|
parameter TXPHASESEL_B = "FALSE";
|
|
parameter TXPLLNDIVSEL_A = 8;
|
|
parameter TXPLLNDIVSEL_B = 8;
|
|
parameter TXPOST_PRDRV_DAC_A = 3'b111;
|
|
parameter TXPOST_PRDRV_DAC_B = 3'b111;
|
|
parameter TXPOST_TAP_DAC_A = 5'b01110;
|
|
parameter TXPOST_TAP_DAC_B = 5'b01110;
|
|
parameter TXPOST_TAP_PD_A = "TRUE";
|
|
parameter TXPOST_TAP_PD_B = "TRUE";
|
|
parameter TXPRE_PRDRV_DAC_A = 3'b111;
|
|
parameter TXPRE_PRDRV_DAC_B = 3'b111;
|
|
parameter TXPRE_TAP_DAC_A = 5'b00000;
|
|
parameter TXPRE_TAP_DAC_B = 5'b00000;
|
|
parameter TXPRE_TAP_PD_A = "TRUE";
|
|
parameter TXPRE_TAP_PD_B = "TRUE";
|
|
parameter TXSLEWRATE_A = "FALSE";
|
|
parameter TXSLEWRATE_B = "FALSE";
|
|
parameter TXTERMTRIM_A = 4'b1100;
|
|
parameter TXTERMTRIM_B = 4'b1100;
|
|
parameter TX_BUFFER_USE_A = "TRUE";
|
|
parameter TX_BUFFER_USE_B = "TRUE";
|
|
parameter TX_CLOCK_DIVIDER_A = 2'b00;
|
|
parameter TX_CLOCK_DIVIDER_B = 2'b00;
|
|
parameter VCODAC_INIT_A = 10'b1010000000;
|
|
parameter VCODAC_INIT_B = 10'b1010000000;
|
|
parameter VCO_CTRL_ENABLE_A = "TRUE";
|
|
parameter VCO_CTRL_ENABLE_B = "TRUE";
|
|
parameter VREFBIASMODE_A = 2'b11;
|
|
parameter VREFBIASMODE_B = 2'b11;
|
|
output DRDYA;
|
|
output DRDYB;
|
|
output RXBUFERRA;
|
|
output RXBUFERRB;
|
|
output RXCALFAILA;
|
|
output RXCALFAILB;
|
|
output RXCOMMADETA;
|
|
output RXCOMMADETB;
|
|
output RXCYCLELIMITA;
|
|
output RXCYCLELIMITB;
|
|
output RXLOCKA;
|
|
output RXLOCKB;
|
|
output RXMCLKA;
|
|
output RXMCLKB;
|
|
output RXPCSHCLKOUTA;
|
|
output RXPCSHCLKOUTB;
|
|
output RXREALIGNA;
|
|
output RXREALIGNB;
|
|
output RXRECCLK1A;
|
|
output RXRECCLK1B;
|
|
output RXRECCLK2A;
|
|
output RXRECCLK2B;
|
|
output RXSIGDETA;
|
|
output RXSIGDETB;
|
|
output TX1NA;
|
|
output TX1NB;
|
|
output TX1PA;
|
|
output TX1PB;
|
|
output TXBUFERRA;
|
|
output TXBUFERRB;
|
|
output TXCALFAILA;
|
|
output TXCALFAILB;
|
|
output TXCYCLELIMITA;
|
|
output TXCYCLELIMITB;
|
|
output TXLOCKA;
|
|
output TXLOCKB;
|
|
output TXOUTCLK1A;
|
|
output TXOUTCLK1B;
|
|
output TXOUTCLK2A;
|
|
output TXOUTCLK2B;
|
|
output TXPCSHCLKOUTA;
|
|
output TXPCSHCLKOUTB;
|
|
output [15:0] DOA;
|
|
output [15:0] DOB;
|
|
output [1:0] RXLOSSOFSYNCA;
|
|
output [1:0] RXLOSSOFSYNCB;
|
|
output [31:0] RXCRCOUTA;
|
|
output [31:0] RXCRCOUTB;
|
|
output [31:0] TXCRCOUTA;
|
|
output [31:0] TXCRCOUTB;
|
|
output [4:0] CHBONDOA;
|
|
output [4:0] CHBONDOB;
|
|
output [5:0] RXSTATUSA;
|
|
output [5:0] RXSTATUSB;
|
|
output [63:0] RXDATAA;
|
|
output [63:0] RXDATAB;
|
|
output [7:0] RXCHARISCOMMAA;
|
|
output [7:0] RXCHARISCOMMAB;
|
|
output [7:0] RXCHARISKA;
|
|
output [7:0] RXCHARISKB;
|
|
output [7:0] RXDISPERRA;
|
|
output [7:0] RXDISPERRB;
|
|
output [7:0] RXNOTINTABLEA;
|
|
output [7:0] RXNOTINTABLEB;
|
|
output [7:0] RXRUNDISPA;
|
|
output [7:0] RXRUNDISPB;
|
|
output [7:0] TXKERRA;
|
|
output [7:0] TXKERRB;
|
|
output [7:0] TXRUNDISPA;
|
|
output [7:0] TXRUNDISPB;
|
|
input DCLKA;
|
|
input DCLKB;
|
|
input DENA;
|
|
input DENB;
|
|
input DWEA;
|
|
input DWEB;
|
|
input ENCHANSYNCA;
|
|
input ENCHANSYNCB;
|
|
input ENMCOMMAALIGNA;
|
|
input ENMCOMMAALIGNB;
|
|
input ENPCOMMAALIGNA;
|
|
input ENPCOMMAALIGNB;
|
|
input GREFCLKA;
|
|
input GREFCLKB;
|
|
input POWERDOWNA;
|
|
input POWERDOWNB;
|
|
input REFCLK1A;
|
|
input REFCLK1B;
|
|
input REFCLK2A;
|
|
input REFCLK2B;
|
|
input RX1NA;
|
|
input RX1NB;
|
|
input RX1PA;
|
|
input RX1PB;
|
|
input RXBLOCKSYNC64B66BUSEA;
|
|
input RXBLOCKSYNC64B66BUSEB;
|
|
input RXCLKSTABLEA;
|
|
input RXCLKSTABLEB;
|
|
input RXCOMMADETUSEA;
|
|
input RXCOMMADETUSEB;
|
|
input RXCRCCLKA;
|
|
input RXCRCCLKB;
|
|
input RXCRCDATAVALIDA;
|
|
input RXCRCDATAVALIDB;
|
|
input RXCRCINITA;
|
|
input RXCRCINITB;
|
|
input RXCRCINTCLKA;
|
|
input RXCRCINTCLKB;
|
|
input RXCRCPDA;
|
|
input RXCRCPDB;
|
|
input RXCRCRESETA;
|
|
input RXCRCRESETB;
|
|
input RXDEC64B66BUSEA;
|
|
input RXDEC64B66BUSEB;
|
|
input RXDEC8B10BUSEA;
|
|
input RXDEC8B10BUSEB;
|
|
input RXDESCRAM64B66BUSEA;
|
|
input RXDESCRAM64B66BUSEB;
|
|
input RXIGNOREBTFA;
|
|
input RXIGNOREBTFB;
|
|
input RXPMARESETA;
|
|
input RXPMARESETB;
|
|
input RXPOLARITYA;
|
|
input RXPOLARITYB;
|
|
input RXRESETA;
|
|
input RXRESETB;
|
|
input RXSLIDEA;
|
|
input RXSLIDEB;
|
|
input RXSYNCA;
|
|
input RXSYNCB;
|
|
input RXUSRCLK2A;
|
|
input RXUSRCLK2B;
|
|
input RXUSRCLKA;
|
|
input RXUSRCLKB;
|
|
input TXCLKSTABLEA;
|
|
input TXCLKSTABLEB;
|
|
input TXCRCCLKA;
|
|
input TXCRCCLKB;
|
|
input TXCRCDATAVALIDA;
|
|
input TXCRCDATAVALIDB;
|
|
input TXCRCINITA;
|
|
input TXCRCINITB;
|
|
input TXCRCINTCLKA;
|
|
input TXCRCINTCLKB;
|
|
input TXCRCPDA;
|
|
input TXCRCPDB;
|
|
input TXCRCRESETA;
|
|
input TXCRCRESETB;
|
|
input TXENC64B66BUSEA;
|
|
input TXENC64B66BUSEB;
|
|
input TXENC8B10BUSEA;
|
|
input TXENC8B10BUSEB;
|
|
input TXENOOBA;
|
|
input TXENOOBB;
|
|
input TXGEARBOX64B66BUSEA;
|
|
input TXGEARBOX64B66BUSEB;
|
|
input TXINHIBITA;
|
|
input TXINHIBITB;
|
|
input TXPMARESETA;
|
|
input TXPMARESETB;
|
|
input TXPOLARITYA;
|
|
input TXPOLARITYB;
|
|
input TXRESETA;
|
|
input TXRESETB;
|
|
input TXSCRAM64B66BUSEA;
|
|
input TXSCRAM64B66BUSEB;
|
|
input TXSYNCA;
|
|
input TXSYNCB;
|
|
input TXUSRCLK2A;
|
|
input TXUSRCLK2B;
|
|
input TXUSRCLKA;
|
|
input TXUSRCLKB;
|
|
input [15:0] DIA;
|
|
input [15:0] DIB;
|
|
input [1:0] LOOPBACKA;
|
|
input [1:0] LOOPBACKB;
|
|
input [1:0] RXDATAWIDTHA;
|
|
input [1:0] RXDATAWIDTHB;
|
|
input [1:0] RXINTDATAWIDTHA;
|
|
input [1:0] RXINTDATAWIDTHB;
|
|
input [1:0] TXDATAWIDTHA;
|
|
input [1:0] TXDATAWIDTHB;
|
|
input [1:0] TXINTDATAWIDTHA;
|
|
input [1:0] TXINTDATAWIDTHB;
|
|
input [2:0] RXCRCDATAWIDTHA;
|
|
input [2:0] RXCRCDATAWIDTHB;
|
|
input [2:0] TXCRCDATAWIDTHA;
|
|
input [2:0] TXCRCDATAWIDTHB;
|
|
input [4:0] CHBONDIA;
|
|
input [4:0] CHBONDIB;
|
|
input [63:0] RXCRCINA;
|
|
input [63:0] RXCRCINB;
|
|
input [63:0] TXCRCINA;
|
|
input [63:0] TXCRCINB;
|
|
input [63:0] TXDATAA;
|
|
input [63:0] TXDATAB;
|
|
input [7:0] DADDRA;
|
|
input [7:0] DADDRB;
|
|
input [7:0] TXBYPASS8B10BA;
|
|
input [7:0] TXBYPASS8B10BB;
|
|
input [7:0] TXCHARDISPMODEA;
|
|
input [7:0] TXCHARDISPMODEB;
|
|
input [7:0] TXCHARDISPVALA;
|
|
input [7:0] TXCHARDISPVALB;
|
|
input [7:0] TXCHARISKA;
|
|
input [7:0] TXCHARISKB;
|
|
endmodule
|
|
|
|
module GT11CLK(SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP, REFCLK, RXBCLK, SYNCLK1IN, SYNCLK2IN);
|
|
parameter REFCLKSEL = "MGTCLK";
|
|
parameter SYNCLK1OUTEN = "ENABLE";
|
|
parameter SYNCLK2OUTEN = "DISABLE";
|
|
output SYNCLK1OUT;
|
|
output SYNCLK2OUT;
|
|
input MGTCLKN;
|
|
input MGTCLKP;
|
|
input REFCLK;
|
|
input RXBCLK;
|
|
input SYNCLK1IN;
|
|
input SYNCLK2IN;
|
|
endmodule
|
|
|
|
module GT11CLK_MGT(SYNCLK1OUT, SYNCLK2OUT, MGTCLKN, MGTCLKP);
|
|
parameter SYNCLK1OUTEN = "ENABLE";
|
|
parameter SYNCLK2OUTEN = "DISABLE";
|
|
output SYNCLK1OUT;
|
|
output SYNCLK2OUT;
|
|
input MGTCLKN;
|
|
input MGTCLKP;
|
|
endmodule
|
|
|
|
module GTP_DUAL(DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCOMMADET0, RXCOMMADET1, RXELECIDLE0, RXELECIDLE1
|
|
, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXVALID0, RXVALID1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0, TXP1, DO, RXDATA0, RXDATA1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1
|
|
, RXDISPERR0, RXDISPERR1, RXLOSSOFSYNC0, RXLOSSOFSYNC1, RXNOTINTABLE0, RXNOTINTABLE1, RXRUNDISP0, RXRUNDISP1, TXBUFSTATUS0, TXBUFSTATUS1, TXKERR0, TXKERR1, TXRUNDISP0, TXRUNDISP1, RXBUFSTATUS0, RXBUFSTATUS1, RXCHBONDO0, RXCHBONDO1, RXCLKCORCNT0, RXCLKCORCNT1, RXSTATUS0
|
|
, RXSTATUS1, CLKIN, DCLK, DEN, DWE, GTPRESET, INTDATAWIDTH, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCOMMADETUSE0, RXCOMMADETUSE1, RXDATAWIDTH0, RXDATAWIDTH1, RXDEC8B10BUSE0
|
|
, RXDEC8B10BUSE1, RXELECIDLERESET0, RXELECIDLERESET1, RXENCHANSYNC0, RXENCHANSYNC1, RXENELECIDLERESETB, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0, RXPMASETPHASE1, RXPOLARITY0
|
|
, RXPOLARITY1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDATAWIDTH0, TXDATAWIDTH1, TXDETECTRX0, TXDETECTRX1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1
|
|
, TXENPMAPHASEALIGN, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE, TXPOLARITY0, TXPOLARITY1, TXRESET0, TXRESET1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21, DI, TXDATA0, TXDATA1, RXENPRBSTST0, RXENPRBSTST1, RXEQMIX0, RXEQMIX1, RXPOWERDOWN0, RXPOWERDOWN1
|
|
, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXENPRBSTST0, TXENPRBSTST1, TXPOWERDOWN0, TXPOWERDOWN1, LOOPBACK0, LOOPBACK1, RXCHBONDI0, RXCHBONDI1, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXDIFFCTRL0, TXDIFFCTRL1, TXPREEMPHASIS0
|
|
, TXPREEMPHASIS1, GTPTEST, RXEQPOLE0, RXEQPOLE1, DADDR);
|
|
parameter AC_CAP_DIS_0 = "TRUE";
|
|
parameter AC_CAP_DIS_1 = "TRUE";
|
|
parameter CHAN_BOND_MODE_0 = "OFF";
|
|
parameter CHAN_BOND_MODE_1 = "OFF";
|
|
parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE";
|
|
parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE";
|
|
parameter CLKINDC_B = "TRUE";
|
|
parameter CLK_CORRECT_USE_0 = "TRUE";
|
|
parameter CLK_CORRECT_USE_1 = "TRUE";
|
|
parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
|
|
parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
|
|
parameter CLK_COR_KEEP_IDLE_0 = "FALSE";
|
|
parameter CLK_COR_KEEP_IDLE_1 = "FALSE";
|
|
parameter CLK_COR_PRECEDENCE_0 = "TRUE";
|
|
parameter CLK_COR_PRECEDENCE_1 = "TRUE";
|
|
parameter CLK_COR_SEQ_2_USE_0 = "FALSE";
|
|
parameter CLK_COR_SEQ_2_USE_1 = "FALSE";
|
|
parameter COMMA_DOUBLE_0 = "FALSE";
|
|
parameter COMMA_DOUBLE_1 = "FALSE";
|
|
parameter DEC_MCOMMA_DETECT_0 = "TRUE";
|
|
parameter DEC_MCOMMA_DETECT_1 = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT_0 = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT_1 = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY_0 = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY_1 = "TRUE";
|
|
parameter MCOMMA_DETECT_0 = "TRUE";
|
|
parameter MCOMMA_DETECT_1 = "TRUE";
|
|
parameter OVERSAMPLE_MODE = "FALSE";
|
|
parameter PCI_EXPRESS_MODE_0 = "TRUE";
|
|
parameter PCI_EXPRESS_MODE_1 = "TRUE";
|
|
parameter PCOMMA_DETECT_0 = "TRUE";
|
|
parameter PCOMMA_DETECT_1 = "TRUE";
|
|
parameter PLL_SATA_0 = "FALSE";
|
|
parameter PLL_SATA_1 = "FALSE";
|
|
parameter RCV_TERM_GND_0 = "TRUE";
|
|
parameter RCV_TERM_GND_1 = "TRUE";
|
|
parameter RCV_TERM_MID_0 = "FALSE";
|
|
parameter RCV_TERM_MID_1 = "FALSE";
|
|
parameter RCV_TERM_VTTRX_0 = "FALSE";
|
|
parameter RCV_TERM_VTTRX_1 = "FALSE";
|
|
parameter RX_BUFFER_USE_0 = "TRUE";
|
|
parameter RX_BUFFER_USE_1 = "TRUE";
|
|
parameter RX_DECODE_SEQ_MATCH_0 = "TRUE";
|
|
parameter RX_DECODE_SEQ_MATCH_1 = "TRUE";
|
|
parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE";
|
|
parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE";
|
|
parameter RX_SLIDE_MODE_0 = "PCS";
|
|
parameter RX_SLIDE_MODE_1 = "PCS";
|
|
parameter RX_STATUS_FMT_0 = "PCIE";
|
|
parameter RX_STATUS_FMT_1 = "PCIE";
|
|
parameter RX_XCLK_SEL_0 = "RXREC";
|
|
parameter RX_XCLK_SEL_1 = "RXREC";
|
|
parameter SIM_PLL_PERDIV2 = 9'h190;
|
|
parameter SIM_RECEIVER_DETECT_PASS0 = "FALSE";
|
|
parameter SIM_RECEIVER_DETECT_PASS1 = "FALSE";
|
|
parameter TERMINATION_OVRD = "FALSE";
|
|
parameter TX_BUFFER_USE_0 = "TRUE";
|
|
parameter TX_BUFFER_USE_1 = "TRUE";
|
|
parameter TX_DIFF_BOOST_0 = "TRUE";
|
|
parameter TX_DIFF_BOOST_1 = "TRUE";
|
|
parameter TX_XCLK_SEL_0 = "TXUSR";
|
|
parameter TX_XCLK_SEL_1 = "TXUSR";
|
|
parameter [15:0] TRANS_TIME_FROM_P2_0 = 16'h003c;
|
|
parameter [15:0] TRANS_TIME_FROM_P2_1 = 16'h003c;
|
|
parameter [15:0] TRANS_TIME_NON_P2_0 = 16'h0019;
|
|
parameter [15:0] TRANS_TIME_NON_P2_1 = 16'h0019;
|
|
parameter [15:0] TRANS_TIME_TO_P2_0 = 16'h0064;
|
|
parameter [15:0] TRANS_TIME_TO_P2_1 = 16'h0064;
|
|
parameter [24:0] PMA_RX_CFG_0 = 25'h09f0089;
|
|
parameter [24:0] PMA_RX_CFG_1 = 25'h09f0089;
|
|
parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c07640;
|
|
parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c07640;
|
|
parameter [27:0] PCS_COM_CFG = 28'h1680a0e;
|
|
parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b001;
|
|
parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b001;
|
|
parameter [2:0] SATA_BURST_VAL_0 = 3'b100;
|
|
parameter [2:0] SATA_BURST_VAL_1 = 3'b100;
|
|
parameter [2:0] SATA_IDLE_VAL_0 = 3'b011;
|
|
parameter [2:0] SATA_IDLE_VAL_1 = 3'b011;
|
|
parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1;
|
|
parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111;
|
|
parameter [3:0] COM_BURST_VAL_0 = 4'b1111;
|
|
parameter [3:0] COM_BURST_VAL_1 = 4'b1111;
|
|
parameter [4:0] TERMINATION_CTRL = 5'b10100;
|
|
parameter [4:0] TXRX_INVERT_0 = 5'b00000;
|
|
parameter [4:0] TXRX_INVERT_1 = 5'b00000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100;
|
|
parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0;
|
|
parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111;
|
|
parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111;
|
|
parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011;
|
|
parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011;
|
|
parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100;
|
|
parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100;
|
|
parameter ALIGN_COMMA_WORD_0 = 1;
|
|
parameter ALIGN_COMMA_WORD_1 = 1;
|
|
parameter CHAN_BOND_1_MAX_SKEW_0 = 7;
|
|
parameter CHAN_BOND_1_MAX_SKEW_1 = 7;
|
|
parameter CHAN_BOND_2_MAX_SKEW_0 = 1;
|
|
parameter CHAN_BOND_2_MAX_SKEW_1 = 1;
|
|
parameter CHAN_BOND_LEVEL_0 = 0;
|
|
parameter CHAN_BOND_LEVEL_1 = 0;
|
|
parameter CHAN_BOND_SEQ_LEN_0 = 4;
|
|
parameter CHAN_BOND_SEQ_LEN_1 = 4;
|
|
parameter CLK25_DIVIDER = 4;
|
|
parameter CLK_COR_ADJ_LEN_0 = 1;
|
|
parameter CLK_COR_ADJ_LEN_1 = 1;
|
|
parameter CLK_COR_DET_LEN_0 = 1;
|
|
parameter CLK_COR_DET_LEN_1 = 1;
|
|
parameter CLK_COR_MAX_LAT_0 = 18;
|
|
parameter CLK_COR_MAX_LAT_1 = 18;
|
|
parameter CLK_COR_MIN_LAT_0 = 16;
|
|
parameter CLK_COR_MIN_LAT_1 = 16;
|
|
parameter CLK_COR_REPEAT_WAIT_0 = 5;
|
|
parameter CLK_COR_REPEAT_WAIT_1 = 5;
|
|
parameter OOB_CLK_DIVIDER = 4;
|
|
parameter PLL_DIVSEL_FB = 5;
|
|
parameter PLL_DIVSEL_REF = 2;
|
|
parameter PLL_RXDIVSEL_OUT_0 = 1;
|
|
parameter PLL_RXDIVSEL_OUT_1 = 1;
|
|
parameter PLL_TXDIVSEL_COMM_OUT = 1;
|
|
parameter PLL_TXDIVSEL_OUT_0 = 1;
|
|
parameter PLL_TXDIVSEL_OUT_1 = 1;
|
|
parameter RX_LOS_INVALID_INCR_0 = 8;
|
|
parameter RX_LOS_INVALID_INCR_1 = 8;
|
|
parameter RX_LOS_THRESHOLD_0 = 128;
|
|
parameter RX_LOS_THRESHOLD_1 = 128;
|
|
parameter SATA_MAX_BURST_0 = 7;
|
|
parameter SATA_MAX_BURST_1 = 7;
|
|
parameter SATA_MAX_INIT_0 = 22;
|
|
parameter SATA_MAX_INIT_1 = 22;
|
|
parameter SATA_MAX_WAKE_0 = 7;
|
|
parameter SATA_MAX_WAKE_1 = 7;
|
|
parameter SATA_MIN_BURST_0 = 4;
|
|
parameter SATA_MIN_BURST_1 = 4;
|
|
parameter SATA_MIN_INIT_0 = 12;
|
|
parameter SATA_MIN_INIT_1 = 12;
|
|
parameter SATA_MIN_WAKE_0 = 4;
|
|
parameter SATA_MIN_WAKE_1 = 4;
|
|
parameter SIM_GTPRESET_SPEEDUP = 0;
|
|
parameter TERMINATION_IMP_0 = 50;
|
|
parameter TERMINATION_IMP_1 = 50;
|
|
parameter TX_SYNC_FILTERB = 1;
|
|
output DRDY;
|
|
output PHYSTATUS0;
|
|
output PHYSTATUS1;
|
|
output PLLLKDET;
|
|
output REFCLKOUT;
|
|
output RESETDONE0;
|
|
output RESETDONE1;
|
|
output RXBYTEISALIGNED0;
|
|
output RXBYTEISALIGNED1;
|
|
output RXBYTEREALIGN0;
|
|
output RXBYTEREALIGN1;
|
|
output RXCHANBONDSEQ0;
|
|
output RXCHANBONDSEQ1;
|
|
output RXCHANISALIGNED0;
|
|
output RXCHANISALIGNED1;
|
|
output RXCHANREALIGN0;
|
|
output RXCHANREALIGN1;
|
|
output RXCOMMADET0;
|
|
output RXCOMMADET1;
|
|
output RXELECIDLE0;
|
|
output RXELECIDLE1;
|
|
output RXOVERSAMPLEERR0;
|
|
output RXOVERSAMPLEERR1;
|
|
output RXPRBSERR0;
|
|
output RXPRBSERR1;
|
|
output RXRECCLK0;
|
|
output RXRECCLK1;
|
|
output RXVALID0;
|
|
output RXVALID1;
|
|
output TXN0;
|
|
output TXN1;
|
|
output TXOUTCLK0;
|
|
output TXOUTCLK1;
|
|
output TXP0;
|
|
output TXP1;
|
|
output [15:0] DO;
|
|
output [15:0] RXDATA0;
|
|
output [15:0] RXDATA1;
|
|
output [1:0] RXCHARISCOMMA0;
|
|
output [1:0] RXCHARISCOMMA1;
|
|
output [1:0] RXCHARISK0;
|
|
output [1:0] RXCHARISK1;
|
|
output [1:0] RXDISPERR0;
|
|
output [1:0] RXDISPERR1;
|
|
output [1:0] RXLOSSOFSYNC0;
|
|
output [1:0] RXLOSSOFSYNC1;
|
|
output [1:0] RXNOTINTABLE0;
|
|
output [1:0] RXNOTINTABLE1;
|
|
output [1:0] RXRUNDISP0;
|
|
output [1:0] RXRUNDISP1;
|
|
output [1:0] TXBUFSTATUS0;
|
|
output [1:0] TXBUFSTATUS1;
|
|
output [1:0] TXKERR0;
|
|
output [1:0] TXKERR1;
|
|
output [1:0] TXRUNDISP0;
|
|
output [1:0] TXRUNDISP1;
|
|
output [2:0] RXBUFSTATUS0;
|
|
output [2:0] RXBUFSTATUS1;
|
|
output [2:0] RXCHBONDO0;
|
|
output [2:0] RXCHBONDO1;
|
|
output [2:0] RXCLKCORCNT0;
|
|
output [2:0] RXCLKCORCNT1;
|
|
output [2:0] RXSTATUS0;
|
|
output [2:0] RXSTATUS1;
|
|
input CLKIN;
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
input GTPRESET;
|
|
input INTDATAWIDTH;
|
|
input PLLLKDETEN;
|
|
input PLLPOWERDOWN;
|
|
input PRBSCNTRESET0;
|
|
input PRBSCNTRESET1;
|
|
input REFCLKPWRDNB;
|
|
input RXBUFRESET0;
|
|
input RXBUFRESET1;
|
|
input RXCDRRESET0;
|
|
input RXCDRRESET1;
|
|
input RXCOMMADETUSE0;
|
|
input RXCOMMADETUSE1;
|
|
input RXDATAWIDTH0;
|
|
input RXDATAWIDTH1;
|
|
input RXDEC8B10BUSE0;
|
|
input RXDEC8B10BUSE1;
|
|
input RXELECIDLERESET0;
|
|
input RXELECIDLERESET1;
|
|
input RXENCHANSYNC0;
|
|
input RXENCHANSYNC1;
|
|
input RXENELECIDLERESETB;
|
|
input RXENEQB0;
|
|
input RXENEQB1;
|
|
input RXENMCOMMAALIGN0;
|
|
input RXENMCOMMAALIGN1;
|
|
input RXENPCOMMAALIGN0;
|
|
input RXENPCOMMAALIGN1;
|
|
input RXENSAMPLEALIGN0;
|
|
input RXENSAMPLEALIGN1;
|
|
input RXN0;
|
|
input RXN1;
|
|
input RXP0;
|
|
input RXP1;
|
|
input RXPMASETPHASE0;
|
|
input RXPMASETPHASE1;
|
|
input RXPOLARITY0;
|
|
input RXPOLARITY1;
|
|
input RXRESET0;
|
|
input RXRESET1;
|
|
input RXSLIDE0;
|
|
input RXSLIDE1;
|
|
input RXUSRCLK0;
|
|
input RXUSRCLK1;
|
|
input RXUSRCLK20;
|
|
input RXUSRCLK21;
|
|
input TXCOMSTART0;
|
|
input TXCOMSTART1;
|
|
input TXCOMTYPE0;
|
|
input TXCOMTYPE1;
|
|
input TXDATAWIDTH0;
|
|
input TXDATAWIDTH1;
|
|
input TXDETECTRX0;
|
|
input TXDETECTRX1;
|
|
input TXELECIDLE0;
|
|
input TXELECIDLE1;
|
|
input TXENC8B10BUSE0;
|
|
input TXENC8B10BUSE1;
|
|
input TXENPMAPHASEALIGN;
|
|
input TXINHIBIT0;
|
|
input TXINHIBIT1;
|
|
input TXPMASETPHASE;
|
|
input TXPOLARITY0;
|
|
input TXPOLARITY1;
|
|
input TXRESET0;
|
|
input TXRESET1;
|
|
input TXUSRCLK0;
|
|
input TXUSRCLK1;
|
|
input TXUSRCLK20;
|
|
input TXUSRCLK21;
|
|
input [15:0] DI;
|
|
input [15:0] TXDATA0;
|
|
input [15:0] TXDATA1;
|
|
input [1:0] RXENPRBSTST0;
|
|
input [1:0] RXENPRBSTST1;
|
|
input [1:0] RXEQMIX0;
|
|
input [1:0] RXEQMIX1;
|
|
input [1:0] RXPOWERDOWN0;
|
|
input [1:0] RXPOWERDOWN1;
|
|
input [1:0] TXBYPASS8B10B0;
|
|
input [1:0] TXBYPASS8B10B1;
|
|
input [1:0] TXCHARDISPMODE0;
|
|
input [1:0] TXCHARDISPMODE1;
|
|
input [1:0] TXCHARDISPVAL0;
|
|
input [1:0] TXCHARDISPVAL1;
|
|
input [1:0] TXCHARISK0;
|
|
input [1:0] TXCHARISK1;
|
|
input [1:0] TXENPRBSTST0;
|
|
input [1:0] TXENPRBSTST1;
|
|
input [1:0] TXPOWERDOWN0;
|
|
input [1:0] TXPOWERDOWN1;
|
|
input [2:0] LOOPBACK0;
|
|
input [2:0] LOOPBACK1;
|
|
input [2:0] RXCHBONDI0;
|
|
input [2:0] RXCHBONDI1;
|
|
input [2:0] TXBUFDIFFCTRL0;
|
|
input [2:0] TXBUFDIFFCTRL1;
|
|
input [2:0] TXDIFFCTRL0;
|
|
input [2:0] TXDIFFCTRL1;
|
|
input [2:0] TXPREEMPHASIS0;
|
|
input [2:0] TXPREEMPHASIS1;
|
|
input [3:0] GTPTEST;
|
|
input [3:0] RXEQPOLE0;
|
|
input [3:0] RXEQPOLE1;
|
|
input [6:0] DADDR;
|
|
endmodule
|
|
|
|
module GTX_DUAL(DRDY, PHYSTATUS0, PHYSTATUS1, PLLLKDET, REFCLKOUT, RESETDONE0, RESETDONE1, RXBYTEISALIGNED0, RXBYTEISALIGNED1, RXBYTEREALIGN0, RXBYTEREALIGN1, RXCHANBONDSEQ0, RXCHANBONDSEQ1, RXCHANISALIGNED0, RXCHANISALIGNED1, RXCHANREALIGN0, RXCHANREALIGN1, RXCOMMADET0, RXCOMMADET1, RXDATAVALID0, RXDATAVALID1
|
|
, RXELECIDLE0, RXELECIDLE1, RXHEADERVALID0, RXHEADERVALID1, RXOVERSAMPLEERR0, RXOVERSAMPLEERR1, RXPRBSERR0, RXPRBSERR1, RXRECCLK0, RXRECCLK1, RXSTARTOFSEQ0, RXSTARTOFSEQ1, RXVALID0, RXVALID1, TXGEARBOXREADY0, TXGEARBOXREADY1, TXN0, TXN1, TXOUTCLK0, TXOUTCLK1, TXP0
|
|
, TXP1, DO, RXLOSSOFSYNC0, RXLOSSOFSYNC1, TXBUFSTATUS0, TXBUFSTATUS1, DFESENSCAL0, DFESENSCAL1, RXBUFSTATUS0, RXBUFSTATUS1, RXCLKCORCNT0, RXCLKCORCNT1, RXHEADER0, RXHEADER1, RXSTATUS0, RXSTATUS1, RXDATA0, RXDATA1, DFETAP3MONITOR0, DFETAP3MONITOR1, DFETAP4MONITOR0
|
|
, DFETAP4MONITOR1, RXCHARISCOMMA0, RXCHARISCOMMA1, RXCHARISK0, RXCHARISK1, RXCHBONDO0, RXCHBONDO1, RXDISPERR0, RXDISPERR1, RXNOTINTABLE0, RXNOTINTABLE1, RXRUNDISP0, RXRUNDISP1, TXKERR0, TXKERR1, TXRUNDISP0, TXRUNDISP1, DFEEYEDACMONITOR0, DFEEYEDACMONITOR1, DFETAP1MONITOR0, DFETAP1MONITOR1
|
|
, DFETAP2MONITOR0, DFETAP2MONITOR1, DFECLKDLYADJMONITOR0, DFECLKDLYADJMONITOR1, CLKIN, DCLK, DEN, DWE, GTXRESET, INTDATAWIDTH, PLLLKDETEN, PLLPOWERDOWN, PRBSCNTRESET0, PRBSCNTRESET1, REFCLKPWRDNB, RXBUFRESET0, RXBUFRESET1, RXCDRRESET0, RXCDRRESET1, RXCOMMADETUSE0, RXCOMMADETUSE1
|
|
, RXDEC8B10BUSE0, RXDEC8B10BUSE1, RXENCHANSYNC0, RXENCHANSYNC1, RXENEQB0, RXENEQB1, RXENMCOMMAALIGN0, RXENMCOMMAALIGN1, RXENPCOMMAALIGN0, RXENPCOMMAALIGN1, RXENPMAPHASEALIGN0, RXENPMAPHASEALIGN1, RXENSAMPLEALIGN0, RXENSAMPLEALIGN1, RXGEARBOXSLIP0, RXGEARBOXSLIP1, RXN0, RXN1, RXP0, RXP1, RXPMASETPHASE0
|
|
, RXPMASETPHASE1, RXPOLARITY0, RXPOLARITY1, RXRESET0, RXRESET1, RXSLIDE0, RXSLIDE1, RXUSRCLK0, RXUSRCLK1, RXUSRCLK20, RXUSRCLK21, TXCOMSTART0, TXCOMSTART1, TXCOMTYPE0, TXCOMTYPE1, TXDETECTRX0, TXDETECTRX1, TXELECIDLE0, TXELECIDLE1, TXENC8B10BUSE0, TXENC8B10BUSE1
|
|
, TXENPMAPHASEALIGN0, TXENPMAPHASEALIGN1, TXINHIBIT0, TXINHIBIT1, TXPMASETPHASE0, TXPMASETPHASE1, TXPOLARITY0, TXPOLARITY1, TXRESET0, TXRESET1, TXSTARTSEQ0, TXSTARTSEQ1, TXUSRCLK0, TXUSRCLK1, TXUSRCLK20, TXUSRCLK21, GTXTEST, DI, RXDATAWIDTH0, RXDATAWIDTH1, RXENPRBSTST0
|
|
, RXENPRBSTST1, RXEQMIX0, RXEQMIX1, RXPOWERDOWN0, RXPOWERDOWN1, TXDATAWIDTH0, TXDATAWIDTH1, TXENPRBSTST0, TXENPRBSTST1, TXPOWERDOWN0, TXPOWERDOWN1, LOOPBACK0, LOOPBACK1, TXBUFDIFFCTRL0, TXBUFDIFFCTRL1, TXDIFFCTRL0, TXDIFFCTRL1, TXHEADER0, TXHEADER1, TXDATA0, TXDATA1
|
|
, DFETAP30, DFETAP31, DFETAP40, DFETAP41, RXCHBONDI0, RXCHBONDI1, RXEQPOLE0, RXEQPOLE1, TXBYPASS8B10B0, TXBYPASS8B10B1, TXCHARDISPMODE0, TXCHARDISPMODE1, TXCHARDISPVAL0, TXCHARDISPVAL1, TXCHARISK0, TXCHARISK1, TXPREEMPHASIS0, TXPREEMPHASIS1, DFETAP10, DFETAP11, DFETAP20
|
|
, DFETAP21, DFECLKDLYADJ0, DFECLKDLYADJ1, DADDR, TXSEQUENCE0, TXSEQUENCE1);
|
|
parameter STEPPING = "0";
|
|
parameter AC_CAP_DIS_0 = "TRUE";
|
|
parameter AC_CAP_DIS_1 = "TRUE";
|
|
parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE";
|
|
parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE";
|
|
parameter CHAN_BOND_MODE_0 = "OFF";
|
|
parameter CHAN_BOND_MODE_1 = "OFF";
|
|
parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE";
|
|
parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE";
|
|
parameter CLKINDC_B = "TRUE";
|
|
parameter CLKRCV_TRST = "FALSE";
|
|
parameter CLK_CORRECT_USE_0 = "TRUE";
|
|
parameter CLK_CORRECT_USE_1 = "TRUE";
|
|
parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE";
|
|
parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE";
|
|
parameter CLK_COR_KEEP_IDLE_0 = "FALSE";
|
|
parameter CLK_COR_KEEP_IDLE_1 = "FALSE";
|
|
parameter CLK_COR_PRECEDENCE_0 = "TRUE";
|
|
parameter CLK_COR_PRECEDENCE_1 = "TRUE";
|
|
parameter CLK_COR_SEQ_2_USE_0 = "FALSE";
|
|
parameter CLK_COR_SEQ_2_USE_1 = "FALSE";
|
|
parameter COMMA_DOUBLE_0 = "FALSE";
|
|
parameter COMMA_DOUBLE_1 = "FALSE";
|
|
parameter DEC_MCOMMA_DETECT_0 = "TRUE";
|
|
parameter DEC_MCOMMA_DETECT_1 = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT_0 = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT_1 = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY_0 = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY_1 = "TRUE";
|
|
parameter MCOMMA_DETECT_0 = "TRUE";
|
|
parameter MCOMMA_DETECT_1 = "TRUE";
|
|
parameter OVERSAMPLE_MODE = "FALSE";
|
|
parameter PCI_EXPRESS_MODE_0 = "TRUE";
|
|
parameter PCI_EXPRESS_MODE_1 = "TRUE";
|
|
parameter PCOMMA_DETECT_0 = "TRUE";
|
|
parameter PCOMMA_DETECT_1 = "TRUE";
|
|
parameter PLL_FB_DCCEN = "FALSE";
|
|
parameter PLL_SATA_0 = "FALSE";
|
|
parameter PLL_SATA_1 = "FALSE";
|
|
parameter RCV_TERM_GND_0 = "TRUE";
|
|
parameter RCV_TERM_GND_1 = "TRUE";
|
|
parameter RCV_TERM_VTTRX_0 = "FALSE";
|
|
parameter RCV_TERM_VTTRX_1 = "FALSE";
|
|
parameter RXGEARBOX_USE_0 = "FALSE";
|
|
parameter RXGEARBOX_USE_1 = "FALSE";
|
|
parameter RX_BUFFER_USE_0 = "TRUE";
|
|
parameter RX_BUFFER_USE_1 = "TRUE";
|
|
parameter RX_DECODE_SEQ_MATCH_0 = "TRUE";
|
|
parameter RX_DECODE_SEQ_MATCH_1 = "TRUE";
|
|
parameter RX_EN_IDLE_HOLD_CDR = "FALSE";
|
|
parameter RX_EN_IDLE_HOLD_DFE_0 = "TRUE";
|
|
parameter RX_EN_IDLE_HOLD_DFE_1 = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_FR = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_PH = "TRUE";
|
|
parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE";
|
|
parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE";
|
|
parameter RX_SLIDE_MODE_0 = "PCS";
|
|
parameter RX_SLIDE_MODE_1 = "PCS";
|
|
parameter RX_STATUS_FMT_0 = "PCIE";
|
|
parameter RX_STATUS_FMT_1 = "PCIE";
|
|
parameter RX_XCLK_SEL_0 = "RXREC";
|
|
parameter RX_XCLK_SEL_1 = "RXREC";
|
|
parameter SIM_PLL_PERDIV2 = 9'h190;
|
|
parameter SIM_RECEIVER_DETECT_PASS_0 = "FALSE";
|
|
parameter SIM_RECEIVER_DETECT_PASS_1 = "FALSE";
|
|
parameter TERMINATION_OVRD = "FALSE";
|
|
parameter TXGEARBOX_USE_0 = "FALSE";
|
|
parameter TXGEARBOX_USE_1 = "FALSE";
|
|
parameter TX_BUFFER_USE_0 = "TRUE";
|
|
parameter TX_BUFFER_USE_1 = "TRUE";
|
|
parameter TX_XCLK_SEL_0 = "TXUSR";
|
|
parameter TX_XCLK_SEL_1 = "TXUSR";
|
|
parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03c;
|
|
parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03c;
|
|
parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832;
|
|
parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832;
|
|
parameter [19:0] PMA_TX_CFG_0 = 20'h00082;
|
|
parameter [19:0] PMA_TX_CFG_1 = 20'h00082;
|
|
parameter [1:0] CM_TRIM_0 = 2'b10;
|
|
parameter [1:0] CM_TRIM_1 = 2'b10;
|
|
parameter [23:0] PLL_COM_CFG = 24'h21680a;
|
|
parameter [24:0] PMA_RX_CFG_0 = 25'h05ce109;
|
|
parameter [24:0] PMA_RX_CFG_1 = 25'h05ce109;
|
|
parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c08040;
|
|
parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c08040;
|
|
parameter [2:0] GEARBOX_ENDEC_0 = 3'b000;
|
|
parameter [2:0] GEARBOX_ENDEC_1 = 3'b000;
|
|
parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b111;
|
|
parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b111;
|
|
parameter [2:0] PLL_LKDET_CFG = 3'b111;
|
|
parameter [2:0] PLL_TDCC_CFG = 3'b000;
|
|
parameter [2:0] SATA_BURST_VAL_0 = 3'b100;
|
|
parameter [2:0] SATA_BURST_VAL_1 = 3'b100;
|
|
parameter [2:0] SATA_IDLE_VAL_0 = 3'b011;
|
|
parameter [2:0] SATA_IDLE_VAL_1 = 3'b011;
|
|
parameter [2:0] TXRX_INVERT_0 = 3'b000;
|
|
parameter [2:0] TXRX_INVERT_1 = 3'b000;
|
|
parameter [2:0] TX_IDLE_DELAY_0 = 3'b010;
|
|
parameter [2:0] TX_IDLE_DELAY_1 = 3'b010;
|
|
parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1;
|
|
parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111;
|
|
parameter [3:0] COM_BURST_VAL_0 = 4'b1111;
|
|
parameter [3:0] COM_BURST_VAL_1 = 4'b1111;
|
|
parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000;
|
|
parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000;
|
|
parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000;
|
|
parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000;
|
|
parameter [4:0] CDR_PH_ADJ_TIME = 5'b01010;
|
|
parameter [4:0] DFE_CAL_TIME = 5'b00110;
|
|
parameter [4:0] TERMINATION_CTRL = 5'b10100;
|
|
parameter [68:0] PMA_COM_CFG = 69'h0;
|
|
parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h0;
|
|
parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h0;
|
|
parameter [7:0] PLL_CP_CFG = 8'h00;
|
|
parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19;
|
|
parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100;
|
|
parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0;
|
|
parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0;
|
|
parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111;
|
|
parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111;
|
|
parameter [9:0] DFE_CFG_0 = 10'b0001111011;
|
|
parameter [9:0] DFE_CFG_1 = 10'b0001111011;
|
|
parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011;
|
|
parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011;
|
|
parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100;
|
|
parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100;
|
|
parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064;
|
|
parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064;
|
|
parameter ALIGN_COMMA_WORD_0 = 1;
|
|
parameter ALIGN_COMMA_WORD_1 = 1;
|
|
parameter CB2_INH_CC_PERIOD_0 = 8;
|
|
parameter CB2_INH_CC_PERIOD_1 = 8;
|
|
parameter CHAN_BOND_1_MAX_SKEW_0 = 7;
|
|
parameter CHAN_BOND_1_MAX_SKEW_1 = 7;
|
|
parameter CHAN_BOND_2_MAX_SKEW_0 = 1;
|
|
parameter CHAN_BOND_2_MAX_SKEW_1 = 1;
|
|
parameter CHAN_BOND_LEVEL_0 = 0;
|
|
parameter CHAN_BOND_LEVEL_1 = 0;
|
|
parameter CHAN_BOND_SEQ_LEN_0 = 4;
|
|
parameter CHAN_BOND_SEQ_LEN_1 = 4;
|
|
parameter CLK25_DIVIDER = 4;
|
|
parameter CLK_COR_ADJ_LEN_0 = 1;
|
|
parameter CLK_COR_ADJ_LEN_1 = 1;
|
|
parameter CLK_COR_DET_LEN_0 = 1;
|
|
parameter CLK_COR_DET_LEN_1 = 1;
|
|
parameter CLK_COR_MAX_LAT_0 = 18;
|
|
parameter CLK_COR_MAX_LAT_1 = 18;
|
|
parameter CLK_COR_MIN_LAT_0 = 16;
|
|
parameter CLK_COR_MIN_LAT_1 = 16;
|
|
parameter CLK_COR_REPEAT_WAIT_0 = 5;
|
|
parameter CLK_COR_REPEAT_WAIT_1 = 5;
|
|
parameter OOB_CLK_DIVIDER = 4;
|
|
parameter PLL_DIVSEL_FB = 5;
|
|
parameter PLL_DIVSEL_REF = 2;
|
|
parameter PLL_RXDIVSEL_OUT_0 = 1;
|
|
parameter PLL_RXDIVSEL_OUT_1 = 1;
|
|
parameter PLL_TXDIVSEL_OUT_0 = 1;
|
|
parameter PLL_TXDIVSEL_OUT_1 = 1;
|
|
parameter RX_LOS_INVALID_INCR_0 = 8;
|
|
parameter RX_LOS_INVALID_INCR_1 = 8;
|
|
parameter RX_LOS_THRESHOLD_0 = 128;
|
|
parameter RX_LOS_THRESHOLD_1 = 128;
|
|
parameter SATA_MAX_BURST_0 = 7;
|
|
parameter SATA_MAX_BURST_1 = 7;
|
|
parameter SATA_MAX_INIT_0 = 22;
|
|
parameter SATA_MAX_INIT_1 = 22;
|
|
parameter SATA_MAX_WAKE_0 = 7;
|
|
parameter SATA_MAX_WAKE_1 = 7;
|
|
parameter SATA_MIN_BURST_0 = 4;
|
|
parameter SATA_MIN_BURST_1 = 4;
|
|
parameter SATA_MIN_INIT_0 = 12;
|
|
parameter SATA_MIN_INIT_1 = 12;
|
|
parameter SATA_MIN_WAKE_0 = 4;
|
|
parameter SATA_MIN_WAKE_1 = 4;
|
|
parameter SIM_GTXRESET_SPEEDUP = 0;
|
|
parameter TERMINATION_IMP_0 = 50;
|
|
parameter TERMINATION_IMP_1 = 50;
|
|
output DRDY;
|
|
output PHYSTATUS0;
|
|
output PHYSTATUS1;
|
|
output PLLLKDET;
|
|
output REFCLKOUT;
|
|
output RESETDONE0;
|
|
output RESETDONE1;
|
|
output RXBYTEISALIGNED0;
|
|
output RXBYTEISALIGNED1;
|
|
output RXBYTEREALIGN0;
|
|
output RXBYTEREALIGN1;
|
|
output RXCHANBONDSEQ0;
|
|
output RXCHANBONDSEQ1;
|
|
output RXCHANISALIGNED0;
|
|
output RXCHANISALIGNED1;
|
|
output RXCHANREALIGN0;
|
|
output RXCHANREALIGN1;
|
|
output RXCOMMADET0;
|
|
output RXCOMMADET1;
|
|
output RXDATAVALID0;
|
|
output RXDATAVALID1;
|
|
output RXELECIDLE0;
|
|
output RXELECIDLE1;
|
|
output RXHEADERVALID0;
|
|
output RXHEADERVALID1;
|
|
output RXOVERSAMPLEERR0;
|
|
output RXOVERSAMPLEERR1;
|
|
output RXPRBSERR0;
|
|
output RXPRBSERR1;
|
|
output RXRECCLK0;
|
|
output RXRECCLK1;
|
|
output RXSTARTOFSEQ0;
|
|
output RXSTARTOFSEQ1;
|
|
output RXVALID0;
|
|
output RXVALID1;
|
|
output TXGEARBOXREADY0;
|
|
output TXGEARBOXREADY1;
|
|
output TXN0;
|
|
output TXN1;
|
|
output TXOUTCLK0;
|
|
output TXOUTCLK1;
|
|
output TXP0;
|
|
output TXP1;
|
|
output [15:0] DO;
|
|
output [1:0] RXLOSSOFSYNC0;
|
|
output [1:0] RXLOSSOFSYNC1;
|
|
output [1:0] TXBUFSTATUS0;
|
|
output [1:0] TXBUFSTATUS1;
|
|
output [2:0] DFESENSCAL0;
|
|
output [2:0] DFESENSCAL1;
|
|
output [2:0] RXBUFSTATUS0;
|
|
output [2:0] RXBUFSTATUS1;
|
|
output [2:0] RXCLKCORCNT0;
|
|
output [2:0] RXCLKCORCNT1;
|
|
output [2:0] RXHEADER0;
|
|
output [2:0] RXHEADER1;
|
|
output [2:0] RXSTATUS0;
|
|
output [2:0] RXSTATUS1;
|
|
output [31:0] RXDATA0;
|
|
output [31:0] RXDATA1;
|
|
output [3:0] DFETAP3MONITOR0;
|
|
output [3:0] DFETAP3MONITOR1;
|
|
output [3:0] DFETAP4MONITOR0;
|
|
output [3:0] DFETAP4MONITOR1;
|
|
output [3:0] RXCHARISCOMMA0;
|
|
output [3:0] RXCHARISCOMMA1;
|
|
output [3:0] RXCHARISK0;
|
|
output [3:0] RXCHARISK1;
|
|
output [3:0] RXCHBONDO0;
|
|
output [3:0] RXCHBONDO1;
|
|
output [3:0] RXDISPERR0;
|
|
output [3:0] RXDISPERR1;
|
|
output [3:0] RXNOTINTABLE0;
|
|
output [3:0] RXNOTINTABLE1;
|
|
output [3:0] RXRUNDISP0;
|
|
output [3:0] RXRUNDISP1;
|
|
output [3:0] TXKERR0;
|
|
output [3:0] TXKERR1;
|
|
output [3:0] TXRUNDISP0;
|
|
output [3:0] TXRUNDISP1;
|
|
output [4:0] DFEEYEDACMONITOR0;
|
|
output [4:0] DFEEYEDACMONITOR1;
|
|
output [4:0] DFETAP1MONITOR0;
|
|
output [4:0] DFETAP1MONITOR1;
|
|
output [4:0] DFETAP2MONITOR0;
|
|
output [4:0] DFETAP2MONITOR1;
|
|
output [5:0] DFECLKDLYADJMONITOR0;
|
|
output [5:0] DFECLKDLYADJMONITOR1;
|
|
input CLKIN;
|
|
input DCLK;
|
|
input DEN;
|
|
input DWE;
|
|
input GTXRESET;
|
|
input INTDATAWIDTH;
|
|
input PLLLKDETEN;
|
|
input PLLPOWERDOWN;
|
|
input PRBSCNTRESET0;
|
|
input PRBSCNTRESET1;
|
|
input REFCLKPWRDNB;
|
|
input RXBUFRESET0;
|
|
input RXBUFRESET1;
|
|
input RXCDRRESET0;
|
|
input RXCDRRESET1;
|
|
input RXCOMMADETUSE0;
|
|
input RXCOMMADETUSE1;
|
|
input RXDEC8B10BUSE0;
|
|
input RXDEC8B10BUSE1;
|
|
input RXENCHANSYNC0;
|
|
input RXENCHANSYNC1;
|
|
input RXENEQB0;
|
|
input RXENEQB1;
|
|
input RXENMCOMMAALIGN0;
|
|
input RXENMCOMMAALIGN1;
|
|
input RXENPCOMMAALIGN0;
|
|
input RXENPCOMMAALIGN1;
|
|
input RXENPMAPHASEALIGN0;
|
|
input RXENPMAPHASEALIGN1;
|
|
input RXENSAMPLEALIGN0;
|
|
input RXENSAMPLEALIGN1;
|
|
input RXGEARBOXSLIP0;
|
|
input RXGEARBOXSLIP1;
|
|
input RXN0;
|
|
input RXN1;
|
|
input RXP0;
|
|
input RXP1;
|
|
input RXPMASETPHASE0;
|
|
input RXPMASETPHASE1;
|
|
input RXPOLARITY0;
|
|
input RXPOLARITY1;
|
|
input RXRESET0;
|
|
input RXRESET1;
|
|
input RXSLIDE0;
|
|
input RXSLIDE1;
|
|
input RXUSRCLK0;
|
|
input RXUSRCLK1;
|
|
input RXUSRCLK20;
|
|
input RXUSRCLK21;
|
|
input TXCOMSTART0;
|
|
input TXCOMSTART1;
|
|
input TXCOMTYPE0;
|
|
input TXCOMTYPE1;
|
|
input TXDETECTRX0;
|
|
input TXDETECTRX1;
|
|
input TXELECIDLE0;
|
|
input TXELECIDLE1;
|
|
input TXENC8B10BUSE0;
|
|
input TXENC8B10BUSE1;
|
|
input TXENPMAPHASEALIGN0;
|
|
input TXENPMAPHASEALIGN1;
|
|
input TXINHIBIT0;
|
|
input TXINHIBIT1;
|
|
input TXPMASETPHASE0;
|
|
input TXPMASETPHASE1;
|
|
input TXPOLARITY0;
|
|
input TXPOLARITY1;
|
|
input TXRESET0;
|
|
input TXRESET1;
|
|
input TXSTARTSEQ0;
|
|
input TXSTARTSEQ1;
|
|
input TXUSRCLK0;
|
|
input TXUSRCLK1;
|
|
input TXUSRCLK20;
|
|
input TXUSRCLK21;
|
|
input [13:0] GTXTEST;
|
|
input [15:0] DI;
|
|
input [1:0] RXDATAWIDTH0;
|
|
input [1:0] RXDATAWIDTH1;
|
|
input [1:0] RXENPRBSTST0;
|
|
input [1:0] RXENPRBSTST1;
|
|
input [1:0] RXEQMIX0;
|
|
input [1:0] RXEQMIX1;
|
|
input [1:0] RXPOWERDOWN0;
|
|
input [1:0] RXPOWERDOWN1;
|
|
input [1:0] TXDATAWIDTH0;
|
|
input [1:0] TXDATAWIDTH1;
|
|
input [1:0] TXENPRBSTST0;
|
|
input [1:0] TXENPRBSTST1;
|
|
input [1:0] TXPOWERDOWN0;
|
|
input [1:0] TXPOWERDOWN1;
|
|
input [2:0] LOOPBACK0;
|
|
input [2:0] LOOPBACK1;
|
|
input [2:0] TXBUFDIFFCTRL0;
|
|
input [2:0] TXBUFDIFFCTRL1;
|
|
input [2:0] TXDIFFCTRL0;
|
|
input [2:0] TXDIFFCTRL1;
|
|
input [2:0] TXHEADER0;
|
|
input [2:0] TXHEADER1;
|
|
input [31:0] TXDATA0;
|
|
input [31:0] TXDATA1;
|
|
input [3:0] DFETAP30;
|
|
input [3:0] DFETAP31;
|
|
input [3:0] DFETAP40;
|
|
input [3:0] DFETAP41;
|
|
input [3:0] RXCHBONDI0;
|
|
input [3:0] RXCHBONDI1;
|
|
input [3:0] RXEQPOLE0;
|
|
input [3:0] RXEQPOLE1;
|
|
input [3:0] TXBYPASS8B10B0;
|
|
input [3:0] TXBYPASS8B10B1;
|
|
input [3:0] TXCHARDISPMODE0;
|
|
input [3:0] TXCHARDISPMODE1;
|
|
input [3:0] TXCHARDISPVAL0;
|
|
input [3:0] TXCHARDISPVAL1;
|
|
input [3:0] TXCHARISK0;
|
|
input [3:0] TXCHARISK1;
|
|
input [3:0] TXPREEMPHASIS0;
|
|
input [3:0] TXPREEMPHASIS1;
|
|
input [4:0] DFETAP10;
|
|
input [4:0] DFETAP11;
|
|
input [4:0] DFETAP20;
|
|
input [4:0] DFETAP21;
|
|
input [5:0] DFECLKDLYADJ0;
|
|
input [5:0] DFECLKDLYADJ1;
|
|
input [6:0] DADDR;
|
|
input [6:0] TXSEQUENCE0;
|
|
input [6:0] TXSEQUENCE1;
|
|
endmodule
|
|
|
|
module CRC32(CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET);
|
|
parameter CRC_INIT = 32'hFFFFFFFF;
|
|
output [31:0] CRCOUT;
|
|
(* clkbuf_sink *)
|
|
input CRCCLK;
|
|
input CRCDATAVALID;
|
|
input [2:0] CRCDATAWIDTH;
|
|
input [31:0] CRCIN;
|
|
input CRCRESET;
|
|
endmodule
|
|
|
|
module CRC64(CRCOUT, CRCCLK, CRCDATAVALID, CRCDATAWIDTH, CRCIN, CRCRESET);
|
|
parameter CRC_INIT = 32'hFFFFFFFF;
|
|
output [31:0] CRCOUT;
|
|
(* clkbuf_sink *)
|
|
input CRCCLK;
|
|
input CRCDATAVALID;
|
|
input [2:0] CRCDATAWIDTH;
|
|
input [63:0] CRCIN;
|
|
input CRCRESET;
|
|
endmodule
|
|
|
|
module GTHE1_QUAD(DRDY, GTHINITDONE, MGMTPCSRDACK, RXCTRLACK0, RXCTRLACK1, RXCTRLACK2, RXCTRLACK3, RXDATATAP0, RXDATATAP1, RXDATATAP2, RXDATATAP3, RXPCSCLKSMPL0, RXPCSCLKSMPL1, RXPCSCLKSMPL2, RXPCSCLKSMPL3, RXUSERCLKOUT0, RXUSERCLKOUT1, RXUSERCLKOUT2, RXUSERCLKOUT3, TSTPATH, TSTREFCLKFAB
|
|
, TSTREFCLKOUT, TXCTRLACK0, TXCTRLACK1, TXCTRLACK2, TXCTRLACK3, TXDATATAP10, TXDATATAP11, TXDATATAP12, TXDATATAP13, TXDATATAP20, TXDATATAP21, TXDATATAP22, TXDATATAP23, TXN0, TXN1, TXN2, TXN3, TXP0, TXP1, TXP2, TXP3
|
|
, TXPCSCLKSMPL0, TXPCSCLKSMPL1, TXPCSCLKSMPL2, TXPCSCLKSMPL3, TXUSERCLKOUT0, TXUSERCLKOUT1, TXUSERCLKOUT2, TXUSERCLKOUT3, DRPDO, MGMTPCSRDDATA, RXDATA0, RXDATA1, RXDATA2, RXDATA3, RXCODEERR0, RXCODEERR1, RXCODEERR2, RXCODEERR3, RXCTRL0, RXCTRL1, RXCTRL2
|
|
, RXCTRL3, RXDISPERR0, RXDISPERR1, RXDISPERR2, RXDISPERR3, RXVALID0, RXVALID1, RXVALID2, RXVALID3, DCLK, DEN, DFETRAINCTRL0, DFETRAINCTRL1, DFETRAINCTRL2, DFETRAINCTRL3, DISABLEDRP, DWE, GTHINIT, GTHRESET, GTHX2LANE01, GTHX2LANE23
|
|
, GTHX4LANE, MGMTPCSREGRD, MGMTPCSREGWR, POWERDOWN0, POWERDOWN1, POWERDOWN2, POWERDOWN3, REFCLK, RXBUFRESET0, RXBUFRESET1, RXBUFRESET2, RXBUFRESET3, RXENCOMMADET0, RXENCOMMADET1, RXENCOMMADET2, RXENCOMMADET3, RXN0, RXN1, RXN2, RXN3, RXP0
|
|
, RXP1, RXP2, RXP3, RXPOLARITY0, RXPOLARITY1, RXPOLARITY2, RXPOLARITY3, RXSLIP0, RXSLIP1, RXSLIP2, RXSLIP3, RXUSERCLKIN0, RXUSERCLKIN1, RXUSERCLKIN2, RXUSERCLKIN3, TXBUFRESET0, TXBUFRESET1, TXBUFRESET2, TXBUFRESET3, TXDEEMPH0, TXDEEMPH1
|
|
, TXDEEMPH2, TXDEEMPH3, TXUSERCLKIN0, TXUSERCLKIN1, TXUSERCLKIN2, TXUSERCLKIN3, DADDR, DI, MGMTPCSREGADDR, MGMTPCSWRDATA, RXPOWERDOWN0, RXPOWERDOWN1, RXPOWERDOWN2, RXPOWERDOWN3, RXRATE0, RXRATE1, RXRATE2, RXRATE3, TXPOWERDOWN0, TXPOWERDOWN1, TXPOWERDOWN2
|
|
, TXPOWERDOWN3, TXRATE0, TXRATE1, TXRATE2, TXRATE3, PLLREFCLKSEL, SAMPLERATE0, SAMPLERATE1, SAMPLERATE2, SAMPLERATE3, TXMARGIN0, TXMARGIN1, TXMARGIN2, TXMARGIN3, MGMTPCSLANESEL, MGMTPCSMMDADDR, PLLPCSCLKDIV, TXDATA0, TXDATA1, TXDATA2, TXDATA3
|
|
, TXCTRL0, TXCTRL1, TXCTRL2, TXCTRL3, TXDATAMSB0, TXDATAMSB1, TXDATAMSB2, TXDATAMSB3);
|
|
parameter [15:0] BER_CONST_PTRN0 = 16'h0000;
|
|
parameter [15:0] BER_CONST_PTRN1 = 16'h0000;
|
|
parameter [15:0] BUFFER_CONFIG_LANE0 = 16'h4004;
|
|
parameter [15:0] BUFFER_CONFIG_LANE1 = 16'h4004;
|
|
parameter [15:0] BUFFER_CONFIG_LANE2 = 16'h4004;
|
|
parameter [15:0] BUFFER_CONFIG_LANE3 = 16'h4004;
|
|
parameter [15:0] DFE_TRAIN_CTRL_LANE0 = 16'h0000;
|
|
parameter [15:0] DFE_TRAIN_CTRL_LANE1 = 16'h0000;
|
|
parameter [15:0] DFE_TRAIN_CTRL_LANE2 = 16'h0000;
|
|
parameter [15:0] DFE_TRAIN_CTRL_LANE3 = 16'h0000;
|
|
parameter [15:0] DLL_CFG0 = 16'h8202;
|
|
parameter [15:0] DLL_CFG1 = 16'h0000;
|
|
parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASEKR_PMA_CTRL_LANE0 = 16'h0002;
|
|
parameter [15:0] E10GBASEKR_PMA_CTRL_LANE1 = 16'h0002;
|
|
parameter [15:0] E10GBASEKR_PMA_CTRL_LANE2 = 16'h0002;
|
|
parameter [15:0] E10GBASEKR_PMA_CTRL_LANE3 = 16'h0002;
|
|
parameter [15:0] E10GBASEKX_CTRL_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASEKX_CTRL_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASEKX_CTRL_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASEKX_CTRL_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_CFG_LANE0 = 16'h070C;
|
|
parameter [15:0] E10GBASER_PCS_CFG_LANE1 = 16'h070C;
|
|
parameter [15:0] E10GBASER_PCS_CFG_LANE2 = 16'h070C;
|
|
parameter [15:0] E10GBASER_PCS_CFG_LANE3 = 16'h070C;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA0_LANE0 = 16'h0001;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA0_LANE1 = 16'h0001;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA0_LANE2 = 16'h0001;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA0_LANE3 = 16'h0001;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA1_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA1_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA1_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA1_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA2_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA2_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA2_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA2_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA3_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA3_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA3_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDA3_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB0_LANE0 = 16'h0001;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB0_LANE1 = 16'h0001;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB0_LANE2 = 16'h0001;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB0_LANE3 = 16'h0001;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB1_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB1_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB1_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB1_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB2_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB2_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB2_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB2_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB3_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB3_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB3_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_SEEDB3_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE3 = 16'h0000;
|
|
parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE0 = 16'h0000;
|
|
parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE1 = 16'h0000;
|
|
parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE2 = 16'h0000;
|
|
parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE3 = 16'h0000;
|
|
parameter [15:0] GLBL0_NOISE_CTRL = 16'hF0B8;
|
|
parameter [15:0] GLBL_AMON_SEL = 16'h0000;
|
|
parameter [15:0] GLBL_DMON_SEL = 16'h0200;
|
|
parameter [15:0] GLBL_PWR_CTRL = 16'h0000;
|
|
parameter [0:0] GTH_CFG_PWRUP_LANE0 = 1'b1;
|
|
parameter [0:0] GTH_CFG_PWRUP_LANE1 = 1'b1;
|
|
parameter [0:0] GTH_CFG_PWRUP_LANE2 = 1'b1;
|
|
parameter [0:0] GTH_CFG_PWRUP_LANE3 = 1'b1;
|
|
parameter [15:0] LANE_AMON_SEL = 16'h00F0;
|
|
parameter [15:0] LANE_DMON_SEL = 16'h0000;
|
|
parameter [15:0] LANE_LNK_CFGOVRD = 16'h0000;
|
|
parameter [15:0] LANE_PWR_CTRL_LANE0 = 16'h0400;
|
|
parameter [15:0] LANE_PWR_CTRL_LANE1 = 16'h0400;
|
|
parameter [15:0] LANE_PWR_CTRL_LANE2 = 16'h0400;
|
|
parameter [15:0] LANE_PWR_CTRL_LANE3 = 16'h0400;
|
|
parameter [15:0] LNK_TRN_CFG_LANE0 = 16'h0000;
|
|
parameter [15:0] LNK_TRN_CFG_LANE1 = 16'h0000;
|
|
parameter [15:0] LNK_TRN_CFG_LANE2 = 16'h0000;
|
|
parameter [15:0] LNK_TRN_CFG_LANE3 = 16'h0000;
|
|
parameter [15:0] LNK_TRN_COEFF_REQ_LANE0 = 16'h0000;
|
|
parameter [15:0] LNK_TRN_COEFF_REQ_LANE1 = 16'h0000;
|
|
parameter [15:0] LNK_TRN_COEFF_REQ_LANE2 = 16'h0000;
|
|
parameter [15:0] LNK_TRN_COEFF_REQ_LANE3 = 16'h0000;
|
|
parameter [15:0] MISC_CFG = 16'h0008;
|
|
parameter [15:0] MODE_CFG1 = 16'h0000;
|
|
parameter [15:0] MODE_CFG2 = 16'h0000;
|
|
parameter [15:0] MODE_CFG3 = 16'h0000;
|
|
parameter [15:0] MODE_CFG4 = 16'h0000;
|
|
parameter [15:0] MODE_CFG5 = 16'h0000;
|
|
parameter [15:0] MODE_CFG6 = 16'h0000;
|
|
parameter [15:0] MODE_CFG7 = 16'h0000;
|
|
parameter [15:0] PCS_ABILITY_LANE0 = 16'h0010;
|
|
parameter [15:0] PCS_ABILITY_LANE1 = 16'h0010;
|
|
parameter [15:0] PCS_ABILITY_LANE2 = 16'h0010;
|
|
parameter [15:0] PCS_ABILITY_LANE3 = 16'h0010;
|
|
parameter [15:0] PCS_CTRL1_LANE0 = 16'h2040;
|
|
parameter [15:0] PCS_CTRL1_LANE1 = 16'h2040;
|
|
parameter [15:0] PCS_CTRL1_LANE2 = 16'h2040;
|
|
parameter [15:0] PCS_CTRL1_LANE3 = 16'h2040;
|
|
parameter [15:0] PCS_CTRL2_LANE0 = 16'h0000;
|
|
parameter [15:0] PCS_CTRL2_LANE1 = 16'h0000;
|
|
parameter [15:0] PCS_CTRL2_LANE2 = 16'h0000;
|
|
parameter [15:0] PCS_CTRL2_LANE3 = 16'h0000;
|
|
parameter [15:0] PCS_MISC_CFG_0_LANE0 = 16'h1116;
|
|
parameter [15:0] PCS_MISC_CFG_0_LANE1 = 16'h1116;
|
|
parameter [15:0] PCS_MISC_CFG_0_LANE2 = 16'h1116;
|
|
parameter [15:0] PCS_MISC_CFG_0_LANE3 = 16'h1116;
|
|
parameter [15:0] PCS_MISC_CFG_1_LANE0 = 16'h0000;
|
|
parameter [15:0] PCS_MISC_CFG_1_LANE1 = 16'h0000;
|
|
parameter [15:0] PCS_MISC_CFG_1_LANE2 = 16'h0000;
|
|
parameter [15:0] PCS_MISC_CFG_1_LANE3 = 16'h0000;
|
|
parameter [15:0] PCS_MODE_LANE0 = 16'h0000;
|
|
parameter [15:0] PCS_MODE_LANE1 = 16'h0000;
|
|
parameter [15:0] PCS_MODE_LANE2 = 16'h0000;
|
|
parameter [15:0] PCS_MODE_LANE3 = 16'h0000;
|
|
parameter [15:0] PCS_RESET_1_LANE0 = 16'h0002;
|
|
parameter [15:0] PCS_RESET_1_LANE1 = 16'h0002;
|
|
parameter [15:0] PCS_RESET_1_LANE2 = 16'h0002;
|
|
parameter [15:0] PCS_RESET_1_LANE3 = 16'h0002;
|
|
parameter [15:0] PCS_RESET_LANE0 = 16'h0000;
|
|
parameter [15:0] PCS_RESET_LANE1 = 16'h0000;
|
|
parameter [15:0] PCS_RESET_LANE2 = 16'h0000;
|
|
parameter [15:0] PCS_RESET_LANE3 = 16'h0000;
|
|
parameter [15:0] PCS_TYPE_LANE0 = 16'h002C;
|
|
parameter [15:0] PCS_TYPE_LANE1 = 16'h002C;
|
|
parameter [15:0] PCS_TYPE_LANE2 = 16'h002C;
|
|
parameter [15:0] PCS_TYPE_LANE3 = 16'h002C;
|
|
parameter [15:0] PLL_CFG0 = 16'h95DF;
|
|
parameter [15:0] PLL_CFG1 = 16'h81C0;
|
|
parameter [15:0] PLL_CFG2 = 16'h0424;
|
|
parameter [15:0] PMA_CTRL1_LANE0 = 16'h0000;
|
|
parameter [15:0] PMA_CTRL1_LANE1 = 16'h0000;
|
|
parameter [15:0] PMA_CTRL1_LANE2 = 16'h0000;
|
|
parameter [15:0] PMA_CTRL1_LANE3 = 16'h0000;
|
|
parameter [15:0] PMA_CTRL2_LANE0 = 16'h000B;
|
|
parameter [15:0] PMA_CTRL2_LANE1 = 16'h000B;
|
|
parameter [15:0] PMA_CTRL2_LANE2 = 16'h000B;
|
|
parameter [15:0] PMA_CTRL2_LANE3 = 16'h000B;
|
|
parameter [15:0] PMA_LPBK_CTRL_LANE0 = 16'h0004;
|
|
parameter [15:0] PMA_LPBK_CTRL_LANE1 = 16'h0004;
|
|
parameter [15:0] PMA_LPBK_CTRL_LANE2 = 16'h0004;
|
|
parameter [15:0] PMA_LPBK_CTRL_LANE3 = 16'h0004;
|
|
parameter [15:0] PRBS_BER_CFG0_LANE0 = 16'h0000;
|
|
parameter [15:0] PRBS_BER_CFG0_LANE1 = 16'h0000;
|
|
parameter [15:0] PRBS_BER_CFG0_LANE2 = 16'h0000;
|
|
parameter [15:0] PRBS_BER_CFG0_LANE3 = 16'h0000;
|
|
parameter [15:0] PRBS_BER_CFG1_LANE0 = 16'h0000;
|
|
parameter [15:0] PRBS_BER_CFG1_LANE1 = 16'h0000;
|
|
parameter [15:0] PRBS_BER_CFG1_LANE2 = 16'h0000;
|
|
parameter [15:0] PRBS_BER_CFG1_LANE3 = 16'h0000;
|
|
parameter [15:0] PRBS_CFG_LANE0 = 16'h000A;
|
|
parameter [15:0] PRBS_CFG_LANE1 = 16'h000A;
|
|
parameter [15:0] PRBS_CFG_LANE2 = 16'h000A;
|
|
parameter [15:0] PRBS_CFG_LANE3 = 16'h000A;
|
|
parameter [15:0] PTRN_CFG0_LSB = 16'h5555;
|
|
parameter [15:0] PTRN_CFG0_MSB = 16'h5555;
|
|
parameter [15:0] PTRN_LEN_CFG = 16'h001F;
|
|
parameter [15:0] PWRUP_DLY = 16'h0000;
|
|
parameter [15:0] RX_AEQ_VAL0_LANE0 = 16'h03C0;
|
|
parameter [15:0] RX_AEQ_VAL0_LANE1 = 16'h03C0;
|
|
parameter [15:0] RX_AEQ_VAL0_LANE2 = 16'h03C0;
|
|
parameter [15:0] RX_AEQ_VAL0_LANE3 = 16'h03C0;
|
|
parameter [15:0] RX_AEQ_VAL1_LANE0 = 16'h0000;
|
|
parameter [15:0] RX_AEQ_VAL1_LANE1 = 16'h0000;
|
|
parameter [15:0] RX_AEQ_VAL1_LANE2 = 16'h0000;
|
|
parameter [15:0] RX_AEQ_VAL1_LANE3 = 16'h0000;
|
|
parameter [15:0] RX_AGC_CTRL_LANE0 = 16'h0000;
|
|
parameter [15:0] RX_AGC_CTRL_LANE1 = 16'h0000;
|
|
parameter [15:0] RX_AGC_CTRL_LANE2 = 16'h0000;
|
|
parameter [15:0] RX_AGC_CTRL_LANE3 = 16'h0000;
|
|
parameter [15:0] RX_CDR_CTRL0_LANE0 = 16'h0005;
|
|
parameter [15:0] RX_CDR_CTRL0_LANE1 = 16'h0005;
|
|
parameter [15:0] RX_CDR_CTRL0_LANE2 = 16'h0005;
|
|
parameter [15:0] RX_CDR_CTRL0_LANE3 = 16'h0005;
|
|
parameter [15:0] RX_CDR_CTRL1_LANE0 = 16'h4200;
|
|
parameter [15:0] RX_CDR_CTRL1_LANE1 = 16'h4200;
|
|
parameter [15:0] RX_CDR_CTRL1_LANE2 = 16'h4200;
|
|
parameter [15:0] RX_CDR_CTRL1_LANE3 = 16'h4200;
|
|
parameter [15:0] RX_CDR_CTRL2_LANE0 = 16'h2000;
|
|
parameter [15:0] RX_CDR_CTRL2_LANE1 = 16'h2000;
|
|
parameter [15:0] RX_CDR_CTRL2_LANE2 = 16'h2000;
|
|
parameter [15:0] RX_CDR_CTRL2_LANE3 = 16'h2000;
|
|
parameter [15:0] RX_CFG0_LANE0 = 16'h0500;
|
|
parameter [15:0] RX_CFG0_LANE1 = 16'h0500;
|
|
parameter [15:0] RX_CFG0_LANE2 = 16'h0500;
|
|
parameter [15:0] RX_CFG0_LANE3 = 16'h0500;
|
|
parameter [15:0] RX_CFG1_LANE0 = 16'h821F;
|
|
parameter [15:0] RX_CFG1_LANE1 = 16'h821F;
|
|
parameter [15:0] RX_CFG1_LANE2 = 16'h821F;
|
|
parameter [15:0] RX_CFG1_LANE3 = 16'h821F;
|
|
parameter [15:0] RX_CFG2_LANE0 = 16'h1001;
|
|
parameter [15:0] RX_CFG2_LANE1 = 16'h1001;
|
|
parameter [15:0] RX_CFG2_LANE2 = 16'h1001;
|
|
parameter [15:0] RX_CFG2_LANE3 = 16'h1001;
|
|
parameter [15:0] RX_CTLE_CTRL_LANE0 = 16'h008F;
|
|
parameter [15:0] RX_CTLE_CTRL_LANE1 = 16'h008F;
|
|
parameter [15:0] RX_CTLE_CTRL_LANE2 = 16'h008F;
|
|
parameter [15:0] RX_CTLE_CTRL_LANE3 = 16'h008F;
|
|
parameter [15:0] RX_CTRL_OVRD_LANE0 = 16'h000C;
|
|
parameter [15:0] RX_CTRL_OVRD_LANE1 = 16'h000C;
|
|
parameter [15:0] RX_CTRL_OVRD_LANE2 = 16'h000C;
|
|
parameter [15:0] RX_CTRL_OVRD_LANE3 = 16'h000C;
|
|
parameter integer RX_FABRIC_WIDTH0 = 6466;
|
|
parameter integer RX_FABRIC_WIDTH1 = 6466;
|
|
parameter integer RX_FABRIC_WIDTH2 = 6466;
|
|
parameter integer RX_FABRIC_WIDTH3 = 6466;
|
|
parameter [15:0] RX_LOOP_CTRL_LANE0 = 16'h007F;
|
|
parameter [15:0] RX_LOOP_CTRL_LANE1 = 16'h007F;
|
|
parameter [15:0] RX_LOOP_CTRL_LANE2 = 16'h007F;
|
|
parameter [15:0] RX_LOOP_CTRL_LANE3 = 16'h007F;
|
|
parameter [15:0] RX_MVAL0_LANE0 = 16'h0000;
|
|
parameter [15:0] RX_MVAL0_LANE1 = 16'h0000;
|
|
parameter [15:0] RX_MVAL0_LANE2 = 16'h0000;
|
|
parameter [15:0] RX_MVAL0_LANE3 = 16'h0000;
|
|
parameter [15:0] RX_MVAL1_LANE0 = 16'h0000;
|
|
parameter [15:0] RX_MVAL1_LANE1 = 16'h0000;
|
|
parameter [15:0] RX_MVAL1_LANE2 = 16'h0000;
|
|
parameter [15:0] RX_MVAL1_LANE3 = 16'h0000;
|
|
parameter [15:0] RX_P0S_CTRL = 16'h1206;
|
|
parameter [15:0] RX_P0_CTRL = 16'h11F0;
|
|
parameter [15:0] RX_P1_CTRL = 16'h120F;
|
|
parameter [15:0] RX_P2_CTRL = 16'h0E0F;
|
|
parameter [15:0] RX_PI_CTRL0 = 16'hD2F0;
|
|
parameter [15:0] RX_PI_CTRL1 = 16'h0080;
|
|
parameter integer SIM_GTHRESET_SPEEDUP = 1;
|
|
parameter SIM_VERSION = "1.0";
|
|
parameter [15:0] SLICE_CFG = 16'h0000;
|
|
parameter [15:0] SLICE_NOISE_CTRL_0_LANE01 = 16'h0000;
|
|
parameter [15:0] SLICE_NOISE_CTRL_0_LANE23 = 16'h0000;
|
|
parameter [15:0] SLICE_NOISE_CTRL_1_LANE01 = 16'h0000;
|
|
parameter [15:0] SLICE_NOISE_CTRL_1_LANE23 = 16'h0000;
|
|
parameter [15:0] SLICE_NOISE_CTRL_2_LANE01 = 16'h7FFF;
|
|
parameter [15:0] SLICE_NOISE_CTRL_2_LANE23 = 16'h7FFF;
|
|
parameter [15:0] SLICE_TX_RESET_LANE01 = 16'h0000;
|
|
parameter [15:0] SLICE_TX_RESET_LANE23 = 16'h0000;
|
|
parameter [15:0] TERM_CTRL_LANE0 = 16'h5007;
|
|
parameter [15:0] TERM_CTRL_LANE1 = 16'h5007;
|
|
parameter [15:0] TERM_CTRL_LANE2 = 16'h5007;
|
|
parameter [15:0] TERM_CTRL_LANE3 = 16'h5007;
|
|
parameter [15:0] TX_CFG0_LANE0 = 16'h203D;
|
|
parameter [15:0] TX_CFG0_LANE1 = 16'h203D;
|
|
parameter [15:0] TX_CFG0_LANE2 = 16'h203D;
|
|
parameter [15:0] TX_CFG0_LANE3 = 16'h203D;
|
|
parameter [15:0] TX_CFG1_LANE0 = 16'h0F00;
|
|
parameter [15:0] TX_CFG1_LANE1 = 16'h0F00;
|
|
parameter [15:0] TX_CFG1_LANE2 = 16'h0F00;
|
|
parameter [15:0] TX_CFG1_LANE3 = 16'h0F00;
|
|
parameter [15:0] TX_CFG2_LANE0 = 16'h0081;
|
|
parameter [15:0] TX_CFG2_LANE1 = 16'h0081;
|
|
parameter [15:0] TX_CFG2_LANE2 = 16'h0081;
|
|
parameter [15:0] TX_CFG2_LANE3 = 16'h0081;
|
|
parameter [15:0] TX_CLK_SEL0_LANE0 = 16'h2121;
|
|
parameter [15:0] TX_CLK_SEL0_LANE1 = 16'h2121;
|
|
parameter [15:0] TX_CLK_SEL0_LANE2 = 16'h2121;
|
|
parameter [15:0] TX_CLK_SEL0_LANE3 = 16'h2121;
|
|
parameter [15:0] TX_CLK_SEL1_LANE0 = 16'h2121;
|
|
parameter [15:0] TX_CLK_SEL1_LANE1 = 16'h2121;
|
|
parameter [15:0] TX_CLK_SEL1_LANE2 = 16'h2121;
|
|
parameter [15:0] TX_CLK_SEL1_LANE3 = 16'h2121;
|
|
parameter [15:0] TX_DISABLE_LANE0 = 16'h0000;
|
|
parameter [15:0] TX_DISABLE_LANE1 = 16'h0000;
|
|
parameter [15:0] TX_DISABLE_LANE2 = 16'h0000;
|
|
parameter [15:0] TX_DISABLE_LANE3 = 16'h0000;
|
|
parameter integer TX_FABRIC_WIDTH0 = 6466;
|
|
parameter integer TX_FABRIC_WIDTH1 = 6466;
|
|
parameter integer TX_FABRIC_WIDTH2 = 6466;
|
|
parameter integer TX_FABRIC_WIDTH3 = 6466;
|
|
parameter [15:0] TX_P0P0S_CTRL = 16'h060C;
|
|
parameter [15:0] TX_P1P2_CTRL = 16'h0C39;
|
|
parameter [15:0] TX_PREEMPH_LANE0 = 16'h00A1;
|
|
parameter [15:0] TX_PREEMPH_LANE1 = 16'h00A1;
|
|
parameter [15:0] TX_PREEMPH_LANE2 = 16'h00A1;
|
|
parameter [15:0] TX_PREEMPH_LANE3 = 16'h00A1;
|
|
parameter [15:0] TX_PWR_RATE_OVRD_LANE0 = 16'h0060;
|
|
parameter [15:0] TX_PWR_RATE_OVRD_LANE1 = 16'h0060;
|
|
parameter [15:0] TX_PWR_RATE_OVRD_LANE2 = 16'h0060;
|
|
parameter [15:0] TX_PWR_RATE_OVRD_LANE3 = 16'h0060;
|
|
output DRDY;
|
|
output GTHINITDONE;
|
|
output MGMTPCSRDACK;
|
|
output RXCTRLACK0;
|
|
output RXCTRLACK1;
|
|
output RXCTRLACK2;
|
|
output RXCTRLACK3;
|
|
output RXDATATAP0;
|
|
output RXDATATAP1;
|
|
output RXDATATAP2;
|
|
output RXDATATAP3;
|
|
output RXPCSCLKSMPL0;
|
|
output RXPCSCLKSMPL1;
|
|
output RXPCSCLKSMPL2;
|
|
output RXPCSCLKSMPL3;
|
|
output RXUSERCLKOUT0;
|
|
output RXUSERCLKOUT1;
|
|
output RXUSERCLKOUT2;
|
|
output RXUSERCLKOUT3;
|
|
output TSTPATH;
|
|
output TSTREFCLKFAB;
|
|
output TSTREFCLKOUT;
|
|
output TXCTRLACK0;
|
|
output TXCTRLACK1;
|
|
output TXCTRLACK2;
|
|
output TXCTRLACK3;
|
|
output TXDATATAP10;
|
|
output TXDATATAP11;
|
|
output TXDATATAP12;
|
|
output TXDATATAP13;
|
|
output TXDATATAP20;
|
|
output TXDATATAP21;
|
|
output TXDATATAP22;
|
|
output TXDATATAP23;
|
|
output TXN0;
|
|
output TXN1;
|
|
output TXN2;
|
|
output TXN3;
|
|
output TXP0;
|
|
output TXP1;
|
|
output TXP2;
|
|
output TXP3;
|
|
output TXPCSCLKSMPL0;
|
|
output TXPCSCLKSMPL1;
|
|
output TXPCSCLKSMPL2;
|
|
output TXPCSCLKSMPL3;
|
|
output TXUSERCLKOUT0;
|
|
output TXUSERCLKOUT1;
|
|
output TXUSERCLKOUT2;
|
|
output TXUSERCLKOUT3;
|
|
output [15:0] DRPDO;
|
|
output [15:0] MGMTPCSRDDATA;
|
|
output [63:0] RXDATA0;
|
|
output [63:0] RXDATA1;
|
|
output [63:0] RXDATA2;
|
|
output [63:0] RXDATA3;
|
|
output [7:0] RXCODEERR0;
|
|
output [7:0] RXCODEERR1;
|
|
output [7:0] RXCODEERR2;
|
|
output [7:0] RXCODEERR3;
|
|
output [7:0] RXCTRL0;
|
|
output [7:0] RXCTRL1;
|
|
output [7:0] RXCTRL2;
|
|
output [7:0] RXCTRL3;
|
|
output [7:0] RXDISPERR0;
|
|
output [7:0] RXDISPERR1;
|
|
output [7:0] RXDISPERR2;
|
|
output [7:0] RXDISPERR3;
|
|
output [7:0] RXVALID0;
|
|
output [7:0] RXVALID1;
|
|
output [7:0] RXVALID2;
|
|
output [7:0] RXVALID3;
|
|
input DCLK;
|
|
input DEN;
|
|
input DFETRAINCTRL0;
|
|
input DFETRAINCTRL1;
|
|
input DFETRAINCTRL2;
|
|
input DFETRAINCTRL3;
|
|
input DISABLEDRP;
|
|
input DWE;
|
|
input GTHINIT;
|
|
input GTHRESET;
|
|
input GTHX2LANE01;
|
|
input GTHX2LANE23;
|
|
input GTHX4LANE;
|
|
input MGMTPCSREGRD;
|
|
input MGMTPCSREGWR;
|
|
input POWERDOWN0;
|
|
input POWERDOWN1;
|
|
input POWERDOWN2;
|
|
input POWERDOWN3;
|
|
input REFCLK;
|
|
input RXBUFRESET0;
|
|
input RXBUFRESET1;
|
|
input RXBUFRESET2;
|
|
input RXBUFRESET3;
|
|
input RXENCOMMADET0;
|
|
input RXENCOMMADET1;
|
|
input RXENCOMMADET2;
|
|
input RXENCOMMADET3;
|
|
input RXN0;
|
|
input RXN1;
|
|
input RXN2;
|
|
input RXN3;
|
|
input RXP0;
|
|
input RXP1;
|
|
input RXP2;
|
|
input RXP3;
|
|
input RXPOLARITY0;
|
|
input RXPOLARITY1;
|
|
input RXPOLARITY2;
|
|
input RXPOLARITY3;
|
|
input RXSLIP0;
|
|
input RXSLIP1;
|
|
input RXSLIP2;
|
|
input RXSLIP3;
|
|
input RXUSERCLKIN0;
|
|
input RXUSERCLKIN1;
|
|
input RXUSERCLKIN2;
|
|
input RXUSERCLKIN3;
|
|
input TXBUFRESET0;
|
|
input TXBUFRESET1;
|
|
input TXBUFRESET2;
|
|
input TXBUFRESET3;
|
|
input TXDEEMPH0;
|
|
input TXDEEMPH1;
|
|
input TXDEEMPH2;
|
|
input TXDEEMPH3;
|
|
input TXUSERCLKIN0;
|
|
input TXUSERCLKIN1;
|
|
input TXUSERCLKIN2;
|
|
input TXUSERCLKIN3;
|
|
input [15:0] DADDR;
|
|
input [15:0] DI;
|
|
input [15:0] MGMTPCSREGADDR;
|
|
input [15:0] MGMTPCSWRDATA;
|
|
input [1:0] RXPOWERDOWN0;
|
|
input [1:0] RXPOWERDOWN1;
|
|
input [1:0] RXPOWERDOWN2;
|
|
input [1:0] RXPOWERDOWN3;
|
|
input [1:0] RXRATE0;
|
|
input [1:0] RXRATE1;
|
|
input [1:0] RXRATE2;
|
|
input [1:0] RXRATE3;
|
|
input [1:0] TXPOWERDOWN0;
|
|
input [1:0] TXPOWERDOWN1;
|
|
input [1:0] TXPOWERDOWN2;
|
|
input [1:0] TXPOWERDOWN3;
|
|
input [1:0] TXRATE0;
|
|
input [1:0] TXRATE1;
|
|
input [1:0] TXRATE2;
|
|
input [1:0] TXRATE3;
|
|
input [2:0] PLLREFCLKSEL;
|
|
input [2:0] SAMPLERATE0;
|
|
input [2:0] SAMPLERATE1;
|
|
input [2:0] SAMPLERATE2;
|
|
input [2:0] SAMPLERATE3;
|
|
input [2:0] TXMARGIN0;
|
|
input [2:0] TXMARGIN1;
|
|
input [2:0] TXMARGIN2;
|
|
input [2:0] TXMARGIN3;
|
|
input [3:0] MGMTPCSLANESEL;
|
|
input [4:0] MGMTPCSMMDADDR;
|
|
input [5:0] PLLPCSCLKDIV;
|
|
input [63:0] TXDATA0;
|
|
input [63:0] TXDATA1;
|
|
input [63:0] TXDATA2;
|
|
input [63:0] TXDATA3;
|
|
input [7:0] TXCTRL0;
|
|
input [7:0] TXCTRL1;
|
|
input [7:0] TXCTRL2;
|
|
input [7:0] TXCTRL3;
|
|
input [7:0] TXDATAMSB0;
|
|
input [7:0] TXDATAMSB1;
|
|
input [7:0] TXDATAMSB2;
|
|
input [7:0] TXDATAMSB3;
|
|
endmodule
|
|
|
|
module GTXE1(COMFINISH, COMINITDET, COMSASDET, COMWAKEDET, DRDY, PHYSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMMADET, RXDATAVALID, RXELECIDLE, RXHEADERVALID, RXOVERSAMPLEERR, RXPLLLKDET, RXPRBSERR, RXRATEDONE, RXRECCLK, RXRECCLKPCS
|
|
, RXRESETDONE, RXSTARTOFSEQ, RXVALID, TXGEARBOXREADY, TXN, TXOUTCLK, TXOUTCLKPCS, TXP, TXPLLLKDET, TXRATEDONE, TXRESETDONE, DRPDO, MGTREFCLKFAB, RXLOSSOFSYNC, TXBUFSTATUS, DFESENSCAL, RXBUFSTATUS, RXCLKCORCNT, RXHEADER, RXSTATUS, RXDATA
|
|
, DFETAP3MONITOR, DFETAP4MONITOR, RXCHARISCOMMA, RXCHARISK, RXCHBONDO, RXDISPERR, RXNOTINTABLE, RXRUNDISP, TXKERR, TXRUNDISP, DFEEYEDACMON, DFETAP1MONITOR, DFETAP2MONITOR, DFECLKDLYADJMON, RXDLYALIGNMONITOR, TXDLYALIGNMONITOR, TSTOUT, DCLK, DEN, DFEDLYOVRD, DFETAPOVRD
|
|
, DWE, GATERXELECIDLE, GREFCLKRX, GREFCLKTX, GTXRXRESET, GTXTXRESET, IGNORESIGDET, PERFCLKRX, PERFCLKTX, PLLRXRESET, PLLTXRESET, PRBSCNTRESET, RXBUFRESET, RXCDRRESET, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETUSE, RXDEC8B10BUSE, RXDLYALIGNDISABLE, RXDLYALIGNMONENB, RXDLYALIGNOVERRIDE
|
|
, RXDLYALIGNRESET, RXDLYALIGNSWPPRECURB, RXDLYALIGNUPDSW, RXENCHANSYNC, RXENMCOMMAALIGN, RXENPCOMMAALIGN, RXENPMAPHASEALIGN, RXENSAMPLEALIGN, RXGEARBOXSLIP, RXN, RXP, RXPLLLKDETEN, RXPLLPOWERDOWN, RXPMASETPHASE, RXPOLARITY, RXRESET, RXSLIDE, RXUSRCLK2, RXUSRCLK, TSTCLK0, TSTCLK1
|
|
, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDLYALIGNDISABLE, TXDLYALIGNMONENB, TXDLYALIGNOVERRIDE, TXDLYALIGNRESET, TXDLYALIGNUPDSW, TXELECIDLE, TXENC8B10BUSE, TXENPMAPHASEALIGN, TXINHIBIT, TXPDOWNASYNCH, TXPLLLKDETEN, TXPLLPOWERDOWN, TXPMASETPHASE, TXPOLARITY, TXPRBSFORCEERR, TXRESET
|
|
, TXSTARTSEQ, TXSWING, TXUSRCLK2, TXUSRCLK, USRCODEERR, GTXTEST, DI, TSTIN, MGTREFCLKRX, MGTREFCLKTX, NORTHREFCLKRX, NORTHREFCLKTX, RXPOWERDOWN, RXRATE, SOUTHREFCLKRX, SOUTHREFCLKTX, TXPOWERDOWN, TXRATE, LOOPBACK, RXCHBONDLEVEL, RXENPRBSTST
|
|
, RXPLLREFSELDY, TXBUFDIFFCTRL, TXENPRBSTST, TXHEADER, TXMARGIN, TXPLLREFSELDY, TXDATA, DFETAP3, DFETAP4, RXCHBONDI, TXBYPASS8B10B, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDIFFCTRL, TXPREEMPHASIS, DFETAP1, DFETAP2, TXPOSTEMPHASIS, DFECLKDLYADJ, TXSEQUENCE
|
|
, DADDR, RXEQMIX);
|
|
parameter AC_CAP_DIS = "TRUE";
|
|
parameter integer ALIGN_COMMA_WORD = 1;
|
|
parameter [1:0] BGTEST_CFG = 2'b00;
|
|
parameter [16:0] BIAS_CFG = 17'h00000;
|
|
parameter [4:0] CDR_PH_ADJ_TIME = 5'b10100;
|
|
parameter integer CHAN_BOND_1_MAX_SKEW = 7;
|
|
parameter integer CHAN_BOND_2_MAX_SKEW = 1;
|
|
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0001001010;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0110111100;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0110111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100111100;
|
|
parameter [4:0] CHAN_BOND_SEQ_2_CFG = 5'b00000;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
|
|
parameter integer CHAN_BOND_SEQ_LEN = 1;
|
|
parameter CLK_CORRECT_USE = "TRUE";
|
|
parameter integer CLK_COR_ADJ_LEN = 1;
|
|
parameter integer CLK_COR_DET_LEN = 1;
|
|
parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE";
|
|
parameter CLK_COR_KEEP_IDLE = "FALSE";
|
|
parameter integer CLK_COR_MAX_LAT = 20;
|
|
parameter integer CLK_COR_MIN_LAT = 18;
|
|
parameter CLK_COR_PRECEDENCE = "TRUE";
|
|
parameter integer CLK_COR_REPEAT_WAIT = 0;
|
|
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CLK_COR_SEQ_2_USE = "FALSE";
|
|
parameter [1:0] CM_TRIM = 2'b01;
|
|
parameter [9:0] COMMA_10B_ENABLE = 10'b1111111111;
|
|
parameter COMMA_DOUBLE = "FALSE";
|
|
parameter [3:0] COM_BURST_VAL = 4'b1111;
|
|
parameter DEC_MCOMMA_DETECT = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY = "TRUE";
|
|
parameter [4:0] DFE_CAL_TIME = 5'b01100;
|
|
parameter [7:0] DFE_CFG = 8'b00011011;
|
|
parameter [2:0] GEARBOX_ENDEC = 3'b000;
|
|
parameter GEN_RXUSRCLK = "TRUE";
|
|
parameter GEN_TXUSRCLK = "TRUE";
|
|
parameter GTX_CFG_PWRUP = "TRUE";
|
|
parameter [9:0] MCOMMA_10B_VALUE = 10'b1010000011;
|
|
parameter MCOMMA_DETECT = "TRUE";
|
|
parameter [2:0] OOBDETECT_THRESHOLD = 3'b011;
|
|
parameter PCI_EXPRESS_MODE = "FALSE";
|
|
parameter [9:0] PCOMMA_10B_VALUE = 10'b0101111100;
|
|
parameter PCOMMA_DETECT = "TRUE";
|
|
parameter PMA_CAS_CLK_EN = "FALSE";
|
|
parameter [26:0] PMA_CDR_SCAN = 27'h640404C;
|
|
parameter [75:0] PMA_CFG = 76'h0040000040000000003;
|
|
parameter [6:0] PMA_RXSYNC_CFG = 7'h00;
|
|
parameter [24:0] PMA_RX_CFG = 25'h05CE048;
|
|
parameter [19:0] PMA_TX_CFG = 20'h00082;
|
|
parameter [9:0] POWER_SAVE = 10'b0000110100;
|
|
parameter RCV_TERM_GND = "FALSE";
|
|
parameter RCV_TERM_VTTRX = "TRUE";
|
|
parameter RXGEARBOX_USE = "FALSE";
|
|
parameter [23:0] RXPLL_COM_CFG = 24'h21680A;
|
|
parameter [7:0] RXPLL_CP_CFG = 8'h00;
|
|
parameter integer RXPLL_DIVSEL45_FB = 5;
|
|
parameter integer RXPLL_DIVSEL_FB = 2;
|
|
parameter integer RXPLL_DIVSEL_OUT = 1;
|
|
parameter integer RXPLL_DIVSEL_REF = 1;
|
|
parameter [2:0] RXPLL_LKDET_CFG = 3'b111;
|
|
parameter [0:0] RXPRBSERR_LOOPBACK = 1'b0;
|
|
parameter RXRECCLK_CTRL = "RXRECCLKPCS";
|
|
parameter [9:0] RXRECCLK_DLY = 10'b0000000000;
|
|
parameter [15:0] RXUSRCLK_DLY = 16'h0000;
|
|
parameter RX_BUFFER_USE = "TRUE";
|
|
parameter integer RX_CLK25_DIVIDER = 6;
|
|
parameter integer RX_DATA_WIDTH = 20;
|
|
parameter RX_DECODE_SEQ_MATCH = "TRUE";
|
|
parameter [3:0] RX_DLYALIGN_CTRINC = 4'b0100;
|
|
parameter [4:0] RX_DLYALIGN_EDGESET = 5'b00110;
|
|
parameter [3:0] RX_DLYALIGN_LPFINC = 4'b0111;
|
|
parameter [2:0] RX_DLYALIGN_MONSEL = 3'b000;
|
|
parameter [7:0] RX_DLYALIGN_OVRDSETTING = 8'b00000000;
|
|
parameter RX_EN_IDLE_HOLD_CDR = "FALSE";
|
|
parameter RX_EN_IDLE_HOLD_DFE = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_BUF = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_FR = "TRUE";
|
|
parameter RX_EN_IDLE_RESET_PH = "TRUE";
|
|
parameter RX_EN_MODE_RESET_BUF = "TRUE";
|
|
parameter RX_EN_RATE_RESET_BUF = "TRUE";
|
|
parameter RX_EN_REALIGN_RESET_BUF = "FALSE";
|
|
parameter RX_EN_REALIGN_RESET_BUF2 = "FALSE";
|
|
parameter [7:0] RX_EYE_OFFSET = 8'h4C;
|
|
parameter [1:0] RX_EYE_SCANMODE = 2'b00;
|
|
parameter RX_FIFO_ADDR_MODE = "FULL";
|
|
parameter [3:0] RX_IDLE_HI_CNT = 4'b1000;
|
|
parameter [3:0] RX_IDLE_LO_CNT = 4'b0000;
|
|
parameter RX_LOSS_OF_SYNC_FSM = "FALSE";
|
|
parameter integer RX_LOS_INVALID_INCR = 1;
|
|
parameter integer RX_LOS_THRESHOLD = 4;
|
|
parameter RX_OVERSAMPLE_MODE = "FALSE";
|
|
parameter integer RX_SLIDE_AUTO_WAIT = 5;
|
|
parameter RX_SLIDE_MODE = "OFF";
|
|
parameter RX_XCLK_SEL = "RXREC";
|
|
parameter integer SAS_MAX_COMSAS = 52;
|
|
parameter integer SAS_MIN_COMSAS = 40;
|
|
parameter [2:0] SATA_BURST_VAL = 3'b100;
|
|
parameter [2:0] SATA_IDLE_VAL = 3'b100;
|
|
parameter integer SATA_MAX_BURST = 7;
|
|
parameter integer SATA_MAX_INIT = 22;
|
|
parameter integer SATA_MAX_WAKE = 7;
|
|
parameter integer SATA_MIN_BURST = 4;
|
|
parameter integer SATA_MIN_INIT = 12;
|
|
parameter integer SATA_MIN_WAKE = 4;
|
|
parameter SHOW_REALIGN_COMMA = "TRUE";
|
|
parameter integer SIM_GTXRESET_SPEEDUP = 1;
|
|
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
|
|
parameter [2:0] SIM_RXREFCLK_SOURCE = 3'b000;
|
|
parameter [2:0] SIM_TXREFCLK_SOURCE = 3'b000;
|
|
parameter SIM_TX_ELEC_IDLE_LEVEL = "X";
|
|
parameter SIM_VERSION = "2.0";
|
|
parameter [4:0] TERMINATION_CTRL = 5'b10100;
|
|
parameter TERMINATION_OVRD = "FALSE";
|
|
parameter [11:0] TRANS_TIME_FROM_P2 = 12'h03C;
|
|
parameter [7:0] TRANS_TIME_NON_P2 = 8'h19;
|
|
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
|
|
parameter [9:0] TRANS_TIME_TO_P2 = 10'h064;
|
|
parameter [31:0] TST_ATTR = 32'h00000000;
|
|
parameter TXDRIVE_LOOPBACK_HIZ = "FALSE";
|
|
parameter TXDRIVE_LOOPBACK_PD = "FALSE";
|
|
parameter TXGEARBOX_USE = "FALSE";
|
|
parameter TXOUTCLK_CTRL = "TXOUTCLKPCS";
|
|
parameter [9:0] TXOUTCLK_DLY = 10'b0000000000;
|
|
parameter [23:0] TXPLL_COM_CFG = 24'h21680A;
|
|
parameter [7:0] TXPLL_CP_CFG = 8'h00;
|
|
parameter integer TXPLL_DIVSEL45_FB = 5;
|
|
parameter integer TXPLL_DIVSEL_FB = 2;
|
|
parameter integer TXPLL_DIVSEL_OUT = 1;
|
|
parameter integer TXPLL_DIVSEL_REF = 1;
|
|
parameter [2:0] TXPLL_LKDET_CFG = 3'b111;
|
|
parameter [1:0] TXPLL_SATA = 2'b00;
|
|
parameter TX_BUFFER_USE = "TRUE";
|
|
parameter [5:0] TX_BYTECLK_CFG = 6'h00;
|
|
parameter integer TX_CLK25_DIVIDER = 6;
|
|
parameter TX_CLK_SOURCE = "RXPLL";
|
|
parameter integer TX_DATA_WIDTH = 20;
|
|
parameter [4:0] TX_DEEMPH_0 = 5'b11010;
|
|
parameter [4:0] TX_DEEMPH_1 = 5'b10000;
|
|
parameter [13:0] TX_DETECT_RX_CFG = 14'h1832;
|
|
parameter [3:0] TX_DLYALIGN_CTRINC = 4'b0100;
|
|
parameter [3:0] TX_DLYALIGN_LPFINC = 4'b0110;
|
|
parameter [2:0] TX_DLYALIGN_MONSEL = 3'b000;
|
|
parameter [7:0] TX_DLYALIGN_OVRDSETTING = 8'b10000000;
|
|
parameter TX_DRIVE_MODE = "DIRECT";
|
|
parameter TX_EN_RATE_RESET_BUF = "TRUE";
|
|
parameter [2:0] TX_IDLE_ASSERT_DELAY = 3'b100;
|
|
parameter [2:0] TX_IDLE_DEASSERT_DELAY = 3'b010;
|
|
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
|
|
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
|
|
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
|
|
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
|
|
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
|
|
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
|
|
parameter TX_OVERSAMPLE_MODE = "FALSE";
|
|
parameter [0:0] TX_PMADATA_OPT = 1'b0;
|
|
parameter [1:0] TX_TDCC_CFG = 2'b11;
|
|
parameter [5:0] TX_USRCLK_CFG = 6'h00;
|
|
parameter TX_XCLK_SEL = "TXUSR";
|
|
output COMFINISH;
|
|
output COMINITDET;
|
|
output COMSASDET;
|
|
output COMWAKEDET;
|
|
output DRDY;
|
|
output PHYSTATUS;
|
|
output RXBYTEISALIGNED;
|
|
output RXBYTEREALIGN;
|
|
output RXCHANBONDSEQ;
|
|
output RXCHANISALIGNED;
|
|
output RXCHANREALIGN;
|
|
output RXCOMMADET;
|
|
output RXDATAVALID;
|
|
output RXELECIDLE;
|
|
output RXHEADERVALID;
|
|
output RXOVERSAMPLEERR;
|
|
output RXPLLLKDET;
|
|
output RXPRBSERR;
|
|
output RXRATEDONE;
|
|
output RXRECCLK;
|
|
output RXRECCLKPCS;
|
|
output RXRESETDONE;
|
|
output RXSTARTOFSEQ;
|
|
output RXVALID;
|
|
output TXGEARBOXREADY;
|
|
output TXN;
|
|
output TXOUTCLK;
|
|
output TXOUTCLKPCS;
|
|
output TXP;
|
|
output TXPLLLKDET;
|
|
output TXRATEDONE;
|
|
output TXRESETDONE;
|
|
output [15:0] DRPDO;
|
|
output [1:0] MGTREFCLKFAB;
|
|
output [1:0] RXLOSSOFSYNC;
|
|
output [1:0] TXBUFSTATUS;
|
|
output [2:0] DFESENSCAL;
|
|
output [2:0] RXBUFSTATUS;
|
|
output [2:0] RXCLKCORCNT;
|
|
output [2:0] RXHEADER;
|
|
output [2:0] RXSTATUS;
|
|
output [31:0] RXDATA;
|
|
output [3:0] DFETAP3MONITOR;
|
|
output [3:0] DFETAP4MONITOR;
|
|
output [3:0] RXCHARISCOMMA;
|
|
output [3:0] RXCHARISK;
|
|
output [3:0] RXCHBONDO;
|
|
output [3:0] RXDISPERR;
|
|
output [3:0] RXNOTINTABLE;
|
|
output [3:0] RXRUNDISP;
|
|
output [3:0] TXKERR;
|
|
output [3:0] TXRUNDISP;
|
|
output [4:0] DFEEYEDACMON;
|
|
output [4:0] DFETAP1MONITOR;
|
|
output [4:0] DFETAP2MONITOR;
|
|
output [5:0] DFECLKDLYADJMON;
|
|
output [7:0] RXDLYALIGNMONITOR;
|
|
output [7:0] TXDLYALIGNMONITOR;
|
|
output [9:0] TSTOUT;
|
|
input DCLK;
|
|
input DEN;
|
|
input DFEDLYOVRD;
|
|
input DFETAPOVRD;
|
|
input DWE;
|
|
input GATERXELECIDLE;
|
|
input GREFCLKRX;
|
|
input GREFCLKTX;
|
|
input GTXRXRESET;
|
|
input GTXTXRESET;
|
|
input IGNORESIGDET;
|
|
input PERFCLKRX;
|
|
input PERFCLKTX;
|
|
input PLLRXRESET;
|
|
input PLLTXRESET;
|
|
input PRBSCNTRESET;
|
|
input RXBUFRESET;
|
|
input RXCDRRESET;
|
|
input RXCHBONDMASTER;
|
|
input RXCHBONDSLAVE;
|
|
input RXCOMMADETUSE;
|
|
input RXDEC8B10BUSE;
|
|
input RXDLYALIGNDISABLE;
|
|
input RXDLYALIGNMONENB;
|
|
input RXDLYALIGNOVERRIDE;
|
|
input RXDLYALIGNRESET;
|
|
input RXDLYALIGNSWPPRECURB;
|
|
input RXDLYALIGNUPDSW;
|
|
input RXENCHANSYNC;
|
|
input RXENMCOMMAALIGN;
|
|
input RXENPCOMMAALIGN;
|
|
input RXENPMAPHASEALIGN;
|
|
input RXENSAMPLEALIGN;
|
|
input RXGEARBOXSLIP;
|
|
input RXN;
|
|
input RXP;
|
|
input RXPLLLKDETEN;
|
|
input RXPLLPOWERDOWN;
|
|
input RXPMASETPHASE;
|
|
input RXPOLARITY;
|
|
input RXRESET;
|
|
input RXSLIDE;
|
|
input RXUSRCLK2;
|
|
input RXUSRCLK;
|
|
input TSTCLK0;
|
|
input TSTCLK1;
|
|
input TXCOMINIT;
|
|
input TXCOMSAS;
|
|
input TXCOMWAKE;
|
|
input TXDEEMPH;
|
|
input TXDETECTRX;
|
|
input TXDLYALIGNDISABLE;
|
|
input TXDLYALIGNMONENB;
|
|
input TXDLYALIGNOVERRIDE;
|
|
input TXDLYALIGNRESET;
|
|
input TXDLYALIGNUPDSW;
|
|
input TXELECIDLE;
|
|
input TXENC8B10BUSE;
|
|
input TXENPMAPHASEALIGN;
|
|
input TXINHIBIT;
|
|
input TXPDOWNASYNCH;
|
|
input TXPLLLKDETEN;
|
|
input TXPLLPOWERDOWN;
|
|
input TXPMASETPHASE;
|
|
input TXPOLARITY;
|
|
input TXPRBSFORCEERR;
|
|
input TXRESET;
|
|
input TXSTARTSEQ;
|
|
input TXSWING;
|
|
input TXUSRCLK2;
|
|
input TXUSRCLK;
|
|
input USRCODEERR;
|
|
input [12:0] GTXTEST;
|
|
input [15:0] DI;
|
|
input [19:0] TSTIN;
|
|
input [1:0] MGTREFCLKRX;
|
|
input [1:0] MGTREFCLKTX;
|
|
input [1:0] NORTHREFCLKRX;
|
|
input [1:0] NORTHREFCLKTX;
|
|
input [1:0] RXPOWERDOWN;
|
|
input [1:0] RXRATE;
|
|
input [1:0] SOUTHREFCLKRX;
|
|
input [1:0] SOUTHREFCLKTX;
|
|
input [1:0] TXPOWERDOWN;
|
|
input [1:0] TXRATE;
|
|
input [2:0] LOOPBACK;
|
|
input [2:0] RXCHBONDLEVEL;
|
|
input [2:0] RXENPRBSTST;
|
|
input [2:0] RXPLLREFSELDY;
|
|
input [2:0] TXBUFDIFFCTRL;
|
|
input [2:0] TXENPRBSTST;
|
|
input [2:0] TXHEADER;
|
|
input [2:0] TXMARGIN;
|
|
input [2:0] TXPLLREFSELDY;
|
|
input [31:0] TXDATA;
|
|
input [3:0] DFETAP3;
|
|
input [3:0] DFETAP4;
|
|
input [3:0] RXCHBONDI;
|
|
input [3:0] TXBYPASS8B10B;
|
|
input [3:0] TXCHARDISPMODE;
|
|
input [3:0] TXCHARDISPVAL;
|
|
input [3:0] TXCHARISK;
|
|
input [3:0] TXDIFFCTRL;
|
|
input [3:0] TXPREEMPHASIS;
|
|
input [4:0] DFETAP1;
|
|
input [4:0] DFETAP2;
|
|
input [4:0] TXPOSTEMPHASIS;
|
|
input [5:0] DFECLKDLYADJ;
|
|
input [6:0] TXSEQUENCE;
|
|
input [7:0] DADDR;
|
|
input [9:0] RXEQMIX;
|
|
endmodule
|
|
|
|
module IBUFDS_GTXE1(O, ODIV2, CEB, I, IB);
|
|
parameter CLKCM_CFG = "TRUE";
|
|
parameter CLKRCV_TRST = "TRUE";
|
|
parameter [9:0] REFCLKOUT_DLY = 10'b0000000000;
|
|
output O;
|
|
output ODIV2;
|
|
input CEB;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module IBUFDS_GTHE1(O, I, IB);
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module GTHE2_CHANNEL(CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DRPRDY, EYESCANDATAERROR, GTHTXN, GTHTXP, GTREFCLKMONITOR, PHYSTATUS, RSOSINTDONE, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDFESLIDETAPSTARTED
|
|
, RXDFESLIDETAPSTROBEDONE, RXDFESLIDETAPSTROBESTARTED, RXDFESTADAPTDONE, RXDLYSRESETDONE, RXELECIDLE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPMARESETDONE, RXPRBSERR, RXQPISENN, RXQPISENP, RXRATEDONE, RXRESETDONE, RXSYNCDONE, RXSYNCOUT, RXVALID
|
|
, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, DMONITOROUT, DRPDO, PCSRSVDOUT, RXCLKCORCNT, RXDATAVALID, RXHEADERVALID
|
|
, RXSTARTOFSEQ, TXBUFSTATUS, RXBUFSTATUS, RXSTATUS, RXCHBONDO, RXPHMONITOR, RXPHSLIPMONITOR, RXHEADER, RXDATA, RXMONITOROUT, RXCHARISCOMMA, RXCHARISK, RXDISPERR, RXNOTINTABLE, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLRESET
|
|
, DMONFIFORESET, DMONITORCLK, DRPCLK, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTHRXN, GTHRXP, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, QPLLCLK
|
|
, QPLLREFCLK, RESETOVRD, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFECM1EN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFESLIDETAPADAPTEN
|
|
, RXDFESLIDETAPHOLD, RXDFESLIDETAPINITOVRDEN, RXDFESLIDETAPONLYADAPTEN, RXDFESLIDETAPOVRDEN, RXDFESLIDETAPSTROBE, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN
|
|
, RXDFEVSEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXGEARBOXSLIP, RXLPMEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXMCOMMAALIGNEN, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTEN, RXOSINTHOLD, RXOSINTNTRLEN, RXOSINTOVRDEN, RXOSINTSTROBE
|
|
, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXPCOMMAALIGNEN, RXPCSRESET, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXQPIEN, RXRATEMODE, RXSLIDE, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXUSERRDY, RXUSRCLK2, RXUSRCLK
|
|
, SETERRSTATUS, SIGVALIDCLK, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXINHIBIT, TXPCSRESET, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN
|
|
, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRECURSORINV, TXQPIBIASEN, TXQPISTRONGPDOWN, TXQPIWEAKPUP, TXRATEMODE, TXSTARTSEQ, TXSWING
|
|
, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXUSERRDY, TXUSRCLK2, TXUSRCLK, RXADAPTSELTEST, DRPDI, GTRSVD, PCSRSVDIN, TSTIN, RXELECIDLEMODE, RXMONITORSEL, RXPD, RXSYSCLKSEL, TXPD, TXSYSCLKSEL, CPLLREFCLKSEL, LOOPBACK, RXCHBONDLEVEL, RXOUTCLKSEL
|
|
, RXPRBSSEL, RXRATE, TXBUFDIFFCTRL, TXHEADER, TXMARGIN, TXOUTCLKSEL, TXPRBSSEL, TXRATE, RXOSINTCFG, RXOSINTID0, TXDIFFCTRL, PCSRSVDIN2, PMARSVDIN, RXCHBONDI, RXDFEAGCTRL, RXDFESLIDETAP, TXPIPPMSTEPSIZE, TXPOSTCURSOR, TXPRECURSOR, RXDFESLIDETAPID, TXDATA
|
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, TXMAINCURSOR, TXSEQUENCE, TX8B10BBYPASS, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, DRPADDR);
|
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parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_RESET = 1'b0;
|
|
parameter [19:0] ADAPT_CFG0 = 20'h00C10;
|
|
parameter ALIGN_COMMA_DOUBLE = "FALSE";
|
|
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
|
|
parameter integer ALIGN_COMMA_WORD = 1;
|
|
parameter ALIGN_MCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
|
|
parameter ALIGN_PCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
|
|
parameter [0:0] A_RXOSCALRESET = 1'b0;
|
|
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
|
|
parameter [41:0] CFOK_CFG = 42'h24800040E80;
|
|
parameter [5:0] CFOK_CFG2 = 6'b100000;
|
|
parameter [5:0] CFOK_CFG3 = 6'b100000;
|
|
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
|
|
parameter integer CHAN_BOND_MAX_SKEW = 7;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
|
|
parameter integer CHAN_BOND_SEQ_LEN = 1;
|
|
parameter CLK_CORRECT_USE = "TRUE";
|
|
parameter CLK_COR_KEEP_IDLE = "FALSE";
|
|
parameter integer CLK_COR_MAX_LAT = 20;
|
|
parameter integer CLK_COR_MIN_LAT = 18;
|
|
parameter CLK_COR_PRECEDENCE = "TRUE";
|
|
parameter integer CLK_COR_REPEAT_WAIT = 0;
|
|
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CLK_COR_SEQ_2_USE = "FALSE";
|
|
parameter integer CLK_COR_SEQ_LEN = 1;
|
|
parameter [28:0] CPLL_CFG = 29'h00BC07DC;
|
|
parameter integer CPLL_FBDIV = 4;
|
|
parameter integer CPLL_FBDIV_45 = 5;
|
|
parameter [23:0] CPLL_INIT_CFG = 24'h00001E;
|
|
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
|
|
parameter integer CPLL_REFCLK_DIV = 1;
|
|
parameter DEC_MCOMMA_DETECT = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY = "TRUE";
|
|
parameter [23:0] DMONITOR_CFG = 24'h000A00;
|
|
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
|
|
parameter [5:0] ES_CONTROL = 6'b000000;
|
|
parameter ES_ERRDET_EN = "FALSE";
|
|
parameter ES_EYE_SCAN_EN = "TRUE";
|
|
parameter [11:0] ES_HORZ_OFFSET = 12'h000;
|
|
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
|
|
parameter [4:0] ES_PRESCALE = 5'b00000;
|
|
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
|
|
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
|
|
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
|
|
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
|
|
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
|
|
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
|
|
parameter FTS_LANE_DESKEW_EN = "FALSE";
|
|
parameter [2:0] GEARBOX_MODE = 3'b000;
|
|
parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
|
|
parameter [0:0] LOOPBACK_CFG = 1'b0;
|
|
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
|
|
parameter PCS_PCIE_EN = "FALSE";
|
|
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
|
|
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
|
|
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
|
|
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
|
|
parameter [31:0] PMA_RSV = 32'b00000000000000000000000010000000;
|
|
parameter [31:0] PMA_RSV2 = 32'b00011100000000000000000000001010;
|
|
parameter [1:0] PMA_RSV3 = 2'b00;
|
|
parameter [14:0] PMA_RSV4 = 15'b000000000001000;
|
|
parameter [3:0] PMA_RSV5 = 4'b0000;
|
|
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
|
|
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
|
|
parameter RXBUF_ADDR_MODE = "FULL";
|
|
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
|
|
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
|
|
parameter RXBUF_EN = "TRUE";
|
|
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
|
|
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
|
|
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
|
|
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
|
|
parameter integer RXBUF_THRESH_OVFLW = 61;
|
|
parameter RXBUF_THRESH_OVRD = "FALSE";
|
|
parameter integer RXBUF_THRESH_UNDFLW = 4;
|
|
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
|
|
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
|
|
parameter [82:0] RXCDR_CFG = 83'h0002007FE2000C208001A;
|
|
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
|
|
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
|
|
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
|
|
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
|
|
parameter [15:0] RXDLY_CFG = 16'h001F;
|
|
parameter [8:0] RXDLY_LCFG = 9'h030;
|
|
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
|
|
parameter RXGEARBOX_EN = "FALSE";
|
|
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
|
|
parameter [13:0] RXLPM_HF_CFG = 14'b00001000000000;
|
|
parameter [17:0] RXLPM_LF_CFG = 18'b001001000000000000;
|
|
parameter [6:0] RXOOB_CFG = 7'b0000110;
|
|
parameter RXOOB_CLK_CFG = "PMA";
|
|
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
|
|
parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
|
|
parameter integer RXOUT_DIV = 2;
|
|
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
|
|
parameter [23:0] RXPHDLY_CFG = 24'h084020;
|
|
parameter [23:0] RXPH_CFG = 24'hC00002;
|
|
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [1:0] RXPI_CFG0 = 2'b00;
|
|
parameter [1:0] RXPI_CFG1 = 2'b00;
|
|
parameter [1:0] RXPI_CFG2 = 2'b00;
|
|
parameter [1:0] RXPI_CFG3 = 2'b00;
|
|
parameter [0:0] RXPI_CFG4 = 1'b0;
|
|
parameter [0:0] RXPI_CFG5 = 1'b0;
|
|
parameter [2:0] RXPI_CFG6 = 3'b100;
|
|
parameter [4:0] RXPMARESET_TIME = 5'b00011;
|
|
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
|
|
parameter integer RXSLIDE_AUTO_WAIT = 7;
|
|
parameter RXSLIDE_MODE = "OFF";
|
|
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] RXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
|
|
parameter [23:0] RX_BIAS_CFG = 24'b000011000000000000010000;
|
|
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
|
|
parameter integer RX_CLK25_DIV = 7;
|
|
parameter [0:0] RX_CLKMUX_PD = 1'b1;
|
|
parameter [1:0] RX_CM_SEL = 2'b11;
|
|
parameter [3:0] RX_CM_TRIM = 4'b0100;
|
|
parameter integer RX_DATA_WIDTH = 20;
|
|
parameter [5:0] RX_DDI_SEL = 6'b000000;
|
|
parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
|
|
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
|
|
parameter [3:0] RX_DFELPM_CFG0 = 4'b0110;
|
|
parameter [0:0] RX_DFELPM_CFG1 = 1'b0;
|
|
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
|
|
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
|
|
parameter [2:0] RX_DFE_AGC_CFG1 = 3'b010;
|
|
parameter [3:0] RX_DFE_AGC_CFG2 = 4'b0000;
|
|
parameter [0:0] RX_DFE_AGC_OVRDEN = 1'b1;
|
|
parameter [22:0] RX_DFE_GAIN_CFG = 23'h0020C0;
|
|
parameter [11:0] RX_DFE_H2_CFG = 12'b000000000000;
|
|
parameter [11:0] RX_DFE_H3_CFG = 12'b000001000000;
|
|
parameter [10:0] RX_DFE_H4_CFG = 11'b00011100000;
|
|
parameter [10:0] RX_DFE_H5_CFG = 11'b00011100000;
|
|
parameter [10:0] RX_DFE_H6_CFG = 11'b00000100000;
|
|
parameter [10:0] RX_DFE_H7_CFG = 11'b00000100000;
|
|
parameter [32:0] RX_DFE_KL_CFG = 33'b000000000000000000000001100010000;
|
|
parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01;
|
|
parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010;
|
|
parameter [3:0] RX_DFE_KL_LPM_KH_CFG2 = 4'b0010;
|
|
parameter [0:0] RX_DFE_KL_LPM_KH_OVRDEN = 1'b1;
|
|
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b10;
|
|
parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010;
|
|
parameter [3:0] RX_DFE_KL_LPM_KL_CFG2 = 4'b0010;
|
|
parameter [0:0] RX_DFE_KL_LPM_KL_OVRDEN = 1'b1;
|
|
parameter [15:0] RX_DFE_LPM_CFG = 16'h0080;
|
|
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [53:0] RX_DFE_ST_CFG = 54'h00E100000C003F;
|
|
parameter [16:0] RX_DFE_UT_CFG = 17'b00011100000000000;
|
|
parameter [16:0] RX_DFE_VP_CFG = 17'b00011101010100011;
|
|
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
|
|
parameter integer RX_INT_DATAWIDTH = 0;
|
|
parameter [12:0] RX_OS_CFG = 13'b0000010000000;
|
|
parameter integer RX_SIG_VALID_DLY = 10;
|
|
parameter RX_XCLK_SEL = "RXREC";
|
|
parameter integer SAS_MAX_COM = 64;
|
|
parameter integer SAS_MIN_COM = 36;
|
|
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
|
|
parameter [2:0] SATA_BURST_VAL = 3'b100;
|
|
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
|
|
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
|
|
parameter integer SATA_MAX_BURST = 8;
|
|
parameter integer SATA_MAX_INIT = 21;
|
|
parameter integer SATA_MAX_WAKE = 7;
|
|
parameter integer SATA_MIN_BURST = 4;
|
|
parameter integer SATA_MIN_INIT = 12;
|
|
parameter integer SATA_MIN_WAKE = 4;
|
|
parameter SHOW_REALIGN_COMMA = "TRUE";
|
|
parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001;
|
|
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
|
|
parameter SIM_VERSION = "1.1";
|
|
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
|
|
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
|
|
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
|
|
parameter [31:0] TST_RSV = 32'h00000000;
|
|
parameter TXBUF_EN = "TRUE";
|
|
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
|
|
parameter [15:0] TXDLY_CFG = 16'h001F;
|
|
parameter [8:0] TXDLY_LCFG = 9'h030;
|
|
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
|
|
parameter TXGEARBOX_EN = "FALSE";
|
|
parameter [0:0] TXOOB_CFG = 1'b0;
|
|
parameter integer TXOUT_DIV = 2;
|
|
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
|
|
parameter [23:0] TXPHDLY_CFG = 24'h084020;
|
|
parameter [15:0] TXPH_CFG = 16'h0780;
|
|
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [1:0] TXPI_CFG0 = 2'b00;
|
|
parameter [1:0] TXPI_CFG1 = 2'b00;
|
|
parameter [1:0] TXPI_CFG2 = 2'b00;
|
|
parameter [0:0] TXPI_CFG3 = 1'b0;
|
|
parameter [0:0] TXPI_CFG4 = 1'b0;
|
|
parameter [2:0] TXPI_CFG5 = 3'b100;
|
|
parameter [0:0] TXPI_GREY_SEL = 1'b0;
|
|
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
|
|
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
|
|
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
|
|
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
|
|
parameter [4:0] TXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] TXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
|
|
parameter integer TX_CLK25_DIV = 7;
|
|
parameter [0:0] TX_CLKMUX_PD = 1'b1;
|
|
parameter integer TX_DATA_WIDTH = 20;
|
|
parameter [5:0] TX_DEEMPH0 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH1 = 6'b000000;
|
|
parameter TX_DRIVE_MODE = "DIRECT";
|
|
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
|
|
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
|
|
parameter integer TX_INT_DATAWIDTH = 0;
|
|
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
|
|
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
|
|
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
|
|
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
|
|
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
|
|
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
|
|
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
|
|
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
|
|
parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
|
|
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
|
|
parameter [16:0] TX_RXDETECT_PRECHARGE_TIME = 17'h00000;
|
|
parameter [2:0] TX_RXDETECT_REF = 3'b100;
|
|
parameter TX_XCLK_SEL = "TXUSR";
|
|
parameter [0:0] UCODEER_CLR = 1'b0;
|
|
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
|
|
output CPLLFBCLKLOST;
|
|
output CPLLLOCK;
|
|
output CPLLREFCLKLOST;
|
|
output DRPRDY;
|
|
output EYESCANDATAERROR;
|
|
output GTHTXN;
|
|
output GTHTXP;
|
|
output GTREFCLKMONITOR;
|
|
output PHYSTATUS;
|
|
output RSOSINTDONE;
|
|
output RXBYTEISALIGNED;
|
|
output RXBYTEREALIGN;
|
|
output RXCDRLOCK;
|
|
output RXCHANBONDSEQ;
|
|
output RXCHANISALIGNED;
|
|
output RXCHANREALIGN;
|
|
output RXCOMINITDET;
|
|
output RXCOMMADET;
|
|
output RXCOMSASDET;
|
|
output RXCOMWAKEDET;
|
|
output RXDFESLIDETAPSTARTED;
|
|
output RXDFESLIDETAPSTROBEDONE;
|
|
output RXDFESLIDETAPSTROBESTARTED;
|
|
output RXDFESTADAPTDONE;
|
|
output RXDLYSRESETDONE;
|
|
output RXELECIDLE;
|
|
output RXOSINTSTARTED;
|
|
output RXOSINTSTROBEDONE;
|
|
output RXOSINTSTROBESTARTED;
|
|
output RXOUTCLK;
|
|
output RXOUTCLKFABRIC;
|
|
output RXOUTCLKPCS;
|
|
output RXPHALIGNDONE;
|
|
output RXPMARESETDONE;
|
|
output RXPRBSERR;
|
|
output RXQPISENN;
|
|
output RXQPISENP;
|
|
output RXRATEDONE;
|
|
output RXRESETDONE;
|
|
output RXSYNCDONE;
|
|
output RXSYNCOUT;
|
|
output RXVALID;
|
|
output TXCOMFINISH;
|
|
output TXDLYSRESETDONE;
|
|
output TXGEARBOXREADY;
|
|
output TXOUTCLK;
|
|
output TXOUTCLKFABRIC;
|
|
output TXOUTCLKPCS;
|
|
output TXPHALIGNDONE;
|
|
output TXPHINITDONE;
|
|
output TXPMARESETDONE;
|
|
output TXQPISENN;
|
|
output TXQPISENP;
|
|
output TXRATEDONE;
|
|
output TXRESETDONE;
|
|
output TXSYNCDONE;
|
|
output TXSYNCOUT;
|
|
output [14:0] DMONITOROUT;
|
|
output [15:0] DRPDO;
|
|
output [15:0] PCSRSVDOUT;
|
|
output [1:0] RXCLKCORCNT;
|
|
output [1:0] RXDATAVALID;
|
|
output [1:0] RXHEADERVALID;
|
|
output [1:0] RXSTARTOFSEQ;
|
|
output [1:0] TXBUFSTATUS;
|
|
output [2:0] RXBUFSTATUS;
|
|
output [2:0] RXSTATUS;
|
|
output [4:0] RXCHBONDO;
|
|
output [4:0] RXPHMONITOR;
|
|
output [4:0] RXPHSLIPMONITOR;
|
|
output [5:0] RXHEADER;
|
|
output [63:0] RXDATA;
|
|
output [6:0] RXMONITOROUT;
|
|
output [7:0] RXCHARISCOMMA;
|
|
output [7:0] RXCHARISK;
|
|
output [7:0] RXDISPERR;
|
|
output [7:0] RXNOTINTABLE;
|
|
input CFGRESET;
|
|
(* invertible_pin = "IS_CLKRSVD0_INVERTED" *)
|
|
input CLKRSVD0;
|
|
(* invertible_pin = "IS_CLKRSVD1_INVERTED" *)
|
|
input CLKRSVD1;
|
|
(* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *)
|
|
input CPLLLOCKDETCLK;
|
|
input CPLLLOCKEN;
|
|
input CPLLPD;
|
|
input CPLLRESET;
|
|
input DMONFIFORESET;
|
|
(* invertible_pin = "IS_DMONITORCLK_INVERTED" *)
|
|
input DMONITORCLK;
|
|
(* invertible_pin = "IS_DRPCLK_INVERTED" *)
|
|
input DRPCLK;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input EYESCANMODE;
|
|
input EYESCANRESET;
|
|
input EYESCANTRIGGER;
|
|
(* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
|
|
input GTGREFCLK;
|
|
input GTHRXN;
|
|
input GTHRXP;
|
|
input GTNORTHREFCLK0;
|
|
input GTNORTHREFCLK1;
|
|
input GTREFCLK0;
|
|
input GTREFCLK1;
|
|
input GTRESETSEL;
|
|
input GTRXRESET;
|
|
input GTSOUTHREFCLK0;
|
|
input GTSOUTHREFCLK1;
|
|
input GTTXRESET;
|
|
input QPLLCLK;
|
|
input QPLLREFCLK;
|
|
input RESETOVRD;
|
|
input RX8B10BEN;
|
|
input RXBUFRESET;
|
|
input RXCDRFREQRESET;
|
|
input RXCDRHOLD;
|
|
input RXCDROVRDEN;
|
|
input RXCDRRESET;
|
|
input RXCDRRESETRSV;
|
|
input RXCHBONDEN;
|
|
input RXCHBONDMASTER;
|
|
input RXCHBONDSLAVE;
|
|
input RXCOMMADETEN;
|
|
input RXDDIEN;
|
|
input RXDFEAGCHOLD;
|
|
input RXDFEAGCOVRDEN;
|
|
input RXDFECM1EN;
|
|
input RXDFELFHOLD;
|
|
input RXDFELFOVRDEN;
|
|
input RXDFELPMRESET;
|
|
input RXDFESLIDETAPADAPTEN;
|
|
input RXDFESLIDETAPHOLD;
|
|
input RXDFESLIDETAPINITOVRDEN;
|
|
input RXDFESLIDETAPONLYADAPTEN;
|
|
input RXDFESLIDETAPOVRDEN;
|
|
input RXDFESLIDETAPSTROBE;
|
|
input RXDFETAP2HOLD;
|
|
input RXDFETAP2OVRDEN;
|
|
input RXDFETAP3HOLD;
|
|
input RXDFETAP3OVRDEN;
|
|
input RXDFETAP4HOLD;
|
|
input RXDFETAP4OVRDEN;
|
|
input RXDFETAP5HOLD;
|
|
input RXDFETAP5OVRDEN;
|
|
input RXDFETAP6HOLD;
|
|
input RXDFETAP6OVRDEN;
|
|
input RXDFETAP7HOLD;
|
|
input RXDFETAP7OVRDEN;
|
|
input RXDFEUTHOLD;
|
|
input RXDFEUTOVRDEN;
|
|
input RXDFEVPHOLD;
|
|
input RXDFEVPOVRDEN;
|
|
input RXDFEVSEN;
|
|
input RXDFEXYDEN;
|
|
input RXDLYBYPASS;
|
|
input RXDLYEN;
|
|
input RXDLYOVRDEN;
|
|
input RXDLYSRESET;
|
|
input RXGEARBOXSLIP;
|
|
input RXLPMEN;
|
|
input RXLPMHFHOLD;
|
|
input RXLPMHFOVRDEN;
|
|
input RXLPMLFHOLD;
|
|
input RXLPMLFKLOVRDEN;
|
|
input RXMCOMMAALIGNEN;
|
|
input RXOOBRESET;
|
|
input RXOSCALRESET;
|
|
input RXOSHOLD;
|
|
input RXOSINTEN;
|
|
input RXOSINTHOLD;
|
|
input RXOSINTNTRLEN;
|
|
input RXOSINTOVRDEN;
|
|
input RXOSINTSTROBE;
|
|
input RXOSINTTESTOVRDEN;
|
|
input RXOSOVRDEN;
|
|
input RXPCOMMAALIGNEN;
|
|
input RXPCSRESET;
|
|
input RXPHALIGN;
|
|
input RXPHALIGNEN;
|
|
input RXPHDLYPD;
|
|
input RXPHDLYRESET;
|
|
input RXPHOVRDEN;
|
|
input RXPMARESET;
|
|
input RXPOLARITY;
|
|
input RXPRBSCNTRESET;
|
|
input RXQPIEN;
|
|
input RXRATEMODE;
|
|
input RXSLIDE;
|
|
input RXSYNCALLIN;
|
|
input RXSYNCIN;
|
|
input RXSYNCMODE;
|
|
input RXUSERRDY;
|
|
(* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
|
|
input RXUSRCLK2;
|
|
(* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
|
|
input RXUSRCLK;
|
|
input SETERRSTATUS;
|
|
(* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *)
|
|
input SIGVALIDCLK;
|
|
input TX8B10BEN;
|
|
input TXCOMINIT;
|
|
input TXCOMSAS;
|
|
input TXCOMWAKE;
|
|
input TXDEEMPH;
|
|
input TXDETECTRX;
|
|
input TXDIFFPD;
|
|
input TXDLYBYPASS;
|
|
input TXDLYEN;
|
|
input TXDLYHOLD;
|
|
input TXDLYOVRDEN;
|
|
input TXDLYSRESET;
|
|
input TXDLYUPDOWN;
|
|
input TXELECIDLE;
|
|
input TXINHIBIT;
|
|
input TXPCSRESET;
|
|
input TXPDELECIDLEMODE;
|
|
input TXPHALIGN;
|
|
input TXPHALIGNEN;
|
|
input TXPHDLYPD;
|
|
input TXPHDLYRESET;
|
|
(* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
|
|
input TXPHDLYTSTCLK;
|
|
input TXPHINIT;
|
|
input TXPHOVRDEN;
|
|
input TXPIPPMEN;
|
|
input TXPIPPMOVRDEN;
|
|
input TXPIPPMPD;
|
|
input TXPIPPMSEL;
|
|
input TXPISOPD;
|
|
input TXPMARESET;
|
|
input TXPOLARITY;
|
|
input TXPOSTCURSORINV;
|
|
input TXPRBSFORCEERR;
|
|
input TXPRECURSORINV;
|
|
input TXQPIBIASEN;
|
|
input TXQPISTRONGPDOWN;
|
|
input TXQPIWEAKPUP;
|
|
input TXRATEMODE;
|
|
input TXSTARTSEQ;
|
|
input TXSWING;
|
|
input TXSYNCALLIN;
|
|
input TXSYNCIN;
|
|
input TXSYNCMODE;
|
|
input TXUSERRDY;
|
|
(* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
|
|
input TXUSRCLK2;
|
|
(* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
|
|
input TXUSRCLK;
|
|
input [13:0] RXADAPTSELTEST;
|
|
input [15:0] DRPDI;
|
|
input [15:0] GTRSVD;
|
|
input [15:0] PCSRSVDIN;
|
|
input [19:0] TSTIN;
|
|
input [1:0] RXELECIDLEMODE;
|
|
input [1:0] RXMONITORSEL;
|
|
input [1:0] RXPD;
|
|
input [1:0] RXSYSCLKSEL;
|
|
input [1:0] TXPD;
|
|
input [1:0] TXSYSCLKSEL;
|
|
input [2:0] CPLLREFCLKSEL;
|
|
input [2:0] LOOPBACK;
|
|
input [2:0] RXCHBONDLEVEL;
|
|
input [2:0] RXOUTCLKSEL;
|
|
input [2:0] RXPRBSSEL;
|
|
input [2:0] RXRATE;
|
|
input [2:0] TXBUFDIFFCTRL;
|
|
input [2:0] TXHEADER;
|
|
input [2:0] TXMARGIN;
|
|
input [2:0] TXOUTCLKSEL;
|
|
input [2:0] TXPRBSSEL;
|
|
input [2:0] TXRATE;
|
|
input [3:0] RXOSINTCFG;
|
|
input [3:0] RXOSINTID0;
|
|
input [3:0] TXDIFFCTRL;
|
|
input [4:0] PCSRSVDIN2;
|
|
input [4:0] PMARSVDIN;
|
|
input [4:0] RXCHBONDI;
|
|
input [4:0] RXDFEAGCTRL;
|
|
input [4:0] RXDFESLIDETAP;
|
|
input [4:0] TXPIPPMSTEPSIZE;
|
|
input [4:0] TXPOSTCURSOR;
|
|
input [4:0] TXPRECURSOR;
|
|
input [5:0] RXDFESLIDETAPID;
|
|
input [63:0] TXDATA;
|
|
input [6:0] TXMAINCURSOR;
|
|
input [6:0] TXSEQUENCE;
|
|
input [7:0] TX8B10BBYPASS;
|
|
input [7:0] TXCHARDISPMODE;
|
|
input [7:0] TXCHARDISPVAL;
|
|
input [7:0] TXCHARISK;
|
|
input [8:0] DRPADDR;
|
|
endmodule
|
|
|
|
module GTHE2_COMMON(DRPRDY, QPLLFBCLKLOST, QPLLLOCK, QPLLOUTCLK, QPLLOUTREFCLK, QPLLREFCLKLOST, REFCLKOUTMONITOR, DRPDO, PMARSVDOUT, QPLLDMONITOR, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRDENB, DRPCLK, DRPEN, DRPWE, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0
|
|
, GTREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1, QPLLLOCKDETCLK, QPLLLOCKEN, QPLLOUTRESET, QPLLPD, QPLLRESET, RCALENB, DRPDI, QPLLRSVD1, QPLLREFCLKSEL, BGRCALOVRD, QPLLRSVD2, DRPADDR, PMARSVD);
|
|
parameter [63:0] BIAS_CFG = 64'h0000040000001000;
|
|
parameter [31:0] COMMON_CFG = 32'h0000001C;
|
|
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0;
|
|
parameter [26:0] QPLL_CFG = 27'h0480181;
|
|
parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000;
|
|
parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000;
|
|
parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0;
|
|
parameter [9:0] QPLL_CP = 10'b0000011111;
|
|
parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0;
|
|
parameter [0:0] QPLL_DMONITOR_SEL = 1'b0;
|
|
parameter [9:0] QPLL_FBDIV = 10'b0000000000;
|
|
parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0;
|
|
parameter [0:0] QPLL_FBDIV_RATIO = 1'b0;
|
|
parameter [23:0] QPLL_INIT_CFG = 24'h000006;
|
|
parameter [15:0] QPLL_LOCK_CFG = 16'h01E8;
|
|
parameter [3:0] QPLL_LPF = 4'b1111;
|
|
parameter integer QPLL_REFCLK_DIV = 2;
|
|
parameter [0:0] QPLL_RP_COMP = 1'b0;
|
|
parameter [1:0] QPLL_VTRL_RESET = 2'b00;
|
|
parameter [1:0] RCAL_CFG = 2'b00;
|
|
parameter [15:0] RSVD_ATTR0 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR1 = 16'h0000;
|
|
parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001;
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter SIM_VERSION = "1.1";
|
|
output DRPRDY;
|
|
output QPLLFBCLKLOST;
|
|
output QPLLLOCK;
|
|
output QPLLOUTCLK;
|
|
output QPLLOUTREFCLK;
|
|
output QPLLREFCLKLOST;
|
|
output REFCLKOUTMONITOR;
|
|
output [15:0] DRPDO;
|
|
output [15:0] PMARSVDOUT;
|
|
output [7:0] QPLLDMONITOR;
|
|
input BGBYPASSB;
|
|
input BGMONITORENB;
|
|
input BGPDB;
|
|
input BGRCALOVRDENB;
|
|
(* invertible_pin = "IS_DRPCLK_INVERTED" *)
|
|
input DRPCLK;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
(* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
|
|
input GTGREFCLK;
|
|
input GTNORTHREFCLK0;
|
|
input GTNORTHREFCLK1;
|
|
input GTREFCLK0;
|
|
input GTREFCLK1;
|
|
input GTSOUTHREFCLK0;
|
|
input GTSOUTHREFCLK1;
|
|
(* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *)
|
|
input QPLLLOCKDETCLK;
|
|
input QPLLLOCKEN;
|
|
input QPLLOUTRESET;
|
|
input QPLLPD;
|
|
input QPLLRESET;
|
|
input RCALENB;
|
|
input [15:0] DRPDI;
|
|
input [15:0] QPLLRSVD1;
|
|
input [2:0] QPLLREFCLKSEL;
|
|
input [4:0] BGRCALOVRD;
|
|
input [4:0] QPLLRSVD2;
|
|
input [7:0] DRPADDR;
|
|
input [7:0] PMARSVD;
|
|
endmodule
|
|
|
|
module GTPE2_CHANNEL(DRPRDY, EYESCANDATAERROR, GTPTXN, GTPTXP, PHYSTATUS, PMARSVDOUT0, PMARSVDOUT1, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDLYSRESETDONE, RXELECIDLE, RXHEADERVALID, RXOSINTDONE
|
|
, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPMARESETDONE, RXPRBSERR, RXRATEDONE, RXRESETDONE, RXSYNCDONE, RXSYNCOUT, RXVALID, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE
|
|
, TXPHINITDONE, TXPMARESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, DMONITOROUT, DRPDO, PCSRSVDOUT, RXCLKCORCNT, RXDATAVALID, RXSTARTOFSEQ, TXBUFSTATUS, RXBUFSTATUS, RXHEADER, RXSTATUS, RXDATA, RXCHARISCOMMA, RXCHARISK, RXCHBONDO, RXDISPERR
|
|
, RXNOTINTABLE, RXPHMONITOR, RXPHSLIPMONITOR, CFGRESET, CLKRSVD0, CLKRSVD1, DMONFIFORESET, DMONITORCLK, DRPCLK, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTPRXN, GTPRXP, GTRESETSEL, GTRXRESET, GTTXRESET, PLL0CLK, PLL0REFCLK
|
|
, PLL1CLK, PLL1REFCLK, PMARSVDIN0, PMARSVDIN1, PMARSVDIN2, PMARSVDIN3, PMARSVDIN4, RESETOVRD, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEXYDEN
|
|
, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXGEARBOXSLIP, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFOVRDEN, RXLPMOSINTNTRLEN, RXLPMRESET, RXMCOMMAALIGNEN, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTEN, RXOSINTHOLD, RXOSINTNTRLEN, RXOSINTOVRDEN, RXOSINTPD, RXOSINTSTROBE
|
|
, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXPCOMMAALIGNEN, RXPCSRESET, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXRATEMODE, RXSLIDE, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXUSERRDY, RXUSRCLK2, RXUSRCLK, SETERRSTATUS
|
|
, SIGVALIDCLK, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXINHIBIT, TXPCSRESET, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD
|
|
, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRECURSORINV, TXRATEMODE, TXSTARTSEQ, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXUSERRDY
|
|
, TXUSRCLK2, TXUSRCLK, RXADAPTSELTEST, DRPDI, GTRSVD, PCSRSVDIN, TSTIN, RXELECIDLEMODE, RXPD, RXSYSCLKSEL, TXPD, TXSYSCLKSEL, LOOPBACK, RXCHBONDLEVEL, RXOUTCLKSEL, RXPRBSSEL, RXRATE, TXBUFDIFFCTRL, TXHEADER, TXMARGIN, TXOUTCLKSEL
|
|
, TXPRBSSEL, TXRATE, TXDATA, RXCHBONDI, RXOSINTCFG, RXOSINTID0, TX8B10BBYPASS, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, TXDIFFCTRL, TXPIPPMSTEPSIZE, TXPOSTCURSOR, TXPRECURSOR, TXMAINCURSOR, TXSEQUENCE, DRPADDR);
|
|
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_RESET = 1'b0;
|
|
parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000;
|
|
parameter ALIGN_COMMA_DOUBLE = "FALSE";
|
|
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
|
|
parameter integer ALIGN_COMMA_WORD = 1;
|
|
parameter ALIGN_MCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
|
|
parameter ALIGN_PCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
|
|
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
|
|
parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000;
|
|
parameter [6:0] CFOK_CFG2 = 7'b0100000;
|
|
parameter [6:0] CFOK_CFG3 = 7'b0100000;
|
|
parameter [0:0] CFOK_CFG4 = 1'b0;
|
|
parameter [1:0] CFOK_CFG5 = 2'b00;
|
|
parameter [3:0] CFOK_CFG6 = 4'b0000;
|
|
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
|
|
parameter integer CHAN_BOND_MAX_SKEW = 7;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
|
|
parameter integer CHAN_BOND_SEQ_LEN = 1;
|
|
parameter [0:0] CLK_COMMON_SWING = 1'b0;
|
|
parameter CLK_CORRECT_USE = "TRUE";
|
|
parameter CLK_COR_KEEP_IDLE = "FALSE";
|
|
parameter integer CLK_COR_MAX_LAT = 20;
|
|
parameter integer CLK_COR_MIN_LAT = 18;
|
|
parameter CLK_COR_PRECEDENCE = "TRUE";
|
|
parameter integer CLK_COR_REPEAT_WAIT = 0;
|
|
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CLK_COR_SEQ_2_USE = "FALSE";
|
|
parameter integer CLK_COR_SEQ_LEN = 1;
|
|
parameter DEC_MCOMMA_DETECT = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY = "TRUE";
|
|
parameter [23:0] DMONITOR_CFG = 24'h000A00;
|
|
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
|
|
parameter [5:0] ES_CONTROL = 6'b000000;
|
|
parameter ES_ERRDET_EN = "FALSE";
|
|
parameter ES_EYE_SCAN_EN = "FALSE";
|
|
parameter [11:0] ES_HORZ_OFFSET = 12'h010;
|
|
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
|
|
parameter [4:0] ES_PRESCALE = 5'b00000;
|
|
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
|
|
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
|
|
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
|
|
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
|
|
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
|
|
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
|
|
parameter FTS_LANE_DESKEW_EN = "FALSE";
|
|
parameter [2:0] GEARBOX_MODE = 3'b000;
|
|
parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
|
|
parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
|
|
parameter [0:0] LOOPBACK_CFG = 1'b0;
|
|
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
|
|
parameter PCS_PCIE_EN = "FALSE";
|
|
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
|
|
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
|
|
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
|
|
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
|
|
parameter [0:0] PMA_LOOPBACK_CFG = 1'b0;
|
|
parameter [31:0] PMA_RSV = 32'h00000333;
|
|
parameter [31:0] PMA_RSV2 = 32'h00002050;
|
|
parameter [1:0] PMA_RSV3 = 2'b00;
|
|
parameter [3:0] PMA_RSV4 = 4'b0000;
|
|
parameter [0:0] PMA_RSV5 = 1'b0;
|
|
parameter [0:0] PMA_RSV6 = 1'b0;
|
|
parameter [0:0] PMA_RSV7 = 1'b0;
|
|
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
|
|
parameter RXBUF_ADDR_MODE = "FULL";
|
|
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
|
|
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
|
|
parameter RXBUF_EN = "TRUE";
|
|
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
|
|
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
|
|
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
|
|
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
|
|
parameter integer RXBUF_THRESH_OVFLW = 61;
|
|
parameter RXBUF_THRESH_OVRD = "FALSE";
|
|
parameter integer RXBUF_THRESH_UNDFLW = 4;
|
|
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
|
|
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
|
|
parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010;
|
|
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
|
|
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
|
|
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
|
|
parameter [15:0] RXDLY_CFG = 16'h0010;
|
|
parameter [8:0] RXDLY_LCFG = 9'h020;
|
|
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
|
|
parameter RXGEARBOX_EN = "FALSE";
|
|
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
|
|
parameter [6:0] RXLPMRESET_TIME = 7'b0001111;
|
|
parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0;
|
|
parameter [3:0] RXLPM_CFG = 4'b0110;
|
|
parameter [0:0] RXLPM_CFG1 = 1'b0;
|
|
parameter [0:0] RXLPM_CM_CFG = 1'b0;
|
|
parameter [8:0] RXLPM_GC_CFG = 9'b111100010;
|
|
parameter [2:0] RXLPM_GC_CFG2 = 3'b001;
|
|
parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000;
|
|
parameter [4:0] RXLPM_HF_CFG2 = 5'b01010;
|
|
parameter [3:0] RXLPM_HF_CFG3 = 4'b0000;
|
|
parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [0:0] RXLPM_INCM_CFG = 1'b0;
|
|
parameter [0:0] RXLPM_IPCM_CFG = 1'b0;
|
|
parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000;
|
|
parameter [4:0] RXLPM_LF_CFG2 = 5'b01010;
|
|
parameter [2:0] RXLPM_OSINT_CFG = 3'b100;
|
|
parameter [6:0] RXOOB_CFG = 7'b0000110;
|
|
parameter RXOOB_CLK_CFG = "PMA";
|
|
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
|
|
parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
|
|
parameter integer RXOUT_DIV = 2;
|
|
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
|
|
parameter [23:0] RXPHDLY_CFG = 24'h084000;
|
|
parameter [23:0] RXPH_CFG = 24'hC00002;
|
|
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [2:0] RXPI_CFG0 = 3'b000;
|
|
parameter [0:0] RXPI_CFG1 = 1'b0;
|
|
parameter [0:0] RXPI_CFG2 = 1'b0;
|
|
parameter [4:0] RXPMARESET_TIME = 5'b00011;
|
|
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
|
|
parameter integer RXSLIDE_AUTO_WAIT = 7;
|
|
parameter RXSLIDE_MODE = "OFF";
|
|
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] RXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
|
|
parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011;
|
|
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
|
|
parameter integer RX_CLK25_DIV = 7;
|
|
parameter [0:0] RX_CLKMUX_EN = 1'b1;
|
|
parameter [1:0] RX_CM_SEL = 2'b11;
|
|
parameter [3:0] RX_CM_TRIM = 4'b0100;
|
|
parameter integer RX_DATA_WIDTH = 20;
|
|
parameter [5:0] RX_DDI_SEL = 6'b000000;
|
|
parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
|
|
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
|
|
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
|
|
parameter [12:0] RX_OS_CFG = 13'b0001111110000;
|
|
parameter integer RX_SIG_VALID_DLY = 10;
|
|
parameter RX_XCLK_SEL = "RXREC";
|
|
parameter integer SAS_MAX_COM = 64;
|
|
parameter integer SAS_MIN_COM = 36;
|
|
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
|
|
parameter [2:0] SATA_BURST_VAL = 3'b100;
|
|
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
|
|
parameter integer SATA_MAX_BURST = 8;
|
|
parameter integer SATA_MAX_INIT = 21;
|
|
parameter integer SATA_MAX_WAKE = 7;
|
|
parameter integer SATA_MIN_BURST = 4;
|
|
parameter integer SATA_MIN_INIT = 12;
|
|
parameter integer SATA_MIN_WAKE = 4;
|
|
parameter SATA_PLL_CFG = "VCO_3000MHZ";
|
|
parameter SHOW_REALIGN_COMMA = "TRUE";
|
|
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
|
|
parameter SIM_VERSION = "1.0";
|
|
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
|
|
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
|
|
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
|
|
parameter [31:0] TST_RSV = 32'h00000000;
|
|
parameter TXBUF_EN = "TRUE";
|
|
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
|
|
parameter [15:0] TXDLY_CFG = 16'h0010;
|
|
parameter [8:0] TXDLY_LCFG = 9'h020;
|
|
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
|
|
parameter TXGEARBOX_EN = "FALSE";
|
|
parameter [0:0] TXOOB_CFG = 1'b0;
|
|
parameter integer TXOUT_DIV = 2;
|
|
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
|
|
parameter [23:0] TXPHDLY_CFG = 24'h084000;
|
|
parameter [15:0] TXPH_CFG = 16'h0400;
|
|
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [1:0] TXPI_CFG0 = 2'b00;
|
|
parameter [1:0] TXPI_CFG1 = 2'b00;
|
|
parameter [1:0] TXPI_CFG2 = 2'b00;
|
|
parameter [0:0] TXPI_CFG3 = 1'b0;
|
|
parameter [0:0] TXPI_CFG4 = 1'b0;
|
|
parameter [2:0] TXPI_CFG5 = 3'b000;
|
|
parameter [0:0] TXPI_GREY_SEL = 1'b0;
|
|
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
|
|
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
|
|
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
|
|
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
|
|
parameter [4:0] TXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] TXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
|
|
parameter integer TX_CLK25_DIV = 7;
|
|
parameter [0:0] TX_CLKMUX_EN = 1'b1;
|
|
parameter integer TX_DATA_WIDTH = 20;
|
|
parameter [5:0] TX_DEEMPH0 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH1 = 6'b000000;
|
|
parameter TX_DRIVE_MODE = "DIRECT";
|
|
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
|
|
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
|
|
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
|
|
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
|
|
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
|
|
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
|
|
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
|
|
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
|
|
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
|
|
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
|
|
parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
|
|
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
|
|
parameter [2:0] TX_RXDETECT_REF = 3'b100;
|
|
parameter TX_XCLK_SEL = "TXUSR";
|
|
parameter [0:0] UCODEER_CLR = 1'b0;
|
|
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
|
|
output DRPRDY;
|
|
output EYESCANDATAERROR;
|
|
output GTPTXN;
|
|
output GTPTXP;
|
|
output PHYSTATUS;
|
|
output PMARSVDOUT0;
|
|
output PMARSVDOUT1;
|
|
output RXBYTEISALIGNED;
|
|
output RXBYTEREALIGN;
|
|
output RXCDRLOCK;
|
|
output RXCHANBONDSEQ;
|
|
output RXCHANISALIGNED;
|
|
output RXCHANREALIGN;
|
|
output RXCOMINITDET;
|
|
output RXCOMMADET;
|
|
output RXCOMSASDET;
|
|
output RXCOMWAKEDET;
|
|
output RXDLYSRESETDONE;
|
|
output RXELECIDLE;
|
|
output RXHEADERVALID;
|
|
output RXOSINTDONE;
|
|
output RXOSINTSTARTED;
|
|
output RXOSINTSTROBEDONE;
|
|
output RXOSINTSTROBESTARTED;
|
|
output RXOUTCLK;
|
|
output RXOUTCLKFABRIC;
|
|
output RXOUTCLKPCS;
|
|
output RXPHALIGNDONE;
|
|
output RXPMARESETDONE;
|
|
output RXPRBSERR;
|
|
output RXRATEDONE;
|
|
output RXRESETDONE;
|
|
output RXSYNCDONE;
|
|
output RXSYNCOUT;
|
|
output RXVALID;
|
|
output TXCOMFINISH;
|
|
output TXDLYSRESETDONE;
|
|
output TXGEARBOXREADY;
|
|
output TXOUTCLK;
|
|
output TXOUTCLKFABRIC;
|
|
output TXOUTCLKPCS;
|
|
output TXPHALIGNDONE;
|
|
output TXPHINITDONE;
|
|
output TXPMARESETDONE;
|
|
output TXRATEDONE;
|
|
output TXRESETDONE;
|
|
output TXSYNCDONE;
|
|
output TXSYNCOUT;
|
|
output [14:0] DMONITOROUT;
|
|
output [15:0] DRPDO;
|
|
output [15:0] PCSRSVDOUT;
|
|
output [1:0] RXCLKCORCNT;
|
|
output [1:0] RXDATAVALID;
|
|
output [1:0] RXSTARTOFSEQ;
|
|
output [1:0] TXBUFSTATUS;
|
|
output [2:0] RXBUFSTATUS;
|
|
output [2:0] RXHEADER;
|
|
output [2:0] RXSTATUS;
|
|
output [31:0] RXDATA;
|
|
output [3:0] RXCHARISCOMMA;
|
|
output [3:0] RXCHARISK;
|
|
output [3:0] RXCHBONDO;
|
|
output [3:0] RXDISPERR;
|
|
output [3:0] RXNOTINTABLE;
|
|
output [4:0] RXPHMONITOR;
|
|
output [4:0] RXPHSLIPMONITOR;
|
|
input CFGRESET;
|
|
(* invertible_pin = "IS_CLKRSVD0_INVERTED" *)
|
|
input CLKRSVD0;
|
|
(* invertible_pin = "IS_CLKRSVD1_INVERTED" *)
|
|
input CLKRSVD1;
|
|
input DMONFIFORESET;
|
|
(* invertible_pin = "IS_DMONITORCLK_INVERTED" *)
|
|
input DMONITORCLK;
|
|
(* invertible_pin = "IS_DRPCLK_INVERTED" *)
|
|
input DRPCLK;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input EYESCANMODE;
|
|
input EYESCANRESET;
|
|
input EYESCANTRIGGER;
|
|
input GTPRXN;
|
|
input GTPRXP;
|
|
input GTRESETSEL;
|
|
input GTRXRESET;
|
|
input GTTXRESET;
|
|
input PLL0CLK;
|
|
input PLL0REFCLK;
|
|
input PLL1CLK;
|
|
input PLL1REFCLK;
|
|
input PMARSVDIN0;
|
|
input PMARSVDIN1;
|
|
input PMARSVDIN2;
|
|
input PMARSVDIN3;
|
|
input PMARSVDIN4;
|
|
input RESETOVRD;
|
|
input RX8B10BEN;
|
|
input RXBUFRESET;
|
|
input RXCDRFREQRESET;
|
|
input RXCDRHOLD;
|
|
input RXCDROVRDEN;
|
|
input RXCDRRESET;
|
|
input RXCDRRESETRSV;
|
|
input RXCHBONDEN;
|
|
input RXCHBONDMASTER;
|
|
input RXCHBONDSLAVE;
|
|
input RXCOMMADETEN;
|
|
input RXDDIEN;
|
|
input RXDFEXYDEN;
|
|
input RXDLYBYPASS;
|
|
input RXDLYEN;
|
|
input RXDLYOVRDEN;
|
|
input RXDLYSRESET;
|
|
input RXGEARBOXSLIP;
|
|
input RXLPMHFHOLD;
|
|
input RXLPMHFOVRDEN;
|
|
input RXLPMLFHOLD;
|
|
input RXLPMLFOVRDEN;
|
|
input RXLPMOSINTNTRLEN;
|
|
input RXLPMRESET;
|
|
input RXMCOMMAALIGNEN;
|
|
input RXOOBRESET;
|
|
input RXOSCALRESET;
|
|
input RXOSHOLD;
|
|
input RXOSINTEN;
|
|
input RXOSINTHOLD;
|
|
input RXOSINTNTRLEN;
|
|
input RXOSINTOVRDEN;
|
|
input RXOSINTPD;
|
|
input RXOSINTSTROBE;
|
|
input RXOSINTTESTOVRDEN;
|
|
input RXOSOVRDEN;
|
|
input RXPCOMMAALIGNEN;
|
|
input RXPCSRESET;
|
|
input RXPHALIGN;
|
|
input RXPHALIGNEN;
|
|
input RXPHDLYPD;
|
|
input RXPHDLYRESET;
|
|
input RXPHOVRDEN;
|
|
input RXPMARESET;
|
|
input RXPOLARITY;
|
|
input RXPRBSCNTRESET;
|
|
input RXRATEMODE;
|
|
input RXSLIDE;
|
|
input RXSYNCALLIN;
|
|
input RXSYNCIN;
|
|
input RXSYNCMODE;
|
|
input RXUSERRDY;
|
|
(* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
|
|
input RXUSRCLK2;
|
|
(* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
|
|
input RXUSRCLK;
|
|
input SETERRSTATUS;
|
|
(* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *)
|
|
input SIGVALIDCLK;
|
|
input TX8B10BEN;
|
|
input TXCOMINIT;
|
|
input TXCOMSAS;
|
|
input TXCOMWAKE;
|
|
input TXDEEMPH;
|
|
input TXDETECTRX;
|
|
input TXDIFFPD;
|
|
input TXDLYBYPASS;
|
|
input TXDLYEN;
|
|
input TXDLYHOLD;
|
|
input TXDLYOVRDEN;
|
|
input TXDLYSRESET;
|
|
input TXDLYUPDOWN;
|
|
input TXELECIDLE;
|
|
input TXINHIBIT;
|
|
input TXPCSRESET;
|
|
input TXPDELECIDLEMODE;
|
|
input TXPHALIGN;
|
|
input TXPHALIGNEN;
|
|
input TXPHDLYPD;
|
|
input TXPHDLYRESET;
|
|
(* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
|
|
input TXPHDLYTSTCLK;
|
|
input TXPHINIT;
|
|
input TXPHOVRDEN;
|
|
input TXPIPPMEN;
|
|
input TXPIPPMOVRDEN;
|
|
input TXPIPPMPD;
|
|
input TXPIPPMSEL;
|
|
input TXPISOPD;
|
|
input TXPMARESET;
|
|
input TXPOLARITY;
|
|
input TXPOSTCURSORINV;
|
|
input TXPRBSFORCEERR;
|
|
input TXPRECURSORINV;
|
|
input TXRATEMODE;
|
|
input TXSTARTSEQ;
|
|
input TXSWING;
|
|
input TXSYNCALLIN;
|
|
input TXSYNCIN;
|
|
input TXSYNCMODE;
|
|
input TXUSERRDY;
|
|
(* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
|
|
input TXUSRCLK2;
|
|
(* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
|
|
input TXUSRCLK;
|
|
input [13:0] RXADAPTSELTEST;
|
|
input [15:0] DRPDI;
|
|
input [15:0] GTRSVD;
|
|
input [15:0] PCSRSVDIN;
|
|
input [19:0] TSTIN;
|
|
input [1:0] RXELECIDLEMODE;
|
|
input [1:0] RXPD;
|
|
input [1:0] RXSYSCLKSEL;
|
|
input [1:0] TXPD;
|
|
input [1:0] TXSYSCLKSEL;
|
|
input [2:0] LOOPBACK;
|
|
input [2:0] RXCHBONDLEVEL;
|
|
input [2:0] RXOUTCLKSEL;
|
|
input [2:0] RXPRBSSEL;
|
|
input [2:0] RXRATE;
|
|
input [2:0] TXBUFDIFFCTRL;
|
|
input [2:0] TXHEADER;
|
|
input [2:0] TXMARGIN;
|
|
input [2:0] TXOUTCLKSEL;
|
|
input [2:0] TXPRBSSEL;
|
|
input [2:0] TXRATE;
|
|
input [31:0] TXDATA;
|
|
input [3:0] RXCHBONDI;
|
|
input [3:0] RXOSINTCFG;
|
|
input [3:0] RXOSINTID0;
|
|
input [3:0] TX8B10BBYPASS;
|
|
input [3:0] TXCHARDISPMODE;
|
|
input [3:0] TXCHARDISPVAL;
|
|
input [3:0] TXCHARISK;
|
|
input [3:0] TXDIFFCTRL;
|
|
input [4:0] TXPIPPMSTEPSIZE;
|
|
input [4:0] TXPOSTCURSOR;
|
|
input [4:0] TXPRECURSOR;
|
|
input [6:0] TXMAINCURSOR;
|
|
input [6:0] TXSEQUENCE;
|
|
input [8:0] DRPADDR;
|
|
endmodule
|
|
|
|
module GTPE2_COMMON(DRPRDY, PLL0FBCLKLOST, PLL0LOCK, PLL0OUTCLK, PLL0OUTREFCLK, PLL0REFCLKLOST, PLL1FBCLKLOST, PLL1LOCK, PLL1OUTCLK, PLL1OUTREFCLK, PLL1REFCLKLOST, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, DRPDO, PMARSVDOUT, DMONITOROUT, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRDENB, DRPCLK
|
|
, DRPEN, DRPWE, GTEASTREFCLK0, GTEASTREFCLK1, GTGREFCLK0, GTGREFCLK1, GTREFCLK0, GTREFCLK1, GTWESTREFCLK0, GTWESTREFCLK1, PLL0LOCKDETCLK, PLL0LOCKEN, PLL0PD, PLL0RESET, PLL1LOCKDETCLK, PLL1LOCKEN, PLL1PD, PLL1RESET, RCALENB, DRPDI, PLLRSVD1
|
|
, PLL0REFCLKSEL, PLL1REFCLKSEL, BGRCALOVRD, PLLRSVD2, DRPADDR, PMARSVD);
|
|
parameter [63:0] BIAS_CFG = 64'h0000000000000000;
|
|
parameter [31:0] COMMON_CFG = 32'h00000000;
|
|
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0;
|
|
parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0;
|
|
parameter [26:0] PLL0_CFG = 27'h01F03DC;
|
|
parameter [0:0] PLL0_DMON_CFG = 1'b0;
|
|
parameter integer PLL0_FBDIV = 4;
|
|
parameter integer PLL0_FBDIV_45 = 5;
|
|
parameter [23:0] PLL0_INIT_CFG = 24'h00001E;
|
|
parameter [8:0] PLL0_LOCK_CFG = 9'h1E8;
|
|
parameter integer PLL0_REFCLK_DIV = 1;
|
|
parameter [26:0] PLL1_CFG = 27'h01F03DC;
|
|
parameter [0:0] PLL1_DMON_CFG = 1'b0;
|
|
parameter integer PLL1_FBDIV = 4;
|
|
parameter integer PLL1_FBDIV_45 = 5;
|
|
parameter [23:0] PLL1_INIT_CFG = 24'h00001E;
|
|
parameter [8:0] PLL1_LOCK_CFG = 9'h1E8;
|
|
parameter integer PLL1_REFCLK_DIV = 1;
|
|
parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000;
|
|
parameter [15:0] RSVD_ATTR0 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR1 = 16'h0000;
|
|
parameter [2:0] SIM_PLL0REFCLK_SEL = 3'b001;
|
|
parameter [2:0] SIM_PLL1REFCLK_SEL = 3'b001;
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter SIM_VERSION = "1.0";
|
|
output DRPRDY;
|
|
output PLL0FBCLKLOST;
|
|
output PLL0LOCK;
|
|
output PLL0OUTCLK;
|
|
output PLL0OUTREFCLK;
|
|
output PLL0REFCLKLOST;
|
|
output PLL1FBCLKLOST;
|
|
output PLL1LOCK;
|
|
output PLL1OUTCLK;
|
|
output PLL1OUTREFCLK;
|
|
output PLL1REFCLKLOST;
|
|
output REFCLKOUTMONITOR0;
|
|
output REFCLKOUTMONITOR1;
|
|
output [15:0] DRPDO;
|
|
output [15:0] PMARSVDOUT;
|
|
output [7:0] DMONITOROUT;
|
|
input BGBYPASSB;
|
|
input BGMONITORENB;
|
|
input BGPDB;
|
|
input BGRCALOVRDENB;
|
|
(* invertible_pin = "IS_DRPCLK_INVERTED" *)
|
|
input DRPCLK;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input GTEASTREFCLK0;
|
|
input GTEASTREFCLK1;
|
|
(* invertible_pin = "IS_GTGREFCLK0_INVERTED" *)
|
|
input GTGREFCLK0;
|
|
(* invertible_pin = "IS_GTGREFCLK1_INVERTED" *)
|
|
input GTGREFCLK1;
|
|
input GTREFCLK0;
|
|
input GTREFCLK1;
|
|
input GTWESTREFCLK0;
|
|
input GTWESTREFCLK1;
|
|
(* invertible_pin = "IS_PLL0LOCKDETCLK_INVERTED" *)
|
|
input PLL0LOCKDETCLK;
|
|
input PLL0LOCKEN;
|
|
input PLL0PD;
|
|
input PLL0RESET;
|
|
(* invertible_pin = "IS_PLL1LOCKDETCLK_INVERTED" *)
|
|
input PLL1LOCKDETCLK;
|
|
input PLL1LOCKEN;
|
|
input PLL1PD;
|
|
input PLL1RESET;
|
|
input RCALENB;
|
|
input [15:0] DRPDI;
|
|
input [15:0] PLLRSVD1;
|
|
input [2:0] PLL0REFCLKSEL;
|
|
input [2:0] PLL1REFCLKSEL;
|
|
input [4:0] BGRCALOVRD;
|
|
input [4:0] PLLRSVD2;
|
|
input [7:0] DRPADDR;
|
|
input [7:0] PMARSVD;
|
|
endmodule
|
|
|
|
module GTXE2_CHANNEL(CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DRPRDY, EYESCANDATAERROR, GTREFCLKMONITOR, GTXTXN, GTXTXP, PHYSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXDATAVALID, RXDLYSRESETDONE
|
|
, RXELECIDLE, RXHEADERVALID, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPRBSERR, RXQPISENN, RXQPISENP, RXRATEDONE, RXRESETDONE, RXSTARTOFSEQ, RXVALID, TXCOMFINISH, TXDLYSRESETDONE, TXGEARBOXREADY, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE
|
|
, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, DRPDO, PCSRSVDOUT, RXCLKCORCNT, TXBUFSTATUS, RXBUFSTATUS, RXHEADER, RXSTATUS, RXCHBONDO, RXPHMONITOR, RXPHSLIPMONITOR, RXDATA, RXMONITOROUT, DMONITOROUT, RXCHARISCOMMA, RXCHARISK, RXDISPERR, RXNOTINTABLE
|
|
, TSTOUT, CFGRESET, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLRESET, DRPCLK, DRPEN, DRPWE, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1
|
|
, GTTXRESET, GTXRXN, GTXRXP, QPLLCLK, QPLLREFCLK, RESETOVRD, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDDIEN, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFECM1EN
|
|
, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEVSEN, RXDFEXYDEN, RXDFEXYDHOLD, RXDFEXYDOVRDEN, RXDLYBYPASS, RXDLYEN
|
|
, RXDLYOVRDEN, RXDLYSRESET, RXGEARBOXSLIP, RXLPMEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXMCOMMAALIGNEN, RXOOBRESET, RXOSHOLD, RXOSOVRDEN, RXPCOMMAALIGNEN, RXPCSRESET, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPMARESET, RXPOLARITY
|
|
, RXPRBSCNTRESET, RXQPIEN, RXSLIDE, RXUSERRDY, RXUSRCLK2, RXUSRCLK, SETERRSTATUS, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXDEEMPH, TXDETECTRX, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE
|
|
, TXINHIBIT, TXPCSRESET, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPISOPD, TXPMARESET, TXPOLARITY, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRECURSORINV, TXQPIBIASEN, TXQPISTRONGPDOWN, TXQPIWEAKPUP, TXSTARTSEQ, TXSWING
|
|
, TXUSERRDY, TXUSRCLK2, TXUSRCLK, DRPDI, GTRSVD, PCSRSVDIN, TSTIN, RXELECIDLEMODE, RXMONITORSEL, RXPD, RXSYSCLKSEL, TXPD, TXSYSCLKSEL, CPLLREFCLKSEL, LOOPBACK, RXCHBONDLEVEL, RXOUTCLKSEL, RXPRBSSEL, RXRATE, TXBUFDIFFCTRL, TXHEADER
|
|
, TXMARGIN, TXOUTCLKSEL, TXPRBSSEL, TXRATE, CLKRSVD, TXDIFFCTRL, PCSRSVDIN2, PMARSVDIN2, PMARSVDIN, RXCHBONDI, TXPOSTCURSOR, TXPRECURSOR, TXDATA, TXMAINCURSOR, TXSEQUENCE, TX8B10BBYPASS, TXCHARDISPMODE, TXCHARDISPVAL, TXCHARISK, DRPADDR);
|
|
parameter ALIGN_COMMA_DOUBLE = "FALSE";
|
|
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
|
|
parameter integer ALIGN_COMMA_WORD = 1;
|
|
parameter ALIGN_MCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
|
|
parameter ALIGN_PCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
|
|
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
|
|
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
|
|
parameter integer CHAN_BOND_MAX_SKEW = 7;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
|
|
parameter integer CHAN_BOND_SEQ_LEN = 1;
|
|
parameter CLK_CORRECT_USE = "TRUE";
|
|
parameter CLK_COR_KEEP_IDLE = "FALSE";
|
|
parameter integer CLK_COR_MAX_LAT = 20;
|
|
parameter integer CLK_COR_MIN_LAT = 18;
|
|
parameter CLK_COR_PRECEDENCE = "TRUE";
|
|
parameter integer CLK_COR_REPEAT_WAIT = 0;
|
|
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CLK_COR_SEQ_2_USE = "FALSE";
|
|
parameter integer CLK_COR_SEQ_LEN = 1;
|
|
parameter [23:0] CPLL_CFG = 24'hB007D8;
|
|
parameter integer CPLL_FBDIV = 4;
|
|
parameter integer CPLL_FBDIV_45 = 5;
|
|
parameter [23:0] CPLL_INIT_CFG = 24'h00001E;
|
|
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
|
|
parameter integer CPLL_REFCLK_DIV = 1;
|
|
parameter DEC_MCOMMA_DETECT = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY = "TRUE";
|
|
parameter [23:0] DMONITOR_CFG = 24'h000A00;
|
|
parameter [5:0] ES_CONTROL = 6'b000000;
|
|
parameter ES_ERRDET_EN = "FALSE";
|
|
parameter ES_EYE_SCAN_EN = "FALSE";
|
|
parameter [11:0] ES_HORZ_OFFSET = 12'h000;
|
|
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
|
|
parameter [4:0] ES_PRESCALE = 5'b00000;
|
|
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
|
|
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
|
|
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
|
|
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
|
|
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
|
|
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
|
|
parameter FTS_LANE_DESKEW_EN = "FALSE";
|
|
parameter [2:0] GEARBOX_MODE = 3'b000;
|
|
parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
|
|
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
|
|
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
|
|
parameter PCS_PCIE_EN = "FALSE";
|
|
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
|
|
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
|
|
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
|
|
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
|
|
parameter [31:0] PMA_RSV = 32'h00000000;
|
|
parameter [15:0] PMA_RSV2 = 16'h2050;
|
|
parameter [1:0] PMA_RSV3 = 2'b00;
|
|
parameter [31:0] PMA_RSV4 = 32'h00000000;
|
|
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
|
|
parameter RXBUF_ADDR_MODE = "FULL";
|
|
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
|
|
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
|
|
parameter RXBUF_EN = "TRUE";
|
|
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
|
|
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
|
|
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
|
|
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
|
|
parameter integer RXBUF_THRESH_OVFLW = 61;
|
|
parameter RXBUF_THRESH_OVRD = "FALSE";
|
|
parameter integer RXBUF_THRESH_UNDFLW = 4;
|
|
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
|
|
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
|
|
parameter [71:0] RXCDR_CFG = 72'h0B000023FF20400020;
|
|
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
|
|
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [5:0] RXCDR_LOCK_CFG = 6'b010101;
|
|
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
|
|
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
|
|
parameter [15:0] RXDLY_CFG = 16'h001F;
|
|
parameter [8:0] RXDLY_LCFG = 9'h030;
|
|
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
|
|
parameter RXGEARBOX_EN = "FALSE";
|
|
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
|
|
parameter [13:0] RXLPM_HF_CFG = 14'b00000011110000;
|
|
parameter [13:0] RXLPM_LF_CFG = 14'b00000011110000;
|
|
parameter [6:0] RXOOB_CFG = 7'b0000110;
|
|
parameter integer RXOUT_DIV = 2;
|
|
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
|
|
parameter [23:0] RXPHDLY_CFG = 24'h084020;
|
|
parameter [23:0] RXPH_CFG = 24'h000000;
|
|
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [4:0] RXPMARESET_TIME = 5'b00011;
|
|
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
|
|
parameter integer RXSLIDE_AUTO_WAIT = 7;
|
|
parameter RXSLIDE_MODE = "OFF";
|
|
parameter [11:0] RX_BIAS_CFG = 12'b000000000000;
|
|
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
|
|
parameter integer RX_CLK25_DIV = 7;
|
|
parameter [0:0] RX_CLKMUX_PD = 1'b1;
|
|
parameter [1:0] RX_CM_SEL = 2'b11;
|
|
parameter [2:0] RX_CM_TRIM = 3'b100;
|
|
parameter integer RX_DATA_WIDTH = 20;
|
|
parameter [5:0] RX_DDI_SEL = 6'b000000;
|
|
parameter [11:0] RX_DEBUG_CFG = 12'b000000000000;
|
|
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
|
|
parameter [22:0] RX_DFE_GAIN_CFG = 23'h180E0F;
|
|
parameter [11:0] RX_DFE_H2_CFG = 12'b000111100000;
|
|
parameter [11:0] RX_DFE_H3_CFG = 12'b000111100000;
|
|
parameter [10:0] RX_DFE_H4_CFG = 11'b00011110000;
|
|
parameter [10:0] RX_DFE_H5_CFG = 11'b00011110000;
|
|
parameter [12:0] RX_DFE_KL_CFG = 13'b0001111110000;
|
|
parameter [31:0] RX_DFE_KL_CFG2 = 32'h3008E56A;
|
|
parameter [15:0] RX_DFE_LPM_CFG = 16'h0904;
|
|
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [16:0] RX_DFE_UT_CFG = 17'b00111111000000000;
|
|
parameter [16:0] RX_DFE_VP_CFG = 17'b00011111100000000;
|
|
parameter [12:0] RX_DFE_XYD_CFG = 13'b0000000010000;
|
|
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
|
|
parameter integer RX_INT_DATAWIDTH = 0;
|
|
parameter [12:0] RX_OS_CFG = 13'b0001111110000;
|
|
parameter integer RX_SIG_VALID_DLY = 10;
|
|
parameter RX_XCLK_SEL = "RXREC";
|
|
parameter integer SAS_MAX_COM = 64;
|
|
parameter integer SAS_MIN_COM = 36;
|
|
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
|
|
parameter [2:0] SATA_BURST_VAL = 3'b100;
|
|
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
|
|
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
|
|
parameter integer SATA_MAX_BURST = 8;
|
|
parameter integer SATA_MAX_INIT = 21;
|
|
parameter integer SATA_MAX_WAKE = 7;
|
|
parameter integer SATA_MIN_BURST = 4;
|
|
parameter integer SATA_MIN_INIT = 12;
|
|
parameter integer SATA_MIN_WAKE = 4;
|
|
parameter SHOW_REALIGN_COMMA = "TRUE";
|
|
parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001;
|
|
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
|
|
parameter SIM_VERSION = "4.0";
|
|
parameter [4:0] TERM_RCAL_CFG = 5'b10000;
|
|
parameter [0:0] TERM_RCAL_OVRD = 1'b0;
|
|
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
|
|
parameter [31:0] TST_RSV = 32'h00000000;
|
|
parameter TXBUF_EN = "TRUE";
|
|
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
|
|
parameter [15:0] TXDLY_CFG = 16'h001F;
|
|
parameter [8:0] TXDLY_LCFG = 9'h030;
|
|
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
|
|
parameter TXGEARBOX_EN = "FALSE";
|
|
parameter integer TXOUT_DIV = 2;
|
|
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
|
|
parameter [23:0] TXPHDLY_CFG = 24'h084020;
|
|
parameter [15:0] TXPH_CFG = 16'h0780;
|
|
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [4:0] TXPMARESET_TIME = 5'b00001;
|
|
parameter integer TX_CLK25_DIV = 7;
|
|
parameter [0:0] TX_CLKMUX_PD = 1'b1;
|
|
parameter integer TX_DATA_WIDTH = 20;
|
|
parameter [4:0] TX_DEEMPH0 = 5'b00000;
|
|
parameter [4:0] TX_DEEMPH1 = 5'b00000;
|
|
parameter TX_DRIVE_MODE = "DIRECT";
|
|
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
|
|
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
|
|
parameter integer TX_INT_DATAWIDTH = 0;
|
|
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
|
|
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
|
|
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
|
|
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
|
|
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
|
|
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
|
|
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
|
|
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
|
|
parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
|
|
parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
|
|
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
|
|
parameter [2:0] TX_RXDETECT_REF = 3'b100;
|
|
parameter TX_XCLK_SEL = "TXUSR";
|
|
parameter [0:0] UCODEER_CLR = 1'b0;
|
|
output CPLLFBCLKLOST;
|
|
output CPLLLOCK;
|
|
output CPLLREFCLKLOST;
|
|
output DRPRDY;
|
|
output EYESCANDATAERROR;
|
|
output GTREFCLKMONITOR;
|
|
output GTXTXN;
|
|
output GTXTXP;
|
|
output PHYSTATUS;
|
|
output RXBYTEISALIGNED;
|
|
output RXBYTEREALIGN;
|
|
output RXCDRLOCK;
|
|
output RXCHANBONDSEQ;
|
|
output RXCHANISALIGNED;
|
|
output RXCHANREALIGN;
|
|
output RXCOMINITDET;
|
|
output RXCOMMADET;
|
|
output RXCOMSASDET;
|
|
output RXCOMWAKEDET;
|
|
output RXDATAVALID;
|
|
output RXDLYSRESETDONE;
|
|
output RXELECIDLE;
|
|
output RXHEADERVALID;
|
|
output RXOUTCLK;
|
|
output RXOUTCLKFABRIC;
|
|
output RXOUTCLKPCS;
|
|
output RXPHALIGNDONE;
|
|
output RXPRBSERR;
|
|
output RXQPISENN;
|
|
output RXQPISENP;
|
|
output RXRATEDONE;
|
|
output RXRESETDONE;
|
|
output RXSTARTOFSEQ;
|
|
output RXVALID;
|
|
output TXCOMFINISH;
|
|
output TXDLYSRESETDONE;
|
|
output TXGEARBOXREADY;
|
|
output TXOUTCLK;
|
|
output TXOUTCLKFABRIC;
|
|
output TXOUTCLKPCS;
|
|
output TXPHALIGNDONE;
|
|
output TXPHINITDONE;
|
|
output TXQPISENN;
|
|
output TXQPISENP;
|
|
output TXRATEDONE;
|
|
output TXRESETDONE;
|
|
output [15:0] DRPDO;
|
|
output [15:0] PCSRSVDOUT;
|
|
output [1:0] RXCLKCORCNT;
|
|
output [1:0] TXBUFSTATUS;
|
|
output [2:0] RXBUFSTATUS;
|
|
output [2:0] RXHEADER;
|
|
output [2:0] RXSTATUS;
|
|
output [4:0] RXCHBONDO;
|
|
output [4:0] RXPHMONITOR;
|
|
output [4:0] RXPHSLIPMONITOR;
|
|
output [63:0] RXDATA;
|
|
output [6:0] RXMONITOROUT;
|
|
output [7:0] DMONITOROUT;
|
|
output [7:0] RXCHARISCOMMA;
|
|
output [7:0] RXCHARISK;
|
|
output [7:0] RXDISPERR;
|
|
output [7:0] RXNOTINTABLE;
|
|
output [9:0] TSTOUT;
|
|
input CFGRESET;
|
|
(* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *)
|
|
input CPLLLOCKDETCLK;
|
|
input CPLLLOCKEN;
|
|
input CPLLPD;
|
|
input CPLLRESET;
|
|
(* invertible_pin = "IS_DRPCLK_INVERTED" *)
|
|
input DRPCLK;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input EYESCANMODE;
|
|
input EYESCANRESET;
|
|
input EYESCANTRIGGER;
|
|
(* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
|
|
input GTGREFCLK;
|
|
input GTNORTHREFCLK0;
|
|
input GTNORTHREFCLK1;
|
|
input GTREFCLK0;
|
|
input GTREFCLK1;
|
|
input GTRESETSEL;
|
|
input GTRXRESET;
|
|
input GTSOUTHREFCLK0;
|
|
input GTSOUTHREFCLK1;
|
|
input GTTXRESET;
|
|
input GTXRXN;
|
|
input GTXRXP;
|
|
input QPLLCLK;
|
|
input QPLLREFCLK;
|
|
input RESETOVRD;
|
|
input RX8B10BEN;
|
|
input RXBUFRESET;
|
|
input RXCDRFREQRESET;
|
|
input RXCDRHOLD;
|
|
input RXCDROVRDEN;
|
|
input RXCDRRESET;
|
|
input RXCDRRESETRSV;
|
|
input RXCHBONDEN;
|
|
input RXCHBONDMASTER;
|
|
input RXCHBONDSLAVE;
|
|
input RXCOMMADETEN;
|
|
input RXDDIEN;
|
|
input RXDFEAGCHOLD;
|
|
input RXDFEAGCOVRDEN;
|
|
input RXDFECM1EN;
|
|
input RXDFELFHOLD;
|
|
input RXDFELFOVRDEN;
|
|
input RXDFELPMRESET;
|
|
input RXDFETAP2HOLD;
|
|
input RXDFETAP2OVRDEN;
|
|
input RXDFETAP3HOLD;
|
|
input RXDFETAP3OVRDEN;
|
|
input RXDFETAP4HOLD;
|
|
input RXDFETAP4OVRDEN;
|
|
input RXDFETAP5HOLD;
|
|
input RXDFETAP5OVRDEN;
|
|
input RXDFEUTHOLD;
|
|
input RXDFEUTOVRDEN;
|
|
input RXDFEVPHOLD;
|
|
input RXDFEVPOVRDEN;
|
|
input RXDFEVSEN;
|
|
input RXDFEXYDEN;
|
|
input RXDFEXYDHOLD;
|
|
input RXDFEXYDOVRDEN;
|
|
input RXDLYBYPASS;
|
|
input RXDLYEN;
|
|
input RXDLYOVRDEN;
|
|
input RXDLYSRESET;
|
|
input RXGEARBOXSLIP;
|
|
input RXLPMEN;
|
|
input RXLPMHFHOLD;
|
|
input RXLPMHFOVRDEN;
|
|
input RXLPMLFHOLD;
|
|
input RXLPMLFKLOVRDEN;
|
|
input RXMCOMMAALIGNEN;
|
|
input RXOOBRESET;
|
|
input RXOSHOLD;
|
|
input RXOSOVRDEN;
|
|
input RXPCOMMAALIGNEN;
|
|
input RXPCSRESET;
|
|
input RXPHALIGN;
|
|
input RXPHALIGNEN;
|
|
input RXPHDLYPD;
|
|
input RXPHDLYRESET;
|
|
input RXPHOVRDEN;
|
|
input RXPMARESET;
|
|
input RXPOLARITY;
|
|
input RXPRBSCNTRESET;
|
|
input RXQPIEN;
|
|
input RXSLIDE;
|
|
input RXUSERRDY;
|
|
(* invertible_pin = "IS_RXUSRCLK2_INVERTED" *)
|
|
input RXUSRCLK2;
|
|
(* invertible_pin = "IS_RXUSRCLK_INVERTED" *)
|
|
input RXUSRCLK;
|
|
input SETERRSTATUS;
|
|
input TX8B10BEN;
|
|
input TXCOMINIT;
|
|
input TXCOMSAS;
|
|
input TXCOMWAKE;
|
|
input TXDEEMPH;
|
|
input TXDETECTRX;
|
|
input TXDIFFPD;
|
|
input TXDLYBYPASS;
|
|
input TXDLYEN;
|
|
input TXDLYHOLD;
|
|
input TXDLYOVRDEN;
|
|
input TXDLYSRESET;
|
|
input TXDLYUPDOWN;
|
|
input TXELECIDLE;
|
|
input TXINHIBIT;
|
|
input TXPCSRESET;
|
|
input TXPDELECIDLEMODE;
|
|
input TXPHALIGN;
|
|
input TXPHALIGNEN;
|
|
input TXPHDLYPD;
|
|
input TXPHDLYRESET;
|
|
(* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *)
|
|
input TXPHDLYTSTCLK;
|
|
input TXPHINIT;
|
|
input TXPHOVRDEN;
|
|
input TXPISOPD;
|
|
input TXPMARESET;
|
|
input TXPOLARITY;
|
|
input TXPOSTCURSORINV;
|
|
input TXPRBSFORCEERR;
|
|
input TXPRECURSORINV;
|
|
input TXQPIBIASEN;
|
|
input TXQPISTRONGPDOWN;
|
|
input TXQPIWEAKPUP;
|
|
input TXSTARTSEQ;
|
|
input TXSWING;
|
|
input TXUSERRDY;
|
|
(* invertible_pin = "IS_TXUSRCLK2_INVERTED" *)
|
|
input TXUSRCLK2;
|
|
(* invertible_pin = "IS_TXUSRCLK_INVERTED" *)
|
|
input TXUSRCLK;
|
|
input [15:0] DRPDI;
|
|
input [15:0] GTRSVD;
|
|
input [15:0] PCSRSVDIN;
|
|
input [19:0] TSTIN;
|
|
input [1:0] RXELECIDLEMODE;
|
|
input [1:0] RXMONITORSEL;
|
|
input [1:0] RXPD;
|
|
input [1:0] RXSYSCLKSEL;
|
|
input [1:0] TXPD;
|
|
input [1:0] TXSYSCLKSEL;
|
|
input [2:0] CPLLREFCLKSEL;
|
|
input [2:0] LOOPBACK;
|
|
input [2:0] RXCHBONDLEVEL;
|
|
input [2:0] RXOUTCLKSEL;
|
|
input [2:0] RXPRBSSEL;
|
|
input [2:0] RXRATE;
|
|
input [2:0] TXBUFDIFFCTRL;
|
|
input [2:0] TXHEADER;
|
|
input [2:0] TXMARGIN;
|
|
input [2:0] TXOUTCLKSEL;
|
|
input [2:0] TXPRBSSEL;
|
|
input [2:0] TXRATE;
|
|
input [3:0] CLKRSVD;
|
|
input [3:0] TXDIFFCTRL;
|
|
input [4:0] PCSRSVDIN2;
|
|
input [4:0] PMARSVDIN2;
|
|
input [4:0] PMARSVDIN;
|
|
input [4:0] RXCHBONDI;
|
|
input [4:0] TXPOSTCURSOR;
|
|
input [4:0] TXPRECURSOR;
|
|
input [63:0] TXDATA;
|
|
input [6:0] TXMAINCURSOR;
|
|
input [6:0] TXSEQUENCE;
|
|
input [7:0] TX8B10BBYPASS;
|
|
input [7:0] TXCHARDISPMODE;
|
|
input [7:0] TXCHARDISPVAL;
|
|
input [7:0] TXCHARISK;
|
|
input [8:0] DRPADDR;
|
|
endmodule
|
|
|
|
module GTXE2_COMMON(DRPRDY, QPLLFBCLKLOST, QPLLLOCK, QPLLOUTCLK, QPLLOUTREFCLK, QPLLREFCLKLOST, REFCLKOUTMONITOR, DRPDO, QPLLDMONITOR, BGBYPASSB, BGMONITORENB, BGPDB, DRPCLK, DRPEN, DRPWE, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTSOUTHREFCLK0
|
|
, GTSOUTHREFCLK1, QPLLLOCKDETCLK, QPLLLOCKEN, QPLLOUTRESET, QPLLPD, QPLLRESET, RCALENB, DRPDI, QPLLRSVD1, QPLLREFCLKSEL, BGRCALOVRD, QPLLRSVD2, DRPADDR, PMARSVD);
|
|
parameter [63:0] BIAS_CFG = 64'h0000040000001000;
|
|
parameter [31:0] COMMON_CFG = 32'h00000000;
|
|
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0;
|
|
parameter [26:0] QPLL_CFG = 27'h0680181;
|
|
parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000;
|
|
parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000;
|
|
parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0;
|
|
parameter [9:0] QPLL_CP = 10'b0000011111;
|
|
parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0;
|
|
parameter [0:0] QPLL_DMONITOR_SEL = 1'b0;
|
|
parameter [9:0] QPLL_FBDIV = 10'b0000000000;
|
|
parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0;
|
|
parameter [0:0] QPLL_FBDIV_RATIO = 1'b0;
|
|
parameter [23:0] QPLL_INIT_CFG = 24'h000006;
|
|
parameter [15:0] QPLL_LOCK_CFG = 16'h21E8;
|
|
parameter [3:0] QPLL_LPF = 4'b1111;
|
|
parameter integer QPLL_REFCLK_DIV = 2;
|
|
parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001;
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter SIM_VERSION = "4.0";
|
|
output DRPRDY;
|
|
output QPLLFBCLKLOST;
|
|
output QPLLLOCK;
|
|
output QPLLOUTCLK;
|
|
output QPLLOUTREFCLK;
|
|
output QPLLREFCLKLOST;
|
|
output REFCLKOUTMONITOR;
|
|
output [15:0] DRPDO;
|
|
output [7:0] QPLLDMONITOR;
|
|
input BGBYPASSB;
|
|
input BGMONITORENB;
|
|
input BGPDB;
|
|
(* invertible_pin = "IS_DRPCLK_INVERTED" *)
|
|
input DRPCLK;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
(* invertible_pin = "IS_GTGREFCLK_INVERTED" *)
|
|
input GTGREFCLK;
|
|
input GTNORTHREFCLK0;
|
|
input GTNORTHREFCLK1;
|
|
input GTREFCLK0;
|
|
input GTREFCLK1;
|
|
input GTSOUTHREFCLK0;
|
|
input GTSOUTHREFCLK1;
|
|
(* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *)
|
|
input QPLLLOCKDETCLK;
|
|
input QPLLLOCKEN;
|
|
input QPLLOUTRESET;
|
|
input QPLLPD;
|
|
input QPLLRESET;
|
|
input RCALENB;
|
|
input [15:0] DRPDI;
|
|
input [15:0] QPLLRSVD1;
|
|
input [2:0] QPLLREFCLKSEL;
|
|
input [4:0] BGRCALOVRD;
|
|
input [4:0] QPLLRSVD2;
|
|
input [7:0] DRPADDR;
|
|
input [7:0] PMARSVD;
|
|
endmodule
|
|
|
|
module IBUFDS_GTE2(O, ODIV2, CEB, I, IB);
|
|
parameter CLKCM_CFG = "TRUE";
|
|
parameter CLKRCV_TRST = "TRUE";
|
|
parameter CLKSWING_CFG = "TRUE";
|
|
output O;
|
|
output ODIV2;
|
|
input CEB;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module GTHE3_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DRPDO, DRPRDY, EYESCANDATAERROR, GTHTXN, GTHTXP, GTPOWERGOOD, GTREFCLKMONITOR, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET, PCIESYNCTXSYNCDONE
|
|
, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCLKCORCNT, RXCOMINITDET, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET
|
|
, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHALIGNERR
|
|
, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXQPISENN, RXQPISENP, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDLYSRESETDONE
|
|
, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL, CPLLRESET
|
|
, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, EVODDPHICALDONE, EVODDPHICALSTART, EVODDPHIDRDEN, EVODDPHIDWREN, EVODDPHIXRDEN, EVODDPHIXWREN, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTHRXN, GTHRXP, GTNORTHREFCLK0, GTNORTHREFCLK1
|
|
, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRSVD, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, LOOPBACK, LPBKRXTXSEREN, LPBKTXRXSEREN, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE, PCSRSVDIN, PCSRSVDIN2, PMARSVDIN, QPLL0CLK, QPLL0REFCLK, QPLL1CLK
|
|
, QPLL1REFCLK, RESETOVRD, RSTCLKENTX, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCOMMADETEN, RXDFEAGCCTRL, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN
|
|
, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN
|
|
, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEVSEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXGEARBOXSLIP, RXLATCLK
|
|
, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTCFG, RXOSINTEN, RXOSINTHOLD, RXOSINTOVRDEN, RXOSINTSTROBE, RXOSINTTESTOVRDEN, RXOSOVRDEN
|
|
, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXPROGDIVRESET, RXQPIEN, RXRATE, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK, RXSLIPPMA
|
|
, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXBUFDIFFCTRL, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1, TXCTRL2, TXDATA, TXDATAEXTENDRSVD, TXDEEMPH
|
|
, TXDETECTRX, TXDIFFCTRL, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT, TXLATCLK, TXMAINCURSOR, TXMARGIN, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN
|
|
, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET, TXPOLARITY, TXPOSTCURSOR, TXPOSTCURSORINV, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPRECURSORINV, TXPROGDIVRESET
|
|
, TXQPIBIASEN, TXQPISTRONGPDOWN, TXQPIWEAKPUP, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2);
|
|
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_RESET = 1'b0;
|
|
parameter [15:0] ADAPT_CFG0 = 16'hF800;
|
|
parameter [15:0] ADAPT_CFG1 = 16'h0000;
|
|
parameter ALIGN_COMMA_DOUBLE = "FALSE";
|
|
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
|
|
parameter integer ALIGN_COMMA_WORD = 1;
|
|
parameter ALIGN_MCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
|
|
parameter ALIGN_PCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
|
|
parameter [0:0] A_RXOSCALRESET = 1'b0;
|
|
parameter [0:0] A_RXPROGDIVRESET = 1'b0;
|
|
parameter [0:0] A_TXPROGDIVRESET = 1'b0;
|
|
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
|
|
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
|
|
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
|
|
parameter integer CHAN_BOND_MAX_SKEW = 7;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
|
|
parameter integer CHAN_BOND_SEQ_LEN = 2;
|
|
parameter CLK_CORRECT_USE = "TRUE";
|
|
parameter CLK_COR_KEEP_IDLE = "FALSE";
|
|
parameter integer CLK_COR_MAX_LAT = 20;
|
|
parameter integer CLK_COR_MIN_LAT = 18;
|
|
parameter CLK_COR_PRECEDENCE = "TRUE";
|
|
parameter integer CLK_COR_REPEAT_WAIT = 0;
|
|
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CLK_COR_SEQ_2_USE = "FALSE";
|
|
parameter integer CLK_COR_SEQ_LEN = 2;
|
|
parameter [15:0] CPLL_CFG0 = 16'h20F8;
|
|
parameter [15:0] CPLL_CFG1 = 16'hA494;
|
|
parameter [15:0] CPLL_CFG2 = 16'hF001;
|
|
parameter [5:0] CPLL_CFG3 = 6'h00;
|
|
parameter integer CPLL_FBDIV = 4;
|
|
parameter integer CPLL_FBDIV_45 = 4;
|
|
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
|
|
parameter [7:0] CPLL_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
|
|
parameter integer CPLL_REFCLK_DIV = 1;
|
|
parameter [1:0] DDI_CTRL = 2'b00;
|
|
parameter integer DDI_REALIGN_WAIT = 15;
|
|
parameter DEC_MCOMMA_DETECT = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY = "TRUE";
|
|
parameter [0:0] DFE_D_X_REL_POS = 1'b0;
|
|
parameter [0:0] DFE_VCM_COMP_EN = 1'b0;
|
|
parameter [9:0] DMONITOR_CFG0 = 10'h000;
|
|
parameter [7:0] DMONITOR_CFG1 = 8'h00;
|
|
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
|
|
parameter [5:0] ES_CONTROL = 6'b000000;
|
|
parameter ES_ERRDET_EN = "FALSE";
|
|
parameter ES_EYE_SCAN_EN = "FALSE";
|
|
parameter [11:0] ES_HORZ_OFFSET = 12'h000;
|
|
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
|
|
parameter [4:0] ES_PRESCALE = 5'b00000;
|
|
parameter [15:0] ES_QUALIFIER0 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER1 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER2 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER3 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER4 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK0 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK1 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK2 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK3 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK4 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK0 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK1 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK2 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK3 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK4 = 16'h0000;
|
|
parameter [10:0] EVODD_PHI_CFG = 11'b00000000000;
|
|
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
|
|
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
|
|
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
|
|
parameter FTS_LANE_DESKEW_EN = "FALSE";
|
|
parameter [4:0] GEARBOX_MODE = 5'b00000;
|
|
parameter [0:0] GM_BIAS_SELECT = 1'b0;
|
|
parameter [0:0] LOCAL_MASTER = 1'b0;
|
|
parameter [1:0] OOBDIVCTL = 2'b00;
|
|
parameter [0:0] OOB_PWRUP = 1'b0;
|
|
parameter PCI3_AUTO_REALIGN = "FRST_SMPL";
|
|
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1;
|
|
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00;
|
|
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0;
|
|
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000;
|
|
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000;
|
|
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
|
|
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
|
|
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
|
|
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
|
|
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
|
|
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
|
|
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
|
|
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
|
|
parameter PCS_PCIE_EN = "FALSE";
|
|
parameter [15:0] PCS_RSVD0 = 16'b0000000000000000;
|
|
parameter [2:0] PCS_RSVD1 = 3'b000;
|
|
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
|
|
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
|
|
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
|
|
parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0;
|
|
parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0;
|
|
parameter [15:0] PMA_RSV1 = 16'h0000;
|
|
parameter [2:0] PROCESS_PAR = 3'b010;
|
|
parameter [0:0] RATE_SW_USE_DRP = 1'b0;
|
|
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
|
|
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
|
|
parameter RXBUF_ADDR_MODE = "FULL";
|
|
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
|
|
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
|
|
parameter RXBUF_EN = "TRUE";
|
|
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
|
|
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
|
|
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
|
|
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
|
|
parameter integer RXBUF_THRESH_OVFLW = 0;
|
|
parameter RXBUF_THRESH_OVRD = "FALSE";
|
|
parameter integer RXBUF_THRESH_UNDFLW = 4;
|
|
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
|
|
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXCDR_CFG0 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG1 = 16'h0080;
|
|
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG2 = 16'h07E6;
|
|
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG4 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG5 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000;
|
|
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
|
|
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080;
|
|
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0;
|
|
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42;
|
|
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
|
|
parameter [15:0] RXCFOK_CFG0 = 16'h4000;
|
|
parameter [15:0] RXCFOK_CFG1 = 16'h0060;
|
|
parameter [15:0] RXCFOK_CFG2 = 16'h000E;
|
|
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
|
|
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032;
|
|
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000;
|
|
parameter [15:0] RXDFE_CFG0 = 16'h0A00;
|
|
parameter [15:0] RXDFE_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_GC_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_GC_CFG1 = 16'h7840;
|
|
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
|
|
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H2_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_H3_CFG0 = 16'h4000;
|
|
parameter [15:0] RXDFE_H3_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_H4_CFG0 = 16'h2000;
|
|
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003;
|
|
parameter [15:0] RXDFE_H5_CFG0 = 16'h2000;
|
|
parameter [15:0] RXDFE_H5_CFG1 = 16'h0003;
|
|
parameter [15:0] RXDFE_H6_CFG0 = 16'h2000;
|
|
parameter [15:0] RXDFE_H6_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_H7_CFG0 = 16'h2000;
|
|
parameter [15:0] RXDFE_H7_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_H8_CFG0 = 16'h2000;
|
|
parameter [15:0] RXDFE_H8_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_H9_CFG0 = 16'h2000;
|
|
parameter [15:0] RXDFE_H9_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_HA_CFG0 = 16'h2000;
|
|
parameter [15:0] RXDFE_HA_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_HB_CFG0 = 16'h2000;
|
|
parameter [15:0] RXDFE_HB_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HC_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HD_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HE_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HF_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_OS_CFG0 = 16'h8000;
|
|
parameter [15:0] RXDFE_OS_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_UT_CFG0 = 16'h8000;
|
|
parameter [15:0] RXDFE_UT_CFG1 = 16'h0003;
|
|
parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00;
|
|
parameter [15:0] RXDFE_VP_CFG1 = 16'h0033;
|
|
parameter [15:0] RXDLY_CFG = 16'h001F;
|
|
parameter [15:0] RXDLY_LCFG = 16'h0030;
|
|
parameter RXELECIDLE_CFG = "Sigcfg_4";
|
|
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
|
|
parameter RXGEARBOX_EN = "FALSE";
|
|
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXLPM_CFG = 16'h0000;
|
|
parameter [15:0] RXLPM_GC_CFG = 16'h0000;
|
|
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
|
|
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
|
|
parameter [15:0] RXLPM_OS_CFG0 = 16'h8000;
|
|
parameter [15:0] RXLPM_OS_CFG1 = 16'h0002;
|
|
parameter [8:0] RXOOB_CFG = 9'b000000110;
|
|
parameter RXOOB_CLK_CFG = "PMA";
|
|
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
|
|
parameter integer RXOUT_DIV = 4;
|
|
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXPHBEACON_CFG = 16'h0000;
|
|
parameter [15:0] RXPHDLY_CFG = 16'h2020;
|
|
parameter [15:0] RXPHSAMP_CFG = 16'h2100;
|
|
parameter [15:0] RXPHSLIP_CFG = 16'h6622;
|
|
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [1:0] RXPI_CFG0 = 2'b00;
|
|
parameter [1:0] RXPI_CFG1 = 2'b00;
|
|
parameter [1:0] RXPI_CFG2 = 2'b00;
|
|
parameter [1:0] RXPI_CFG3 = 2'b00;
|
|
parameter [0:0] RXPI_CFG4 = 1'b0;
|
|
parameter [0:0] RXPI_CFG5 = 1'b1;
|
|
parameter [2:0] RXPI_CFG6 = 3'b000;
|
|
parameter [0:0] RXPI_LPM = 1'b0;
|
|
parameter [0:0] RXPI_VREFSEL = 1'b0;
|
|
parameter RXPMACLK_SEL = "DATA";
|
|
parameter [4:0] RXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
|
|
parameter integer RXPRBS_LINKACQ_CNT = 15;
|
|
parameter integer RXSLIDE_AUTO_WAIT = 7;
|
|
parameter RXSLIDE_MODE = "OFF";
|
|
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] RXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
|
|
parameter [0:0] RX_AFE_CM_EN = 1'b0;
|
|
parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4;
|
|
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
|
|
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
|
|
parameter integer RX_CLK25_DIV = 8;
|
|
parameter [0:0] RX_CLKMUX_EN = 1'b1;
|
|
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000;
|
|
parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
|
|
parameter [0:0] RX_CM_BUF_PD = 1'b0;
|
|
parameter [1:0] RX_CM_SEL = 2'b11;
|
|
parameter [3:0] RX_CM_TRIM = 4'b0100;
|
|
parameter [7:0] RX_CTLE3_LPF = 8'b00000000;
|
|
parameter integer RX_DATA_WIDTH = 20;
|
|
parameter [5:0] RX_DDI_SEL = 6'b000000;
|
|
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
|
|
parameter [3:0] RX_DFELPM_CFG0 = 4'b0110;
|
|
parameter [0:0] RX_DFELPM_CFG1 = 1'b0;
|
|
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
|
|
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
|
|
parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100;
|
|
parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01;
|
|
parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010;
|
|
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
|
|
parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010;
|
|
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
|
|
parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
|
|
parameter [0:0] RX_EN_HI_LR = 1'b0;
|
|
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
|
|
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
|
|
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00;
|
|
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0;
|
|
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
|
|
parameter integer RX_INT_DATAWIDTH = 1;
|
|
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
|
|
parameter real RX_PROGDIV_CFG = 4.0;
|
|
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
|
|
parameter integer RX_SIG_VALID_DLY = 11;
|
|
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
|
|
parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000;
|
|
parameter [1:0] RX_SUM_RES_CTRL = 2'b00;
|
|
parameter [3:0] RX_SUM_VCMTUNE = 4'b0000;
|
|
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
|
|
parameter [2:0] RX_SUM_VREF_TUNE = 3'b000;
|
|
parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
|
|
parameter [0:0] RX_WIDEMODE_CDR = 1'b0;
|
|
parameter RX_XCLK_SEL = "RXDES";
|
|
parameter integer SAS_MAX_COM = 64;
|
|
parameter integer SAS_MIN_COM = 36;
|
|
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
|
|
parameter [2:0] SATA_BURST_VAL = 3'b100;
|
|
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
|
|
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
|
|
parameter integer SATA_MAX_BURST = 8;
|
|
parameter integer SATA_MAX_INIT = 21;
|
|
parameter integer SATA_MAX_WAKE = 7;
|
|
parameter integer SATA_MIN_BURST = 4;
|
|
parameter integer SATA_MIN_INIT = 12;
|
|
parameter integer SATA_MIN_WAKE = 4;
|
|
parameter SHOW_REALIGN_COMMA = "TRUE";
|
|
parameter SIM_MODE = "FAST";
|
|
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0;
|
|
parameter integer SIM_VERSION = 2;
|
|
parameter [1:0] TAPDLY_SET_TX = 2'h0;
|
|
parameter [3:0] TEMPERATUR_PAR = 4'b0010;
|
|
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
|
|
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
|
|
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
|
|
parameter [7:0] TST_RSV0 = 8'h00;
|
|
parameter [7:0] TST_RSV1 = 8'h00;
|
|
parameter TXBUF_EN = "TRUE";
|
|
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
|
|
parameter [15:0] TXDLY_CFG = 16'h001F;
|
|
parameter [15:0] TXDLY_LCFG = 16'h0030;
|
|
parameter [3:0] TXDRVBIAS_N = 4'b1010;
|
|
parameter [3:0] TXDRVBIAS_P = 4'b1100;
|
|
parameter TXFIFO_ADDR_CFG = "LOW";
|
|
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
|
|
parameter TXGEARBOX_EN = "FALSE";
|
|
parameter integer TXOUT_DIV = 4;
|
|
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
|
|
parameter [15:0] TXPHDLY_CFG0 = 16'h2020;
|
|
parameter [15:0] TXPHDLY_CFG1 = 16'h0001;
|
|
parameter [15:0] TXPH_CFG = 16'h0980;
|
|
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [1:0] TXPI_CFG0 = 2'b00;
|
|
parameter [1:0] TXPI_CFG1 = 2'b00;
|
|
parameter [1:0] TXPI_CFG2 = 2'b00;
|
|
parameter [0:0] TXPI_CFG3 = 1'b0;
|
|
parameter [0:0] TXPI_CFG4 = 1'b1;
|
|
parameter [2:0] TXPI_CFG5 = 3'b000;
|
|
parameter [0:0] TXPI_GRAY_SEL = 1'b0;
|
|
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
|
|
parameter [0:0] TXPI_LPM = 1'b0;
|
|
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
|
|
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
|
|
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
|
|
parameter [0:0] TXPI_VREFSEL = 1'b0;
|
|
parameter [4:0] TXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] TXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
|
|
parameter integer TX_CLK25_DIV = 8;
|
|
parameter [0:0] TX_CLKMUX_EN = 1'b1;
|
|
parameter integer TX_DATA_WIDTH = 20;
|
|
parameter [5:0] TX_DCD_CFG = 6'b000010;
|
|
parameter [0:0] TX_DCD_EN = 1'b0;
|
|
parameter [5:0] TX_DEEMPH0 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH1 = 6'b000000;
|
|
parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
|
|
parameter TX_DRIVE_MODE = "DIRECT";
|
|
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
|
|
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
|
|
parameter [0:0] TX_EML_PHI_TUNE = 1'b0;
|
|
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
|
|
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
|
|
parameter integer TX_INT_DATAWIDTH = 1;
|
|
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
|
|
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
|
|
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
|
|
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
|
|
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
|
|
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
|
|
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
|
|
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
|
|
parameter [2:0] TX_MODE_SEL = 3'b000;
|
|
parameter [0:0] TX_PMADATA_OPT = 1'b0;
|
|
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
|
|
parameter TX_PROGCLK_SEL = "POSTPI";
|
|
parameter real TX_PROGDIV_CFG = 4.0;
|
|
parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
|
|
parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
|
|
parameter [2:0] TX_RXDETECT_REF = 3'b100;
|
|
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
|
|
parameter [0:0] TX_SARC_LPBK_ENB = 1'b0;
|
|
parameter TX_XCLK_SEL = "TXOUT";
|
|
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
|
|
parameter [1:0] WB_MODE = 2'b00;
|
|
output [2:0] BUFGTCE;
|
|
output [2:0] BUFGTCEMASK;
|
|
output [8:0] BUFGTDIV;
|
|
output [2:0] BUFGTRESET;
|
|
output [2:0] BUFGTRSTMASK;
|
|
output CPLLFBCLKLOST;
|
|
output CPLLLOCK;
|
|
output CPLLREFCLKLOST;
|
|
output [16:0] DMONITOROUT;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output EYESCANDATAERROR;
|
|
output GTHTXN;
|
|
output GTHTXP;
|
|
output GTPOWERGOOD;
|
|
output GTREFCLKMONITOR;
|
|
output PCIERATEGEN3;
|
|
output PCIERATEIDLE;
|
|
output [1:0] PCIERATEQPLLPD;
|
|
output [1:0] PCIERATEQPLLRESET;
|
|
output PCIESYNCTXSYNCDONE;
|
|
output PCIEUSERGEN3RDY;
|
|
output PCIEUSERPHYSTATUSRST;
|
|
output PCIEUSERRATESTART;
|
|
output [11:0] PCSRSVDOUT;
|
|
output PHYSTATUS;
|
|
output [7:0] PINRSRVDAS;
|
|
output RESETEXCEPTION;
|
|
output [2:0] RXBUFSTATUS;
|
|
output RXBYTEISALIGNED;
|
|
output RXBYTEREALIGN;
|
|
output RXCDRLOCK;
|
|
output RXCDRPHDONE;
|
|
output RXCHANBONDSEQ;
|
|
output RXCHANISALIGNED;
|
|
output RXCHANREALIGN;
|
|
output [4:0] RXCHBONDO;
|
|
output [1:0] RXCLKCORCNT;
|
|
output RXCOMINITDET;
|
|
output RXCOMMADET;
|
|
output RXCOMSASDET;
|
|
output RXCOMWAKEDET;
|
|
output [15:0] RXCTRL0;
|
|
output [15:0] RXCTRL1;
|
|
output [7:0] RXCTRL2;
|
|
output [7:0] RXCTRL3;
|
|
output [127:0] RXDATA;
|
|
output [7:0] RXDATAEXTENDRSVD;
|
|
output [1:0] RXDATAVALID;
|
|
output RXDLYSRESETDONE;
|
|
output RXELECIDLE;
|
|
output [5:0] RXHEADER;
|
|
output [1:0] RXHEADERVALID;
|
|
output [6:0] RXMONITOROUT;
|
|
output RXOSINTDONE;
|
|
output RXOSINTSTARTED;
|
|
output RXOSINTSTROBEDONE;
|
|
output RXOSINTSTROBESTARTED;
|
|
output RXOUTCLK;
|
|
output RXOUTCLKFABRIC;
|
|
output RXOUTCLKPCS;
|
|
output RXPHALIGNDONE;
|
|
output RXPHALIGNERR;
|
|
output RXPMARESETDONE;
|
|
output RXPRBSERR;
|
|
output RXPRBSLOCKED;
|
|
output RXPRGDIVRESETDONE;
|
|
output RXQPISENN;
|
|
output RXQPISENP;
|
|
output RXRATEDONE;
|
|
output RXRECCLKOUT;
|
|
output RXRESETDONE;
|
|
output RXSLIDERDY;
|
|
output RXSLIPDONE;
|
|
output RXSLIPOUTCLKRDY;
|
|
output RXSLIPPMARDY;
|
|
output [1:0] RXSTARTOFSEQ;
|
|
output [2:0] RXSTATUS;
|
|
output RXSYNCDONE;
|
|
output RXSYNCOUT;
|
|
output RXVALID;
|
|
output [1:0] TXBUFSTATUS;
|
|
output TXCOMFINISH;
|
|
output TXDLYSRESETDONE;
|
|
output TXOUTCLK;
|
|
output TXOUTCLKFABRIC;
|
|
output TXOUTCLKPCS;
|
|
output TXPHALIGNDONE;
|
|
output TXPHINITDONE;
|
|
output TXPMARESETDONE;
|
|
output TXPRGDIVRESETDONE;
|
|
output TXQPISENN;
|
|
output TXQPISENP;
|
|
output TXRATEDONE;
|
|
output TXRESETDONE;
|
|
output TXSYNCDONE;
|
|
output TXSYNCOUT;
|
|
input CFGRESET;
|
|
input CLKRSVD0;
|
|
input CLKRSVD1;
|
|
input CPLLLOCKDETCLK;
|
|
input CPLLLOCKEN;
|
|
input CPLLPD;
|
|
input [2:0] CPLLREFCLKSEL;
|
|
input CPLLRESET;
|
|
input DMONFIFORESET;
|
|
input DMONITORCLK;
|
|
input [8:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input EVODDPHICALDONE;
|
|
input EVODDPHICALSTART;
|
|
input EVODDPHIDRDEN;
|
|
input EVODDPHIDWREN;
|
|
input EVODDPHIXRDEN;
|
|
input EVODDPHIXWREN;
|
|
input EYESCANMODE;
|
|
input EYESCANRESET;
|
|
input EYESCANTRIGGER;
|
|
input GTGREFCLK;
|
|
input GTHRXN;
|
|
input GTHRXP;
|
|
input GTNORTHREFCLK0;
|
|
input GTNORTHREFCLK1;
|
|
input GTREFCLK0;
|
|
input GTREFCLK1;
|
|
input GTRESETSEL;
|
|
input [15:0] GTRSVD;
|
|
input GTRXRESET;
|
|
input GTSOUTHREFCLK0;
|
|
input GTSOUTHREFCLK1;
|
|
input GTTXRESET;
|
|
input [2:0] LOOPBACK;
|
|
input LPBKRXTXSEREN;
|
|
input LPBKTXRXSEREN;
|
|
input PCIEEQRXEQADAPTDONE;
|
|
input PCIERSTIDLE;
|
|
input PCIERSTTXSYNCSTART;
|
|
input PCIEUSERRATEDONE;
|
|
input [15:0] PCSRSVDIN;
|
|
input [4:0] PCSRSVDIN2;
|
|
input [4:0] PMARSVDIN;
|
|
input QPLL0CLK;
|
|
input QPLL0REFCLK;
|
|
input QPLL1CLK;
|
|
input QPLL1REFCLK;
|
|
input RESETOVRD;
|
|
input RSTCLKENTX;
|
|
input RX8B10BEN;
|
|
input RXBUFRESET;
|
|
input RXCDRFREQRESET;
|
|
input RXCDRHOLD;
|
|
input RXCDROVRDEN;
|
|
input RXCDRRESET;
|
|
input RXCDRRESETRSV;
|
|
input RXCHBONDEN;
|
|
input [4:0] RXCHBONDI;
|
|
input [2:0] RXCHBONDLEVEL;
|
|
input RXCHBONDMASTER;
|
|
input RXCHBONDSLAVE;
|
|
input RXCOMMADETEN;
|
|
input [1:0] RXDFEAGCCTRL;
|
|
input RXDFEAGCHOLD;
|
|
input RXDFEAGCOVRDEN;
|
|
input RXDFELFHOLD;
|
|
input RXDFELFOVRDEN;
|
|
input RXDFELPMRESET;
|
|
input RXDFETAP10HOLD;
|
|
input RXDFETAP10OVRDEN;
|
|
input RXDFETAP11HOLD;
|
|
input RXDFETAP11OVRDEN;
|
|
input RXDFETAP12HOLD;
|
|
input RXDFETAP12OVRDEN;
|
|
input RXDFETAP13HOLD;
|
|
input RXDFETAP13OVRDEN;
|
|
input RXDFETAP14HOLD;
|
|
input RXDFETAP14OVRDEN;
|
|
input RXDFETAP15HOLD;
|
|
input RXDFETAP15OVRDEN;
|
|
input RXDFETAP2HOLD;
|
|
input RXDFETAP2OVRDEN;
|
|
input RXDFETAP3HOLD;
|
|
input RXDFETAP3OVRDEN;
|
|
input RXDFETAP4HOLD;
|
|
input RXDFETAP4OVRDEN;
|
|
input RXDFETAP5HOLD;
|
|
input RXDFETAP5OVRDEN;
|
|
input RXDFETAP6HOLD;
|
|
input RXDFETAP6OVRDEN;
|
|
input RXDFETAP7HOLD;
|
|
input RXDFETAP7OVRDEN;
|
|
input RXDFETAP8HOLD;
|
|
input RXDFETAP8OVRDEN;
|
|
input RXDFETAP9HOLD;
|
|
input RXDFETAP9OVRDEN;
|
|
input RXDFEUTHOLD;
|
|
input RXDFEUTOVRDEN;
|
|
input RXDFEVPHOLD;
|
|
input RXDFEVPOVRDEN;
|
|
input RXDFEVSEN;
|
|
input RXDFEXYDEN;
|
|
input RXDLYBYPASS;
|
|
input RXDLYEN;
|
|
input RXDLYOVRDEN;
|
|
input RXDLYSRESET;
|
|
input [1:0] RXELECIDLEMODE;
|
|
input RXGEARBOXSLIP;
|
|
input RXLATCLK;
|
|
input RXLPMEN;
|
|
input RXLPMGCHOLD;
|
|
input RXLPMGCOVRDEN;
|
|
input RXLPMHFHOLD;
|
|
input RXLPMHFOVRDEN;
|
|
input RXLPMLFHOLD;
|
|
input RXLPMLFKLOVRDEN;
|
|
input RXLPMOSHOLD;
|
|
input RXLPMOSOVRDEN;
|
|
input RXMCOMMAALIGNEN;
|
|
input [1:0] RXMONITORSEL;
|
|
input RXOOBRESET;
|
|
input RXOSCALRESET;
|
|
input RXOSHOLD;
|
|
input [3:0] RXOSINTCFG;
|
|
input RXOSINTEN;
|
|
input RXOSINTHOLD;
|
|
input RXOSINTOVRDEN;
|
|
input RXOSINTSTROBE;
|
|
input RXOSINTTESTOVRDEN;
|
|
input RXOSOVRDEN;
|
|
input [2:0] RXOUTCLKSEL;
|
|
input RXPCOMMAALIGNEN;
|
|
input RXPCSRESET;
|
|
input [1:0] RXPD;
|
|
input RXPHALIGN;
|
|
input RXPHALIGNEN;
|
|
input RXPHDLYPD;
|
|
input RXPHDLYRESET;
|
|
input RXPHOVRDEN;
|
|
input [1:0] RXPLLCLKSEL;
|
|
input RXPMARESET;
|
|
input RXPOLARITY;
|
|
input RXPRBSCNTRESET;
|
|
input [3:0] RXPRBSSEL;
|
|
input RXPROGDIVRESET;
|
|
input RXQPIEN;
|
|
input [2:0] RXRATE;
|
|
input RXRATEMODE;
|
|
input RXSLIDE;
|
|
input RXSLIPOUTCLK;
|
|
input RXSLIPPMA;
|
|
input RXSYNCALLIN;
|
|
input RXSYNCIN;
|
|
input RXSYNCMODE;
|
|
input [1:0] RXSYSCLKSEL;
|
|
input RXUSERRDY;
|
|
input RXUSRCLK;
|
|
input RXUSRCLK2;
|
|
input SIGVALIDCLK;
|
|
input [19:0] TSTIN;
|
|
input [7:0] TX8B10BBYPASS;
|
|
input TX8B10BEN;
|
|
input [2:0] TXBUFDIFFCTRL;
|
|
input TXCOMINIT;
|
|
input TXCOMSAS;
|
|
input TXCOMWAKE;
|
|
input [15:0] TXCTRL0;
|
|
input [15:0] TXCTRL1;
|
|
input [7:0] TXCTRL2;
|
|
input [127:0] TXDATA;
|
|
input [7:0] TXDATAEXTENDRSVD;
|
|
input TXDEEMPH;
|
|
input TXDETECTRX;
|
|
input [3:0] TXDIFFCTRL;
|
|
input TXDIFFPD;
|
|
input TXDLYBYPASS;
|
|
input TXDLYEN;
|
|
input TXDLYHOLD;
|
|
input TXDLYOVRDEN;
|
|
input TXDLYSRESET;
|
|
input TXDLYUPDOWN;
|
|
input TXELECIDLE;
|
|
input [5:0] TXHEADER;
|
|
input TXINHIBIT;
|
|
input TXLATCLK;
|
|
input [6:0] TXMAINCURSOR;
|
|
input [2:0] TXMARGIN;
|
|
input [2:0] TXOUTCLKSEL;
|
|
input TXPCSRESET;
|
|
input [1:0] TXPD;
|
|
input TXPDELECIDLEMODE;
|
|
input TXPHALIGN;
|
|
input TXPHALIGNEN;
|
|
input TXPHDLYPD;
|
|
input TXPHDLYRESET;
|
|
input TXPHDLYTSTCLK;
|
|
input TXPHINIT;
|
|
input TXPHOVRDEN;
|
|
input TXPIPPMEN;
|
|
input TXPIPPMOVRDEN;
|
|
input TXPIPPMPD;
|
|
input TXPIPPMSEL;
|
|
input [4:0] TXPIPPMSTEPSIZE;
|
|
input TXPISOPD;
|
|
input [1:0] TXPLLCLKSEL;
|
|
input TXPMARESET;
|
|
input TXPOLARITY;
|
|
input [4:0] TXPOSTCURSOR;
|
|
input TXPOSTCURSORINV;
|
|
input TXPRBSFORCEERR;
|
|
input [3:0] TXPRBSSEL;
|
|
input [4:0] TXPRECURSOR;
|
|
input TXPRECURSORINV;
|
|
input TXPROGDIVRESET;
|
|
input TXQPIBIASEN;
|
|
input TXQPISTRONGPDOWN;
|
|
input TXQPIWEAKPUP;
|
|
input [2:0] TXRATE;
|
|
input TXRATEMODE;
|
|
input [6:0] TXSEQUENCE;
|
|
input TXSWING;
|
|
input TXSYNCALLIN;
|
|
input TXSYNCIN;
|
|
input TXSYNCMODE;
|
|
input [1:0] TXSYSCLKSEL;
|
|
input TXUSERRDY;
|
|
input TXUSRCLK;
|
|
input TXUSRCLK2;
|
|
endmodule
|
|
|
|
module GTHE3_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0_SEL, RXRECCLK1_SEL, BGBYPASSB
|
|
, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11, GTREFCLK00, GTREFCLK01, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01
|
|
, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0CLKRSVD1, QPLL0LOCKDETCLK, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0, QPLL1CLKRSVD1, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1, QPLLRSVD2, QPLLRSVD3
|
|
, QPLLRSVD4, RCALENB);
|
|
parameter [15:0] BIAS_CFG0 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG1 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG2 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG3 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG4 = 16'h0000;
|
|
parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000;
|
|
parameter [15:0] COMMON_CFG0 = 16'h0000;
|
|
parameter [15:0] COMMON_CFG1 = 16'h0000;
|
|
parameter [15:0] POR_CFG = 16'h0004;
|
|
parameter [15:0] QPLL0_CFG0 = 16'h3018;
|
|
parameter [15:0] QPLL0_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
|
|
parameter [15:0] QPLL0_CFG2 = 16'h0000;
|
|
parameter [15:0] QPLL0_CFG2_G3 = 16'h0000;
|
|
parameter [15:0] QPLL0_CFG3 = 16'h0120;
|
|
parameter [15:0] QPLL0_CFG4 = 16'h0009;
|
|
parameter [9:0] QPLL0_CP = 10'b0000011111;
|
|
parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
|
|
parameter integer QPLL0_FBDIV = 66;
|
|
parameter integer QPLL0_FBDIV_G3 = 80;
|
|
parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000;
|
|
parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
|
|
parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h01E8;
|
|
parameter [9:0] QPLL0_LPF = 10'b1111111111;
|
|
parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
|
|
parameter integer QPLL0_REFCLK_DIV = 2;
|
|
parameter [15:0] QPLL0_SDM_CFG0 = 16'b0000000000000000;
|
|
parameter [15:0] QPLL0_SDM_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] QPLL0_SDM_CFG2 = 16'b0000000000000000;
|
|
parameter [15:0] QPLL1_CFG0 = 16'h3018;
|
|
parameter [15:0] QPLL1_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
|
|
parameter [15:0] QPLL1_CFG2 = 16'h0000;
|
|
parameter [15:0] QPLL1_CFG2_G3 = 16'h0000;
|
|
parameter [15:0] QPLL1_CFG3 = 16'h0120;
|
|
parameter [15:0] QPLL1_CFG4 = 16'h0009;
|
|
parameter [9:0] QPLL1_CP = 10'b0000011111;
|
|
parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
|
|
parameter integer QPLL1_FBDIV = 66;
|
|
parameter integer QPLL1_FBDIV_G3 = 80;
|
|
parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000;
|
|
parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
|
|
parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
|
|
parameter [9:0] QPLL1_LPF = 10'b1111111111;
|
|
parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
|
|
parameter integer QPLL1_REFCLK_DIV = 2;
|
|
parameter [15:0] QPLL1_SDM_CFG0 = 16'b0000000000000000;
|
|
parameter [15:0] QPLL1_SDM_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] QPLL1_SDM_CFG2 = 16'b0000000000000000;
|
|
parameter [15:0] RSVD_ATTR0 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR1 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR2 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR3 = 16'h0000;
|
|
parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
|
|
parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
|
|
parameter [0:0] SARC_EN = 1'b1;
|
|
parameter [0:0] SARC_SEL = 1'b0;
|
|
parameter [15:0] SDM0DATA1_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM0DATA1_1 = 9'b000000000;
|
|
parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
|
|
parameter [0:0] SDM0_DATA_PIN_SEL = 1'b0;
|
|
parameter [0:0] SDM0_WIDTH_PIN_SEL = 1'b0;
|
|
parameter [15:0] SDM1DATA1_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM1DATA1_1 = 9'b000000000;
|
|
parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
|
|
parameter [0:0] SDM1_DATA_PIN_SEL = 1'b0;
|
|
parameter [0:0] SDM1_WIDTH_PIN_SEL = 1'b0;
|
|
parameter SIM_MODE = "FAST";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter integer SIM_VERSION = 2;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output [7:0] PMARSVDOUT0;
|
|
output [7:0] PMARSVDOUT1;
|
|
output QPLL0FBCLKLOST;
|
|
output QPLL0LOCK;
|
|
output QPLL0OUTCLK;
|
|
output QPLL0OUTREFCLK;
|
|
output QPLL0REFCLKLOST;
|
|
output QPLL1FBCLKLOST;
|
|
output QPLL1LOCK;
|
|
output QPLL1OUTCLK;
|
|
output QPLL1OUTREFCLK;
|
|
output QPLL1REFCLKLOST;
|
|
output [7:0] QPLLDMONITOR0;
|
|
output [7:0] QPLLDMONITOR1;
|
|
output REFCLKOUTMONITOR0;
|
|
output REFCLKOUTMONITOR1;
|
|
output [1:0] RXRECCLK0_SEL;
|
|
output [1:0] RXRECCLK1_SEL;
|
|
input BGBYPASSB;
|
|
input BGMONITORENB;
|
|
input BGPDB;
|
|
input [4:0] BGRCALOVRD;
|
|
input BGRCALOVRDENB;
|
|
input [8:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input GTGREFCLK0;
|
|
input GTGREFCLK1;
|
|
input GTNORTHREFCLK00;
|
|
input GTNORTHREFCLK01;
|
|
input GTNORTHREFCLK10;
|
|
input GTNORTHREFCLK11;
|
|
input GTREFCLK00;
|
|
input GTREFCLK01;
|
|
input GTREFCLK10;
|
|
input GTREFCLK11;
|
|
input GTSOUTHREFCLK00;
|
|
input GTSOUTHREFCLK01;
|
|
input GTSOUTHREFCLK10;
|
|
input GTSOUTHREFCLK11;
|
|
input [7:0] PMARSVD0;
|
|
input [7:0] PMARSVD1;
|
|
input QPLL0CLKRSVD0;
|
|
input QPLL0CLKRSVD1;
|
|
input QPLL0LOCKDETCLK;
|
|
input QPLL0LOCKEN;
|
|
input QPLL0PD;
|
|
input [2:0] QPLL0REFCLKSEL;
|
|
input QPLL0RESET;
|
|
input QPLL1CLKRSVD0;
|
|
input QPLL1CLKRSVD1;
|
|
input QPLL1LOCKDETCLK;
|
|
input QPLL1LOCKEN;
|
|
input QPLL1PD;
|
|
input [2:0] QPLL1REFCLKSEL;
|
|
input QPLL1RESET;
|
|
input [7:0] QPLLRSVD1;
|
|
input [4:0] QPLLRSVD2;
|
|
input [4:0] QPLLRSVD3;
|
|
input [7:0] QPLLRSVD4;
|
|
input RCALENB;
|
|
endmodule
|
|
|
|
module GTYE3_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DRPDO, DRPRDY, EYESCANDATAERROR, GTPOWERGOOD, GTREFCLKMONITOR, GTYTXN, GTYTXP, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET, PCIESYNCTXSYNCDONE
|
|
, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCKCALDONE, RXCLKCORCNT, RXCOMINITDET, RXCOMMADET, RXCOMSASDET
|
|
, RXCOMWAKEDET, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE
|
|
, RXPHALIGNERR, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDCCDONE, TXDLYSRESETDONE
|
|
, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CDRSTEPDIR, CDRSTEPSQ, CDRSTEPSX, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL
|
|
, CPLLRESET, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, ELPCALDVORWREN, ELPCALPAORWREN, EVODDPHICALDONE, EVODDPHICALSTART, EVODDPHIDRDEN, EVODDPHIDWREN, EVODDPHIXRDEN, EVODDPHIXWREN, EYESCANMODE, EYESCANRESET, EYESCANTRIGGER, GTGREFCLK, GTNORTHREFCLK0
|
|
, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRESETSEL, GTRSVD, GTRXRESET, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, GTYRXN, GTYRXP, LOOPBACK, LOOPRSVD, LPBKRXTXSEREN, LPBKTXRXSEREN, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE, PCSRSVDIN, PCSRSVDIN2
|
|
, PMARSVDIN, QPLL0CLK, QPLL0REFCLK, QPLL1CLK, QPLL1REFCLK, RESETOVRD, RSTCLKENTX, RX8B10BEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCDRRESETRSV, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCKCALRESET, RXCOMMADETEN
|
|
, RXDCCFORCESTART, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD
|
|
, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEVSEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN
|
|
, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXGEARBOXSLIP, RXLATCLK, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSINTCFG, RXOSINTEN
|
|
, RXOSINTHOLD, RXOSINTOVRDEN, RXOSINTSTROBE, RXOSINTTESTOVRDEN, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXPROGDIVRESET, RXRATE
|
|
, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK, RXSLIPPMA, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXBUFDIFFCTRL, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1
|
|
, TXCTRL2, TXDATA, TXDATAEXTENDRSVD, TXDCCFORCESTART, TXDCCRESET, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDIFFPD, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXELFORCESTART, TXHEADER, TXINHIBIT, TXLATCLK, TXMAINCURSOR
|
|
, TXMARGIN, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET, TXPOLARITY
|
|
, TXPOSTCURSOR, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPROGDIVRESET, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2);
|
|
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_RESET = 1'b0;
|
|
parameter [15:0] ADAPT_CFG0 = 16'h9200;
|
|
parameter [15:0] ADAPT_CFG1 = 16'h801C;
|
|
parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000;
|
|
parameter ALIGN_COMMA_DOUBLE = "FALSE";
|
|
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
|
|
parameter integer ALIGN_COMMA_WORD = 1;
|
|
parameter ALIGN_MCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
|
|
parameter ALIGN_PCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
|
|
parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0;
|
|
parameter [0:0] A_RXOSCALRESET = 1'b0;
|
|
parameter [0:0] A_RXPROGDIVRESET = 1'b0;
|
|
parameter [4:0] A_TXDIFFCTRL = 5'b01100;
|
|
parameter [0:0] A_TXPROGDIVRESET = 1'b0;
|
|
parameter [0:0] CAPBYPASS_FORCE = 1'b0;
|
|
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
|
|
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
|
|
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
|
|
parameter integer CHAN_BOND_MAX_SKEW = 7;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
|
|
parameter integer CHAN_BOND_SEQ_LEN = 2;
|
|
parameter [15:0] CH_HSPMUX = 16'h0000;
|
|
parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL_RSVD0 = 16'h0000;
|
|
parameter [15:0] CKCAL_RSVD1 = 16'h0000;
|
|
parameter CLK_CORRECT_USE = "TRUE";
|
|
parameter CLK_COR_KEEP_IDLE = "FALSE";
|
|
parameter integer CLK_COR_MAX_LAT = 20;
|
|
parameter integer CLK_COR_MIN_LAT = 18;
|
|
parameter CLK_COR_PRECEDENCE = "TRUE";
|
|
parameter integer CLK_COR_REPEAT_WAIT = 0;
|
|
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CLK_COR_SEQ_2_USE = "FALSE";
|
|
parameter integer CLK_COR_SEQ_LEN = 2;
|
|
parameter [15:0] CPLL_CFG0 = 16'h20F8;
|
|
parameter [15:0] CPLL_CFG1 = 16'hA494;
|
|
parameter [15:0] CPLL_CFG2 = 16'hF001;
|
|
parameter [5:0] CPLL_CFG3 = 6'h00;
|
|
parameter integer CPLL_FBDIV = 4;
|
|
parameter integer CPLL_FBDIV_45 = 4;
|
|
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
|
|
parameter [7:0] CPLL_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
|
|
parameter integer CPLL_REFCLK_DIV = 1;
|
|
parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000;
|
|
parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0;
|
|
parameter [1:0] DDI_CTRL = 2'b00;
|
|
parameter integer DDI_REALIGN_WAIT = 15;
|
|
parameter DEC_MCOMMA_DETECT = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY = "TRUE";
|
|
parameter [0:0] DFE_D_X_REL_POS = 1'b0;
|
|
parameter [0:0] DFE_VCM_COMP_EN = 1'b0;
|
|
parameter [9:0] DMONITOR_CFG0 = 10'h000;
|
|
parameter [7:0] DMONITOR_CFG1 = 8'h00;
|
|
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
|
|
parameter [5:0] ES_CONTROL = 6'b000000;
|
|
parameter ES_ERRDET_EN = "FALSE";
|
|
parameter ES_EYE_SCAN_EN = "FALSE";
|
|
parameter [11:0] ES_HORZ_OFFSET = 12'h000;
|
|
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
|
|
parameter [4:0] ES_PRESCALE = 5'b00000;
|
|
parameter [15:0] ES_QUALIFIER0 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER1 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER2 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER3 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER4 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER5 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER6 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER7 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER8 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER9 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK0 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK1 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK2 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK3 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK4 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK5 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK6 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK7 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK8 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK9 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK0 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK1 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK2 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK3 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK4 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK5 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK6 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK7 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK8 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK9 = 16'h0000;
|
|
parameter [10:0] EVODD_PHI_CFG = 11'b00000000000;
|
|
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
|
|
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
|
|
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
|
|
parameter FTS_LANE_DESKEW_EN = "FALSE";
|
|
parameter [4:0] GEARBOX_MODE = 5'b00000;
|
|
parameter [0:0] GM_BIAS_SELECT = 1'b0;
|
|
parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0;
|
|
parameter [0:0] LOCAL_MASTER = 1'b0;
|
|
parameter [15:0] LOOP0_CFG = 16'h0000;
|
|
parameter [15:0] LOOP10_CFG = 16'h0000;
|
|
parameter [15:0] LOOP11_CFG = 16'h0000;
|
|
parameter [15:0] LOOP12_CFG = 16'h0000;
|
|
parameter [15:0] LOOP13_CFG = 16'h0000;
|
|
parameter [15:0] LOOP1_CFG = 16'h0000;
|
|
parameter [15:0] LOOP2_CFG = 16'h0000;
|
|
parameter [15:0] LOOP3_CFG = 16'h0000;
|
|
parameter [15:0] LOOP4_CFG = 16'h0000;
|
|
parameter [15:0] LOOP5_CFG = 16'h0000;
|
|
parameter [15:0] LOOP6_CFG = 16'h0000;
|
|
parameter [15:0] LOOP7_CFG = 16'h0000;
|
|
parameter [15:0] LOOP8_CFG = 16'h0000;
|
|
parameter [15:0] LOOP9_CFG = 16'h0000;
|
|
parameter [2:0] LPBK_BIAS_CTRL = 3'b000;
|
|
parameter [0:0] LPBK_EN_RCAL_B = 1'b0;
|
|
parameter [3:0] LPBK_EXT_RCAL = 4'b0000;
|
|
parameter [3:0] LPBK_RG_CTRL = 4'b0000;
|
|
parameter [1:0] OOBDIVCTL = 2'b00;
|
|
parameter [0:0] OOB_PWRUP = 1'b0;
|
|
parameter PCI3_AUTO_REALIGN = "FRST_SMPL";
|
|
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1;
|
|
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00;
|
|
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0;
|
|
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000;
|
|
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000;
|
|
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
|
|
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
|
|
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
|
|
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
|
|
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
|
|
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
|
|
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
|
|
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
|
|
parameter PCS_PCIE_EN = "FALSE";
|
|
parameter [15:0] PCS_RSVD0 = 16'b0000000000000000;
|
|
parameter [2:0] PCS_RSVD1 = 3'b000;
|
|
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
|
|
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
|
|
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
|
|
parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0;
|
|
parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0;
|
|
parameter [15:0] PMA_RSV0 = 16'h0000;
|
|
parameter [15:0] PMA_RSV1 = 16'h0000;
|
|
parameter integer PREIQ_FREQ_BST = 0;
|
|
parameter [2:0] PROCESS_PAR = 3'b010;
|
|
parameter [0:0] RATE_SW_USE_DRP = 1'b0;
|
|
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
|
|
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
|
|
parameter RXBUF_ADDR_MODE = "FULL";
|
|
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
|
|
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
|
|
parameter RXBUF_EN = "TRUE";
|
|
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
|
|
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
|
|
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
|
|
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
|
|
parameter integer RXBUF_THRESH_OVFLW = 0;
|
|
parameter RXBUF_THRESH_OVRD = "FALSE";
|
|
parameter integer RXBUF_THRESH_UNDFLW = 4;
|
|
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
|
|
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXCDR_CFG0 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG1 = 16'h0300;
|
|
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300;
|
|
parameter [15:0] RXCDR_CFG2 = 16'h0060;
|
|
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060;
|
|
parameter [15:0] RXCDR_CFG3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG4 = 16'h0002;
|
|
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002;
|
|
parameter [15:0] RXCDR_CFG5 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000;
|
|
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
|
|
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001;
|
|
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000;
|
|
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000;
|
|
parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000;
|
|
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
|
|
parameter [1:0] RXCFOKDONE_SRC = 2'b00;
|
|
parameter [15:0] RXCFOK_CFG0 = 16'h3E00;
|
|
parameter [15:0] RXCFOK_CFG1 = 16'h0042;
|
|
parameter [15:0] RXCFOK_CFG2 = 16'h002D;
|
|
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
|
|
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022;
|
|
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100;
|
|
parameter [15:0] RXDFE_CFG0 = 16'h4C00;
|
|
parameter [15:0] RXDFE_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00;
|
|
parameter [15:0] RXDFE_GC_CFG1 = 16'h1900;
|
|
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
|
|
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H2_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H3_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H3_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H4_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003;
|
|
parameter [15:0] RXDFE_H5_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H5_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H6_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H6_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H7_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H7_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H8_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H8_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H9_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H9_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HA_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HA_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HB_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HB_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HC_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HD_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HE_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HF_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_OS_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_OS_CFG1 = 16'h0200;
|
|
parameter [0:0] RXDFE_PWR_SAVING = 1'b0;
|
|
parameter [15:0] RXDFE_UT_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_UT_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_VP_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_VP_CFG1 = 16'h0022;
|
|
parameter [15:0] RXDLY_CFG = 16'h001F;
|
|
parameter [15:0] RXDLY_LCFG = 16'h0030;
|
|
parameter RXELECIDLE_CFG = "SIGCFG_4";
|
|
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
|
|
parameter RXGEARBOX_EN = "FALSE";
|
|
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXLPM_CFG = 16'h0000;
|
|
parameter [15:0] RXLPM_GC_CFG = 16'h0200;
|
|
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
|
|
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
|
|
parameter [15:0] RXLPM_OS_CFG0 = 16'h0400;
|
|
parameter [15:0] RXLPM_OS_CFG1 = 16'h0000;
|
|
parameter [8:0] RXOOB_CFG = 9'b000000110;
|
|
parameter RXOOB_CLK_CFG = "PMA";
|
|
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
|
|
parameter integer RXOUT_DIV = 4;
|
|
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXPHBEACON_CFG = 16'h0000;
|
|
parameter [15:0] RXPHDLY_CFG = 16'h2020;
|
|
parameter [15:0] RXPHSAMP_CFG = 16'h2100;
|
|
parameter [15:0] RXPHSLIP_CFG = 16'h9933;
|
|
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0;
|
|
parameter [15:0] RXPI_CFG = 16'h0100;
|
|
parameter [0:0] RXPI_LPM = 1'b0;
|
|
parameter [15:0] RXPI_RSV0 = 16'h0000;
|
|
parameter [1:0] RXPI_SEL_LC = 2'b00;
|
|
parameter [1:0] RXPI_STARTCODE = 2'b00;
|
|
parameter [0:0] RXPI_VREFSEL = 1'b0;
|
|
parameter RXPMACLK_SEL = "DATA";
|
|
parameter [4:0] RXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
|
|
parameter integer RXPRBS_LINKACQ_CNT = 15;
|
|
parameter integer RXSLIDE_AUTO_WAIT = 7;
|
|
parameter RXSLIDE_MODE = "OFF";
|
|
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] RXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
|
|
parameter [0:0] RX_AFE_CM_EN = 1'b0;
|
|
parameter [15:0] RX_BIAS_CFG0 = 16'h1534;
|
|
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
|
|
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
|
|
parameter integer RX_CLK25_DIV = 8;
|
|
parameter [0:0] RX_CLKMUX_EN = 1'b1;
|
|
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000;
|
|
parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
|
|
parameter [0:0] RX_CM_BUF_PD = 1'b0;
|
|
parameter integer RX_CM_SEL = 3;
|
|
parameter integer RX_CM_TRIM = 10;
|
|
parameter [0:0] RX_CTLE1_KHKL = 1'b0;
|
|
parameter [0:0] RX_CTLE2_KHKL = 1'b0;
|
|
parameter [0:0] RX_CTLE3_AGC = 1'b0;
|
|
parameter integer RX_DATA_WIDTH = 20;
|
|
parameter [5:0] RX_DDI_SEL = 6'b000000;
|
|
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
|
|
parameter [2:0] RX_DEGEN_CTRL = 3'b010;
|
|
parameter integer RX_DFELPM_CFG0 = 6;
|
|
parameter [0:0] RX_DFELPM_CFG1 = 1'b0;
|
|
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
|
|
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
|
|
parameter integer RX_DFE_AGC_CFG1 = 4;
|
|
parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1;
|
|
parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2;
|
|
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
|
|
parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010;
|
|
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
|
|
parameter [0:0] RX_DIV2_MODE_B = 1'b0;
|
|
parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
|
|
parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0;
|
|
parameter [0:0] RX_EN_HI_LR = 1'b0;
|
|
parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000;
|
|
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
|
|
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
|
|
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00;
|
|
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0;
|
|
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
|
|
parameter integer RX_INT_DATAWIDTH = 1;
|
|
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
|
|
parameter real RX_PROGDIV_CFG = 0.0;
|
|
parameter [15:0] RX_PROGDIV_RATE = 16'h0001;
|
|
parameter [3:0] RX_RESLOAD_CTRL = 4'b0000;
|
|
parameter [0:0] RX_RESLOAD_OVRD = 1'b0;
|
|
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
|
|
parameter integer RX_SIG_VALID_DLY = 11;
|
|
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
|
|
parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000;
|
|
parameter [3:0] RX_SUM_VCMTUNE = 4'b1000;
|
|
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
|
|
parameter [2:0] RX_SUM_VREF_TUNE = 3'b100;
|
|
parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
|
|
parameter [2:0] RX_VREG_CTRL = 3'b101;
|
|
parameter [0:0] RX_VREG_PDB = 1'b1;
|
|
parameter [1:0] RX_WIDEMODE_CDR = 2'b01;
|
|
parameter RX_XCLK_SEL = "RXDES";
|
|
parameter [0:0] RX_XMODE_SEL = 1'b0;
|
|
parameter integer SAS_MAX_COM = 64;
|
|
parameter integer SAS_MIN_COM = 36;
|
|
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
|
|
parameter [2:0] SATA_BURST_VAL = 3'b100;
|
|
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
|
|
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
|
|
parameter integer SATA_MAX_BURST = 8;
|
|
parameter integer SATA_MAX_INIT = 21;
|
|
parameter integer SATA_MAX_WAKE = 7;
|
|
parameter integer SATA_MIN_BURST = 4;
|
|
parameter integer SATA_MIN_INIT = 12;
|
|
parameter integer SATA_MIN_WAKE = 4;
|
|
parameter SHOW_REALIGN_COMMA = "TRUE";
|
|
parameter SIM_MODE = "FAST";
|
|
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0;
|
|
parameter integer SIM_VERSION = 2;
|
|
parameter [1:0] TAPDLY_SET_TX = 2'h0;
|
|
parameter [3:0] TEMPERATURE_PAR = 4'b0010;
|
|
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
|
|
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
|
|
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
|
|
parameter [7:0] TST_RSV0 = 8'h00;
|
|
parameter [7:0] TST_RSV1 = 8'h00;
|
|
parameter TXBUF_EN = "TRUE";
|
|
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
|
|
parameter [15:0] TXDLY_CFG = 16'h001F;
|
|
parameter [15:0] TXDLY_LCFG = 16'h0030;
|
|
parameter TXFIFO_ADDR_CFG = "LOW";
|
|
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
|
|
parameter TXGEARBOX_EN = "FALSE";
|
|
parameter integer TXOUT_DIV = 4;
|
|
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
|
|
parameter [15:0] TXPHDLY_CFG0 = 16'h2020;
|
|
parameter [15:0] TXPHDLY_CFG1 = 16'h0001;
|
|
parameter [15:0] TXPH_CFG = 16'h0123;
|
|
parameter [15:0] TXPH_CFG2 = 16'h0000;
|
|
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [1:0] TXPI_CFG0 = 2'b00;
|
|
parameter [1:0] TXPI_CFG1 = 2'b00;
|
|
parameter [1:0] TXPI_CFG2 = 2'b00;
|
|
parameter [0:0] TXPI_CFG3 = 1'b0;
|
|
parameter [0:0] TXPI_CFG4 = 1'b1;
|
|
parameter [2:0] TXPI_CFG5 = 3'b000;
|
|
parameter [0:0] TXPI_GRAY_SEL = 1'b0;
|
|
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
|
|
parameter [0:0] TXPI_LPM = 1'b0;
|
|
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
|
|
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
|
|
parameter [15:0] TXPI_RSV0 = 16'h0000;
|
|
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
|
|
parameter [0:0] TXPI_VREFSEL = 1'b0;
|
|
parameter [4:0] TXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] TXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
|
|
parameter integer TX_CLK25_DIV = 8;
|
|
parameter [0:0] TX_CLKMUX_EN = 1'b1;
|
|
parameter [0:0] TX_CLKREG_PDB = 1'b0;
|
|
parameter [2:0] TX_CLKREG_SET = 3'b000;
|
|
parameter integer TX_DATA_WIDTH = 20;
|
|
parameter [5:0] TX_DCD_CFG = 6'b000010;
|
|
parameter [0:0] TX_DCD_EN = 1'b0;
|
|
parameter [5:0] TX_DEEMPH0 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH1 = 6'b000000;
|
|
parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
|
|
parameter TX_DRIVE_MODE = "DIRECT";
|
|
parameter integer TX_DRVMUX_CTRL = 2;
|
|
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
|
|
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
|
|
parameter [0:0] TX_EML_PHI_TUNE = 1'b0;
|
|
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
|
|
parameter [0:0] TX_FIFO_BYP_EN = 1'b0;
|
|
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
|
|
parameter integer TX_INT_DATAWIDTH = 1;
|
|
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
|
|
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
|
|
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
|
|
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
|
|
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
|
|
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
|
|
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
|
|
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
|
|
parameter [2:0] TX_MODE_SEL = 3'b000;
|
|
parameter [15:0] TX_PHICAL_CFG0 = 16'h0000;
|
|
parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00;
|
|
parameter [15:0] TX_PHICAL_CFG2 = 16'h0000;
|
|
parameter integer TX_PI_BIASSET = 0;
|
|
parameter [15:0] TX_PI_CFG0 = 16'h0000;
|
|
parameter [15:0] TX_PI_CFG1 = 16'h0000;
|
|
parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0;
|
|
parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0;
|
|
parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0;
|
|
parameter [0:0] TX_PMADATA_OPT = 1'b0;
|
|
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
|
|
parameter integer TX_PREDRV_CTRL = 2;
|
|
parameter TX_PROGCLK_SEL = "POSTPI";
|
|
parameter real TX_PROGDIV_CFG = 0.0;
|
|
parameter [15:0] TX_PROGDIV_RATE = 16'h0001;
|
|
parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
|
|
parameter integer TX_RXDETECT_REF = 4;
|
|
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
|
|
parameter [0:0] TX_SARC_LPBK_ENB = 1'b0;
|
|
parameter TX_XCLK_SEL = "TXOUT";
|
|
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
|
|
output [2:0] BUFGTCE;
|
|
output [2:0] BUFGTCEMASK;
|
|
output [8:0] BUFGTDIV;
|
|
output [2:0] BUFGTRESET;
|
|
output [2:0] BUFGTRSTMASK;
|
|
output CPLLFBCLKLOST;
|
|
output CPLLLOCK;
|
|
output CPLLREFCLKLOST;
|
|
output [16:0] DMONITOROUT;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output EYESCANDATAERROR;
|
|
output GTPOWERGOOD;
|
|
output GTREFCLKMONITOR;
|
|
output GTYTXN;
|
|
output GTYTXP;
|
|
output PCIERATEGEN3;
|
|
output PCIERATEIDLE;
|
|
output [1:0] PCIERATEQPLLPD;
|
|
output [1:0] PCIERATEQPLLRESET;
|
|
output PCIESYNCTXSYNCDONE;
|
|
output PCIEUSERGEN3RDY;
|
|
output PCIEUSERPHYSTATUSRST;
|
|
output PCIEUSERRATESTART;
|
|
output [15:0] PCSRSVDOUT;
|
|
output PHYSTATUS;
|
|
output [7:0] PINRSRVDAS;
|
|
output RESETEXCEPTION;
|
|
output [2:0] RXBUFSTATUS;
|
|
output RXBYTEISALIGNED;
|
|
output RXBYTEREALIGN;
|
|
output RXCDRLOCK;
|
|
output RXCDRPHDONE;
|
|
output RXCHANBONDSEQ;
|
|
output RXCHANISALIGNED;
|
|
output RXCHANREALIGN;
|
|
output [4:0] RXCHBONDO;
|
|
output RXCKCALDONE;
|
|
output [1:0] RXCLKCORCNT;
|
|
output RXCOMINITDET;
|
|
output RXCOMMADET;
|
|
output RXCOMSASDET;
|
|
output RXCOMWAKEDET;
|
|
output [15:0] RXCTRL0;
|
|
output [15:0] RXCTRL1;
|
|
output [7:0] RXCTRL2;
|
|
output [7:0] RXCTRL3;
|
|
output [127:0] RXDATA;
|
|
output [7:0] RXDATAEXTENDRSVD;
|
|
output [1:0] RXDATAVALID;
|
|
output RXDLYSRESETDONE;
|
|
output RXELECIDLE;
|
|
output [5:0] RXHEADER;
|
|
output [1:0] RXHEADERVALID;
|
|
output [6:0] RXMONITOROUT;
|
|
output RXOSINTDONE;
|
|
output RXOSINTSTARTED;
|
|
output RXOSINTSTROBEDONE;
|
|
output RXOSINTSTROBESTARTED;
|
|
output RXOUTCLK;
|
|
output RXOUTCLKFABRIC;
|
|
output RXOUTCLKPCS;
|
|
output RXPHALIGNDONE;
|
|
output RXPHALIGNERR;
|
|
output RXPMARESETDONE;
|
|
output RXPRBSERR;
|
|
output RXPRBSLOCKED;
|
|
output RXPRGDIVRESETDONE;
|
|
output RXRATEDONE;
|
|
output RXRECCLKOUT;
|
|
output RXRESETDONE;
|
|
output RXSLIDERDY;
|
|
output RXSLIPDONE;
|
|
output RXSLIPOUTCLKRDY;
|
|
output RXSLIPPMARDY;
|
|
output [1:0] RXSTARTOFSEQ;
|
|
output [2:0] RXSTATUS;
|
|
output RXSYNCDONE;
|
|
output RXSYNCOUT;
|
|
output RXVALID;
|
|
output [1:0] TXBUFSTATUS;
|
|
output TXCOMFINISH;
|
|
output TXDCCDONE;
|
|
output TXDLYSRESETDONE;
|
|
output TXOUTCLK;
|
|
output TXOUTCLKFABRIC;
|
|
output TXOUTCLKPCS;
|
|
output TXPHALIGNDONE;
|
|
output TXPHINITDONE;
|
|
output TXPMARESETDONE;
|
|
output TXPRGDIVRESETDONE;
|
|
output TXRATEDONE;
|
|
output TXRESETDONE;
|
|
output TXSYNCDONE;
|
|
output TXSYNCOUT;
|
|
input CDRSTEPDIR;
|
|
input CDRSTEPSQ;
|
|
input CDRSTEPSX;
|
|
input CFGRESET;
|
|
input CLKRSVD0;
|
|
input CLKRSVD1;
|
|
input CPLLLOCKDETCLK;
|
|
input CPLLLOCKEN;
|
|
input CPLLPD;
|
|
input [2:0] CPLLREFCLKSEL;
|
|
input CPLLRESET;
|
|
input DMONFIFORESET;
|
|
input DMONITORCLK;
|
|
input [9:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input ELPCALDVORWREN;
|
|
input ELPCALPAORWREN;
|
|
input EVODDPHICALDONE;
|
|
input EVODDPHICALSTART;
|
|
input EVODDPHIDRDEN;
|
|
input EVODDPHIDWREN;
|
|
input EVODDPHIXRDEN;
|
|
input EVODDPHIXWREN;
|
|
input EYESCANMODE;
|
|
input EYESCANRESET;
|
|
input EYESCANTRIGGER;
|
|
input GTGREFCLK;
|
|
input GTNORTHREFCLK0;
|
|
input GTNORTHREFCLK1;
|
|
input GTREFCLK0;
|
|
input GTREFCLK1;
|
|
input GTRESETSEL;
|
|
input [15:0] GTRSVD;
|
|
input GTRXRESET;
|
|
input GTSOUTHREFCLK0;
|
|
input GTSOUTHREFCLK1;
|
|
input GTTXRESET;
|
|
input GTYRXN;
|
|
input GTYRXP;
|
|
input [2:0] LOOPBACK;
|
|
input [15:0] LOOPRSVD;
|
|
input LPBKRXTXSEREN;
|
|
input LPBKTXRXSEREN;
|
|
input PCIEEQRXEQADAPTDONE;
|
|
input PCIERSTIDLE;
|
|
input PCIERSTTXSYNCSTART;
|
|
input PCIEUSERRATEDONE;
|
|
input [15:0] PCSRSVDIN;
|
|
input [4:0] PCSRSVDIN2;
|
|
input [4:0] PMARSVDIN;
|
|
input QPLL0CLK;
|
|
input QPLL0REFCLK;
|
|
input QPLL1CLK;
|
|
input QPLL1REFCLK;
|
|
input RESETOVRD;
|
|
input RSTCLKENTX;
|
|
input RX8B10BEN;
|
|
input RXBUFRESET;
|
|
input RXCDRFREQRESET;
|
|
input RXCDRHOLD;
|
|
input RXCDROVRDEN;
|
|
input RXCDRRESET;
|
|
input RXCDRRESETRSV;
|
|
input RXCHBONDEN;
|
|
input [4:0] RXCHBONDI;
|
|
input [2:0] RXCHBONDLEVEL;
|
|
input RXCHBONDMASTER;
|
|
input RXCHBONDSLAVE;
|
|
input RXCKCALRESET;
|
|
input RXCOMMADETEN;
|
|
input RXDCCFORCESTART;
|
|
input RXDFEAGCHOLD;
|
|
input RXDFEAGCOVRDEN;
|
|
input RXDFELFHOLD;
|
|
input RXDFELFOVRDEN;
|
|
input RXDFELPMRESET;
|
|
input RXDFETAP10HOLD;
|
|
input RXDFETAP10OVRDEN;
|
|
input RXDFETAP11HOLD;
|
|
input RXDFETAP11OVRDEN;
|
|
input RXDFETAP12HOLD;
|
|
input RXDFETAP12OVRDEN;
|
|
input RXDFETAP13HOLD;
|
|
input RXDFETAP13OVRDEN;
|
|
input RXDFETAP14HOLD;
|
|
input RXDFETAP14OVRDEN;
|
|
input RXDFETAP15HOLD;
|
|
input RXDFETAP15OVRDEN;
|
|
input RXDFETAP2HOLD;
|
|
input RXDFETAP2OVRDEN;
|
|
input RXDFETAP3HOLD;
|
|
input RXDFETAP3OVRDEN;
|
|
input RXDFETAP4HOLD;
|
|
input RXDFETAP4OVRDEN;
|
|
input RXDFETAP5HOLD;
|
|
input RXDFETAP5OVRDEN;
|
|
input RXDFETAP6HOLD;
|
|
input RXDFETAP6OVRDEN;
|
|
input RXDFETAP7HOLD;
|
|
input RXDFETAP7OVRDEN;
|
|
input RXDFETAP8HOLD;
|
|
input RXDFETAP8OVRDEN;
|
|
input RXDFETAP9HOLD;
|
|
input RXDFETAP9OVRDEN;
|
|
input RXDFEUTHOLD;
|
|
input RXDFEUTOVRDEN;
|
|
input RXDFEVPHOLD;
|
|
input RXDFEVPOVRDEN;
|
|
input RXDFEVSEN;
|
|
input RXDFEXYDEN;
|
|
input RXDLYBYPASS;
|
|
input RXDLYEN;
|
|
input RXDLYOVRDEN;
|
|
input RXDLYSRESET;
|
|
input [1:0] RXELECIDLEMODE;
|
|
input RXGEARBOXSLIP;
|
|
input RXLATCLK;
|
|
input RXLPMEN;
|
|
input RXLPMGCHOLD;
|
|
input RXLPMGCOVRDEN;
|
|
input RXLPMHFHOLD;
|
|
input RXLPMHFOVRDEN;
|
|
input RXLPMLFHOLD;
|
|
input RXLPMLFKLOVRDEN;
|
|
input RXLPMOSHOLD;
|
|
input RXLPMOSOVRDEN;
|
|
input RXMCOMMAALIGNEN;
|
|
input [1:0] RXMONITORSEL;
|
|
input RXOOBRESET;
|
|
input RXOSCALRESET;
|
|
input RXOSHOLD;
|
|
input [3:0] RXOSINTCFG;
|
|
input RXOSINTEN;
|
|
input RXOSINTHOLD;
|
|
input RXOSINTOVRDEN;
|
|
input RXOSINTSTROBE;
|
|
input RXOSINTTESTOVRDEN;
|
|
input RXOSOVRDEN;
|
|
input [2:0] RXOUTCLKSEL;
|
|
input RXPCOMMAALIGNEN;
|
|
input RXPCSRESET;
|
|
input [1:0] RXPD;
|
|
input RXPHALIGN;
|
|
input RXPHALIGNEN;
|
|
input RXPHDLYPD;
|
|
input RXPHDLYRESET;
|
|
input RXPHOVRDEN;
|
|
input [1:0] RXPLLCLKSEL;
|
|
input RXPMARESET;
|
|
input RXPOLARITY;
|
|
input RXPRBSCNTRESET;
|
|
input [3:0] RXPRBSSEL;
|
|
input RXPROGDIVRESET;
|
|
input [2:0] RXRATE;
|
|
input RXRATEMODE;
|
|
input RXSLIDE;
|
|
input RXSLIPOUTCLK;
|
|
input RXSLIPPMA;
|
|
input RXSYNCALLIN;
|
|
input RXSYNCIN;
|
|
input RXSYNCMODE;
|
|
input [1:0] RXSYSCLKSEL;
|
|
input RXUSERRDY;
|
|
input RXUSRCLK;
|
|
input RXUSRCLK2;
|
|
input SIGVALIDCLK;
|
|
input [19:0] TSTIN;
|
|
input [7:0] TX8B10BBYPASS;
|
|
input TX8B10BEN;
|
|
input [2:0] TXBUFDIFFCTRL;
|
|
input TXCOMINIT;
|
|
input TXCOMSAS;
|
|
input TXCOMWAKE;
|
|
input [15:0] TXCTRL0;
|
|
input [15:0] TXCTRL1;
|
|
input [7:0] TXCTRL2;
|
|
input [127:0] TXDATA;
|
|
input [7:0] TXDATAEXTENDRSVD;
|
|
input TXDCCFORCESTART;
|
|
input TXDCCRESET;
|
|
input TXDEEMPH;
|
|
input TXDETECTRX;
|
|
input [4:0] TXDIFFCTRL;
|
|
input TXDIFFPD;
|
|
input TXDLYBYPASS;
|
|
input TXDLYEN;
|
|
input TXDLYHOLD;
|
|
input TXDLYOVRDEN;
|
|
input TXDLYSRESET;
|
|
input TXDLYUPDOWN;
|
|
input TXELECIDLE;
|
|
input TXELFORCESTART;
|
|
input [5:0] TXHEADER;
|
|
input TXINHIBIT;
|
|
input TXLATCLK;
|
|
input [6:0] TXMAINCURSOR;
|
|
input [2:0] TXMARGIN;
|
|
input [2:0] TXOUTCLKSEL;
|
|
input TXPCSRESET;
|
|
input [1:0] TXPD;
|
|
input TXPDELECIDLEMODE;
|
|
input TXPHALIGN;
|
|
input TXPHALIGNEN;
|
|
input TXPHDLYPD;
|
|
input TXPHDLYRESET;
|
|
input TXPHDLYTSTCLK;
|
|
input TXPHINIT;
|
|
input TXPHOVRDEN;
|
|
input TXPIPPMEN;
|
|
input TXPIPPMOVRDEN;
|
|
input TXPIPPMPD;
|
|
input TXPIPPMSEL;
|
|
input [4:0] TXPIPPMSTEPSIZE;
|
|
input TXPISOPD;
|
|
input [1:0] TXPLLCLKSEL;
|
|
input TXPMARESET;
|
|
input TXPOLARITY;
|
|
input [4:0] TXPOSTCURSOR;
|
|
input TXPRBSFORCEERR;
|
|
input [3:0] TXPRBSSEL;
|
|
input [4:0] TXPRECURSOR;
|
|
input TXPROGDIVRESET;
|
|
input [2:0] TXRATE;
|
|
input TXRATEMODE;
|
|
input [6:0] TXSEQUENCE;
|
|
input TXSWING;
|
|
input TXSYNCALLIN;
|
|
input TXSYNCIN;
|
|
input TXSYNCMODE;
|
|
input [1:0] TXSYSCLKSEL;
|
|
input TXUSERRDY;
|
|
input TXUSRCLK;
|
|
input TXUSRCLK2;
|
|
endmodule
|
|
|
|
module GTYE3_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0_SEL, RXRECCLK1_SEL, SDM0FINALOUT
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, SDM0TESTDATA, SDM1FINALOUT, SDM1TESTDATA, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11, GTREFCLK00, GTREFCLK01
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|
, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0LOCKDETCLK, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1
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, QPLLRSVD2, QPLLRSVD3, QPLLRSVD4, RCALENB, SDM0DATA, SDM0RESET, SDM0WIDTH, SDM1DATA, SDM1RESET, SDM1WIDTH);
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parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000;
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parameter [8:0] A_SDM1DATA1_1 = 9'b000000000;
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parameter [15:0] BIAS_CFG0 = 16'h0000;
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parameter [15:0] BIAS_CFG1 = 16'h0000;
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parameter [15:0] BIAS_CFG2 = 16'h0000;
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parameter [15:0] BIAS_CFG3 = 16'h0000;
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parameter [15:0] BIAS_CFG4 = 16'h0000;
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parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000;
|
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parameter [15:0] COMMON_CFG0 = 16'h0000;
|
|
parameter [15:0] COMMON_CFG1 = 16'h0000;
|
|
parameter [15:0] POR_CFG = 16'h0004;
|
|
parameter [15:0] PPF0_CFG = 16'h0FFF;
|
|
parameter [15:0] PPF1_CFG = 16'h0FFF;
|
|
parameter QPLL0CLKOUT_RATE = "FULL";
|
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parameter [15:0] QPLL0_CFG0 = 16'h301C;
|
|
parameter [15:0] QPLL0_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
|
|
parameter [15:0] QPLL0_CFG2 = 16'h0780;
|
|
parameter [15:0] QPLL0_CFG2_G3 = 16'h0780;
|
|
parameter [15:0] QPLL0_CFG3 = 16'h0120;
|
|
parameter [15:0] QPLL0_CFG4 = 16'h0021;
|
|
parameter [9:0] QPLL0_CP = 10'b0000011111;
|
|
parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
|
|
parameter integer QPLL0_FBDIV = 66;
|
|
parameter integer QPLL0_FBDIV_G3 = 80;
|
|
parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000;
|
|
parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
|
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parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8;
|
|
parameter [9:0] QPLL0_LPF = 10'b1111111111;
|
|
parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
|
|
parameter integer QPLL0_REFCLK_DIV = 2;
|
|
parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040;
|
|
parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000;
|
|
parameter QPLL1CLKOUT_RATE = "FULL";
|
|
parameter [15:0] QPLL1_CFG0 = 16'h301C;
|
|
parameter [15:0] QPLL1_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
|
|
parameter [15:0] QPLL1_CFG2 = 16'h0780;
|
|
parameter [15:0] QPLL1_CFG2_G3 = 16'h0780;
|
|
parameter [15:0] QPLL1_CFG3 = 16'h0120;
|
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parameter [15:0] QPLL1_CFG4 = 16'h0021;
|
|
parameter [9:0] QPLL1_CP = 10'b0000011111;
|
|
parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
|
|
parameter integer QPLL1_FBDIV = 66;
|
|
parameter integer QPLL1_FBDIV_G3 = 80;
|
|
parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000;
|
|
parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
|
|
parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
|
|
parameter [9:0] QPLL1_LPF = 10'b1111111111;
|
|
parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
|
|
parameter integer QPLL1_REFCLK_DIV = 2;
|
|
parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040;
|
|
parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR0 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR1 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR2 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR3 = 16'h0000;
|
|
parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
|
|
parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
|
|
parameter [0:0] SARC_EN = 1'b1;
|
|
parameter [0:0] SARC_SEL = 1'b0;
|
|
parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
|
|
parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
|
|
parameter SIM_MODE = "FAST";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter integer SIM_VERSION = 2;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output [7:0] PMARSVDOUT0;
|
|
output [7:0] PMARSVDOUT1;
|
|
output QPLL0FBCLKLOST;
|
|
output QPLL0LOCK;
|
|
output QPLL0OUTCLK;
|
|
output QPLL0OUTREFCLK;
|
|
output QPLL0REFCLKLOST;
|
|
output QPLL1FBCLKLOST;
|
|
output QPLL1LOCK;
|
|
output QPLL1OUTCLK;
|
|
output QPLL1OUTREFCLK;
|
|
output QPLL1REFCLKLOST;
|
|
output [7:0] QPLLDMONITOR0;
|
|
output [7:0] QPLLDMONITOR1;
|
|
output REFCLKOUTMONITOR0;
|
|
output REFCLKOUTMONITOR1;
|
|
output [1:0] RXRECCLK0_SEL;
|
|
output [1:0] RXRECCLK1_SEL;
|
|
output [3:0] SDM0FINALOUT;
|
|
output [14:0] SDM0TESTDATA;
|
|
output [3:0] SDM1FINALOUT;
|
|
output [14:0] SDM1TESTDATA;
|
|
input BGBYPASSB;
|
|
input BGMONITORENB;
|
|
input BGPDB;
|
|
input [4:0] BGRCALOVRD;
|
|
input BGRCALOVRDENB;
|
|
input [9:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input GTGREFCLK0;
|
|
input GTGREFCLK1;
|
|
input GTNORTHREFCLK00;
|
|
input GTNORTHREFCLK01;
|
|
input GTNORTHREFCLK10;
|
|
input GTNORTHREFCLK11;
|
|
input GTREFCLK00;
|
|
input GTREFCLK01;
|
|
input GTREFCLK10;
|
|
input GTREFCLK11;
|
|
input GTSOUTHREFCLK00;
|
|
input GTSOUTHREFCLK01;
|
|
input GTSOUTHREFCLK10;
|
|
input GTSOUTHREFCLK11;
|
|
input [7:0] PMARSVD0;
|
|
input [7:0] PMARSVD1;
|
|
input QPLL0CLKRSVD0;
|
|
input QPLL0LOCKDETCLK;
|
|
input QPLL0LOCKEN;
|
|
input QPLL0PD;
|
|
input [2:0] QPLL0REFCLKSEL;
|
|
input QPLL0RESET;
|
|
input QPLL1CLKRSVD0;
|
|
input QPLL1LOCKDETCLK;
|
|
input QPLL1LOCKEN;
|
|
input QPLL1PD;
|
|
input [2:0] QPLL1REFCLKSEL;
|
|
input QPLL1RESET;
|
|
input [7:0] QPLLRSVD1;
|
|
input [4:0] QPLLRSVD2;
|
|
input [4:0] QPLLRSVD3;
|
|
input [7:0] QPLLRSVD4;
|
|
input RCALENB;
|
|
input [24:0] SDM0DATA;
|
|
input SDM0RESET;
|
|
input [1:0] SDM0WIDTH;
|
|
input [24:0] SDM1DATA;
|
|
input SDM1RESET;
|
|
input [1:0] SDM1WIDTH;
|
|
endmodule
|
|
|
|
module IBUFDS_GTE3(O, ODIV2, CEB, I, IB);
|
|
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
|
|
parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00;
|
|
parameter [1:0] REFCLK_ICNTL_RX = 2'b00;
|
|
output O;
|
|
output ODIV2;
|
|
input CEB;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module OBUFDS_GTE3(O, OB, CEB, I);
|
|
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
|
|
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
output OB;
|
|
input CEB;
|
|
input I;
|
|
endmodule
|
|
|
|
module OBUFDS_GTE3_ADV(O, OB, CEB, I, RXRECCLK_SEL);
|
|
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
|
|
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
output OB;
|
|
input CEB;
|
|
input [3:0] I;
|
|
input [1:0] RXRECCLK_SEL;
|
|
endmodule
|
|
|
|
module GTHE4_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DMONITOROUTCLK, DRPDO, DRPRDY, EYESCANDATAERROR, GTHTXN, GTHTXP, GTPOWERGOOD, GTREFCLKMONITOR, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET
|
|
, PCIESYNCTXSYNCDONE, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, POWERPRESENT, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCKCALDONE, RXCLKCORCNT, RXCOMINITDET
|
|
, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXLFPSTRESETDET, RXLFPSU2LPEXITDET, RXLFPSU3WAKEDET, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE
|
|
, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHALIGNERR, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXQPISENN, RXQPISENP, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS
|
|
, RXSYNCDONE, RXSYNCOUT, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDCCDONE, TXDLYSRESETDONE, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXQPISENN, TXQPISENP, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CDRSTEPDIR
|
|
, CDRSTEPSQ, CDRSTEPSX, CFGRESET, CLKRSVD0, CLKRSVD1, CPLLFREQLOCK, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL, CPLLRESET, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPRST, DRPWE, EYESCANRESET, EYESCANTRIGGER
|
|
, FREQOS, GTGREFCLK, GTHRXN, GTHRXP, GTNORTHREFCLK0, GTNORTHREFCLK1, GTREFCLK0, GTREFCLK1, GTRSVD, GTRXRESET, GTRXRESETSEL, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, GTTXRESETSEL, INCPCTRL, LOOPBACK, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE
|
|
, PCSRSVDIN, QPLL0CLK, QPLL0FREQLOCK, QPLL0REFCLK, QPLL1CLK, QPLL1FREQLOCK, QPLL1REFCLK, RESETOVRD, RX8B10BEN, RXAFECFOKEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCKCALRESET
|
|
, RXCKCALSTART, RXCOMMADETEN, RXDFEAGCCTRL, RXDFEAGCHOLD, RXDFEAGCOVRDEN, RXDFECFOKFCNUM, RXDFECFOKFEN, RXDFECFOKFPULSE, RXDFECFOKHOLD, RXDFECFOKOVREN, RXDFEKHHOLD, RXDFEKHOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN
|
|
, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD
|
|
, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXEQTRAINING, RXGEARBOXSLIP, RXLATCLK, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN
|
|
, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET, RXOSCALRESET, RXOSHOLD, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPHOVRDEN, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET
|
|
, RXPRBSSEL, RXPROGDIVRESET, RXQPIEN, RXRATE, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK, RXSLIPPMA, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXTERMINATION, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXCOMINIT
|
|
, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1, TXCTRL2, TXDATA, TXDATAEXTENDRSVD, TXDCCFORCESTART, TXDCCRESET, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT
|
|
, TXLATCLK, TXLFPSTRESET, TXLFPSU2LPEXIT, TXLFPSU3WAKE, TXMAINCURSOR, TXMARGIN, TXMUXDCDEXHOLD, TXMUXDCDORWREN, TXONESZEROS, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN
|
|
, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET, TXPOLARITY, TXPOSTCURSOR, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPROGDIVRESET, TXQPIBIASEN, TXQPIWEAKPUP, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN
|
|
, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2);
|
|
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_RESET = 1'b0;
|
|
parameter [15:0] ADAPT_CFG0 = 16'h9200;
|
|
parameter [15:0] ADAPT_CFG1 = 16'h801C;
|
|
parameter [15:0] ADAPT_CFG2 = 16'h0000;
|
|
parameter ALIGN_COMMA_DOUBLE = "FALSE";
|
|
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
|
|
parameter integer ALIGN_COMMA_WORD = 1;
|
|
parameter ALIGN_MCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
|
|
parameter ALIGN_PCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
|
|
parameter [0:0] A_RXOSCALRESET = 1'b0;
|
|
parameter [0:0] A_RXPROGDIVRESET = 1'b0;
|
|
parameter [0:0] A_RXTERMINATION = 1'b1;
|
|
parameter [4:0] A_TXDIFFCTRL = 5'b01100;
|
|
parameter [0:0] A_TXPROGDIVRESET = 1'b0;
|
|
parameter [0:0] CAPBYPASS_FORCE = 1'b0;
|
|
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
|
|
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
|
|
parameter [0:0] CFOK_PWRSVE_EN = 1'b1;
|
|
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
|
|
parameter integer CHAN_BOND_MAX_SKEW = 7;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
|
|
parameter integer CHAN_BOND_SEQ_LEN = 2;
|
|
parameter [15:0] CH_HSPMUX = 16'h2424;
|
|
parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL_RSVD0 = 16'h4000;
|
|
parameter [15:0] CKCAL_RSVD1 = 16'h0000;
|
|
parameter CLK_CORRECT_USE = "TRUE";
|
|
parameter CLK_COR_KEEP_IDLE = "FALSE";
|
|
parameter integer CLK_COR_MAX_LAT = 20;
|
|
parameter integer CLK_COR_MIN_LAT = 18;
|
|
parameter CLK_COR_PRECEDENCE = "TRUE";
|
|
parameter integer CLK_COR_REPEAT_WAIT = 0;
|
|
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CLK_COR_SEQ_2_USE = "FALSE";
|
|
parameter integer CLK_COR_SEQ_LEN = 2;
|
|
parameter [15:0] CPLL_CFG0 = 16'h01FA;
|
|
parameter [15:0] CPLL_CFG1 = 16'h24A9;
|
|
parameter [15:0] CPLL_CFG2 = 16'h6807;
|
|
parameter [15:0] CPLL_CFG3 = 16'h0000;
|
|
parameter integer CPLL_FBDIV = 4;
|
|
parameter integer CPLL_FBDIV_45 = 4;
|
|
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
|
|
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
|
|
parameter integer CPLL_REFCLK_DIV = 1;
|
|
parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000;
|
|
parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0;
|
|
parameter [1:0] DDI_CTRL = 2'b00;
|
|
parameter integer DDI_REALIGN_WAIT = 15;
|
|
parameter DEC_MCOMMA_DETECT = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY = "TRUE";
|
|
parameter [0:0] DELAY_ELEC = 1'b0;
|
|
parameter [9:0] DMONITOR_CFG0 = 10'h000;
|
|
parameter [7:0] DMONITOR_CFG1 = 8'h00;
|
|
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
|
|
parameter [5:0] ES_CONTROL = 6'b000000;
|
|
parameter ES_ERRDET_EN = "FALSE";
|
|
parameter ES_EYE_SCAN_EN = "FALSE";
|
|
parameter [11:0] ES_HORZ_OFFSET = 12'h800;
|
|
parameter [4:0] ES_PRESCALE = 5'b00000;
|
|
parameter [15:0] ES_QUALIFIER0 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER1 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER2 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER3 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER4 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER5 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER6 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER7 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER8 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER9 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK0 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK1 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK2 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK3 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK4 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK5 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK6 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK7 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK8 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK9 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK0 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK1 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK2 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK3 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK4 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK5 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK6 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK7 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK8 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK9 = 16'h0000;
|
|
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
|
|
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
|
|
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
|
|
parameter FTS_LANE_DESKEW_EN = "FALSE";
|
|
parameter [4:0] GEARBOX_MODE = 5'b00000;
|
|
parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0;
|
|
parameter [0:0] LOCAL_MASTER = 1'b0;
|
|
parameter [2:0] LPBK_BIAS_CTRL = 3'b000;
|
|
parameter [0:0] LPBK_EN_RCAL_B = 1'b0;
|
|
parameter [3:0] LPBK_EXT_RCAL = 4'b0000;
|
|
parameter [2:0] LPBK_IND_CTRL0 = 3'b000;
|
|
parameter [2:0] LPBK_IND_CTRL1 = 3'b000;
|
|
parameter [2:0] LPBK_IND_CTRL2 = 3'b000;
|
|
parameter [3:0] LPBK_RG_CTRL = 4'b0000;
|
|
parameter [1:0] OOBDIVCTL = 2'b00;
|
|
parameter [0:0] OOB_PWRUP = 1'b0;
|
|
parameter PCI3_AUTO_REALIGN = "FRST_SMPL";
|
|
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1;
|
|
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00;
|
|
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0;
|
|
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000;
|
|
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000;
|
|
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
|
|
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
|
|
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
|
|
parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000;
|
|
parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000;
|
|
parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000;
|
|
parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100;
|
|
parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000;
|
|
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
|
|
parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0;
|
|
parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0;
|
|
parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0;
|
|
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
|
|
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
|
|
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
|
|
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
|
|
parameter PCS_PCIE_EN = "FALSE";
|
|
parameter [15:0] PCS_RSVD0 = 16'b0000000000000000;
|
|
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
|
|
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
|
|
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
|
|
parameter integer PREIQ_FREQ_BST = 0;
|
|
parameter [2:0] PROCESS_PAR = 3'b010;
|
|
parameter [0:0] RATE_SW_USE_DRP = 1'b0;
|
|
parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0;
|
|
parameter [0:0] RCLK_SIPO_INV_EN = 1'b0;
|
|
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0;
|
|
parameter [2:0] RTX_BUF_CML_CTRL = 3'b010;
|
|
parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00;
|
|
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
|
|
parameter RXBUF_ADDR_MODE = "FULL";
|
|
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
|
|
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
|
|
parameter RXBUF_EN = "TRUE";
|
|
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
|
|
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
|
|
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
|
|
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
|
|
parameter integer RXBUF_THRESH_OVFLW = 0;
|
|
parameter RXBUF_THRESH_OVRD = "FALSE";
|
|
parameter integer RXBUF_THRESH_UNDFLW = 4;
|
|
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
|
|
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXCDR_CFG0 = 16'h0003;
|
|
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003;
|
|
parameter [15:0] RXCDR_CFG1 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG2 = 16'h0164;
|
|
parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164;
|
|
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034;
|
|
parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034;
|
|
parameter [15:0] RXCDR_CFG3 = 16'h0024;
|
|
parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24;
|
|
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024;
|
|
parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024;
|
|
parameter [15:0] RXCDR_CFG4 = 16'h5CF6;
|
|
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6;
|
|
parameter [15:0] RXCDR_CFG5 = 16'hB46B;
|
|
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B;
|
|
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
|
|
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040;
|
|
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000;
|
|
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000;
|
|
parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000;
|
|
parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000;
|
|
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
|
|
parameter [15:0] RXCFOK_CFG0 = 16'h0000;
|
|
parameter [15:0] RXCFOK_CFG1 = 16'h0002;
|
|
parameter [15:0] RXCFOK_CFG2 = 16'h002D;
|
|
parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000;
|
|
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
|
|
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022;
|
|
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100;
|
|
parameter [15:0] RXDFE_CFG0 = 16'h4000;
|
|
parameter [15:0] RXDFE_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_GC_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_GC_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
|
|
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H2_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H3_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H3_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H4_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003;
|
|
parameter [15:0] RXDFE_H5_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H5_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H6_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H6_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H7_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H7_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H8_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H8_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H9_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H9_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HA_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HA_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HB_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HB_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HC_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HD_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HE_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HF_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_KH_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_KH_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_KH_CFG2 = 16'h0000;
|
|
parameter [15:0] RXDFE_KH_CFG3 = 16'h0000;
|
|
parameter [15:0] RXDFE_OS_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_OS_CFG1 = 16'h0002;
|
|
parameter [0:0] RXDFE_PWR_SAVING = 1'b0;
|
|
parameter [15:0] RXDFE_UT_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_UT_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_UT_CFG2 = 16'h0000;
|
|
parameter [15:0] RXDFE_VP_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_VP_CFG1 = 16'h0022;
|
|
parameter [15:0] RXDLY_CFG = 16'h0010;
|
|
parameter [15:0] RXDLY_LCFG = 16'h0030;
|
|
parameter RXELECIDLE_CFG = "SIGCFG_4";
|
|
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
|
|
parameter RXGEARBOX_EN = "FALSE";
|
|
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXLPM_CFG = 16'h0000;
|
|
parameter [15:0] RXLPM_GC_CFG = 16'h1000;
|
|
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
|
|
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
|
|
parameter [15:0] RXLPM_OS_CFG0 = 16'h0000;
|
|
parameter [15:0] RXLPM_OS_CFG1 = 16'h0000;
|
|
parameter [8:0] RXOOB_CFG = 9'b000110000;
|
|
parameter RXOOB_CLK_CFG = "PMA";
|
|
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
|
|
parameter integer RXOUT_DIV = 4;
|
|
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXPHBEACON_CFG = 16'h0000;
|
|
parameter [15:0] RXPHDLY_CFG = 16'h2020;
|
|
parameter [15:0] RXPHSAMP_CFG = 16'h2100;
|
|
parameter [15:0] RXPHSLIP_CFG = 16'h9933;
|
|
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0;
|
|
parameter [15:0] RXPI_CFG0 = 16'h0002;
|
|
parameter [15:0] RXPI_CFG1 = 16'b0000000000000000;
|
|
parameter [0:0] RXPI_LPM = 1'b0;
|
|
parameter [1:0] RXPI_SEL_LC = 2'b00;
|
|
parameter [1:0] RXPI_STARTCODE = 2'b00;
|
|
parameter [0:0] RXPI_VREFSEL = 1'b0;
|
|
parameter RXPMACLK_SEL = "DATA";
|
|
parameter [4:0] RXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
|
|
parameter integer RXPRBS_LINKACQ_CNT = 15;
|
|
parameter [0:0] RXREFCLKDIV2_SEL = 1'b0;
|
|
parameter integer RXSLIDE_AUTO_WAIT = 7;
|
|
parameter RXSLIDE_MODE = "OFF";
|
|
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] RXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
|
|
parameter [0:0] RX_AFE_CM_EN = 1'b0;
|
|
parameter [15:0] RX_BIAS_CFG0 = 16'h12B0;
|
|
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
|
|
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
|
|
parameter integer RX_CLK25_DIV = 8;
|
|
parameter [0:0] RX_CLKMUX_EN = 1'b1;
|
|
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000;
|
|
parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
|
|
parameter [0:0] RX_CM_BUF_PD = 1'b0;
|
|
parameter integer RX_CM_SEL = 3;
|
|
parameter integer RX_CM_TRIM = 12;
|
|
parameter [7:0] RX_CTLE3_LPF = 8'b00000000;
|
|
parameter integer RX_DATA_WIDTH = 20;
|
|
parameter [5:0] RX_DDI_SEL = 6'b000000;
|
|
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
|
|
parameter [2:0] RX_DEGEN_CTRL = 3'b011;
|
|
parameter integer RX_DFELPM_CFG0 = 0;
|
|
parameter [0:0] RX_DFELPM_CFG1 = 1'b1;
|
|
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
|
|
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00;
|
|
parameter integer RX_DFE_AGC_CFG1 = 4;
|
|
parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1;
|
|
parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4;
|
|
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
|
|
parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4;
|
|
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
|
|
parameter [0:0] RX_DIV2_MODE_B = 1'b0;
|
|
parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
|
|
parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0;
|
|
parameter [0:0] RX_EN_HI_LR = 1'b1;
|
|
parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000;
|
|
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
|
|
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
|
|
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00;
|
|
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0;
|
|
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
|
|
parameter integer RX_INT_DATAWIDTH = 1;
|
|
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
|
|
parameter [15:0] RX_PMA_RSV0 = 16'h0000;
|
|
parameter real RX_PROGDIV_CFG = 0.0;
|
|
parameter [15:0] RX_PROGDIV_RATE = 16'h0001;
|
|
parameter [3:0] RX_RESLOAD_CTRL = 4'b0000;
|
|
parameter [0:0] RX_RESLOAD_OVRD = 1'b0;
|
|
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
|
|
parameter integer RX_SIG_VALID_DLY = 11;
|
|
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
|
|
parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001;
|
|
parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000;
|
|
parameter [3:0] RX_SUM_VCMTUNE = 4'b1010;
|
|
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
|
|
parameter [2:0] RX_SUM_VREF_TUNE = 3'b100;
|
|
parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
|
|
parameter [2:0] RX_VREG_CTRL = 3'b101;
|
|
parameter [0:0] RX_VREG_PDB = 1'b1;
|
|
parameter [1:0] RX_WIDEMODE_CDR = 2'b01;
|
|
parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01;
|
|
parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01;
|
|
parameter RX_XCLK_SEL = "RXDES";
|
|
parameter [0:0] RX_XMODE_SEL = 1'b0;
|
|
parameter [0:0] SAMPLE_CLK_PHASE = 1'b0;
|
|
parameter [0:0] SAS_12G_MODE = 1'b0;
|
|
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
|
|
parameter [2:0] SATA_BURST_VAL = 3'b100;
|
|
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
|
|
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
|
|
parameter SHOW_REALIGN_COMMA = "TRUE";
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter SIM_MODE = "FAST";
|
|
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z";
|
|
parameter [0:0] SRSTMODE = 1'b0;
|
|
parameter [1:0] TAPDLY_SET_TX = 2'h0;
|
|
parameter [3:0] TEMPERATURE_PAR = 4'b0010;
|
|
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
|
|
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
|
|
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
|
|
parameter [7:0] TST_RSV0 = 8'h00;
|
|
parameter [7:0] TST_RSV1 = 8'h00;
|
|
parameter TXBUF_EN = "TRUE";
|
|
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
|
|
parameter [15:0] TXDLY_CFG = 16'h0010;
|
|
parameter [15:0] TXDLY_LCFG = 16'h0030;
|
|
parameter [3:0] TXDRVBIAS_N = 4'b1010;
|
|
parameter TXFIFO_ADDR_CFG = "LOW";
|
|
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
|
|
parameter TXGEARBOX_EN = "FALSE";
|
|
parameter integer TXOUT_DIV = 4;
|
|
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
|
|
parameter [15:0] TXPHDLY_CFG0 = 16'h6020;
|
|
parameter [15:0] TXPHDLY_CFG1 = 16'h0002;
|
|
parameter [15:0] TXPH_CFG = 16'h0123;
|
|
parameter [15:0] TXPH_CFG2 = 16'h0000;
|
|
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [15:0] TXPI_CFG = 16'h0000;
|
|
parameter [1:0] TXPI_CFG0 = 2'b00;
|
|
parameter [1:0] TXPI_CFG1 = 2'b00;
|
|
parameter [1:0] TXPI_CFG2 = 2'b00;
|
|
parameter [0:0] TXPI_CFG3 = 1'b0;
|
|
parameter [0:0] TXPI_CFG4 = 1'b1;
|
|
parameter [2:0] TXPI_CFG5 = 3'b000;
|
|
parameter [0:0] TXPI_GRAY_SEL = 1'b0;
|
|
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
|
|
parameter [0:0] TXPI_LPM = 1'b0;
|
|
parameter [0:0] TXPI_PPM = 1'b0;
|
|
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
|
|
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
|
|
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
|
|
parameter [0:0] TXPI_VREFSEL = 1'b0;
|
|
parameter [4:0] TXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] TXREFCLKDIV2_SEL = 1'b0;
|
|
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] TXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
|
|
parameter integer TX_CLK25_DIV = 8;
|
|
parameter [0:0] TX_CLKMUX_EN = 1'b1;
|
|
parameter integer TX_DATA_WIDTH = 20;
|
|
parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000;
|
|
parameter [5:0] TX_DEEMPH0 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH1 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH2 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH3 = 6'b000000;
|
|
parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
|
|
parameter TX_DRIVE_MODE = "DIRECT";
|
|
parameter integer TX_DRVMUX_CTRL = 2;
|
|
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
|
|
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
|
|
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
|
|
parameter [0:0] TX_FIFO_BYP_EN = 1'b0;
|
|
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
|
|
parameter integer TX_INT_DATAWIDTH = 1;
|
|
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
|
|
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
|
|
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
|
|
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
|
|
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
|
|
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
|
|
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
|
|
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
|
|
parameter [15:0] TX_PHICAL_CFG0 = 16'h0000;
|
|
parameter [15:0] TX_PHICAL_CFG1 = 16'h003F;
|
|
parameter [15:0] TX_PHICAL_CFG2 = 16'h0000;
|
|
parameter integer TX_PI_BIASSET = 0;
|
|
parameter [1:0] TX_PI_IBIAS_MID = 2'b00;
|
|
parameter [0:0] TX_PMADATA_OPT = 1'b0;
|
|
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
|
|
parameter [15:0] TX_PMA_RSV0 = 16'h0008;
|
|
parameter integer TX_PREDRV_CTRL = 2;
|
|
parameter TX_PROGCLK_SEL = "POSTPI";
|
|
parameter real TX_PROGDIV_CFG = 0.0;
|
|
parameter [15:0] TX_PROGDIV_RATE = 16'h0001;
|
|
parameter [0:0] TX_QPI_STATUS_EN = 1'b0;
|
|
parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
|
|
parameter integer TX_RXDETECT_REF = 3;
|
|
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
|
|
parameter [0:0] TX_SARC_LPBK_ENB = 1'b0;
|
|
parameter [1:0] TX_SW_MEAS = 2'b00;
|
|
parameter [2:0] TX_VREG_CTRL = 3'b000;
|
|
parameter [0:0] TX_VREG_PDB = 1'b0;
|
|
parameter [1:0] TX_VREG_VREFSEL = 2'b00;
|
|
parameter TX_XCLK_SEL = "TXOUT";
|
|
parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0;
|
|
parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111;
|
|
parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011;
|
|
parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0;
|
|
parameter [0:0] USB_EXT_CNTL = 1'b1;
|
|
parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011;
|
|
parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011;
|
|
parameter [8:0] USB_LFPSPING_BURST = 9'b000000101;
|
|
parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001;
|
|
parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100;
|
|
parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101;
|
|
parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011;
|
|
parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011;
|
|
parameter [3:0] USB_LFPS_TPERIOD = 4'b0011;
|
|
parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1;
|
|
parameter [0:0] USB_MODE = 1'b0;
|
|
parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0;
|
|
parameter integer USB_PING_SATA_MAX_INIT = 21;
|
|
parameter integer USB_PING_SATA_MIN_INIT = 12;
|
|
parameter integer USB_POLL_SATA_MAX_BURST = 8;
|
|
parameter integer USB_POLL_SATA_MIN_BURST = 4;
|
|
parameter [0:0] USB_RAW_ELEC = 1'b0;
|
|
parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1;
|
|
parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1;
|
|
parameter integer USB_U1_SATA_MAX_WAKE = 7;
|
|
parameter integer USB_U1_SATA_MIN_WAKE = 4;
|
|
parameter integer USB_U2_SAS_MAX_COM = 64;
|
|
parameter integer USB_U2_SAS_MIN_COM = 36;
|
|
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
|
|
parameter [0:0] Y_ALL_MODE = 1'b0;
|
|
output BUFGTCE;
|
|
output [2:0] BUFGTCEMASK;
|
|
output [8:0] BUFGTDIV;
|
|
output BUFGTRESET;
|
|
output [2:0] BUFGTRSTMASK;
|
|
output CPLLFBCLKLOST;
|
|
output CPLLLOCK;
|
|
output CPLLREFCLKLOST;
|
|
output [15:0] DMONITOROUT;
|
|
output DMONITOROUTCLK;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output EYESCANDATAERROR;
|
|
output GTHTXN;
|
|
output GTHTXP;
|
|
output GTPOWERGOOD;
|
|
output GTREFCLKMONITOR;
|
|
output PCIERATEGEN3;
|
|
output PCIERATEIDLE;
|
|
output [1:0] PCIERATEQPLLPD;
|
|
output [1:0] PCIERATEQPLLRESET;
|
|
output PCIESYNCTXSYNCDONE;
|
|
output PCIEUSERGEN3RDY;
|
|
output PCIEUSERPHYSTATUSRST;
|
|
output PCIEUSERRATESTART;
|
|
output [15:0] PCSRSVDOUT;
|
|
output PHYSTATUS;
|
|
output [15:0] PINRSRVDAS;
|
|
output POWERPRESENT;
|
|
output RESETEXCEPTION;
|
|
output [2:0] RXBUFSTATUS;
|
|
output RXBYTEISALIGNED;
|
|
output RXBYTEREALIGN;
|
|
output RXCDRLOCK;
|
|
output RXCDRPHDONE;
|
|
output RXCHANBONDSEQ;
|
|
output RXCHANISALIGNED;
|
|
output RXCHANREALIGN;
|
|
output [4:0] RXCHBONDO;
|
|
output RXCKCALDONE;
|
|
output [1:0] RXCLKCORCNT;
|
|
output RXCOMINITDET;
|
|
output RXCOMMADET;
|
|
output RXCOMSASDET;
|
|
output RXCOMWAKEDET;
|
|
output [15:0] RXCTRL0;
|
|
output [15:0] RXCTRL1;
|
|
output [7:0] RXCTRL2;
|
|
output [7:0] RXCTRL3;
|
|
output [127:0] RXDATA;
|
|
output [7:0] RXDATAEXTENDRSVD;
|
|
output [1:0] RXDATAVALID;
|
|
output RXDLYSRESETDONE;
|
|
output RXELECIDLE;
|
|
output [5:0] RXHEADER;
|
|
output [1:0] RXHEADERVALID;
|
|
output RXLFPSTRESETDET;
|
|
output RXLFPSU2LPEXITDET;
|
|
output RXLFPSU3WAKEDET;
|
|
output [7:0] RXMONITOROUT;
|
|
output RXOSINTDONE;
|
|
output RXOSINTSTARTED;
|
|
output RXOSINTSTROBEDONE;
|
|
output RXOSINTSTROBESTARTED;
|
|
output RXOUTCLK;
|
|
output RXOUTCLKFABRIC;
|
|
output RXOUTCLKPCS;
|
|
output RXPHALIGNDONE;
|
|
output RXPHALIGNERR;
|
|
output RXPMARESETDONE;
|
|
output RXPRBSERR;
|
|
output RXPRBSLOCKED;
|
|
output RXPRGDIVRESETDONE;
|
|
output RXQPISENN;
|
|
output RXQPISENP;
|
|
output RXRATEDONE;
|
|
output RXRECCLKOUT;
|
|
output RXRESETDONE;
|
|
output RXSLIDERDY;
|
|
output RXSLIPDONE;
|
|
output RXSLIPOUTCLKRDY;
|
|
output RXSLIPPMARDY;
|
|
output [1:0] RXSTARTOFSEQ;
|
|
output [2:0] RXSTATUS;
|
|
output RXSYNCDONE;
|
|
output RXSYNCOUT;
|
|
output RXVALID;
|
|
output [1:0] TXBUFSTATUS;
|
|
output TXCOMFINISH;
|
|
output TXDCCDONE;
|
|
output TXDLYSRESETDONE;
|
|
output TXOUTCLK;
|
|
output TXOUTCLKFABRIC;
|
|
output TXOUTCLKPCS;
|
|
output TXPHALIGNDONE;
|
|
output TXPHINITDONE;
|
|
output TXPMARESETDONE;
|
|
output TXPRGDIVRESETDONE;
|
|
output TXQPISENN;
|
|
output TXQPISENP;
|
|
output TXRATEDONE;
|
|
output TXRESETDONE;
|
|
output TXSYNCDONE;
|
|
output TXSYNCOUT;
|
|
input CDRSTEPDIR;
|
|
input CDRSTEPSQ;
|
|
input CDRSTEPSX;
|
|
input CFGRESET;
|
|
input CLKRSVD0;
|
|
input CLKRSVD1;
|
|
input CPLLFREQLOCK;
|
|
input CPLLLOCKDETCLK;
|
|
input CPLLLOCKEN;
|
|
input CPLLPD;
|
|
input [2:0] CPLLREFCLKSEL;
|
|
input CPLLRESET;
|
|
input DMONFIFORESET;
|
|
input DMONITORCLK;
|
|
input [9:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPRST;
|
|
input DRPWE;
|
|
input EYESCANRESET;
|
|
input EYESCANTRIGGER;
|
|
input FREQOS;
|
|
input GTGREFCLK;
|
|
input GTHRXN;
|
|
input GTHRXP;
|
|
input GTNORTHREFCLK0;
|
|
input GTNORTHREFCLK1;
|
|
input GTREFCLK0;
|
|
input GTREFCLK1;
|
|
input [15:0] GTRSVD;
|
|
input GTRXRESET;
|
|
input GTRXRESETSEL;
|
|
input GTSOUTHREFCLK0;
|
|
input GTSOUTHREFCLK1;
|
|
input GTTXRESET;
|
|
input GTTXRESETSEL;
|
|
input INCPCTRL;
|
|
input [2:0] LOOPBACK;
|
|
input PCIEEQRXEQADAPTDONE;
|
|
input PCIERSTIDLE;
|
|
input PCIERSTTXSYNCSTART;
|
|
input PCIEUSERRATEDONE;
|
|
input [15:0] PCSRSVDIN;
|
|
input QPLL0CLK;
|
|
input QPLL0FREQLOCK;
|
|
input QPLL0REFCLK;
|
|
input QPLL1CLK;
|
|
input QPLL1FREQLOCK;
|
|
input QPLL1REFCLK;
|
|
input RESETOVRD;
|
|
input RX8B10BEN;
|
|
input RXAFECFOKEN;
|
|
input RXBUFRESET;
|
|
input RXCDRFREQRESET;
|
|
input RXCDRHOLD;
|
|
input RXCDROVRDEN;
|
|
input RXCDRRESET;
|
|
input RXCHBONDEN;
|
|
input [4:0] RXCHBONDI;
|
|
input [2:0] RXCHBONDLEVEL;
|
|
input RXCHBONDMASTER;
|
|
input RXCHBONDSLAVE;
|
|
input RXCKCALRESET;
|
|
input [6:0] RXCKCALSTART;
|
|
input RXCOMMADETEN;
|
|
input [1:0] RXDFEAGCCTRL;
|
|
input RXDFEAGCHOLD;
|
|
input RXDFEAGCOVRDEN;
|
|
input [3:0] RXDFECFOKFCNUM;
|
|
input RXDFECFOKFEN;
|
|
input RXDFECFOKFPULSE;
|
|
input RXDFECFOKHOLD;
|
|
input RXDFECFOKOVREN;
|
|
input RXDFEKHHOLD;
|
|
input RXDFEKHOVRDEN;
|
|
input RXDFELFHOLD;
|
|
input RXDFELFOVRDEN;
|
|
input RXDFELPMRESET;
|
|
input RXDFETAP10HOLD;
|
|
input RXDFETAP10OVRDEN;
|
|
input RXDFETAP11HOLD;
|
|
input RXDFETAP11OVRDEN;
|
|
input RXDFETAP12HOLD;
|
|
input RXDFETAP12OVRDEN;
|
|
input RXDFETAP13HOLD;
|
|
input RXDFETAP13OVRDEN;
|
|
input RXDFETAP14HOLD;
|
|
input RXDFETAP14OVRDEN;
|
|
input RXDFETAP15HOLD;
|
|
input RXDFETAP15OVRDEN;
|
|
input RXDFETAP2HOLD;
|
|
input RXDFETAP2OVRDEN;
|
|
input RXDFETAP3HOLD;
|
|
input RXDFETAP3OVRDEN;
|
|
input RXDFETAP4HOLD;
|
|
input RXDFETAP4OVRDEN;
|
|
input RXDFETAP5HOLD;
|
|
input RXDFETAP5OVRDEN;
|
|
input RXDFETAP6HOLD;
|
|
input RXDFETAP6OVRDEN;
|
|
input RXDFETAP7HOLD;
|
|
input RXDFETAP7OVRDEN;
|
|
input RXDFETAP8HOLD;
|
|
input RXDFETAP8OVRDEN;
|
|
input RXDFETAP9HOLD;
|
|
input RXDFETAP9OVRDEN;
|
|
input RXDFEUTHOLD;
|
|
input RXDFEUTOVRDEN;
|
|
input RXDFEVPHOLD;
|
|
input RXDFEVPOVRDEN;
|
|
input RXDFEXYDEN;
|
|
input RXDLYBYPASS;
|
|
input RXDLYEN;
|
|
input RXDLYOVRDEN;
|
|
input RXDLYSRESET;
|
|
input [1:0] RXELECIDLEMODE;
|
|
input RXEQTRAINING;
|
|
input RXGEARBOXSLIP;
|
|
input RXLATCLK;
|
|
input RXLPMEN;
|
|
input RXLPMGCHOLD;
|
|
input RXLPMGCOVRDEN;
|
|
input RXLPMHFHOLD;
|
|
input RXLPMHFOVRDEN;
|
|
input RXLPMLFHOLD;
|
|
input RXLPMLFKLOVRDEN;
|
|
input RXLPMOSHOLD;
|
|
input RXLPMOSOVRDEN;
|
|
input RXMCOMMAALIGNEN;
|
|
input [1:0] RXMONITORSEL;
|
|
input RXOOBRESET;
|
|
input RXOSCALRESET;
|
|
input RXOSHOLD;
|
|
input RXOSOVRDEN;
|
|
input [2:0] RXOUTCLKSEL;
|
|
input RXPCOMMAALIGNEN;
|
|
input RXPCSRESET;
|
|
input [1:0] RXPD;
|
|
input RXPHALIGN;
|
|
input RXPHALIGNEN;
|
|
input RXPHDLYPD;
|
|
input RXPHDLYRESET;
|
|
input RXPHOVRDEN;
|
|
input [1:0] RXPLLCLKSEL;
|
|
input RXPMARESET;
|
|
input RXPOLARITY;
|
|
input RXPRBSCNTRESET;
|
|
input [3:0] RXPRBSSEL;
|
|
input RXPROGDIVRESET;
|
|
input RXQPIEN;
|
|
input [2:0] RXRATE;
|
|
input RXRATEMODE;
|
|
input RXSLIDE;
|
|
input RXSLIPOUTCLK;
|
|
input RXSLIPPMA;
|
|
input RXSYNCALLIN;
|
|
input RXSYNCIN;
|
|
input RXSYNCMODE;
|
|
input [1:0] RXSYSCLKSEL;
|
|
input RXTERMINATION;
|
|
input RXUSERRDY;
|
|
input RXUSRCLK;
|
|
input RXUSRCLK2;
|
|
input SIGVALIDCLK;
|
|
input [19:0] TSTIN;
|
|
input [7:0] TX8B10BBYPASS;
|
|
input TX8B10BEN;
|
|
input TXCOMINIT;
|
|
input TXCOMSAS;
|
|
input TXCOMWAKE;
|
|
input [15:0] TXCTRL0;
|
|
input [15:0] TXCTRL1;
|
|
input [7:0] TXCTRL2;
|
|
input [127:0] TXDATA;
|
|
input [7:0] TXDATAEXTENDRSVD;
|
|
input TXDCCFORCESTART;
|
|
input TXDCCRESET;
|
|
input [1:0] TXDEEMPH;
|
|
input TXDETECTRX;
|
|
input [4:0] TXDIFFCTRL;
|
|
input TXDLYBYPASS;
|
|
input TXDLYEN;
|
|
input TXDLYHOLD;
|
|
input TXDLYOVRDEN;
|
|
input TXDLYSRESET;
|
|
input TXDLYUPDOWN;
|
|
input TXELECIDLE;
|
|
input [5:0] TXHEADER;
|
|
input TXINHIBIT;
|
|
input TXLATCLK;
|
|
input TXLFPSTRESET;
|
|
input TXLFPSU2LPEXIT;
|
|
input TXLFPSU3WAKE;
|
|
input [6:0] TXMAINCURSOR;
|
|
input [2:0] TXMARGIN;
|
|
input TXMUXDCDEXHOLD;
|
|
input TXMUXDCDORWREN;
|
|
input TXONESZEROS;
|
|
input [2:0] TXOUTCLKSEL;
|
|
input TXPCSRESET;
|
|
input [1:0] TXPD;
|
|
input TXPDELECIDLEMODE;
|
|
input TXPHALIGN;
|
|
input TXPHALIGNEN;
|
|
input TXPHDLYPD;
|
|
input TXPHDLYRESET;
|
|
input TXPHDLYTSTCLK;
|
|
input TXPHINIT;
|
|
input TXPHOVRDEN;
|
|
input TXPIPPMEN;
|
|
input TXPIPPMOVRDEN;
|
|
input TXPIPPMPD;
|
|
input TXPIPPMSEL;
|
|
input [4:0] TXPIPPMSTEPSIZE;
|
|
input TXPISOPD;
|
|
input [1:0] TXPLLCLKSEL;
|
|
input TXPMARESET;
|
|
input TXPOLARITY;
|
|
input [4:0] TXPOSTCURSOR;
|
|
input TXPRBSFORCEERR;
|
|
input [3:0] TXPRBSSEL;
|
|
input [4:0] TXPRECURSOR;
|
|
input TXPROGDIVRESET;
|
|
input TXQPIBIASEN;
|
|
input TXQPIWEAKPUP;
|
|
input [2:0] TXRATE;
|
|
input TXRATEMODE;
|
|
input [6:0] TXSEQUENCE;
|
|
input TXSWING;
|
|
input TXSYNCALLIN;
|
|
input TXSYNCIN;
|
|
input TXSYNCMODE;
|
|
input [1:0] TXSYSCLKSEL;
|
|
input TXUSERRDY;
|
|
input TXUSRCLK;
|
|
input TXUSRCLK2;
|
|
endmodule
|
|
|
|
module GTHE4_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0SEL, RXRECCLK1SEL, SDM0FINALOUT
|
|
, SDM0TESTDATA, SDM1FINALOUT, SDM1TESTDATA, TCONGPO, TCONRSVDOUT0, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11
|
|
, GTREFCLK00, GTREFCLK01, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PCIERATEQPLL0, PCIERATEQPLL1, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0CLKRSVD1, QPLL0FBDIV, QPLL0LOCKDETCLK, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0
|
|
, QPLL1CLKRSVD1, QPLL1FBDIV, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1, QPLLRSVD2, QPLLRSVD3, QPLLRSVD4, RCALENB, SDM0DATA, SDM0RESET, SDM0TOGGLE, SDM0WIDTH, SDM1DATA, SDM1RESET, SDM1TOGGLE, SDM1WIDTH, TCONGPI
|
|
, TCONPOWERUP, TCONRESET, TCONRSVDIN1);
|
|
parameter [0:0] AEN_QPLL0_FBDIV = 1'b1;
|
|
parameter [0:0] AEN_QPLL1_FBDIV = 1'b1;
|
|
parameter [0:0] AEN_SDM0TOGGLE = 1'b0;
|
|
parameter [0:0] AEN_SDM1TOGGLE = 1'b0;
|
|
parameter [0:0] A_SDM0TOGGLE = 1'b0;
|
|
parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000;
|
|
parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000;
|
|
parameter [0:0] A_SDM1TOGGLE = 1'b0;
|
|
parameter [15:0] BIAS_CFG0 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG1 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG2 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG3 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG4 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG_RSVD = 16'h0000;
|
|
parameter [15:0] COMMON_CFG0 = 16'h0000;
|
|
parameter [15:0] COMMON_CFG1 = 16'h0000;
|
|
parameter [15:0] POR_CFG = 16'h0000;
|
|
parameter [15:0] PPF0_CFG = 16'h0F00;
|
|
parameter [15:0] PPF1_CFG = 16'h0F00;
|
|
parameter QPLL0CLKOUT_RATE = "FULL";
|
|
parameter [15:0] QPLL0_CFG0 = 16'h391C;
|
|
parameter [15:0] QPLL0_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
|
|
parameter [15:0] QPLL0_CFG2 = 16'h0F80;
|
|
parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80;
|
|
parameter [15:0] QPLL0_CFG3 = 16'h0120;
|
|
parameter [15:0] QPLL0_CFG4 = 16'h0002;
|
|
parameter [9:0] QPLL0_CP = 10'b0000011111;
|
|
parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
|
|
parameter integer QPLL0_FBDIV = 66;
|
|
parameter integer QPLL0_FBDIV_G3 = 80;
|
|
parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000;
|
|
parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
|
|
parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8;
|
|
parameter [9:0] QPLL0_LPF = 10'b1011111111;
|
|
parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
|
|
parameter [0:0] QPLL0_PCI_EN = 1'b0;
|
|
parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0;
|
|
parameter integer QPLL0_REFCLK_DIV = 1;
|
|
parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040;
|
|
parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000;
|
|
parameter QPLL1CLKOUT_RATE = "FULL";
|
|
parameter [15:0] QPLL1_CFG0 = 16'h691C;
|
|
parameter [15:0] QPLL1_CFG1 = 16'h0020;
|
|
parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
|
|
parameter [15:0] QPLL1_CFG2 = 16'h0F80;
|
|
parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80;
|
|
parameter [15:0] QPLL1_CFG3 = 16'h0120;
|
|
parameter [15:0] QPLL1_CFG4 = 16'h0002;
|
|
parameter [9:0] QPLL1_CP = 10'b0000011111;
|
|
parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
|
|
parameter integer QPLL1_FBDIV = 66;
|
|
parameter integer QPLL1_FBDIV_G3 = 80;
|
|
parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000;
|
|
parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
|
|
parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
|
|
parameter [9:0] QPLL1_LPF = 10'b1011111111;
|
|
parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
|
|
parameter [0:0] QPLL1_PCI_EN = 1'b0;
|
|
parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0;
|
|
parameter integer QPLL1_REFCLK_DIV = 1;
|
|
parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000;
|
|
parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR0 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR1 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR2 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR3 = 16'h0000;
|
|
parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
|
|
parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
|
|
parameter [0:0] SARC_ENB = 1'b0;
|
|
parameter [0:0] SARC_SEL = 1'b0;
|
|
parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
|
|
parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter SIM_MODE = "FAST";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output [7:0] PMARSVDOUT0;
|
|
output [7:0] PMARSVDOUT1;
|
|
output QPLL0FBCLKLOST;
|
|
output QPLL0LOCK;
|
|
output QPLL0OUTCLK;
|
|
output QPLL0OUTREFCLK;
|
|
output QPLL0REFCLKLOST;
|
|
output QPLL1FBCLKLOST;
|
|
output QPLL1LOCK;
|
|
output QPLL1OUTCLK;
|
|
output QPLL1OUTREFCLK;
|
|
output QPLL1REFCLKLOST;
|
|
output [7:0] QPLLDMONITOR0;
|
|
output [7:0] QPLLDMONITOR1;
|
|
output REFCLKOUTMONITOR0;
|
|
output REFCLKOUTMONITOR1;
|
|
output [1:0] RXRECCLK0SEL;
|
|
output [1:0] RXRECCLK1SEL;
|
|
output [3:0] SDM0FINALOUT;
|
|
output [14:0] SDM0TESTDATA;
|
|
output [3:0] SDM1FINALOUT;
|
|
output [14:0] SDM1TESTDATA;
|
|
output [9:0] TCONGPO;
|
|
output TCONRSVDOUT0;
|
|
input BGBYPASSB;
|
|
input BGMONITORENB;
|
|
input BGPDB;
|
|
input [4:0] BGRCALOVRD;
|
|
input BGRCALOVRDENB;
|
|
input [15:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input GTGREFCLK0;
|
|
input GTGREFCLK1;
|
|
input GTNORTHREFCLK00;
|
|
input GTNORTHREFCLK01;
|
|
input GTNORTHREFCLK10;
|
|
input GTNORTHREFCLK11;
|
|
input GTREFCLK00;
|
|
input GTREFCLK01;
|
|
input GTREFCLK10;
|
|
input GTREFCLK11;
|
|
input GTSOUTHREFCLK00;
|
|
input GTSOUTHREFCLK01;
|
|
input GTSOUTHREFCLK10;
|
|
input GTSOUTHREFCLK11;
|
|
input [2:0] PCIERATEQPLL0;
|
|
input [2:0] PCIERATEQPLL1;
|
|
input [7:0] PMARSVD0;
|
|
input [7:0] PMARSVD1;
|
|
input QPLL0CLKRSVD0;
|
|
input QPLL0CLKRSVD1;
|
|
input [7:0] QPLL0FBDIV;
|
|
input QPLL0LOCKDETCLK;
|
|
input QPLL0LOCKEN;
|
|
input QPLL0PD;
|
|
input [2:0] QPLL0REFCLKSEL;
|
|
input QPLL0RESET;
|
|
input QPLL1CLKRSVD0;
|
|
input QPLL1CLKRSVD1;
|
|
input [7:0] QPLL1FBDIV;
|
|
input QPLL1LOCKDETCLK;
|
|
input QPLL1LOCKEN;
|
|
input QPLL1PD;
|
|
input [2:0] QPLL1REFCLKSEL;
|
|
input QPLL1RESET;
|
|
input [7:0] QPLLRSVD1;
|
|
input [4:0] QPLLRSVD2;
|
|
input [4:0] QPLLRSVD3;
|
|
input [7:0] QPLLRSVD4;
|
|
input RCALENB;
|
|
input [24:0] SDM0DATA;
|
|
input SDM0RESET;
|
|
input SDM0TOGGLE;
|
|
input [1:0] SDM0WIDTH;
|
|
input [24:0] SDM1DATA;
|
|
input SDM1RESET;
|
|
input SDM1TOGGLE;
|
|
input [1:0] SDM1WIDTH;
|
|
input [9:0] TCONGPI;
|
|
input TCONPOWERUP;
|
|
input [1:0] TCONRESET;
|
|
input [1:0] TCONRSVDIN1;
|
|
endmodule
|
|
|
|
module GTYE4_CHANNEL(BUFGTCE, BUFGTCEMASK, BUFGTDIV, BUFGTRESET, BUFGTRSTMASK, CPLLFBCLKLOST, CPLLLOCK, CPLLREFCLKLOST, DMONITOROUT, DMONITOROUTCLK, DRPDO, DRPRDY, EYESCANDATAERROR, GTPOWERGOOD, GTREFCLKMONITOR, GTYTXN, GTYTXP, PCIERATEGEN3, PCIERATEIDLE, PCIERATEQPLLPD, PCIERATEQPLLRESET
|
|
, PCIESYNCTXSYNCDONE, PCIEUSERGEN3RDY, PCIEUSERPHYSTATUSRST, PCIEUSERRATESTART, PCSRSVDOUT, PHYSTATUS, PINRSRVDAS, POWERPRESENT, RESETEXCEPTION, RXBUFSTATUS, RXBYTEISALIGNED, RXBYTEREALIGN, RXCDRLOCK, RXCDRPHDONE, RXCHANBONDSEQ, RXCHANISALIGNED, RXCHANREALIGN, RXCHBONDO, RXCKCALDONE, RXCLKCORCNT, RXCOMINITDET
|
|
, RXCOMMADET, RXCOMSASDET, RXCOMWAKEDET, RXCTRL0, RXCTRL1, RXCTRL2, RXCTRL3, RXDATA, RXDATAEXTENDRSVD, RXDATAVALID, RXDLYSRESETDONE, RXELECIDLE, RXHEADER, RXHEADERVALID, RXLFPSTRESETDET, RXLFPSU2LPEXITDET, RXLFPSU3WAKEDET, RXMONITOROUT, RXOSINTDONE, RXOSINTSTARTED, RXOSINTSTROBEDONE
|
|
, RXOSINTSTROBESTARTED, RXOUTCLK, RXOUTCLKFABRIC, RXOUTCLKPCS, RXPHALIGNDONE, RXPHALIGNERR, RXPMARESETDONE, RXPRBSERR, RXPRBSLOCKED, RXPRGDIVRESETDONE, RXRATEDONE, RXRECCLKOUT, RXRESETDONE, RXSLIDERDY, RXSLIPDONE, RXSLIPOUTCLKRDY, RXSLIPPMARDY, RXSTARTOFSEQ, RXSTATUS, RXSYNCDONE, RXSYNCOUT
|
|
, RXVALID, TXBUFSTATUS, TXCOMFINISH, TXDCCDONE, TXDLYSRESETDONE, TXOUTCLK, TXOUTCLKFABRIC, TXOUTCLKPCS, TXPHALIGNDONE, TXPHINITDONE, TXPMARESETDONE, TXPRGDIVRESETDONE, TXRATEDONE, TXRESETDONE, TXSYNCDONE, TXSYNCOUT, CDRSTEPDIR, CDRSTEPSQ, CDRSTEPSX, CFGRESET, CLKRSVD0
|
|
, CLKRSVD1, CPLLFREQLOCK, CPLLLOCKDETCLK, CPLLLOCKEN, CPLLPD, CPLLREFCLKSEL, CPLLRESET, DMONFIFORESET, DMONITORCLK, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPRST, DRPWE, EYESCANRESET, EYESCANTRIGGER, FREQOS, GTGREFCLK, GTNORTHREFCLK0, GTNORTHREFCLK1
|
|
, GTREFCLK0, GTREFCLK1, GTRSVD, GTRXRESET, GTRXRESETSEL, GTSOUTHREFCLK0, GTSOUTHREFCLK1, GTTXRESET, GTTXRESETSEL, GTYRXN, GTYRXP, INCPCTRL, LOOPBACK, PCIEEQRXEQADAPTDONE, PCIERSTIDLE, PCIERSTTXSYNCSTART, PCIEUSERRATEDONE, PCSRSVDIN, QPLL0CLK, QPLL0FREQLOCK, QPLL0REFCLK
|
|
, QPLL1CLK, QPLL1FREQLOCK, QPLL1REFCLK, RESETOVRD, RX8B10BEN, RXAFECFOKEN, RXBUFRESET, RXCDRFREQRESET, RXCDRHOLD, RXCDROVRDEN, RXCDRRESET, RXCHBONDEN, RXCHBONDI, RXCHBONDLEVEL, RXCHBONDMASTER, RXCHBONDSLAVE, RXCKCALRESET, RXCKCALSTART, RXCOMMADETEN, RXDFEAGCHOLD, RXDFEAGCOVRDEN
|
|
, RXDFECFOKFCNUM, RXDFECFOKFEN, RXDFECFOKFPULSE, RXDFECFOKHOLD, RXDFECFOKOVREN, RXDFEKHHOLD, RXDFEKHOVRDEN, RXDFELFHOLD, RXDFELFOVRDEN, RXDFELPMRESET, RXDFETAP10HOLD, RXDFETAP10OVRDEN, RXDFETAP11HOLD, RXDFETAP11OVRDEN, RXDFETAP12HOLD, RXDFETAP12OVRDEN, RXDFETAP13HOLD, RXDFETAP13OVRDEN, RXDFETAP14HOLD, RXDFETAP14OVRDEN, RXDFETAP15HOLD
|
|
, RXDFETAP15OVRDEN, RXDFETAP2HOLD, RXDFETAP2OVRDEN, RXDFETAP3HOLD, RXDFETAP3OVRDEN, RXDFETAP4HOLD, RXDFETAP4OVRDEN, RXDFETAP5HOLD, RXDFETAP5OVRDEN, RXDFETAP6HOLD, RXDFETAP6OVRDEN, RXDFETAP7HOLD, RXDFETAP7OVRDEN, RXDFETAP8HOLD, RXDFETAP8OVRDEN, RXDFETAP9HOLD, RXDFETAP9OVRDEN, RXDFEUTHOLD, RXDFEUTOVRDEN, RXDFEVPHOLD, RXDFEVPOVRDEN
|
|
, RXDFEXYDEN, RXDLYBYPASS, RXDLYEN, RXDLYOVRDEN, RXDLYSRESET, RXELECIDLEMODE, RXEQTRAINING, RXGEARBOXSLIP, RXLATCLK, RXLPMEN, RXLPMGCHOLD, RXLPMGCOVRDEN, RXLPMHFHOLD, RXLPMHFOVRDEN, RXLPMLFHOLD, RXLPMLFKLOVRDEN, RXLPMOSHOLD, RXLPMOSOVRDEN, RXMCOMMAALIGNEN, RXMONITORSEL, RXOOBRESET
|
|
, RXOSCALRESET, RXOSHOLD, RXOSOVRDEN, RXOUTCLKSEL, RXPCOMMAALIGNEN, RXPCSRESET, RXPD, RXPHALIGN, RXPHALIGNEN, RXPHDLYPD, RXPHDLYRESET, RXPLLCLKSEL, RXPMARESET, RXPOLARITY, RXPRBSCNTRESET, RXPRBSSEL, RXPROGDIVRESET, RXRATE, RXRATEMODE, RXSLIDE, RXSLIPOUTCLK
|
|
, RXSLIPPMA, RXSYNCALLIN, RXSYNCIN, RXSYNCMODE, RXSYSCLKSEL, RXTERMINATION, RXUSERRDY, RXUSRCLK, RXUSRCLK2, SIGVALIDCLK, TSTIN, TX8B10BBYPASS, TX8B10BEN, TXCOMINIT, TXCOMSAS, TXCOMWAKE, TXCTRL0, TXCTRL1, TXCTRL2, TXDATA, TXDATAEXTENDRSVD
|
|
, TXDCCFORCESTART, TXDCCRESET, TXDEEMPH, TXDETECTRX, TXDIFFCTRL, TXDLYBYPASS, TXDLYEN, TXDLYHOLD, TXDLYOVRDEN, TXDLYSRESET, TXDLYUPDOWN, TXELECIDLE, TXHEADER, TXINHIBIT, TXLATCLK, TXLFPSTRESET, TXLFPSU2LPEXIT, TXLFPSU3WAKE, TXMAINCURSOR, TXMARGIN, TXMUXDCDEXHOLD
|
|
, TXMUXDCDORWREN, TXONESZEROS, TXOUTCLKSEL, TXPCSRESET, TXPD, TXPDELECIDLEMODE, TXPHALIGN, TXPHALIGNEN, TXPHDLYPD, TXPHDLYRESET, TXPHDLYTSTCLK, TXPHINIT, TXPHOVRDEN, TXPIPPMEN, TXPIPPMOVRDEN, TXPIPPMPD, TXPIPPMSEL, TXPIPPMSTEPSIZE, TXPISOPD, TXPLLCLKSEL, TXPMARESET
|
|
, TXPOLARITY, TXPOSTCURSOR, TXPRBSFORCEERR, TXPRBSSEL, TXPRECURSOR, TXPROGDIVRESET, TXRATE, TXRATEMODE, TXSEQUENCE, TXSWING, TXSYNCALLIN, TXSYNCIN, TXSYNCMODE, TXSYSCLKSEL, TXUSERRDY, TXUSRCLK, TXUSRCLK2);
|
|
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_MODE = 1'b0;
|
|
parameter [0:0] ACJTAG_RESET = 1'b0;
|
|
parameter [15:0] ADAPT_CFG0 = 16'h9200;
|
|
parameter [15:0] ADAPT_CFG1 = 16'h801C;
|
|
parameter [15:0] ADAPT_CFG2 = 16'h0000;
|
|
parameter ALIGN_COMMA_DOUBLE = "FALSE";
|
|
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
|
|
parameter integer ALIGN_COMMA_WORD = 1;
|
|
parameter ALIGN_MCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
|
|
parameter ALIGN_PCOMMA_DET = "TRUE";
|
|
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
|
|
parameter [0:0] A_RXOSCALRESET = 1'b0;
|
|
parameter [0:0] A_RXPROGDIVRESET = 1'b0;
|
|
parameter [0:0] A_RXTERMINATION = 1'b1;
|
|
parameter [4:0] A_TXDIFFCTRL = 5'b01100;
|
|
parameter [0:0] A_TXPROGDIVRESET = 1'b0;
|
|
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
|
|
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0;
|
|
parameter [0:0] CFOK_PWRSVE_EN = 1'b1;
|
|
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
|
|
parameter integer CHAN_BOND_MAX_SKEW = 7;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
|
|
parameter integer CHAN_BOND_SEQ_LEN = 2;
|
|
parameter [15:0] CH_HSPMUX = 16'h2424;
|
|
parameter [15:0] CKCAL1_CFG_0 = 16'b1100000011000000;
|
|
parameter [15:0] CKCAL1_CFG_1 = 16'b0101000011000000;
|
|
parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_0 = 16'b1100000011000000;
|
|
parameter [15:0] CKCAL2_CFG_1 = 16'b1000000011000000;
|
|
parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000;
|
|
parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000;
|
|
parameter CLK_CORRECT_USE = "TRUE";
|
|
parameter CLK_COR_KEEP_IDLE = "FALSE";
|
|
parameter integer CLK_COR_MAX_LAT = 20;
|
|
parameter integer CLK_COR_MIN_LAT = 18;
|
|
parameter CLK_COR_PRECEDENCE = "TRUE";
|
|
parameter integer CLK_COR_REPEAT_WAIT = 0;
|
|
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
|
|
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
|
|
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
|
|
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
|
|
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
|
|
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
|
|
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
|
|
parameter CLK_COR_SEQ_2_USE = "FALSE";
|
|
parameter integer CLK_COR_SEQ_LEN = 2;
|
|
parameter [15:0] CPLL_CFG0 = 16'h01FA;
|
|
parameter [15:0] CPLL_CFG1 = 16'h24A9;
|
|
parameter [15:0] CPLL_CFG2 = 16'h6807;
|
|
parameter [15:0] CPLL_CFG3 = 16'h0000;
|
|
parameter integer CPLL_FBDIV = 4;
|
|
parameter integer CPLL_FBDIV_45 = 4;
|
|
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E;
|
|
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8;
|
|
parameter integer CPLL_REFCLK_DIV = 1;
|
|
parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000;
|
|
parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0;
|
|
parameter [1:0] DDI_CTRL = 2'b00;
|
|
parameter integer DDI_REALIGN_WAIT = 15;
|
|
parameter DEC_MCOMMA_DETECT = "TRUE";
|
|
parameter DEC_PCOMMA_DETECT = "TRUE";
|
|
parameter DEC_VALID_COMMA_ONLY = "TRUE";
|
|
parameter [0:0] DELAY_ELEC = 1'b0;
|
|
parameter [9:0] DMONITOR_CFG0 = 10'h000;
|
|
parameter [7:0] DMONITOR_CFG1 = 8'h00;
|
|
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
|
|
parameter [5:0] ES_CONTROL = 6'b000000;
|
|
parameter ES_ERRDET_EN = "FALSE";
|
|
parameter ES_EYE_SCAN_EN = "FALSE";
|
|
parameter [11:0] ES_HORZ_OFFSET = 12'h800;
|
|
parameter [4:0] ES_PRESCALE = 5'b00000;
|
|
parameter [15:0] ES_QUALIFIER0 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER1 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER2 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER3 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER4 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER5 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER6 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER7 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER8 = 16'h0000;
|
|
parameter [15:0] ES_QUALIFIER9 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK0 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK1 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK2 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK3 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK4 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK5 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK6 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK7 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK8 = 16'h0000;
|
|
parameter [15:0] ES_QUAL_MASK9 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK0 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK1 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK2 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK3 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK4 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK5 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK6 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK7 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK8 = 16'h0000;
|
|
parameter [15:0] ES_SDATA_MASK9 = 16'h0000;
|
|
parameter integer EYESCAN_VP_RANGE = 0;
|
|
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0;
|
|
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
|
|
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
|
|
parameter FTS_LANE_DESKEW_EN = "FALSE";
|
|
parameter [4:0] GEARBOX_MODE = 5'b00000;
|
|
parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0;
|
|
parameter [0:0] LOCAL_MASTER = 1'b0;
|
|
parameter integer LPBK_BIAS_CTRL = 4;
|
|
parameter [0:0] LPBK_EN_RCAL_B = 1'b0;
|
|
parameter [3:0] LPBK_EXT_RCAL = 4'b0000;
|
|
parameter integer LPBK_IND_CTRL0 = 5;
|
|
parameter integer LPBK_IND_CTRL1 = 5;
|
|
parameter integer LPBK_IND_CTRL2 = 5;
|
|
parameter integer LPBK_RG_CTRL = 2;
|
|
parameter [1:0] OOBDIVCTL = 2'b00;
|
|
parameter [0:0] OOB_PWRUP = 1'b0;
|
|
parameter PCI3_AUTO_REALIGN = "FRST_SMPL";
|
|
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1;
|
|
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00;
|
|
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0;
|
|
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000;
|
|
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000;
|
|
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000;
|
|
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0;
|
|
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0;
|
|
parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000;
|
|
parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000;
|
|
parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000;
|
|
parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100;
|
|
parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000;
|
|
parameter PCIE_64B_DYN_CLKSW_DIS = "FALSE";
|
|
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000;
|
|
parameter PCIE_GEN4_64BIT_INT_EN = "FALSE";
|
|
parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0;
|
|
parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0;
|
|
parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0;
|
|
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000;
|
|
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000;
|
|
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000;
|
|
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000;
|
|
parameter PCS_PCIE_EN = "FALSE";
|
|
parameter [15:0] PCS_RSVD0 = 16'h0000;
|
|
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
|
|
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
|
|
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
|
|
parameter integer PREIQ_FREQ_BST = 0;
|
|
parameter [0:0] RATE_SW_USE_DRP = 1'b0;
|
|
parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0;
|
|
parameter [0:0] RCLK_SIPO_INV_EN = 1'b0;
|
|
parameter [2:0] RTX_BUF_CML_CTRL = 3'b010;
|
|
parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00;
|
|
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
|
|
parameter RXBUF_ADDR_MODE = "FULL";
|
|
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
|
|
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
|
|
parameter RXBUF_EN = "TRUE";
|
|
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
|
|
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
|
|
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
|
|
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
|
|
parameter integer RXBUF_THRESH_OVFLW = 0;
|
|
parameter RXBUF_THRESH_OVRD = "FALSE";
|
|
parameter integer RXBUF_THRESH_UNDFLW = 4;
|
|
parameter [4:0] RXCDRFREQRESET_TIME = 5'b10000;
|
|
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXCDR_CFG0 = 16'h0003;
|
|
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003;
|
|
parameter [15:0] RXCDR_CFG1 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000;
|
|
parameter [15:0] RXCDR_CFG2 = 16'h0164;
|
|
parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164;
|
|
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034;
|
|
parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034;
|
|
parameter [15:0] RXCDR_CFG3 = 16'h0024;
|
|
parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24;
|
|
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024;
|
|
parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024;
|
|
parameter [15:0] RXCDR_CFG4 = 16'h5CF6;
|
|
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6;
|
|
parameter [15:0] RXCDR_CFG5 = 16'hB46B;
|
|
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B;
|
|
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
|
|
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040;
|
|
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000;
|
|
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000;
|
|
parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000;
|
|
parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000;
|
|
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
|
|
parameter [15:0] RXCFOK_CFG0 = 16'h0000;
|
|
parameter [15:0] RXCFOK_CFG1 = 16'h0002;
|
|
parameter [15:0] RXCFOK_CFG2 = 16'h002D;
|
|
parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000;
|
|
parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000;
|
|
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111;
|
|
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022;
|
|
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100;
|
|
parameter [15:0] RXDFE_CFG0 = 16'h4000;
|
|
parameter [15:0] RXDFE_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_GC_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_GC_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000;
|
|
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H2_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H3_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H3_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H4_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003;
|
|
parameter [15:0] RXDFE_H5_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H5_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H6_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H6_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H7_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H7_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H8_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H8_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_H9_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_H9_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HA_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HA_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HB_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HB_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HC_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HD_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HE_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_HF_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_KH_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_KH_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_KH_CFG2 = 16'h0000;
|
|
parameter [15:0] RXDFE_KH_CFG3 = 16'h2000;
|
|
parameter [15:0] RXDFE_OS_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_OS_CFG1 = 16'h0000;
|
|
parameter [15:0] RXDFE_UT_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_UT_CFG1 = 16'h0002;
|
|
parameter [15:0] RXDFE_UT_CFG2 = 16'h0000;
|
|
parameter [15:0] RXDFE_VP_CFG0 = 16'h0000;
|
|
parameter [15:0] RXDFE_VP_CFG1 = 16'h0022;
|
|
parameter [15:0] RXDLY_CFG = 16'h0010;
|
|
parameter [15:0] RXDLY_LCFG = 16'h0030;
|
|
parameter RXELECIDLE_CFG = "SIGCFG_4";
|
|
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4;
|
|
parameter RXGEARBOX_EN = "FALSE";
|
|
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXLPM_CFG = 16'h0000;
|
|
parameter [15:0] RXLPM_GC_CFG = 16'h1000;
|
|
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000;
|
|
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002;
|
|
parameter [15:0] RXLPM_OS_CFG0 = 16'h0000;
|
|
parameter [15:0] RXLPM_OS_CFG1 = 16'h0000;
|
|
parameter [8:0] RXOOB_CFG = 9'b000110000;
|
|
parameter RXOOB_CLK_CFG = "PMA";
|
|
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
|
|
parameter integer RXOUT_DIV = 4;
|
|
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
|
|
parameter [15:0] RXPHBEACON_CFG = 16'h0000;
|
|
parameter [15:0] RXPHDLY_CFG = 16'h2020;
|
|
parameter [15:0] RXPHSAMP_CFG = 16'h2100;
|
|
parameter [15:0] RXPHSLIP_CFG = 16'h9933;
|
|
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [15:0] RXPI_CFG0 = 16'h0102;
|
|
parameter [15:0] RXPI_CFG1 = 16'b0000000001010100;
|
|
parameter RXPMACLK_SEL = "DATA";
|
|
parameter [4:0] RXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
|
|
parameter integer RXPRBS_LINKACQ_CNT = 15;
|
|
parameter [0:0] RXREFCLKDIV2_SEL = 1'b0;
|
|
parameter integer RXSLIDE_AUTO_WAIT = 7;
|
|
parameter RXSLIDE_MODE = "OFF";
|
|
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] RXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
|
|
parameter [0:0] RX_AFE_CM_EN = 1'b0;
|
|
parameter [15:0] RX_BIAS_CFG0 = 16'h12B0;
|
|
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
|
|
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0;
|
|
parameter integer RX_CLK25_DIV = 8;
|
|
parameter [0:0] RX_CLKMUX_EN = 1'b1;
|
|
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000;
|
|
parameter [3:0] RX_CM_BUF_CFG = 4'b1010;
|
|
parameter [0:0] RX_CM_BUF_PD = 1'b0;
|
|
parameter integer RX_CM_SEL = 2;
|
|
parameter integer RX_CM_TRIM = 12;
|
|
parameter [0:0] RX_CTLE_PWR_SAVING = 1'b0;
|
|
parameter [3:0] RX_CTLE_RES_CTRL = 4'b0000;
|
|
parameter integer RX_DATA_WIDTH = 20;
|
|
parameter [5:0] RX_DDI_SEL = 6'b000000;
|
|
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
|
|
parameter [2:0] RX_DEGEN_CTRL = 3'b100;
|
|
parameter integer RX_DFELPM_CFG0 = 10;
|
|
parameter [0:0] RX_DFELPM_CFG1 = 1'b1;
|
|
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1;
|
|
parameter integer RX_DFE_AGC_CFG1 = 4;
|
|
parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1;
|
|
parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2;
|
|
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01;
|
|
parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4;
|
|
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
|
|
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
|
|
parameter [4:0] RX_DIVRESET_TIME = 5'b00001;
|
|
parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0;
|
|
parameter integer RX_EN_SUM_RCAL_B = 0;
|
|
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000;
|
|
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0;
|
|
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b10;
|
|
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0;
|
|
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0;
|
|
parameter [0:0] RX_I2V_FILTER_EN = 1'b1;
|
|
parameter integer RX_INT_DATAWIDTH = 1;
|
|
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0;
|
|
parameter [15:0] RX_PMA_RSV0 = 16'h002F;
|
|
parameter real RX_PROGDIV_CFG = 0.0;
|
|
parameter [15:0] RX_PROGDIV_RATE = 16'h0001;
|
|
parameter [3:0] RX_RESLOAD_CTRL = 4'b0000;
|
|
parameter [0:0] RX_RESLOAD_OVRD = 1'b0;
|
|
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101;
|
|
parameter integer RX_SIG_VALID_DLY = 11;
|
|
parameter integer RX_SUM_DEGEN_AVTT_OVERITE = 0;
|
|
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0;
|
|
parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000;
|
|
parameter integer RX_SUM_PWR_SAVING = 0;
|
|
parameter [3:0] RX_SUM_RES_CTRL = 4'b0000;
|
|
parameter [3:0] RX_SUM_VCMTUNE = 4'b0011;
|
|
parameter [0:0] RX_SUM_VCM_BIAS_TUNE_EN = 1'b1;
|
|
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0;
|
|
parameter [2:0] RX_SUM_VREF_TUNE = 3'b100;
|
|
parameter [1:0] RX_TUNE_AFE_OS = 2'b00;
|
|
parameter [2:0] RX_VREG_CTRL = 3'b010;
|
|
parameter [0:0] RX_VREG_PDB = 1'b1;
|
|
parameter [1:0] RX_WIDEMODE_CDR = 2'b01;
|
|
parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01;
|
|
parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01;
|
|
parameter RX_XCLK_SEL = "RXDES";
|
|
parameter [0:0] RX_XMODE_SEL = 1'b0;
|
|
parameter [0:0] SAMPLE_CLK_PHASE = 1'b0;
|
|
parameter [0:0] SAS_12G_MODE = 1'b0;
|
|
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
|
|
parameter [2:0] SATA_BURST_VAL = 3'b100;
|
|
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
|
|
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
|
|
parameter SHOW_REALIGN_COMMA = "TRUE";
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter SIM_MODE = "FAST";
|
|
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z";
|
|
parameter [0:0] SRSTMODE = 1'b0;
|
|
parameter [1:0] TAPDLY_SET_TX = 2'h0;
|
|
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
|
|
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
|
|
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
|
|
parameter [7:0] TST_RSV0 = 8'h00;
|
|
parameter [7:0] TST_RSV1 = 8'h00;
|
|
parameter TXBUF_EN = "TRUE";
|
|
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
|
|
parameter [15:0] TXDLY_CFG = 16'h0010;
|
|
parameter [15:0] TXDLY_LCFG = 16'h0030;
|
|
parameter integer TXDRV_FREQBAND = 0;
|
|
parameter [15:0] TXFE_CFG0 = 16'b0000000000000000;
|
|
parameter [15:0] TXFE_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] TXFE_CFG2 = 16'b0000000000000000;
|
|
parameter [15:0] TXFE_CFG3 = 16'b0000000000000000;
|
|
parameter TXFIFO_ADDR_CFG = "LOW";
|
|
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4;
|
|
parameter TXGEARBOX_EN = "FALSE";
|
|
parameter integer TXOUT_DIV = 4;
|
|
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
|
|
parameter [15:0] TXPHDLY_CFG0 = 16'h6020;
|
|
parameter [15:0] TXPHDLY_CFG1 = 16'h0002;
|
|
parameter [15:0] TXPH_CFG = 16'h0123;
|
|
parameter [15:0] TXPH_CFG2 = 16'h0000;
|
|
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
|
|
parameter [15:0] TXPI_CFG0 = 16'b0000000100000000;
|
|
parameter [15:0] TXPI_CFG1 = 16'b0000000000000000;
|
|
parameter [0:0] TXPI_GRAY_SEL = 1'b0;
|
|
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
|
|
parameter [0:0] TXPI_PPM = 1'b0;
|
|
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
|
|
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
|
|
parameter [4:0] TXPMARESET_TIME = 5'b00001;
|
|
parameter [0:0] TXREFCLKDIV2_SEL = 1'b0;
|
|
parameter integer TXSWBST_BST = 1;
|
|
parameter integer TXSWBST_EN = 0;
|
|
parameter integer TXSWBST_MAG = 6;
|
|
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
|
|
parameter [0:0] TXSYNC_OVRD = 1'b0;
|
|
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
|
|
parameter integer TX_CLK25_DIV = 8;
|
|
parameter [0:0] TX_CLKMUX_EN = 1'b1;
|
|
parameter integer TX_DATA_WIDTH = 20;
|
|
parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000;
|
|
parameter [5:0] TX_DEEMPH0 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH1 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH2 = 6'b000000;
|
|
parameter [5:0] TX_DEEMPH3 = 6'b000000;
|
|
parameter [4:0] TX_DIVRESET_TIME = 5'b00001;
|
|
parameter TX_DRIVE_MODE = "DIRECT";
|
|
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
|
|
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
|
|
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0;
|
|
parameter [0:0] TX_FIFO_BYP_EN = 1'b0;
|
|
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0;
|
|
parameter integer TX_INT_DATAWIDTH = 1;
|
|
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
|
|
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
|
|
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
|
|
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
|
|
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
|
|
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
|
|
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
|
|
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
|
|
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
|
|
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
|
|
parameter [15:0] TX_PHICAL_CFG0 = 16'h0000;
|
|
parameter [15:0] TX_PHICAL_CFG1 = 16'h003F;
|
|
parameter integer TX_PI_BIASSET = 0;
|
|
parameter [0:0] TX_PMADATA_OPT = 1'b0;
|
|
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0;
|
|
parameter [15:0] TX_PMA_RSV0 = 16'h0000;
|
|
parameter [15:0] TX_PMA_RSV1 = 16'h0000;
|
|
parameter TX_PROGCLK_SEL = "POSTPI";
|
|
parameter real TX_PROGDIV_CFG = 0.0;
|
|
parameter [15:0] TX_PROGDIV_RATE = 16'h0001;
|
|
parameter [13:0] TX_RXDETECT_CFG = 14'h0032;
|
|
parameter integer TX_RXDETECT_REF = 3;
|
|
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101;
|
|
parameter [1:0] TX_SW_MEAS = 2'b00;
|
|
parameter [2:0] TX_VREG_CTRL = 3'b000;
|
|
parameter [0:0] TX_VREG_PDB = 1'b0;
|
|
parameter [1:0] TX_VREG_VREFSEL = 2'b00;
|
|
parameter TX_XCLK_SEL = "TXOUT";
|
|
parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0;
|
|
parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111;
|
|
parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011;
|
|
parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0;
|
|
parameter [0:0] USB_EXT_CNTL = 1'b1;
|
|
parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011;
|
|
parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011;
|
|
parameter [8:0] USB_LFPSPING_BURST = 9'b000000101;
|
|
parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001;
|
|
parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100;
|
|
parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101;
|
|
parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011;
|
|
parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011;
|
|
parameter [3:0] USB_LFPS_TPERIOD = 4'b0011;
|
|
parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1;
|
|
parameter [0:0] USB_MODE = 1'b0;
|
|
parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0;
|
|
parameter integer USB_PING_SATA_MAX_INIT = 21;
|
|
parameter integer USB_PING_SATA_MIN_INIT = 12;
|
|
parameter integer USB_POLL_SATA_MAX_BURST = 8;
|
|
parameter integer USB_POLL_SATA_MIN_BURST = 4;
|
|
parameter [0:0] USB_RAW_ELEC = 1'b0;
|
|
parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1;
|
|
parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1;
|
|
parameter integer USB_U1_SATA_MAX_WAKE = 7;
|
|
parameter integer USB_U1_SATA_MIN_WAKE = 4;
|
|
parameter integer USB_U2_SAS_MAX_COM = 64;
|
|
parameter integer USB_U2_SAS_MIN_COM = 36;
|
|
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
|
|
parameter [0:0] Y_ALL_MODE = 1'b0;
|
|
output BUFGTCE;
|
|
output [2:0] BUFGTCEMASK;
|
|
output [8:0] BUFGTDIV;
|
|
output BUFGTRESET;
|
|
output [2:0] BUFGTRSTMASK;
|
|
output CPLLFBCLKLOST;
|
|
output CPLLLOCK;
|
|
output CPLLREFCLKLOST;
|
|
output [15:0] DMONITOROUT;
|
|
output DMONITOROUTCLK;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output EYESCANDATAERROR;
|
|
output GTPOWERGOOD;
|
|
output GTREFCLKMONITOR;
|
|
output GTYTXN;
|
|
output GTYTXP;
|
|
output PCIERATEGEN3;
|
|
output PCIERATEIDLE;
|
|
output [1:0] PCIERATEQPLLPD;
|
|
output [1:0] PCIERATEQPLLRESET;
|
|
output PCIESYNCTXSYNCDONE;
|
|
output PCIEUSERGEN3RDY;
|
|
output PCIEUSERPHYSTATUSRST;
|
|
output PCIEUSERRATESTART;
|
|
output [15:0] PCSRSVDOUT;
|
|
output PHYSTATUS;
|
|
output [15:0] PINRSRVDAS;
|
|
output POWERPRESENT;
|
|
output RESETEXCEPTION;
|
|
output [2:0] RXBUFSTATUS;
|
|
output RXBYTEISALIGNED;
|
|
output RXBYTEREALIGN;
|
|
output RXCDRLOCK;
|
|
output RXCDRPHDONE;
|
|
output RXCHANBONDSEQ;
|
|
output RXCHANISALIGNED;
|
|
output RXCHANREALIGN;
|
|
output [4:0] RXCHBONDO;
|
|
output RXCKCALDONE;
|
|
output [1:0] RXCLKCORCNT;
|
|
output RXCOMINITDET;
|
|
output RXCOMMADET;
|
|
output RXCOMSASDET;
|
|
output RXCOMWAKEDET;
|
|
output [15:0] RXCTRL0;
|
|
output [15:0] RXCTRL1;
|
|
output [7:0] RXCTRL2;
|
|
output [7:0] RXCTRL3;
|
|
output [127:0] RXDATA;
|
|
output [7:0] RXDATAEXTENDRSVD;
|
|
output [1:0] RXDATAVALID;
|
|
output RXDLYSRESETDONE;
|
|
output RXELECIDLE;
|
|
output [5:0] RXHEADER;
|
|
output [1:0] RXHEADERVALID;
|
|
output RXLFPSTRESETDET;
|
|
output RXLFPSU2LPEXITDET;
|
|
output RXLFPSU3WAKEDET;
|
|
output [7:0] RXMONITOROUT;
|
|
output RXOSINTDONE;
|
|
output RXOSINTSTARTED;
|
|
output RXOSINTSTROBEDONE;
|
|
output RXOSINTSTROBESTARTED;
|
|
output RXOUTCLK;
|
|
output RXOUTCLKFABRIC;
|
|
output RXOUTCLKPCS;
|
|
output RXPHALIGNDONE;
|
|
output RXPHALIGNERR;
|
|
output RXPMARESETDONE;
|
|
output RXPRBSERR;
|
|
output RXPRBSLOCKED;
|
|
output RXPRGDIVRESETDONE;
|
|
output RXRATEDONE;
|
|
output RXRECCLKOUT;
|
|
output RXRESETDONE;
|
|
output RXSLIDERDY;
|
|
output RXSLIPDONE;
|
|
output RXSLIPOUTCLKRDY;
|
|
output RXSLIPPMARDY;
|
|
output [1:0] RXSTARTOFSEQ;
|
|
output [2:0] RXSTATUS;
|
|
output RXSYNCDONE;
|
|
output RXSYNCOUT;
|
|
output RXVALID;
|
|
output [1:0] TXBUFSTATUS;
|
|
output TXCOMFINISH;
|
|
output TXDCCDONE;
|
|
output TXDLYSRESETDONE;
|
|
output TXOUTCLK;
|
|
output TXOUTCLKFABRIC;
|
|
output TXOUTCLKPCS;
|
|
output TXPHALIGNDONE;
|
|
output TXPHINITDONE;
|
|
output TXPMARESETDONE;
|
|
output TXPRGDIVRESETDONE;
|
|
output TXRATEDONE;
|
|
output TXRESETDONE;
|
|
output TXSYNCDONE;
|
|
output TXSYNCOUT;
|
|
input CDRSTEPDIR;
|
|
input CDRSTEPSQ;
|
|
input CDRSTEPSX;
|
|
input CFGRESET;
|
|
input CLKRSVD0;
|
|
input CLKRSVD1;
|
|
input CPLLFREQLOCK;
|
|
input CPLLLOCKDETCLK;
|
|
input CPLLLOCKEN;
|
|
input CPLLPD;
|
|
input [2:0] CPLLREFCLKSEL;
|
|
input CPLLRESET;
|
|
input DMONFIFORESET;
|
|
input DMONITORCLK;
|
|
input [9:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPRST;
|
|
input DRPWE;
|
|
input EYESCANRESET;
|
|
input EYESCANTRIGGER;
|
|
input FREQOS;
|
|
input GTGREFCLK;
|
|
input GTNORTHREFCLK0;
|
|
input GTNORTHREFCLK1;
|
|
input GTREFCLK0;
|
|
input GTREFCLK1;
|
|
input [15:0] GTRSVD;
|
|
input GTRXRESET;
|
|
input GTRXRESETSEL;
|
|
input GTSOUTHREFCLK0;
|
|
input GTSOUTHREFCLK1;
|
|
input GTTXRESET;
|
|
input GTTXRESETSEL;
|
|
input GTYRXN;
|
|
input GTYRXP;
|
|
input INCPCTRL;
|
|
input [2:0] LOOPBACK;
|
|
input PCIEEQRXEQADAPTDONE;
|
|
input PCIERSTIDLE;
|
|
input PCIERSTTXSYNCSTART;
|
|
input PCIEUSERRATEDONE;
|
|
input [15:0] PCSRSVDIN;
|
|
input QPLL0CLK;
|
|
input QPLL0FREQLOCK;
|
|
input QPLL0REFCLK;
|
|
input QPLL1CLK;
|
|
input QPLL1FREQLOCK;
|
|
input QPLL1REFCLK;
|
|
input RESETOVRD;
|
|
input RX8B10BEN;
|
|
input RXAFECFOKEN;
|
|
input RXBUFRESET;
|
|
input RXCDRFREQRESET;
|
|
input RXCDRHOLD;
|
|
input RXCDROVRDEN;
|
|
input RXCDRRESET;
|
|
input RXCHBONDEN;
|
|
input [4:0] RXCHBONDI;
|
|
input [2:0] RXCHBONDLEVEL;
|
|
input RXCHBONDMASTER;
|
|
input RXCHBONDSLAVE;
|
|
input RXCKCALRESET;
|
|
input [6:0] RXCKCALSTART;
|
|
input RXCOMMADETEN;
|
|
input RXDFEAGCHOLD;
|
|
input RXDFEAGCOVRDEN;
|
|
input [3:0] RXDFECFOKFCNUM;
|
|
input RXDFECFOKFEN;
|
|
input RXDFECFOKFPULSE;
|
|
input RXDFECFOKHOLD;
|
|
input RXDFECFOKOVREN;
|
|
input RXDFEKHHOLD;
|
|
input RXDFEKHOVRDEN;
|
|
input RXDFELFHOLD;
|
|
input RXDFELFOVRDEN;
|
|
input RXDFELPMRESET;
|
|
input RXDFETAP10HOLD;
|
|
input RXDFETAP10OVRDEN;
|
|
input RXDFETAP11HOLD;
|
|
input RXDFETAP11OVRDEN;
|
|
input RXDFETAP12HOLD;
|
|
input RXDFETAP12OVRDEN;
|
|
input RXDFETAP13HOLD;
|
|
input RXDFETAP13OVRDEN;
|
|
input RXDFETAP14HOLD;
|
|
input RXDFETAP14OVRDEN;
|
|
input RXDFETAP15HOLD;
|
|
input RXDFETAP15OVRDEN;
|
|
input RXDFETAP2HOLD;
|
|
input RXDFETAP2OVRDEN;
|
|
input RXDFETAP3HOLD;
|
|
input RXDFETAP3OVRDEN;
|
|
input RXDFETAP4HOLD;
|
|
input RXDFETAP4OVRDEN;
|
|
input RXDFETAP5HOLD;
|
|
input RXDFETAP5OVRDEN;
|
|
input RXDFETAP6HOLD;
|
|
input RXDFETAP6OVRDEN;
|
|
input RXDFETAP7HOLD;
|
|
input RXDFETAP7OVRDEN;
|
|
input RXDFETAP8HOLD;
|
|
input RXDFETAP8OVRDEN;
|
|
input RXDFETAP9HOLD;
|
|
input RXDFETAP9OVRDEN;
|
|
input RXDFEUTHOLD;
|
|
input RXDFEUTOVRDEN;
|
|
input RXDFEVPHOLD;
|
|
input RXDFEVPOVRDEN;
|
|
input RXDFEXYDEN;
|
|
input RXDLYBYPASS;
|
|
input RXDLYEN;
|
|
input RXDLYOVRDEN;
|
|
input RXDLYSRESET;
|
|
input [1:0] RXELECIDLEMODE;
|
|
input RXEQTRAINING;
|
|
input RXGEARBOXSLIP;
|
|
input RXLATCLK;
|
|
input RXLPMEN;
|
|
input RXLPMGCHOLD;
|
|
input RXLPMGCOVRDEN;
|
|
input RXLPMHFHOLD;
|
|
input RXLPMHFOVRDEN;
|
|
input RXLPMLFHOLD;
|
|
input RXLPMLFKLOVRDEN;
|
|
input RXLPMOSHOLD;
|
|
input RXLPMOSOVRDEN;
|
|
input RXMCOMMAALIGNEN;
|
|
input [1:0] RXMONITORSEL;
|
|
input RXOOBRESET;
|
|
input RXOSCALRESET;
|
|
input RXOSHOLD;
|
|
input RXOSOVRDEN;
|
|
input [2:0] RXOUTCLKSEL;
|
|
input RXPCOMMAALIGNEN;
|
|
input RXPCSRESET;
|
|
input [1:0] RXPD;
|
|
input RXPHALIGN;
|
|
input RXPHALIGNEN;
|
|
input RXPHDLYPD;
|
|
input RXPHDLYRESET;
|
|
input [1:0] RXPLLCLKSEL;
|
|
input RXPMARESET;
|
|
input RXPOLARITY;
|
|
input RXPRBSCNTRESET;
|
|
input [3:0] RXPRBSSEL;
|
|
input RXPROGDIVRESET;
|
|
input [2:0] RXRATE;
|
|
input RXRATEMODE;
|
|
input RXSLIDE;
|
|
input RXSLIPOUTCLK;
|
|
input RXSLIPPMA;
|
|
input RXSYNCALLIN;
|
|
input RXSYNCIN;
|
|
input RXSYNCMODE;
|
|
input [1:0] RXSYSCLKSEL;
|
|
input RXTERMINATION;
|
|
input RXUSERRDY;
|
|
input RXUSRCLK;
|
|
input RXUSRCLK2;
|
|
input SIGVALIDCLK;
|
|
input [19:0] TSTIN;
|
|
input [7:0] TX8B10BBYPASS;
|
|
input TX8B10BEN;
|
|
input TXCOMINIT;
|
|
input TXCOMSAS;
|
|
input TXCOMWAKE;
|
|
input [15:0] TXCTRL0;
|
|
input [15:0] TXCTRL1;
|
|
input [7:0] TXCTRL2;
|
|
input [127:0] TXDATA;
|
|
input [7:0] TXDATAEXTENDRSVD;
|
|
input TXDCCFORCESTART;
|
|
input TXDCCRESET;
|
|
input [1:0] TXDEEMPH;
|
|
input TXDETECTRX;
|
|
input [4:0] TXDIFFCTRL;
|
|
input TXDLYBYPASS;
|
|
input TXDLYEN;
|
|
input TXDLYHOLD;
|
|
input TXDLYOVRDEN;
|
|
input TXDLYSRESET;
|
|
input TXDLYUPDOWN;
|
|
input TXELECIDLE;
|
|
input [5:0] TXHEADER;
|
|
input TXINHIBIT;
|
|
input TXLATCLK;
|
|
input TXLFPSTRESET;
|
|
input TXLFPSU2LPEXIT;
|
|
input TXLFPSU3WAKE;
|
|
input [6:0] TXMAINCURSOR;
|
|
input [2:0] TXMARGIN;
|
|
input TXMUXDCDEXHOLD;
|
|
input TXMUXDCDORWREN;
|
|
input TXONESZEROS;
|
|
input [2:0] TXOUTCLKSEL;
|
|
input TXPCSRESET;
|
|
input [1:0] TXPD;
|
|
input TXPDELECIDLEMODE;
|
|
input TXPHALIGN;
|
|
input TXPHALIGNEN;
|
|
input TXPHDLYPD;
|
|
input TXPHDLYRESET;
|
|
input TXPHDLYTSTCLK;
|
|
input TXPHINIT;
|
|
input TXPHOVRDEN;
|
|
input TXPIPPMEN;
|
|
input TXPIPPMOVRDEN;
|
|
input TXPIPPMPD;
|
|
input TXPIPPMSEL;
|
|
input [4:0] TXPIPPMSTEPSIZE;
|
|
input TXPISOPD;
|
|
input [1:0] TXPLLCLKSEL;
|
|
input TXPMARESET;
|
|
input TXPOLARITY;
|
|
input [4:0] TXPOSTCURSOR;
|
|
input TXPRBSFORCEERR;
|
|
input [3:0] TXPRBSSEL;
|
|
input [4:0] TXPRECURSOR;
|
|
input TXPROGDIVRESET;
|
|
input [2:0] TXRATE;
|
|
input TXRATEMODE;
|
|
input [6:0] TXSEQUENCE;
|
|
input TXSWING;
|
|
input TXSYNCALLIN;
|
|
input TXSYNCIN;
|
|
input TXSYNCMODE;
|
|
input [1:0] TXSYSCLKSEL;
|
|
input TXUSERRDY;
|
|
input TXUSRCLK;
|
|
input TXUSRCLK2;
|
|
endmodule
|
|
|
|
module GTYE4_COMMON(DRPDO, DRPRDY, PMARSVDOUT0, PMARSVDOUT1, QPLL0FBCLKLOST, QPLL0LOCK, QPLL0OUTCLK, QPLL0OUTREFCLK, QPLL0REFCLKLOST, QPLL1FBCLKLOST, QPLL1LOCK, QPLL1OUTCLK, QPLL1OUTREFCLK, QPLL1REFCLKLOST, QPLLDMONITOR0, QPLLDMONITOR1, REFCLKOUTMONITOR0, REFCLKOUTMONITOR1, RXRECCLK0SEL, RXRECCLK1SEL, SDM0FINALOUT
|
|
, SDM0TESTDATA, SDM1FINALOUT, SDM1TESTDATA, UBDADDR, UBDEN, UBDI, UBDWE, UBMDMTDO, UBRSVDOUT, UBTXUART, BGBYPASSB, BGMONITORENB, BGPDB, BGRCALOVRD, BGRCALOVRDENB, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, GTGREFCLK0
|
|
, GTGREFCLK1, GTNORTHREFCLK00, GTNORTHREFCLK01, GTNORTHREFCLK10, GTNORTHREFCLK11, GTREFCLK00, GTREFCLK01, GTREFCLK10, GTREFCLK11, GTSOUTHREFCLK00, GTSOUTHREFCLK01, GTSOUTHREFCLK10, GTSOUTHREFCLK11, PCIERATEQPLL0, PCIERATEQPLL1, PMARSVD0, PMARSVD1, QPLL0CLKRSVD0, QPLL0CLKRSVD1, QPLL0FBDIV, QPLL0LOCKDETCLK
|
|
, QPLL0LOCKEN, QPLL0PD, QPLL0REFCLKSEL, QPLL0RESET, QPLL1CLKRSVD0, QPLL1CLKRSVD1, QPLL1FBDIV, QPLL1LOCKDETCLK, QPLL1LOCKEN, QPLL1PD, QPLL1REFCLKSEL, QPLL1RESET, QPLLRSVD1, QPLLRSVD2, QPLLRSVD3, QPLLRSVD4, RCALENB, SDM0DATA, SDM0RESET, SDM0TOGGLE, SDM0WIDTH
|
|
, SDM1DATA, SDM1RESET, SDM1TOGGLE, SDM1WIDTH, UBCFGSTREAMEN, UBDO, UBDRDY, UBENABLE, UBGPI, UBINTR, UBIOLMBRST, UBMBRST, UBMDMCAPTURE, UBMDMDBGRST, UBMDMDBGUPDATE, UBMDMREGEN, UBMDMSHIFT, UBMDMSYSRST, UBMDMTCK, UBMDMTDI);
|
|
parameter [0:0] AEN_QPLL0_FBDIV = 1'b1;
|
|
parameter [0:0] AEN_QPLL1_FBDIV = 1'b1;
|
|
parameter [0:0] AEN_SDM0TOGGLE = 1'b0;
|
|
parameter [0:0] AEN_SDM1TOGGLE = 1'b0;
|
|
parameter [0:0] A_SDM0TOGGLE = 1'b0;
|
|
parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000;
|
|
parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000;
|
|
parameter [0:0] A_SDM1TOGGLE = 1'b0;
|
|
parameter [15:0] BIAS_CFG0 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG1 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG2 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG3 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG4 = 16'h0000;
|
|
parameter [15:0] BIAS_CFG_RSVD = 16'h0000;
|
|
parameter [15:0] COMMON_CFG0 = 16'h0000;
|
|
parameter [15:0] COMMON_CFG1 = 16'h0000;
|
|
parameter [15:0] POR_CFG = 16'h0000;
|
|
parameter [15:0] PPF0_CFG = 16'h0F00;
|
|
parameter [15:0] PPF1_CFG = 16'h0F00;
|
|
parameter QPLL0CLKOUT_RATE = "FULL";
|
|
parameter [15:0] QPLL0_CFG0 = 16'h391C;
|
|
parameter [15:0] QPLL0_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL0_CFG1_G3 = 16'h0020;
|
|
parameter [15:0] QPLL0_CFG2 = 16'h0F80;
|
|
parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80;
|
|
parameter [15:0] QPLL0_CFG3 = 16'h0120;
|
|
parameter [15:0] QPLL0_CFG4 = 16'h0002;
|
|
parameter [9:0] QPLL0_CP = 10'b0000011111;
|
|
parameter [9:0] QPLL0_CP_G3 = 10'b0000011111;
|
|
parameter integer QPLL0_FBDIV = 66;
|
|
parameter integer QPLL0_FBDIV_G3 = 80;
|
|
parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000;
|
|
parameter [7:0] QPLL0_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8;
|
|
parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8;
|
|
parameter [9:0] QPLL0_LPF = 10'b1011111111;
|
|
parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111;
|
|
parameter [0:0] QPLL0_PCI_EN = 1'b0;
|
|
parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0;
|
|
parameter integer QPLL0_REFCLK_DIV = 1;
|
|
parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040;
|
|
parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000;
|
|
parameter QPLL1CLKOUT_RATE = "FULL";
|
|
parameter [15:0] QPLL1_CFG0 = 16'h691C;
|
|
parameter [15:0] QPLL1_CFG1 = 16'h0020;
|
|
parameter [15:0] QPLL1_CFG1_G3 = 16'h0020;
|
|
parameter [15:0] QPLL1_CFG2 = 16'h0F80;
|
|
parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80;
|
|
parameter [15:0] QPLL1_CFG3 = 16'h0120;
|
|
parameter [15:0] QPLL1_CFG4 = 16'h0002;
|
|
parameter [9:0] QPLL1_CP = 10'b0000011111;
|
|
parameter [9:0] QPLL1_CP_G3 = 10'b0000011111;
|
|
parameter integer QPLL1_FBDIV = 66;
|
|
parameter integer QPLL1_FBDIV_G3 = 80;
|
|
parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000;
|
|
parameter [7:0] QPLL1_INIT_CFG1 = 8'h00;
|
|
parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8;
|
|
parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8;
|
|
parameter [9:0] QPLL1_LPF = 10'b1011111111;
|
|
parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111;
|
|
parameter [0:0] QPLL1_PCI_EN = 1'b0;
|
|
parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0;
|
|
parameter integer QPLL1_REFCLK_DIV = 1;
|
|
parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000;
|
|
parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000;
|
|
parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR0 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR1 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR2 = 16'h0000;
|
|
parameter [15:0] RSVD_ATTR3 = 16'h0000;
|
|
parameter [1:0] RXRECCLKOUT0_SEL = 2'b00;
|
|
parameter [1:0] RXRECCLKOUT1_SEL = 2'b00;
|
|
parameter [0:0] SARC_ENB = 1'b0;
|
|
parameter [0:0] SARC_SEL = 1'b0;
|
|
parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM0INITSEED0_1 = 9'b000000000;
|
|
parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000;
|
|
parameter [8:0] SDM1INITSEED0_1 = 9'b000000000;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter SIM_MODE = "FAST";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter [15:0] UB_CFG0 = 16'h0000;
|
|
parameter [15:0] UB_CFG1 = 16'h0000;
|
|
parameter [15:0] UB_CFG2 = 16'h0000;
|
|
parameter [15:0] UB_CFG3 = 16'h0000;
|
|
parameter [15:0] UB_CFG4 = 16'h0000;
|
|
parameter [15:0] UB_CFG5 = 16'h0400;
|
|
parameter [15:0] UB_CFG6 = 16'h0000;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output [7:0] PMARSVDOUT0;
|
|
output [7:0] PMARSVDOUT1;
|
|
output QPLL0FBCLKLOST;
|
|
output QPLL0LOCK;
|
|
output QPLL0OUTCLK;
|
|
output QPLL0OUTREFCLK;
|
|
output QPLL0REFCLKLOST;
|
|
output QPLL1FBCLKLOST;
|
|
output QPLL1LOCK;
|
|
output QPLL1OUTCLK;
|
|
output QPLL1OUTREFCLK;
|
|
output QPLL1REFCLKLOST;
|
|
output [7:0] QPLLDMONITOR0;
|
|
output [7:0] QPLLDMONITOR1;
|
|
output REFCLKOUTMONITOR0;
|
|
output REFCLKOUTMONITOR1;
|
|
output [1:0] RXRECCLK0SEL;
|
|
output [1:0] RXRECCLK1SEL;
|
|
output [3:0] SDM0FINALOUT;
|
|
output [14:0] SDM0TESTDATA;
|
|
output [3:0] SDM1FINALOUT;
|
|
output [14:0] SDM1TESTDATA;
|
|
output [15:0] UBDADDR;
|
|
output UBDEN;
|
|
output [15:0] UBDI;
|
|
output UBDWE;
|
|
output UBMDMTDO;
|
|
output UBRSVDOUT;
|
|
output UBTXUART;
|
|
input BGBYPASSB;
|
|
input BGMONITORENB;
|
|
input BGPDB;
|
|
input [4:0] BGRCALOVRD;
|
|
input BGRCALOVRDENB;
|
|
input [15:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input GTGREFCLK0;
|
|
input GTGREFCLK1;
|
|
input GTNORTHREFCLK00;
|
|
input GTNORTHREFCLK01;
|
|
input GTNORTHREFCLK10;
|
|
input GTNORTHREFCLK11;
|
|
input GTREFCLK00;
|
|
input GTREFCLK01;
|
|
input GTREFCLK10;
|
|
input GTREFCLK11;
|
|
input GTSOUTHREFCLK00;
|
|
input GTSOUTHREFCLK01;
|
|
input GTSOUTHREFCLK10;
|
|
input GTSOUTHREFCLK11;
|
|
input [2:0] PCIERATEQPLL0;
|
|
input [2:0] PCIERATEQPLL1;
|
|
input [7:0] PMARSVD0;
|
|
input [7:0] PMARSVD1;
|
|
input QPLL0CLKRSVD0;
|
|
input QPLL0CLKRSVD1;
|
|
input [7:0] QPLL0FBDIV;
|
|
input QPLL0LOCKDETCLK;
|
|
input QPLL0LOCKEN;
|
|
input QPLL0PD;
|
|
input [2:0] QPLL0REFCLKSEL;
|
|
input QPLL0RESET;
|
|
input QPLL1CLKRSVD0;
|
|
input QPLL1CLKRSVD1;
|
|
input [7:0] QPLL1FBDIV;
|
|
input QPLL1LOCKDETCLK;
|
|
input QPLL1LOCKEN;
|
|
input QPLL1PD;
|
|
input [2:0] QPLL1REFCLKSEL;
|
|
input QPLL1RESET;
|
|
input [7:0] QPLLRSVD1;
|
|
input [4:0] QPLLRSVD2;
|
|
input [4:0] QPLLRSVD3;
|
|
input [7:0] QPLLRSVD4;
|
|
input RCALENB;
|
|
input [24:0] SDM0DATA;
|
|
input SDM0RESET;
|
|
input SDM0TOGGLE;
|
|
input [1:0] SDM0WIDTH;
|
|
input [24:0] SDM1DATA;
|
|
input SDM1RESET;
|
|
input SDM1TOGGLE;
|
|
input [1:0] SDM1WIDTH;
|
|
input UBCFGSTREAMEN;
|
|
input [15:0] UBDO;
|
|
input UBDRDY;
|
|
input UBENABLE;
|
|
input [1:0] UBGPI;
|
|
input [1:0] UBINTR;
|
|
input UBIOLMBRST;
|
|
input UBMBRST;
|
|
input UBMDMCAPTURE;
|
|
input UBMDMDBGRST;
|
|
input UBMDMDBGUPDATE;
|
|
input [3:0] UBMDMREGEN;
|
|
input UBMDMSHIFT;
|
|
input UBMDMSYSRST;
|
|
input UBMDMTCK;
|
|
input UBMDMTDI;
|
|
endmodule
|
|
|
|
module IBUFDS_GTE4(O, ODIV2, CEB, I, IB);
|
|
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
|
|
parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00;
|
|
parameter [1:0] REFCLK_ICNTL_RX = 2'b00;
|
|
output O;
|
|
output ODIV2;
|
|
input CEB;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module OBUFDS_GTE4(O, OB, CEB, I);
|
|
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
|
|
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
output OB;
|
|
input CEB;
|
|
input I;
|
|
endmodule
|
|
|
|
module OBUFDS_GTE4_ADV(O, OB, CEB, I, RXRECCLK_SEL);
|
|
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
|
|
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000;
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
output OB;
|
|
input CEB;
|
|
input [3:0] I;
|
|
input [1:0] RXRECCLK_SEL;
|
|
endmodule
|
|
|
|
module GTM_DUAL(CH0_AXISTDATA, CH0_AXISTLAST, CH0_AXISTVALID, CH0_DMONITOROUT, CH0_DMONITOROUTCLK, CH0_GTMTXN, CH0_GTMTXP, CH0_PCSRSVDOUT, CH0_PMARSVDOUT, CH0_RESETEXCEPTION, CH0_RXBUFSTATUS, CH0_RXDATA, CH0_RXDATAFLAGS, CH0_RXDATAISAM, CH0_RXDATASTART, CH0_RXOUTCLK, CH0_RXPMARESETDONE, CH0_RXPRBSERR, CH0_RXPRBSLOCKED, CH0_RXPRGDIVRESETDONE, CH0_RXPROGDIVCLK
|
|
, CH0_RXRESETDONE, CH0_TXBUFSTATUS, CH0_TXOUTCLK, CH0_TXPMARESETDONE, CH0_TXPRGDIVRESETDONE, CH0_TXPROGDIVCLK, CH0_TXRESETDONE, CH1_AXISTDATA, CH1_AXISTLAST, CH1_AXISTVALID, CH1_DMONITOROUT, CH1_DMONITOROUTCLK, CH1_GTMTXN, CH1_GTMTXP, CH1_PCSRSVDOUT, CH1_PMARSVDOUT, CH1_RESETEXCEPTION, CH1_RXBUFSTATUS, CH1_RXDATA, CH1_RXDATAFLAGS, CH1_RXDATAISAM
|
|
, CH1_RXDATASTART, CH1_RXOUTCLK, CH1_RXPMARESETDONE, CH1_RXPRBSERR, CH1_RXPRBSLOCKED, CH1_RXPRGDIVRESETDONE, CH1_RXPROGDIVCLK, CH1_RXRESETDONE, CH1_TXBUFSTATUS, CH1_TXOUTCLK, CH1_TXPMARESETDONE, CH1_TXPRGDIVRESETDONE, CH1_TXPROGDIVCLK, CH1_TXRESETDONE, CLKTESTSIG2PAD, DMONITOROUTPLLCLK, DRPDO, DRPRDY, FECRX0ALIGNED, FECRX0CORRCWINC, FECRX0CWINC
|
|
, FECRX0UNCORRCWINC, FECRX1ALIGNED, FECRX1CORRCWINC, FECRX1CWINC, FECRX1UNCORRCWINC, FECRXLN0BITERR0TO1INC, FECRXLN0BITERR1TO0INC, FECRXLN0DLY, FECRXLN0ERRCNTINC, FECRXLN0MAPPING, FECRXLN1BITERR0TO1INC, FECRXLN1BITERR1TO0INC, FECRXLN1DLY, FECRXLN1ERRCNTINC, FECRXLN1MAPPING, FECRXLN2BITERR0TO1INC, FECRXLN2BITERR1TO0INC, FECRXLN2DLY, FECRXLN2ERRCNTINC, FECRXLN2MAPPING, FECRXLN3BITERR0TO1INC
|
|
, FECRXLN3BITERR1TO0INC, FECRXLN3DLY, FECRXLN3ERRCNTINC, FECRXLN3MAPPING, FECTRXLN0LOCK, FECTRXLN1LOCK, FECTRXLN2LOCK, FECTRXLN3LOCK, GTPOWERGOOD, PLLFBCLKLOST, PLLLOCK, PLLREFCLKLOST, PLLREFCLKMONITOR, PLLRESETDONE, PLLRSVDOUT, RCALCMP, RCALOUT, RXRECCLK0, RXRECCLK1, BGBYPASSB, BGMONITORENB
|
|
, BGPDB, BGRCALOVRD, BGRCALOVRDENB, CH0_AXISEN, CH0_AXISRST, CH0_AXISTRDY, CH0_CFGRESET, CH0_DMONFIFORESET, CH0_DMONITORCLK, CH0_GTMRXN, CH0_GTMRXP, CH0_GTRXRESET, CH0_GTTXRESET, CH0_LOOPBACK, CH0_PCSRSVDIN, CH0_PMARSVDIN, CH0_RESETOVRD, CH0_RXADAPTRESET, CH0_RXADCCALRESET, CH0_RXADCCLKGENRESET, CH0_RXBUFRESET
|
|
, CH0_RXCDRFREQOS, CH0_RXCDRFRRESET, CH0_RXCDRHOLD, CH0_RXCDRINCPCTRL, CH0_RXCDROVRDEN, CH0_RXCDRPHRESET, CH0_RXDFERESET, CH0_RXDSPRESET, CH0_RXEQTRAINING, CH0_RXEYESCANRESET, CH0_RXFECRESET, CH0_RXOUTCLKSEL, CH0_RXPCSRESET, CH0_RXPCSRESETMASK, CH0_RXPMARESET, CH0_RXPMARESETMASK, CH0_RXPOLARITY, CH0_RXPRBSCNTSTOP, CH0_RXPRBSCSCNTRST, CH0_RXPRBSPTN, CH0_RXPROGDIVRESET
|
|
, CH0_RXQPRBSEN, CH0_RXRESETMODE, CH0_RXSPCSEQADV, CH0_RXUSRCLK, CH0_RXUSRCLK2, CH0_RXUSRRDY, CH0_RXUSRSTART, CH0_RXUSRSTOP, CH0_TXCKALRESET, CH0_TXCTLFIRDAT, CH0_TXDATA, CH0_TXDATASTART, CH0_TXDRVAMP, CH0_TXEMPMAIN, CH0_TXEMPPOST, CH0_TXEMPPRE, CH0_TXEMPPRE2, CH0_TXFECRESET, CH0_TXINHIBIT, CH0_TXMUXDCDEXHOLD, CH0_TXMUXDCDORWREN
|
|
, CH0_TXOUTCLKSEL, CH0_TXPCSRESET, CH0_TXPCSRESETMASK, CH0_TXPMARESET, CH0_TXPMARESETMASK, CH0_TXPOLARITY, CH0_TXPRBSINERR, CH0_TXPRBSPTN, CH0_TXPROGDIVRESET, CH0_TXQPRBSEN, CH0_TXRESETMODE, CH0_TXSPCSEQADV, CH0_TXUSRCLK, CH0_TXUSRCLK2, CH0_TXUSRRDY, CH1_AXISEN, CH1_AXISRST, CH1_AXISTRDY, CH1_CFGRESET, CH1_DMONFIFORESET, CH1_DMONITORCLK
|
|
, CH1_GTMRXN, CH1_GTMRXP, CH1_GTRXRESET, CH1_GTTXRESET, CH1_LOOPBACK, CH1_PCSRSVDIN, CH1_PMARSVDIN, CH1_RESETOVRD, CH1_RXADAPTRESET, CH1_RXADCCALRESET, CH1_RXADCCLKGENRESET, CH1_RXBUFRESET, CH1_RXCDRFREQOS, CH1_RXCDRFRRESET, CH1_RXCDRHOLD, CH1_RXCDRINCPCTRL, CH1_RXCDROVRDEN, CH1_RXCDRPHRESET, CH1_RXDFERESET, CH1_RXDSPRESET, CH1_RXEQTRAINING
|
|
, CH1_RXEYESCANRESET, CH1_RXFECRESET, CH1_RXOUTCLKSEL, CH1_RXPCSRESET, CH1_RXPCSRESETMASK, CH1_RXPMARESET, CH1_RXPMARESETMASK, CH1_RXPOLARITY, CH1_RXPRBSCNTSTOP, CH1_RXPRBSCSCNTRST, CH1_RXPRBSPTN, CH1_RXPROGDIVRESET, CH1_RXQPRBSEN, CH1_RXRESETMODE, CH1_RXSPCSEQADV, CH1_RXUSRCLK, CH1_RXUSRCLK2, CH1_RXUSRRDY, CH1_RXUSRSTART, CH1_RXUSRSTOP, CH1_TXCKALRESET
|
|
, CH1_TXCTLFIRDAT, CH1_TXDATA, CH1_TXDATASTART, CH1_TXDRVAMP, CH1_TXEMPMAIN, CH1_TXEMPPOST, CH1_TXEMPPRE, CH1_TXEMPPRE2, CH1_TXFECRESET, CH1_TXINHIBIT, CH1_TXMUXDCDEXHOLD, CH1_TXMUXDCDORWREN, CH1_TXOUTCLKSEL, CH1_TXPCSRESET, CH1_TXPCSRESETMASK, CH1_TXPMARESET, CH1_TXPMARESETMASK, CH1_TXPOLARITY, CH1_TXPRBSINERR, CH1_TXPRBSPTN, CH1_TXPROGDIVRESET
|
|
, CH1_TXQPRBSEN, CH1_TXRESETMODE, CH1_TXSPCSEQADV, CH1_TXUSRCLK, CH1_TXUSRCLK2, CH1_TXUSRRDY, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPRST, DRPWE, FECCTRLRX0BITSLIPFS, FECCTRLRX1BITSLIPFS, GTGREFCLK2PLL, GTNORTHREFCLK, GTREFCLK, GTSOUTHREFCLK, PLLFBDIV, PLLMONCLK, PLLPD
|
|
, PLLREFCLKSEL, PLLRESET, PLLRESETBYPASSMODE, PLLRESETMASK, PLLRSVDIN, RCALENB, SDMDATA, SDMTOGGLE);
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parameter [15:0] A_CFG = 16'b0000100001000000;
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parameter [15:0] A_SDM_DATA_CFG0 = 16'b0000000011010000;
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parameter [15:0] A_SDM_DATA_CFG1 = 16'b0000000011010000;
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|
parameter [15:0] BIAS_CFG0 = 16'b0000000000000000;
|
|
parameter [15:0] BIAS_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] BIAS_CFG2 = 16'b0001000000000000;
|
|
parameter [15:0] BIAS_CFG3 = 16'b0000000000000001;
|
|
parameter [15:0] BIAS_CFG4 = 16'b0000000000000000;
|
|
parameter [15:0] BIAS_CFG5 = 16'b0000000000000000;
|
|
parameter [15:0] BIAS_CFG6 = 16'b0000000010000000;
|
|
parameter [15:0] BIAS_CFG7 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_A_CH_CFG0 = 16'b0000000000000011;
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|
parameter [15:0] CH0_A_CH_CFG1 = 16'b0000000000000000;
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|
parameter [15:0] CH0_A_CH_CFG2 = 16'b0111101111110000;
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parameter [15:0] CH0_A_CH_CFG3 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_A_CH_CFG4 = 16'b0000000000000000;
|
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parameter [15:0] CH0_A_CH_CFG5 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_A_CH_CFG6 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RST_LP_CFG0 = 16'b0001000000010000;
|
|
parameter [15:0] CH0_RST_LP_CFG1 = 16'b0011001000010000;
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parameter [15:0] CH0_RST_LP_CFG2 = 16'b0110010100000100;
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parameter [15:0] CH0_RST_LP_CFG3 = 16'b0011001000010000;
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|
parameter [15:0] CH0_RST_LP_CFG4 = 16'b0000000001000100;
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parameter [15:0] CH0_RST_LP_ID_CFG0 = 16'b0011000001110000;
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parameter [15:0] CH0_RST_LP_ID_CFG1 = 16'b0001000000010000;
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parameter [15:0] CH0_RST_TIME_CFG0 = 16'b0000010000100001;
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parameter [15:0] CH0_RST_TIME_CFG1 = 16'b0000010000100001;
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parameter [15:0] CH0_RST_TIME_CFG2 = 16'b0000010000100001;
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|
parameter [15:0] CH0_RST_TIME_CFG3 = 16'b0000010000100000;
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|
parameter [15:0] CH0_RST_TIME_CFG4 = 16'b0000010000100001;
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|
parameter [15:0] CH0_RST_TIME_CFG5 = 16'b0000000000000001;
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parameter [15:0] CH0_RST_TIME_CFG6 = 16'b0000000000100001;
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|
parameter [15:0] CH0_RX_ADC_CFG0 = 16'b0011010010001111;
|
|
parameter [15:0] CH0_RX_ADC_CFG1 = 16'b0011111001010101;
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|
parameter [15:0] CH0_RX_ANA_CFG0 = 16'b1000000000011101;
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|
parameter [15:0] CH0_RX_ANA_CFG1 = 16'b1110100010000000;
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|
parameter [15:0] CH0_RX_ANA_CFG2 = 16'b0000000010001010;
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|
parameter [15:0] CH0_RX_APT_CFG0A = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG0B = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG10A = 16'b0000000001110000;
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|
parameter [15:0] CH0_RX_APT_CFG10B = 16'b0000000001010000;
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|
parameter [15:0] CH0_RX_APT_CFG11A = 16'b0000000001000000;
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|
parameter [15:0] CH0_RX_APT_CFG11B = 16'b0000000001110000;
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|
parameter [15:0] CH0_RX_APT_CFG12A = 16'b0000000001010000;
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|
parameter [15:0] CH0_RX_APT_CFG12B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG13A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG13B = 16'b0000000000000000;
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|
parameter [15:0] CH0_RX_APT_CFG14A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG14B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG15A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG15B = 16'b0000100000000000;
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|
parameter [15:0] CH0_RX_APT_CFG16A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG16B = 16'b0010000000000000;
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|
parameter [15:0] CH0_RX_APT_CFG17A = 16'b0000000000000000;
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|
parameter [15:0] CH0_RX_APT_CFG17B = 16'b0001000001000000;
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|
parameter [15:0] CH0_RX_APT_CFG18A = 16'b0000100000100000;
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|
parameter [15:0] CH0_RX_APT_CFG18B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG19A = 16'b0000000000000000;
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|
parameter [15:0] CH0_RX_APT_CFG19B = 16'b0000100000000000;
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|
parameter [15:0] CH0_RX_APT_CFG1A = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG1B = 16'b0000000001110000;
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|
parameter [15:0] CH0_RX_APT_CFG20A = 16'b1110000000100000;
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|
parameter [15:0] CH0_RX_APT_CFG20B = 16'b0000000001000000;
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|
parameter [15:0] CH0_RX_APT_CFG21A = 16'b0001000000000100;
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|
parameter [15:0] CH0_RX_APT_CFG21B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG22A = 16'b0000000001110000;
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|
parameter [15:0] CH0_RX_APT_CFG22B = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG23A = 16'b0000100000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG23B = 16'b0000000000000000;
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|
parameter [15:0] CH0_RX_APT_CFG24A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG24B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG25A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG25B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG26A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG26B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG27A = 16'b0100000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG27B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG28A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG28B = 16'b1000000000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG2A = 16'b0000000001110000;
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|
parameter [15:0] CH0_RX_APT_CFG2B = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG3A = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG3B = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG4A = 16'b0000000001110000;
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|
parameter [15:0] CH0_RX_APT_CFG4B = 16'b0000000001110000;
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|
parameter [15:0] CH0_RX_APT_CFG5A = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG5B = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG6A = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG6B = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG7A = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG7B = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG8A = 16'b0000100000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG8B = 16'b0000100000000000;
|
|
parameter [15:0] CH0_RX_APT_CFG9A = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CFG9B = 16'b0000000001110000;
|
|
parameter [15:0] CH0_RX_APT_CTRL_CFG2 = 16'b0000000000000100;
|
|
parameter [15:0] CH0_RX_APT_CTRL_CFG3 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_CAL_CFG0A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_CAL_CFG0B = 16'b0011001100110000;
|
|
parameter [15:0] CH0_RX_CAL_CFG1A = 16'b1110111011100001;
|
|
parameter [15:0] CH0_RX_CAL_CFG1B = 16'b1111111100000100;
|
|
parameter [15:0] CH0_RX_CAL_CFG2A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_CAL_CFG2B = 16'b0011000000000000;
|
|
parameter [15:0] CH0_RX_CDR_CFG0A = 16'b0000000000000011;
|
|
parameter [15:0] CH0_RX_CDR_CFG0B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_CDR_CFG1A = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_CDR_CFG1B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_CDR_CFG2A = 16'b1001000101100100;
|
|
parameter [15:0] CH0_RX_CDR_CFG2B = 16'b0000000100100100;
|
|
parameter [15:0] CH0_RX_CDR_CFG3A = 16'b0101110011110110;
|
|
parameter [15:0] CH0_RX_CDR_CFG3B = 16'b0000000000001011;
|
|
parameter [15:0] CH0_RX_CDR_CFG4A = 16'b0000000000000110;
|
|
parameter [15:0] CH0_RX_CDR_CFG4B = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_CLKGN_CFG0 = 16'b1100000000000000;
|
|
parameter [15:0] CH0_RX_CLKGN_CFG1 = 16'b0000000110000000;
|
|
parameter [15:0] CH0_RX_CTLE_CFG0 = 16'b0011010010001000;
|
|
parameter [15:0] CH0_RX_CTLE_CFG1 = 16'b0010000000100010;
|
|
parameter [15:0] CH0_RX_CTLE_CFG2 = 16'b0000101000000000;
|
|
parameter [15:0] CH0_RX_CTLE_CFG3 = 16'b1111001001000000;
|
|
parameter [15:0] CH0_RX_DSP_CFG = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_MON_CFG = 16'b0000000000000000;
|
|
parameter [15:0] CH0_RX_PAD_CFG0 = 16'b0001111000000000;
|
|
parameter [15:0] CH0_RX_PAD_CFG1 = 16'b0001100000001010;
|
|
parameter [15:0] CH0_RX_PCS_CFG0 = 16'b0000000100000000;
|
|
parameter [15:0] CH0_RX_PCS_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_ANA_CFG0 = 16'b0000001010101111;
|
|
parameter [15:0] CH0_TX_ANA_CFG1 = 16'b0000000100000000;
|
|
parameter [15:0] CH0_TX_ANA_CFG2 = 16'b1000000000010100;
|
|
parameter [15:0] CH0_TX_ANA_CFG3 = 16'b0000101000100010;
|
|
parameter [15:0] CH0_TX_ANA_CFG4 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_CAL_CFG0 = 16'b0000000000100000;
|
|
parameter [15:0] CH0_TX_CAL_CFG1 = 16'b0000000001000000;
|
|
parameter [15:0] CH0_TX_DRV_CFG0 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_DRV_CFG1 = 16'b0000000000100111;
|
|
parameter [15:0] CH0_TX_DRV_CFG2 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_DRV_CFG3 = 16'b0110110000000000;
|
|
parameter [15:0] CH0_TX_DRV_CFG4 = 16'b0000000011000101;
|
|
parameter [15:0] CH0_TX_DRV_CFG5 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_LPBK_CFG0 = 16'b0000000000000011;
|
|
parameter [15:0] CH0_TX_LPBK_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG0 = 16'b0000000101100000;
|
|
parameter [15:0] CH0_TX_PCS_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG10 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG11 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG12 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG13 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG14 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG15 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG16 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG17 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG2 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG3 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG4 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG5 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG6 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG7 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG8 = 16'b0000000000000000;
|
|
parameter [15:0] CH0_TX_PCS_CFG9 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_A_CH_CFG0 = 16'b0000000000000011;
|
|
parameter [15:0] CH1_A_CH_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_A_CH_CFG2 = 16'b0111101111110000;
|
|
parameter [15:0] CH1_A_CH_CFG3 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_A_CH_CFG4 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_A_CH_CFG5 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_A_CH_CFG6 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RST_LP_CFG0 = 16'b0001000000010000;
|
|
parameter [15:0] CH1_RST_LP_CFG1 = 16'b0011001000010000;
|
|
parameter [15:0] CH1_RST_LP_CFG2 = 16'b0110010100000100;
|
|
parameter [15:0] CH1_RST_LP_CFG3 = 16'b0011001000010000;
|
|
parameter [15:0] CH1_RST_LP_CFG4 = 16'b0000000001000100;
|
|
parameter [15:0] CH1_RST_LP_ID_CFG0 = 16'b0011000001110000;
|
|
parameter [15:0] CH1_RST_LP_ID_CFG1 = 16'b0001000000010000;
|
|
parameter [15:0] CH1_RST_TIME_CFG0 = 16'b0000010000100001;
|
|
parameter [15:0] CH1_RST_TIME_CFG1 = 16'b0000010000100001;
|
|
parameter [15:0] CH1_RST_TIME_CFG2 = 16'b0000010000100001;
|
|
parameter [15:0] CH1_RST_TIME_CFG3 = 16'b0000010000100000;
|
|
parameter [15:0] CH1_RST_TIME_CFG4 = 16'b0000010000100001;
|
|
parameter [15:0] CH1_RST_TIME_CFG5 = 16'b0000000000000001;
|
|
parameter [15:0] CH1_RST_TIME_CFG6 = 16'b0000000000100001;
|
|
parameter [15:0] CH1_RX_ADC_CFG0 = 16'b0011010010001111;
|
|
parameter [15:0] CH1_RX_ADC_CFG1 = 16'b0011111001010101;
|
|
parameter [15:0] CH1_RX_ANA_CFG0 = 16'b1000000000011101;
|
|
parameter [15:0] CH1_RX_ANA_CFG1 = 16'b1110100010000000;
|
|
parameter [15:0] CH1_RX_ANA_CFG2 = 16'b0000000010001010;
|
|
parameter [15:0] CH1_RX_APT_CFG0A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG0B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG10A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG10B = 16'b0000000001010000;
|
|
parameter [15:0] CH1_RX_APT_CFG11A = 16'b0000000001000000;
|
|
parameter [15:0] CH1_RX_APT_CFG11B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG12A = 16'b0000000001010000;
|
|
parameter [15:0] CH1_RX_APT_CFG12B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG13A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG13B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG14A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG14B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG15A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG15B = 16'b0000100000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG16A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG16B = 16'b0010000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG17A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG17B = 16'b0001000001000000;
|
|
parameter [15:0] CH1_RX_APT_CFG18A = 16'b0000100000100000;
|
|
parameter [15:0] CH1_RX_APT_CFG18B = 16'b0000100010000000;
|
|
parameter [15:0] CH1_RX_APT_CFG19A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG19B = 16'b0000100000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG1A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG1B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG20A = 16'b1110000000100000;
|
|
parameter [15:0] CH1_RX_APT_CFG20B = 16'b0000000001000000;
|
|
parameter [15:0] CH1_RX_APT_CFG21A = 16'b0001000000000100;
|
|
parameter [15:0] CH1_RX_APT_CFG21B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG22A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG22B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG23A = 16'b0000100000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG23B = 16'b0000100000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG24A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG24B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG25A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG25B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG26A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG26B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG27A = 16'b0100000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG27B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG28A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG28B = 16'b1000000000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG2A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG2B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG3A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG3B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG4A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG4B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG5A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG5B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG6A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG6B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG7A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG7B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG8A = 16'b0000100000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG8B = 16'b0000100000000000;
|
|
parameter [15:0] CH1_RX_APT_CFG9A = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CFG9B = 16'b0000000001110000;
|
|
parameter [15:0] CH1_RX_APT_CTRL_CFG2 = 16'b0000000000000100;
|
|
parameter [15:0] CH1_RX_APT_CTRL_CFG3 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_CAL_CFG0A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_CAL_CFG0B = 16'b0011001100110000;
|
|
parameter [15:0] CH1_RX_CAL_CFG1A = 16'b1110111011100001;
|
|
parameter [15:0] CH1_RX_CAL_CFG1B = 16'b1111111100000100;
|
|
parameter [15:0] CH1_RX_CAL_CFG2A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_CAL_CFG2B = 16'b0011000000000000;
|
|
parameter [15:0] CH1_RX_CDR_CFG0A = 16'b0000000000000011;
|
|
parameter [15:0] CH1_RX_CDR_CFG0B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_CDR_CFG1A = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_CDR_CFG1B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_CDR_CFG2A = 16'b1001000101100100;
|
|
parameter [15:0] CH1_RX_CDR_CFG2B = 16'b0000000100100100;
|
|
parameter [15:0] CH1_RX_CDR_CFG3A = 16'b0101110011110110;
|
|
parameter [15:0] CH1_RX_CDR_CFG3B = 16'b0000000000001011;
|
|
parameter [15:0] CH1_RX_CDR_CFG4A = 16'b0000000000000110;
|
|
parameter [15:0] CH1_RX_CDR_CFG4B = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_CLKGN_CFG0 = 16'b1100000000000000;
|
|
parameter [15:0] CH1_RX_CLKGN_CFG1 = 16'b0000000110000000;
|
|
parameter [15:0] CH1_RX_CTLE_CFG0 = 16'b0011010010001000;
|
|
parameter [15:0] CH1_RX_CTLE_CFG1 = 16'b0010000000100010;
|
|
parameter [15:0] CH1_RX_CTLE_CFG2 = 16'b0000101000000000;
|
|
parameter [15:0] CH1_RX_CTLE_CFG3 = 16'b1111001001000000;
|
|
parameter [15:0] CH1_RX_DSP_CFG = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_MON_CFG = 16'b0000000000000000;
|
|
parameter [15:0] CH1_RX_PAD_CFG0 = 16'b0001111000000000;
|
|
parameter [15:0] CH1_RX_PAD_CFG1 = 16'b0001100000001010;
|
|
parameter [15:0] CH1_RX_PCS_CFG0 = 16'b0000000100000000;
|
|
parameter [15:0] CH1_RX_PCS_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_ANA_CFG0 = 16'b0000001010101111;
|
|
parameter [15:0] CH1_TX_ANA_CFG1 = 16'b0000000100000000;
|
|
parameter [15:0] CH1_TX_ANA_CFG2 = 16'b1000000000010100;
|
|
parameter [15:0] CH1_TX_ANA_CFG3 = 16'b0000101000100010;
|
|
parameter [15:0] CH1_TX_ANA_CFG4 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_CAL_CFG0 = 16'b0000000000100000;
|
|
parameter [15:0] CH1_TX_CAL_CFG1 = 16'b0000000001000000;
|
|
parameter [15:0] CH1_TX_DRV_CFG0 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_DRV_CFG1 = 16'b0000000000100111;
|
|
parameter [15:0] CH1_TX_DRV_CFG2 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_DRV_CFG3 = 16'b0110110000000000;
|
|
parameter [15:0] CH1_TX_DRV_CFG4 = 16'b0000000011000101;
|
|
parameter [15:0] CH1_TX_DRV_CFG5 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_LPBK_CFG0 = 16'b0000000000000011;
|
|
parameter [15:0] CH1_TX_LPBK_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG0 = 16'b0000000101100000;
|
|
parameter [15:0] CH1_TX_PCS_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG10 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG11 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG12 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG13 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG14 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG15 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG16 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG17 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG2 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG3 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG4 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG5 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG6 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG7 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG8 = 16'b0000000000000000;
|
|
parameter [15:0] CH1_TX_PCS_CFG9 = 16'b0000000000000000;
|
|
parameter real DATARATE = 10.000;
|
|
parameter [15:0] DRPEN_CFG = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG0 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG10 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG11 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG12 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG13 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG14 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG15 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG16 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG17 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG18 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG19 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG2 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG20 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG21 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG22 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG23 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG24 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG25 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG26 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG27 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG3 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG4 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG5 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG6 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG7 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG8 = 16'b0000000000000000;
|
|
parameter [15:0] FEC_CFG9 = 16'b0000000000000000;
|
|
parameter FEC_MODE = "BYPASS";
|
|
parameter real INS_LOSS_NYQ = 20.000;
|
|
parameter integer INTERFACE_WIDTH = 64;
|
|
parameter MODULATION_MODE = "NRZ";
|
|
parameter [15:0] PLL_CFG0 = 16'b0001100111110000;
|
|
parameter [15:0] PLL_CFG1 = 16'b0000111101110000;
|
|
parameter [15:0] PLL_CFG2 = 16'b1000000111101000;
|
|
parameter [15:0] PLL_CFG3 = 16'b0100000000000000;
|
|
parameter [15:0] PLL_CFG4 = 16'b0111111111101010;
|
|
parameter [15:0] PLL_CFG5 = 16'b0100101100111000;
|
|
parameter [15:0] PLL_CFG6 = 16'b0000000000100101;
|
|
parameter [15:0] PLL_CRS_CTRL_CFG0 = 16'b0000101100100000;
|
|
parameter [15:0] PLL_CRS_CTRL_CFG1 = 16'b1100010111010100;
|
|
parameter [0:0] PLL_IPS_PIN_EN = 1'b1;
|
|
parameter integer PLL_IPS_REFCLK_SEL = 0;
|
|
parameter [0:0] RCALSAP_TESTEN = 1'b0;
|
|
parameter [0:0] RCAL_APROBE = 1'b0;
|
|
parameter [15:0] RST_CFG = 16'b0000000000000010;
|
|
parameter [15:0] RST_PLL_CFG0 = 16'b0111011000010100;
|
|
parameter [15:0] SAP_CFG0 = 16'b0000000000000000;
|
|
parameter [15:0] SDM_CFG0 = 16'b0001100001000000;
|
|
parameter [15:0] SDM_CFG1 = 16'b0000000000000000;
|
|
parameter [15:0] SDM_CFG2 = 16'b0000000000000000;
|
|
parameter [15:0] SDM_SEED_CFG0 = 16'b0000000000000000;
|
|
parameter [15:0] SDM_SEED_CFG1 = 16'b0000000000000000;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS_ES1";
|
|
parameter SIM_RESET_SPEEDUP = "TRUE";
|
|
parameter integer TX_AMPLITUDE_SWING = 250;
|
|
output [27:0] CH0_AXISTDATA;
|
|
output CH0_AXISTLAST;
|
|
output CH0_AXISTVALID;
|
|
output [31:0] CH0_DMONITOROUT;
|
|
output CH0_DMONITOROUTCLK;
|
|
output CH0_GTMTXN;
|
|
output CH0_GTMTXP;
|
|
output [15:0] CH0_PCSRSVDOUT;
|
|
output [15:0] CH0_PMARSVDOUT;
|
|
output CH0_RESETEXCEPTION;
|
|
output [2:0] CH0_RXBUFSTATUS;
|
|
output [255:0] CH0_RXDATA;
|
|
output [3:0] CH0_RXDATAFLAGS;
|
|
output CH0_RXDATAISAM;
|
|
output CH0_RXDATASTART;
|
|
output CH0_RXOUTCLK;
|
|
output CH0_RXPMARESETDONE;
|
|
output CH0_RXPRBSERR;
|
|
output CH0_RXPRBSLOCKED;
|
|
output CH0_RXPRGDIVRESETDONE;
|
|
output CH0_RXPROGDIVCLK;
|
|
output CH0_RXRESETDONE;
|
|
output [1:0] CH0_TXBUFSTATUS;
|
|
output CH0_TXOUTCLK;
|
|
output CH0_TXPMARESETDONE;
|
|
output CH0_TXPRGDIVRESETDONE;
|
|
output CH0_TXPROGDIVCLK;
|
|
output CH0_TXRESETDONE;
|
|
output [27:0] CH1_AXISTDATA;
|
|
output CH1_AXISTLAST;
|
|
output CH1_AXISTVALID;
|
|
output [31:0] CH1_DMONITOROUT;
|
|
output CH1_DMONITOROUTCLK;
|
|
output CH1_GTMTXN;
|
|
output CH1_GTMTXP;
|
|
output [15:0] CH1_PCSRSVDOUT;
|
|
output [15:0] CH1_PMARSVDOUT;
|
|
output CH1_RESETEXCEPTION;
|
|
output [2:0] CH1_RXBUFSTATUS;
|
|
output [255:0] CH1_RXDATA;
|
|
output [3:0] CH1_RXDATAFLAGS;
|
|
output CH1_RXDATAISAM;
|
|
output CH1_RXDATASTART;
|
|
output CH1_RXOUTCLK;
|
|
output CH1_RXPMARESETDONE;
|
|
output CH1_RXPRBSERR;
|
|
output CH1_RXPRBSLOCKED;
|
|
output CH1_RXPRGDIVRESETDONE;
|
|
output CH1_RXPROGDIVCLK;
|
|
output CH1_RXRESETDONE;
|
|
output [1:0] CH1_TXBUFSTATUS;
|
|
output CH1_TXOUTCLK;
|
|
output CH1_TXPMARESETDONE;
|
|
output CH1_TXPRGDIVRESETDONE;
|
|
output CH1_TXPROGDIVCLK;
|
|
output CH1_TXRESETDONE;
|
|
output CLKTESTSIG2PAD;
|
|
output DMONITOROUTPLLCLK;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output FECRX0ALIGNED;
|
|
output FECRX0CORRCWINC;
|
|
output FECRX0CWINC;
|
|
output FECRX0UNCORRCWINC;
|
|
output FECRX1ALIGNED;
|
|
output FECRX1CORRCWINC;
|
|
output FECRX1CWINC;
|
|
output FECRX1UNCORRCWINC;
|
|
output [7:0] FECRXLN0BITERR0TO1INC;
|
|
output [7:0] FECRXLN0BITERR1TO0INC;
|
|
output [14:0] FECRXLN0DLY;
|
|
output [3:0] FECRXLN0ERRCNTINC;
|
|
output [1:0] FECRXLN0MAPPING;
|
|
output [7:0] FECRXLN1BITERR0TO1INC;
|
|
output [7:0] FECRXLN1BITERR1TO0INC;
|
|
output [14:0] FECRXLN1DLY;
|
|
output [3:0] FECRXLN1ERRCNTINC;
|
|
output [1:0] FECRXLN1MAPPING;
|
|
output [7:0] FECRXLN2BITERR0TO1INC;
|
|
output [7:0] FECRXLN2BITERR1TO0INC;
|
|
output [14:0] FECRXLN2DLY;
|
|
output [3:0] FECRXLN2ERRCNTINC;
|
|
output [1:0] FECRXLN2MAPPING;
|
|
output [7:0] FECRXLN3BITERR0TO1INC;
|
|
output [7:0] FECRXLN3BITERR1TO0INC;
|
|
output [14:0] FECRXLN3DLY;
|
|
output [3:0] FECRXLN3ERRCNTINC;
|
|
output [1:0] FECRXLN3MAPPING;
|
|
output FECTRXLN0LOCK;
|
|
output FECTRXLN1LOCK;
|
|
output FECTRXLN2LOCK;
|
|
output FECTRXLN3LOCK;
|
|
output GTPOWERGOOD;
|
|
output PLLFBCLKLOST;
|
|
output PLLLOCK;
|
|
output PLLREFCLKLOST;
|
|
output PLLREFCLKMONITOR;
|
|
output PLLRESETDONE;
|
|
output [15:0] PLLRSVDOUT;
|
|
output RCALCMP;
|
|
output [4:0] RCALOUT;
|
|
output RXRECCLK0;
|
|
output RXRECCLK1;
|
|
input BGBYPASSB;
|
|
input BGMONITORENB;
|
|
input BGPDB;
|
|
input [4:0] BGRCALOVRD;
|
|
input BGRCALOVRDENB;
|
|
input CH0_AXISEN;
|
|
input CH0_AXISRST;
|
|
input CH0_AXISTRDY;
|
|
input CH0_CFGRESET;
|
|
input CH0_DMONFIFORESET;
|
|
input CH0_DMONITORCLK;
|
|
input CH0_GTMRXN;
|
|
input CH0_GTMRXP;
|
|
input CH0_GTRXRESET;
|
|
input CH0_GTTXRESET;
|
|
input [2:0] CH0_LOOPBACK;
|
|
input [15:0] CH0_PCSRSVDIN;
|
|
input [15:0] CH0_PMARSVDIN;
|
|
input CH0_RESETOVRD;
|
|
input CH0_RXADAPTRESET;
|
|
input CH0_RXADCCALRESET;
|
|
input CH0_RXADCCLKGENRESET;
|
|
input CH0_RXBUFRESET;
|
|
input CH0_RXCDRFREQOS;
|
|
input CH0_RXCDRFRRESET;
|
|
input CH0_RXCDRHOLD;
|
|
input CH0_RXCDRINCPCTRL;
|
|
input CH0_RXCDROVRDEN;
|
|
input CH0_RXCDRPHRESET;
|
|
input CH0_RXDFERESET;
|
|
input CH0_RXDSPRESET;
|
|
input CH0_RXEQTRAINING;
|
|
input CH0_RXEYESCANRESET;
|
|
input CH0_RXFECRESET;
|
|
input [2:0] CH0_RXOUTCLKSEL;
|
|
input CH0_RXPCSRESET;
|
|
input [3:0] CH0_RXPCSRESETMASK;
|
|
input CH0_RXPMARESET;
|
|
input [7:0] CH0_RXPMARESETMASK;
|
|
input CH0_RXPOLARITY;
|
|
input CH0_RXPRBSCNTSTOP;
|
|
input CH0_RXPRBSCSCNTRST;
|
|
input [3:0] CH0_RXPRBSPTN;
|
|
input CH0_RXPROGDIVRESET;
|
|
input CH0_RXQPRBSEN;
|
|
input [1:0] CH0_RXRESETMODE;
|
|
input CH0_RXSPCSEQADV;
|
|
input CH0_RXUSRCLK;
|
|
input CH0_RXUSRCLK2;
|
|
input CH0_RXUSRRDY;
|
|
input CH0_RXUSRSTART;
|
|
input CH0_RXUSRSTOP;
|
|
input CH0_TXCKALRESET;
|
|
input [5:0] CH0_TXCTLFIRDAT;
|
|
input [255:0] CH0_TXDATA;
|
|
input CH0_TXDATASTART;
|
|
input [4:0] CH0_TXDRVAMP;
|
|
input [5:0] CH0_TXEMPMAIN;
|
|
input [4:0] CH0_TXEMPPOST;
|
|
input [4:0] CH0_TXEMPPRE;
|
|
input [3:0] CH0_TXEMPPRE2;
|
|
input CH0_TXFECRESET;
|
|
input CH0_TXINHIBIT;
|
|
input CH0_TXMUXDCDEXHOLD;
|
|
input CH0_TXMUXDCDORWREN;
|
|
input [2:0] CH0_TXOUTCLKSEL;
|
|
input CH0_TXPCSRESET;
|
|
input [1:0] CH0_TXPCSRESETMASK;
|
|
input CH0_TXPMARESET;
|
|
input [1:0] CH0_TXPMARESETMASK;
|
|
input CH0_TXPOLARITY;
|
|
input CH0_TXPRBSINERR;
|
|
input [3:0] CH0_TXPRBSPTN;
|
|
input CH0_TXPROGDIVRESET;
|
|
input CH0_TXQPRBSEN;
|
|
input [1:0] CH0_TXRESETMODE;
|
|
input CH0_TXSPCSEQADV;
|
|
input CH0_TXUSRCLK;
|
|
input CH0_TXUSRCLK2;
|
|
input CH0_TXUSRRDY;
|
|
input CH1_AXISEN;
|
|
input CH1_AXISRST;
|
|
input CH1_AXISTRDY;
|
|
input CH1_CFGRESET;
|
|
input CH1_DMONFIFORESET;
|
|
input CH1_DMONITORCLK;
|
|
input CH1_GTMRXN;
|
|
input CH1_GTMRXP;
|
|
input CH1_GTRXRESET;
|
|
input CH1_GTTXRESET;
|
|
input [2:0] CH1_LOOPBACK;
|
|
input [15:0] CH1_PCSRSVDIN;
|
|
input [15:0] CH1_PMARSVDIN;
|
|
input CH1_RESETOVRD;
|
|
input CH1_RXADAPTRESET;
|
|
input CH1_RXADCCALRESET;
|
|
input CH1_RXADCCLKGENRESET;
|
|
input CH1_RXBUFRESET;
|
|
input CH1_RXCDRFREQOS;
|
|
input CH1_RXCDRFRRESET;
|
|
input CH1_RXCDRHOLD;
|
|
input CH1_RXCDRINCPCTRL;
|
|
input CH1_RXCDROVRDEN;
|
|
input CH1_RXCDRPHRESET;
|
|
input CH1_RXDFERESET;
|
|
input CH1_RXDSPRESET;
|
|
input CH1_RXEQTRAINING;
|
|
input CH1_RXEYESCANRESET;
|
|
input CH1_RXFECRESET;
|
|
input [2:0] CH1_RXOUTCLKSEL;
|
|
input CH1_RXPCSRESET;
|
|
input [3:0] CH1_RXPCSRESETMASK;
|
|
input CH1_RXPMARESET;
|
|
input [7:0] CH1_RXPMARESETMASK;
|
|
input CH1_RXPOLARITY;
|
|
input CH1_RXPRBSCNTSTOP;
|
|
input CH1_RXPRBSCSCNTRST;
|
|
input [3:0] CH1_RXPRBSPTN;
|
|
input CH1_RXPROGDIVRESET;
|
|
input CH1_RXQPRBSEN;
|
|
input [1:0] CH1_RXRESETMODE;
|
|
input CH1_RXSPCSEQADV;
|
|
input CH1_RXUSRCLK;
|
|
input CH1_RXUSRCLK2;
|
|
input CH1_RXUSRRDY;
|
|
input CH1_RXUSRSTART;
|
|
input CH1_RXUSRSTOP;
|
|
input CH1_TXCKALRESET;
|
|
input [5:0] CH1_TXCTLFIRDAT;
|
|
input [255:0] CH1_TXDATA;
|
|
input CH1_TXDATASTART;
|
|
input [4:0] CH1_TXDRVAMP;
|
|
input [5:0] CH1_TXEMPMAIN;
|
|
input [4:0] CH1_TXEMPPOST;
|
|
input [4:0] CH1_TXEMPPRE;
|
|
input [3:0] CH1_TXEMPPRE2;
|
|
input CH1_TXFECRESET;
|
|
input CH1_TXINHIBIT;
|
|
input CH1_TXMUXDCDEXHOLD;
|
|
input CH1_TXMUXDCDORWREN;
|
|
input [2:0] CH1_TXOUTCLKSEL;
|
|
input CH1_TXPCSRESET;
|
|
input [1:0] CH1_TXPCSRESETMASK;
|
|
input CH1_TXPMARESET;
|
|
input [1:0] CH1_TXPMARESETMASK;
|
|
input CH1_TXPOLARITY;
|
|
input CH1_TXPRBSINERR;
|
|
input [3:0] CH1_TXPRBSPTN;
|
|
input CH1_TXPROGDIVRESET;
|
|
input CH1_TXQPRBSEN;
|
|
input [1:0] CH1_TXRESETMODE;
|
|
input CH1_TXSPCSEQADV;
|
|
input CH1_TXUSRCLK;
|
|
input CH1_TXUSRCLK2;
|
|
input CH1_TXUSRRDY;
|
|
input [10:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPRST;
|
|
input DRPWE;
|
|
input FECCTRLRX0BITSLIPFS;
|
|
input FECCTRLRX1BITSLIPFS;
|
|
input GTGREFCLK2PLL;
|
|
input GTNORTHREFCLK;
|
|
input GTREFCLK;
|
|
input GTSOUTHREFCLK;
|
|
input [7:0] PLLFBDIV;
|
|
input PLLMONCLK;
|
|
input PLLPD;
|
|
input [2:0] PLLREFCLKSEL;
|
|
input PLLRESET;
|
|
input PLLRESETBYPASSMODE;
|
|
input [1:0] PLLRESETMASK;
|
|
input [15:0] PLLRSVDIN;
|
|
input RCALENB;
|
|
input [25:0] SDMDATA;
|
|
input SDMTOGGLE;
|
|
endmodule
|
|
|
|
module IBUFDS_GTM(O, ODIV2, CEB, I, IB);
|
|
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
|
|
parameter integer REFCLK_HROW_CK_SEL = 0;
|
|
parameter integer REFCLK_ICNTL_RX = 0;
|
|
output O;
|
|
output ODIV2;
|
|
input CEB;
|
|
(* iopad_external_pin *)
|
|
input I;
|
|
(* iopad_external_pin *)
|
|
input IB;
|
|
endmodule
|
|
|
|
module OBUFDS_GTM(O, OB, CEB, I);
|
|
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
|
|
parameter integer REFCLK_ICNTL_TX = 0;
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
output OB;
|
|
input CEB;
|
|
input I;
|
|
endmodule
|
|
|
|
module OBUFDS_GTM_ADV(O, OB, CEB, I);
|
|
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0;
|
|
parameter integer REFCLK_ICNTL_TX = 0;
|
|
parameter [1:0] RXRECCLK_SEL = 2'b00;
|
|
(* iopad_external_pin *)
|
|
output O;
|
|
(* iopad_external_pin *)
|
|
output OB;
|
|
input CEB;
|
|
input [3:0] I;
|
|
endmodule
|
|
|
|
module HSDAC(CLK_DAC, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_COMMON, STATUS_DAC0, STATUS_DAC1, STATUS_DAC2, STATUS_DAC3, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, VOUT0_N, VOUT0_P, VOUT1_N, VOUT1_P, VOUT2_N, VOUT2_P, VOUT3_N, VOUT3_P, CLK_FIFO_LM
|
|
, CONTROL_COMMON, CONTROL_DAC0, CONTROL_DAC1, CONTROL_DAC2, CONTROL_DAC3, DAC_CLK_N, DAC_CLK_P, DADDR, DATA_DAC0, DATA_DAC1, DATA_DAC2, DATA_DAC3, DCLK, DEN, DI, DWE, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH
|
|
, SYSREF_N, SYSREF_P);
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter integer XPA_CFG0 = 0;
|
|
parameter integer XPA_CFG1 = 0;
|
|
parameter integer XPA_NUM_DACS = 0;
|
|
parameter integer XPA_NUM_DUCS = 0;
|
|
parameter XPA_PLL_USED = "No";
|
|
parameter integer XPA_SAMPLE_RATE_MSPS = 0;
|
|
output CLK_DAC;
|
|
output [15:0] DOUT;
|
|
output DRDY;
|
|
output PLL_DMON_OUT;
|
|
output PLL_REFCLK_OUT;
|
|
output [15:0] STATUS_COMMON;
|
|
output [15:0] STATUS_DAC0;
|
|
output [15:0] STATUS_DAC1;
|
|
output [15:0] STATUS_DAC2;
|
|
output [15:0] STATUS_DAC3;
|
|
output SYSREF_OUT_NORTH;
|
|
output SYSREF_OUT_SOUTH;
|
|
output VOUT0_N;
|
|
output VOUT0_P;
|
|
output VOUT1_N;
|
|
output VOUT1_P;
|
|
output VOUT2_N;
|
|
output VOUT2_P;
|
|
output VOUT3_N;
|
|
output VOUT3_P;
|
|
input CLK_FIFO_LM;
|
|
input [15:0] CONTROL_COMMON;
|
|
input [15:0] CONTROL_DAC0;
|
|
input [15:0] CONTROL_DAC1;
|
|
input [15:0] CONTROL_DAC2;
|
|
input [15:0] CONTROL_DAC3;
|
|
input DAC_CLK_N;
|
|
input DAC_CLK_P;
|
|
input [11:0] DADDR;
|
|
input [255:0] DATA_DAC0;
|
|
input [255:0] DATA_DAC1;
|
|
input [255:0] DATA_DAC2;
|
|
input [255:0] DATA_DAC3;
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
input FABRIC_CLK;
|
|
input PLL_MONCLK;
|
|
input PLL_REFCLK_IN;
|
|
input SYSREF_IN_NORTH;
|
|
input SYSREF_IN_SOUTH;
|
|
input SYSREF_N;
|
|
input SYSREF_P;
|
|
endmodule
|
|
|
|
module HSADC(CLK_ADC, DATA_ADC0, DATA_ADC1, DATA_ADC2, DATA_ADC3, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_ADC0, STATUS_ADC1, STATUS_ADC2, STATUS_ADC3, STATUS_COMMON, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, ADC_CLK_N, ADC_CLK_P, CLK_FIFO_LM, CONTROL_ADC0, CONTROL_ADC1
|
|
, CONTROL_ADC2, CONTROL_ADC3, CONTROL_COMMON, DADDR, DCLK, DEN, DI, DWE, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH, SYSREF_N, SYSREF_P, VIN0_N, VIN0_P, VIN1_N, VIN1_P, VIN2_N, VIN2_P
|
|
, VIN3_N, VIN3_P, VIN_I01_N, VIN_I01_P, VIN_I23_N, VIN_I23_P);
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter integer XPA_CFG0 = 0;
|
|
parameter integer XPA_CFG1 = 0;
|
|
parameter XPA_NUM_ADCS = "0";
|
|
parameter integer XPA_NUM_DDCS = 0;
|
|
parameter XPA_PLL_USED = "No";
|
|
parameter integer XPA_SAMPLE_RATE_MSPS = 0;
|
|
output CLK_ADC;
|
|
output [127:0] DATA_ADC0;
|
|
output [127:0] DATA_ADC1;
|
|
output [127:0] DATA_ADC2;
|
|
output [127:0] DATA_ADC3;
|
|
output [15:0] DOUT;
|
|
output DRDY;
|
|
output PLL_DMON_OUT;
|
|
output PLL_REFCLK_OUT;
|
|
output [15:0] STATUS_ADC0;
|
|
output [15:0] STATUS_ADC1;
|
|
output [15:0] STATUS_ADC2;
|
|
output [15:0] STATUS_ADC3;
|
|
output [15:0] STATUS_COMMON;
|
|
output SYSREF_OUT_NORTH;
|
|
output SYSREF_OUT_SOUTH;
|
|
input ADC_CLK_N;
|
|
input ADC_CLK_P;
|
|
input CLK_FIFO_LM;
|
|
input [15:0] CONTROL_ADC0;
|
|
input [15:0] CONTROL_ADC1;
|
|
input [15:0] CONTROL_ADC2;
|
|
input [15:0] CONTROL_ADC3;
|
|
input [15:0] CONTROL_COMMON;
|
|
input [11:0] DADDR;
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
input FABRIC_CLK;
|
|
input PLL_MONCLK;
|
|
input PLL_REFCLK_IN;
|
|
input SYSREF_IN_NORTH;
|
|
input SYSREF_IN_SOUTH;
|
|
input SYSREF_N;
|
|
input SYSREF_P;
|
|
input VIN0_N;
|
|
input VIN0_P;
|
|
input VIN1_N;
|
|
input VIN1_P;
|
|
input VIN2_N;
|
|
input VIN2_P;
|
|
input VIN3_N;
|
|
input VIN3_P;
|
|
input VIN_I01_N;
|
|
input VIN_I01_P;
|
|
input VIN_I23_N;
|
|
input VIN_I23_P;
|
|
endmodule
|
|
|
|
module RFDAC(CLK_DAC, CLK_DIST_OUT_NORTH, CLK_DIST_OUT_SOUTH, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_COMMON, STATUS_DAC0, STATUS_DAC1, STATUS_DAC2, STATUS_DAC3, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, T1_ALLOWED_SOUTH, VOUT0_N, VOUT0_P, VOUT1_N, VOUT1_P, VOUT2_N, VOUT2_P
|
|
, VOUT3_N, VOUT3_P, CLK_DIST_IN_NORTH, CLK_DIST_IN_SOUTH, CLK_FIFO_LM, CONTROL_COMMON, CONTROL_DAC0, CONTROL_DAC1, CONTROL_DAC2, CONTROL_DAC3, DAC_CLK_N, DAC_CLK_P, DADDR, DATA_DAC0, DATA_DAC1, DATA_DAC2, DATA_DAC3, DCLK, DEN, DI, DWE
|
|
, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH, SYSREF_N, SYSREF_P, T1_ALLOWED_NORTH);
|
|
parameter integer LD_DEVICE = 0;
|
|
parameter integer OPT_CLK_DIST = 0;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter integer XPA_ACTIVE_DUTYCYCLE = 100;
|
|
parameter integer XPA_CFG0 = 0;
|
|
parameter integer XPA_CFG1 = 0;
|
|
parameter integer XPA_CFG2 = 0;
|
|
parameter integer XPA_NUM_DACS = 0;
|
|
parameter integer XPA_NUM_DUCS = 0;
|
|
parameter XPA_PLL_USED = "EXTERNAL";
|
|
parameter integer XPA_SAMPLE_RATE_MSPS = 0;
|
|
output CLK_DAC;
|
|
output CLK_DIST_OUT_NORTH;
|
|
output CLK_DIST_OUT_SOUTH;
|
|
output [15:0] DOUT;
|
|
output DRDY;
|
|
output PLL_DMON_OUT;
|
|
output PLL_REFCLK_OUT;
|
|
output [23:0] STATUS_COMMON;
|
|
output [23:0] STATUS_DAC0;
|
|
output [23:0] STATUS_DAC1;
|
|
output [23:0] STATUS_DAC2;
|
|
output [23:0] STATUS_DAC3;
|
|
output SYSREF_OUT_NORTH;
|
|
output SYSREF_OUT_SOUTH;
|
|
output T1_ALLOWED_SOUTH;
|
|
output VOUT0_N;
|
|
output VOUT0_P;
|
|
output VOUT1_N;
|
|
output VOUT1_P;
|
|
output VOUT2_N;
|
|
output VOUT2_P;
|
|
output VOUT3_N;
|
|
output VOUT3_P;
|
|
input CLK_DIST_IN_NORTH;
|
|
input CLK_DIST_IN_SOUTH;
|
|
input CLK_FIFO_LM;
|
|
input [15:0] CONTROL_COMMON;
|
|
input [15:0] CONTROL_DAC0;
|
|
input [15:0] CONTROL_DAC1;
|
|
input [15:0] CONTROL_DAC2;
|
|
input [15:0] CONTROL_DAC3;
|
|
input DAC_CLK_N;
|
|
input DAC_CLK_P;
|
|
input [11:0] DADDR;
|
|
input [255:0] DATA_DAC0;
|
|
input [255:0] DATA_DAC1;
|
|
input [255:0] DATA_DAC2;
|
|
input [255:0] DATA_DAC3;
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
input FABRIC_CLK;
|
|
input PLL_MONCLK;
|
|
input PLL_REFCLK_IN;
|
|
input SYSREF_IN_NORTH;
|
|
input SYSREF_IN_SOUTH;
|
|
input SYSREF_N;
|
|
input SYSREF_P;
|
|
input T1_ALLOWED_NORTH;
|
|
endmodule
|
|
|
|
module RFADC(CLK_ADC, CLK_DIST_OUT_NORTH, CLK_DIST_OUT_SOUTH, DATA_ADC0, DATA_ADC1, DATA_ADC2, DATA_ADC3, DOUT, DRDY, PLL_DMON_OUT, PLL_REFCLK_OUT, STATUS_ADC0, STATUS_ADC1, STATUS_ADC2, STATUS_ADC3, STATUS_COMMON, SYSREF_OUT_NORTH, SYSREF_OUT_SOUTH, T1_ALLOWED_SOUTH, ADC_CLK_N, ADC_CLK_P
|
|
, CLK_DIST_IN_NORTH, CLK_DIST_IN_SOUTH, CLK_FIFO_LM, CONTROL_ADC0, CONTROL_ADC1, CONTROL_ADC2, CONTROL_ADC3, CONTROL_COMMON, DADDR, DCLK, DEN, DI, DWE, FABRIC_CLK, PLL_MONCLK, PLL_REFCLK_IN, SYSREF_IN_NORTH, SYSREF_IN_SOUTH, SYSREF_N, SYSREF_P, T1_ALLOWED_NORTH
|
|
, VIN0_N, VIN0_P, VIN1_N, VIN1_P, VIN2_N, VIN2_P, VIN3_N, VIN3_P, VIN_I01_N, VIN_I01_P, VIN_I23_N, VIN_I23_P);
|
|
parameter integer LD_DEVICE = 0;
|
|
parameter integer OPT_ANALOG = 0;
|
|
parameter integer OPT_CLK_DIST = 0;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter integer XPA_ACTIVE_DUTYCYCLE = 100;
|
|
parameter integer XPA_CFG0 = 0;
|
|
parameter integer XPA_CFG1 = 0;
|
|
parameter integer XPA_CFG2 = 0;
|
|
parameter XPA_NUM_ADCS = "0";
|
|
parameter integer XPA_NUM_DDCS = 0;
|
|
parameter XPA_PLL_USED = "EXTERNAL";
|
|
parameter integer XPA_SAMPLE_RATE_MSPS = 0;
|
|
output CLK_ADC;
|
|
output CLK_DIST_OUT_NORTH;
|
|
output CLK_DIST_OUT_SOUTH;
|
|
output [191:0] DATA_ADC0;
|
|
output [191:0] DATA_ADC1;
|
|
output [191:0] DATA_ADC2;
|
|
output [191:0] DATA_ADC3;
|
|
output [15:0] DOUT;
|
|
output DRDY;
|
|
output PLL_DMON_OUT;
|
|
output PLL_REFCLK_OUT;
|
|
output [23:0] STATUS_ADC0;
|
|
output [23:0] STATUS_ADC1;
|
|
output [23:0] STATUS_ADC2;
|
|
output [23:0] STATUS_ADC3;
|
|
output [23:0] STATUS_COMMON;
|
|
output SYSREF_OUT_NORTH;
|
|
output SYSREF_OUT_SOUTH;
|
|
output T1_ALLOWED_SOUTH;
|
|
input ADC_CLK_N;
|
|
input ADC_CLK_P;
|
|
input CLK_DIST_IN_NORTH;
|
|
input CLK_DIST_IN_SOUTH;
|
|
input CLK_FIFO_LM;
|
|
input [15:0] CONTROL_ADC0;
|
|
input [15:0] CONTROL_ADC1;
|
|
input [15:0] CONTROL_ADC2;
|
|
input [15:0] CONTROL_ADC3;
|
|
input [15:0] CONTROL_COMMON;
|
|
input [11:0] DADDR;
|
|
input DCLK;
|
|
input DEN;
|
|
input [15:0] DI;
|
|
input DWE;
|
|
input FABRIC_CLK;
|
|
input PLL_MONCLK;
|
|
input PLL_REFCLK_IN;
|
|
input SYSREF_IN_NORTH;
|
|
input SYSREF_IN_SOUTH;
|
|
input SYSREF_N;
|
|
input SYSREF_P;
|
|
input T1_ALLOWED_NORTH;
|
|
input VIN0_N;
|
|
input VIN0_P;
|
|
input VIN1_N;
|
|
input VIN1_P;
|
|
input VIN2_N;
|
|
input VIN2_P;
|
|
input VIN3_N;
|
|
input VIN3_P;
|
|
input VIN_I01_N;
|
|
input VIN_I01_P;
|
|
input VIN_I23_N;
|
|
input VIN_I23_P;
|
|
endmodule
|
|
|
|
module PCIE_A1(CFGCOMMANDBUSMASTERENABLE, CFGCOMMANDINTERRUPTDISABLE, CFGCOMMANDIOENABLE, CFGCOMMANDMEMENABLE, CFGCOMMANDSERREN, CFGDEVCONTROLAUXPOWEREN, CFGDEVCONTROLCORRERRREPORTINGEN, CFGDEVCONTROLENABLERO, CFGDEVCONTROLEXTTAGEN, CFGDEVCONTROLFATALERRREPORTINGEN, CFGDEVCONTROLNONFATALREPORTINGEN, CFGDEVCONTROLNOSNOOPEN, CFGDEVCONTROLPHANTOMEN, CFGDEVCONTROLURERRREPORTINGEN, CFGDEVSTATUSCORRERRDETECTED, CFGDEVSTATUSFATALERRDETECTED, CFGDEVSTATUSNONFATALERRDETECTED, CFGDEVSTATUSURDETECTED, CFGERRCPLRDYN, CFGINTERRUPTMSIENABLE, CFGINTERRUPTRDYN
|
|
, CFGLINKCONTOLRCB, CFGLINKCONTROLCOMMONCLOCK, CFGLINKCONTROLEXTENDEDSYNC, CFGRDWRDONEN, CFGTOTURNOFFN, DBGBADDLLPSTATUS, DBGBADTLPLCRC, DBGBADTLPSEQNUM, DBGBADTLPSTATUS, DBGDLPROTOCOLSTATUS, DBGFCPROTOCOLERRSTATUS, DBGMLFRMDLENGTH, DBGMLFRMDMPS, DBGMLFRMDTCVC, DBGMLFRMDTLPSTATUS, DBGMLFRMDUNRECTYPE, DBGPOISTLPSTATUS, DBGRCVROVERFLOWSTATUS, DBGREGDETECTEDCORRECTABLE, DBGREGDETECTEDFATAL, DBGREGDETECTEDNONFATAL
|
|
, DBGREGDETECTEDUNSUPPORTED, DBGRPLYROLLOVERSTATUS, DBGRPLYTIMEOUTSTATUS, DBGURNOBARHIT, DBGURPOISCFGWR, DBGURSTATUS, DBGURUNSUPMSG, MIMRXREN, MIMRXWEN, MIMTXREN, MIMTXWEN, PIPEGTTXELECIDLEA, PIPEGTTXELECIDLEB, PIPERXPOLARITYA, PIPERXPOLARITYB, PIPERXRESETA, PIPERXRESETB, PIPETXRCVRDETA, PIPETXRCVRDETB, RECEIVEDHOTRESET, TRNLNKUPN
|
|
, TRNREOFN, TRNRERRFWDN, TRNRSOFN, TRNRSRCDSCN, TRNRSRCRDYN, TRNTCFGREQN, TRNTDSTRDYN, TRNTERRDROPN, USERRSTN, MIMRXRADDR, MIMRXWADDR, MIMTXRADDR, MIMTXWADDR, TRNFCCPLD, TRNFCNPD, TRNFCPD, PIPETXDATAA, PIPETXDATAB, CFGLINKCONTROLASPMCONTROL, PIPEGTPOWERDOWNA, PIPEGTPOWERDOWNB
|
|
, PIPETXCHARDISPMODEA, PIPETXCHARDISPMODEB, PIPETXCHARDISPVALA, PIPETXCHARDISPVALB, PIPETXCHARISKA, PIPETXCHARISKB, CFGDEVCONTROLMAXPAYLOAD, CFGDEVCONTROLMAXREADREQ, CFGFUNCTIONNUMBER, CFGINTERRUPTMMENABLE, CFGPCIELINKSTATEN, CFGDO, TRNRD, MIMRXWDATA, MIMTXWDATA, CFGDEVICENUMBER, CFGLTSSMSTATE, TRNTBUFAV, TRNRBARHITN, CFGBUSNUMBER, CFGINTERRUPTDO
|
|
, TRNFCCPLH, TRNFCNPH, TRNFCPH, CFGERRCORN, CFGERRCPLABORTN, CFGERRCPLTIMEOUTN, CFGERRECRCN, CFGERRLOCKEDN, CFGERRPOSTEDN, CFGERRURN, CFGINTERRUPTASSERTN, CFGINTERRUPTN, CFGPMWAKEN, CFGRDENN, CFGTRNPENDINGN, CFGTURNOFFOKN, CLOCKLOCKED, MGTCLK, PIPEGTRESETDONEA, PIPEGTRESETDONEB, PIPEPHYSTATUSA
|
|
, PIPEPHYSTATUSB, PIPERXENTERELECIDLEA, PIPERXENTERELECIDLEB, SYSRESETN, TRNRDSTRDYN, TRNRNPOKN, TRNTCFGGNTN, TRNTEOFN, TRNTERRFWDN, TRNTSOFN, TRNTSRCDSCN, TRNTSRCRDYN, TRNTSTRN, USERCLK, CFGDEVID, CFGSUBSYSID, CFGSUBSYSVENID, CFGVENID, PIPERXDATAA, PIPERXDATAB, PIPERXCHARISKA
|
|
, PIPERXCHARISKB, PIPERXSTATUSA, PIPERXSTATUSB, TRNFCSEL, TRNTD, MIMRXRDATA, MIMTXRDATA, CFGERRTLPCPLHEADER, CFGDSN, CFGINTERRUPTDI, CFGREVID, CFGDWADDR);
|
|
parameter [31:0] BAR0 = 32'h00000000;
|
|
parameter [31:0] BAR1 = 32'h00000000;
|
|
parameter [31:0] BAR2 = 32'h00000000;
|
|
parameter [31:0] BAR3 = 32'h00000000;
|
|
parameter [31:0] BAR4 = 32'h00000000;
|
|
parameter [31:0] BAR5 = 32'h00000000;
|
|
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000;
|
|
parameter [23:0] CLASS_CODE = 24'h000000;
|
|
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 7;
|
|
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7;
|
|
parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE";
|
|
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2;
|
|
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0;
|
|
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE";
|
|
parameter DISABLE_BAR_FILTERING = "FALSE";
|
|
parameter DISABLE_ID_CHECK = "FALSE";
|
|
parameter DISABLE_SCRAMBLING = "FALSE";
|
|
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
|
|
parameter [21:0] EXPANSION_ROM = 22'h000000;
|
|
parameter FAST_TRAIN = "FALSE";
|
|
parameter integer GTP_SEL = 0;
|
|
parameter integer LINK_CAP_ASPM_SUPPORT = 1;
|
|
parameter integer LINK_CAP_L0S_EXIT_LATENCY = 7;
|
|
parameter integer LINK_CAP_L1_EXIT_LATENCY = 7;
|
|
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE";
|
|
parameter [14:0] LL_ACK_TIMEOUT = 15'h0204;
|
|
parameter LL_ACK_TIMEOUT_EN = "FALSE";
|
|
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h060D;
|
|
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
|
|
parameter integer MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0;
|
|
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h1;
|
|
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0;
|
|
parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'b00000;
|
|
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
|
|
parameter [11:0] PCIE_GENERIC = 12'h000;
|
|
parameter PLM_AUTO_CONFIG = "FALSE";
|
|
parameter integer PM_CAP_AUXCURRENT = 0;
|
|
parameter PM_CAP_D1SUPPORT = "TRUE";
|
|
parameter PM_CAP_D2SUPPORT = "TRUE";
|
|
parameter PM_CAP_DSI = "FALSE";
|
|
parameter [4:0] PM_CAP_PMESUPPORT = 5'b01111;
|
|
parameter PM_CAP_PME_CLOCK = "FALSE";
|
|
parameter integer PM_CAP_VERSION = 3;
|
|
parameter [7:0] PM_DATA0 = 8'h1E;
|
|
parameter [7:0] PM_DATA1 = 8'h1E;
|
|
parameter [7:0] PM_DATA2 = 8'h1E;
|
|
parameter [7:0] PM_DATA3 = 8'h1E;
|
|
parameter [7:0] PM_DATA4 = 8'h1E;
|
|
parameter [7:0] PM_DATA5 = 8'h1E;
|
|
parameter [7:0] PM_DATA6 = 8'h1E;
|
|
parameter [7:0] PM_DATA7 = 8'h1E;
|
|
parameter [1:0] PM_DATA_SCALE0 = 2'b01;
|
|
parameter [1:0] PM_DATA_SCALE1 = 2'b01;
|
|
parameter [1:0] PM_DATA_SCALE2 = 2'b01;
|
|
parameter [1:0] PM_DATA_SCALE3 = 2'b01;
|
|
parameter [1:0] PM_DATA_SCALE4 = 2'b01;
|
|
parameter [1:0] PM_DATA_SCALE5 = 2'b01;
|
|
parameter [1:0] PM_DATA_SCALE6 = 2'b01;
|
|
parameter [1:0] PM_DATA_SCALE7 = 2'b01;
|
|
parameter SIM_VERSION = "1.0";
|
|
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
|
|
parameter integer TL_RX_RAM_RADDR_LATENCY = 1;
|
|
parameter integer TL_RX_RAM_RDATA_LATENCY = 2;
|
|
parameter integer TL_RX_RAM_WRITE_LATENCY = 0;
|
|
parameter TL_TFC_DISABLE = "FALSE";
|
|
parameter TL_TX_CHECKS_DISABLE = "FALSE";
|
|
parameter integer TL_TX_RAM_RADDR_LATENCY = 0;
|
|
parameter integer TL_TX_RAM_RDATA_LATENCY = 2;
|
|
parameter USR_CFG = "FALSE";
|
|
parameter USR_EXT_CFG = "FALSE";
|
|
parameter VC0_CPL_INFINITE = "TRUE";
|
|
parameter [11:0] VC0_RX_RAM_LIMIT = 12'h01E;
|
|
parameter integer VC0_TOTAL_CREDITS_CD = 104;
|
|
parameter integer VC0_TOTAL_CREDITS_CH = 36;
|
|
parameter integer VC0_TOTAL_CREDITS_NPH = 8;
|
|
parameter integer VC0_TOTAL_CREDITS_PD = 288;
|
|
parameter integer VC0_TOTAL_CREDITS_PH = 32;
|
|
parameter integer VC0_TX_LASTPACKET = 31;
|
|
output CFGCOMMANDBUSMASTERENABLE;
|
|
output CFGCOMMANDINTERRUPTDISABLE;
|
|
output CFGCOMMANDIOENABLE;
|
|
output CFGCOMMANDMEMENABLE;
|
|
output CFGCOMMANDSERREN;
|
|
output CFGDEVCONTROLAUXPOWEREN;
|
|
output CFGDEVCONTROLCORRERRREPORTINGEN;
|
|
output CFGDEVCONTROLENABLERO;
|
|
output CFGDEVCONTROLEXTTAGEN;
|
|
output CFGDEVCONTROLFATALERRREPORTINGEN;
|
|
output CFGDEVCONTROLNONFATALREPORTINGEN;
|
|
output CFGDEVCONTROLNOSNOOPEN;
|
|
output CFGDEVCONTROLPHANTOMEN;
|
|
output CFGDEVCONTROLURERRREPORTINGEN;
|
|
output CFGDEVSTATUSCORRERRDETECTED;
|
|
output CFGDEVSTATUSFATALERRDETECTED;
|
|
output CFGDEVSTATUSNONFATALERRDETECTED;
|
|
output CFGDEVSTATUSURDETECTED;
|
|
output CFGERRCPLRDYN;
|
|
output CFGINTERRUPTMSIENABLE;
|
|
output CFGINTERRUPTRDYN;
|
|
output CFGLINKCONTOLRCB;
|
|
output CFGLINKCONTROLCOMMONCLOCK;
|
|
output CFGLINKCONTROLEXTENDEDSYNC;
|
|
output CFGRDWRDONEN;
|
|
output CFGTOTURNOFFN;
|
|
output DBGBADDLLPSTATUS;
|
|
output DBGBADTLPLCRC;
|
|
output DBGBADTLPSEQNUM;
|
|
output DBGBADTLPSTATUS;
|
|
output DBGDLPROTOCOLSTATUS;
|
|
output DBGFCPROTOCOLERRSTATUS;
|
|
output DBGMLFRMDLENGTH;
|
|
output DBGMLFRMDMPS;
|
|
output DBGMLFRMDTCVC;
|
|
output DBGMLFRMDTLPSTATUS;
|
|
output DBGMLFRMDUNRECTYPE;
|
|
output DBGPOISTLPSTATUS;
|
|
output DBGRCVROVERFLOWSTATUS;
|
|
output DBGREGDETECTEDCORRECTABLE;
|
|
output DBGREGDETECTEDFATAL;
|
|
output DBGREGDETECTEDNONFATAL;
|
|
output DBGREGDETECTEDUNSUPPORTED;
|
|
output DBGRPLYROLLOVERSTATUS;
|
|
output DBGRPLYTIMEOUTSTATUS;
|
|
output DBGURNOBARHIT;
|
|
output DBGURPOISCFGWR;
|
|
output DBGURSTATUS;
|
|
output DBGURUNSUPMSG;
|
|
output MIMRXREN;
|
|
output MIMRXWEN;
|
|
output MIMTXREN;
|
|
output MIMTXWEN;
|
|
output PIPEGTTXELECIDLEA;
|
|
output PIPEGTTXELECIDLEB;
|
|
output PIPERXPOLARITYA;
|
|
output PIPERXPOLARITYB;
|
|
output PIPERXRESETA;
|
|
output PIPERXRESETB;
|
|
output PIPETXRCVRDETA;
|
|
output PIPETXRCVRDETB;
|
|
output RECEIVEDHOTRESET;
|
|
output TRNLNKUPN;
|
|
output TRNREOFN;
|
|
output TRNRERRFWDN;
|
|
output TRNRSOFN;
|
|
output TRNRSRCDSCN;
|
|
output TRNRSRCRDYN;
|
|
output TRNTCFGREQN;
|
|
output TRNTDSTRDYN;
|
|
output TRNTERRDROPN;
|
|
output USERRSTN;
|
|
output [11:0] MIMRXRADDR;
|
|
output [11:0] MIMRXWADDR;
|
|
output [11:0] MIMTXRADDR;
|
|
output [11:0] MIMTXWADDR;
|
|
output [11:0] TRNFCCPLD;
|
|
output [11:0] TRNFCNPD;
|
|
output [11:0] TRNFCPD;
|
|
output [15:0] PIPETXDATAA;
|
|
output [15:0] PIPETXDATAB;
|
|
output [1:0] CFGLINKCONTROLASPMCONTROL;
|
|
output [1:0] PIPEGTPOWERDOWNA;
|
|
output [1:0] PIPEGTPOWERDOWNB;
|
|
output [1:0] PIPETXCHARDISPMODEA;
|
|
output [1:0] PIPETXCHARDISPMODEB;
|
|
output [1:0] PIPETXCHARDISPVALA;
|
|
output [1:0] PIPETXCHARDISPVALB;
|
|
output [1:0] PIPETXCHARISKA;
|
|
output [1:0] PIPETXCHARISKB;
|
|
output [2:0] CFGDEVCONTROLMAXPAYLOAD;
|
|
output [2:0] CFGDEVCONTROLMAXREADREQ;
|
|
output [2:0] CFGFUNCTIONNUMBER;
|
|
output [2:0] CFGINTERRUPTMMENABLE;
|
|
output [2:0] CFGPCIELINKSTATEN;
|
|
output [31:0] CFGDO;
|
|
output [31:0] TRNRD;
|
|
output [34:0] MIMRXWDATA;
|
|
output [35:0] MIMTXWDATA;
|
|
output [4:0] CFGDEVICENUMBER;
|
|
output [4:0] CFGLTSSMSTATE;
|
|
output [5:0] TRNTBUFAV;
|
|
output [6:0] TRNRBARHITN;
|
|
output [7:0] CFGBUSNUMBER;
|
|
output [7:0] CFGINTERRUPTDO;
|
|
output [7:0] TRNFCCPLH;
|
|
output [7:0] TRNFCNPH;
|
|
output [7:0] TRNFCPH;
|
|
input CFGERRCORN;
|
|
input CFGERRCPLABORTN;
|
|
input CFGERRCPLTIMEOUTN;
|
|
input CFGERRECRCN;
|
|
input CFGERRLOCKEDN;
|
|
input CFGERRPOSTEDN;
|
|
input CFGERRURN;
|
|
input CFGINTERRUPTASSERTN;
|
|
input CFGINTERRUPTN;
|
|
input CFGPMWAKEN;
|
|
input CFGRDENN;
|
|
input CFGTRNPENDINGN;
|
|
input CFGTURNOFFOKN;
|
|
input CLOCKLOCKED;
|
|
input MGTCLK;
|
|
input PIPEGTRESETDONEA;
|
|
input PIPEGTRESETDONEB;
|
|
input PIPEPHYSTATUSA;
|
|
input PIPEPHYSTATUSB;
|
|
input PIPERXENTERELECIDLEA;
|
|
input PIPERXENTERELECIDLEB;
|
|
input SYSRESETN;
|
|
input TRNRDSTRDYN;
|
|
input TRNRNPOKN;
|
|
input TRNTCFGGNTN;
|
|
input TRNTEOFN;
|
|
input TRNTERRFWDN;
|
|
input TRNTSOFN;
|
|
input TRNTSRCDSCN;
|
|
input TRNTSRCRDYN;
|
|
input TRNTSTRN;
|
|
input USERCLK;
|
|
input [15:0] CFGDEVID;
|
|
input [15:0] CFGSUBSYSID;
|
|
input [15:0] CFGSUBSYSVENID;
|
|
input [15:0] CFGVENID;
|
|
input [15:0] PIPERXDATAA;
|
|
input [15:0] PIPERXDATAB;
|
|
input [1:0] PIPERXCHARISKA;
|
|
input [1:0] PIPERXCHARISKB;
|
|
input [2:0] PIPERXSTATUSA;
|
|
input [2:0] PIPERXSTATUSB;
|
|
input [2:0] TRNFCSEL;
|
|
input [31:0] TRNTD;
|
|
input [34:0] MIMRXRDATA;
|
|
input [35:0] MIMTXRDATA;
|
|
input [47:0] CFGERRTLPCPLHEADER;
|
|
input [63:0] CFGDSN;
|
|
input [7:0] CFGINTERRUPTDI;
|
|
input [7:0] CFGREVID;
|
|
input [9:0] CFGDWADDR;
|
|
endmodule
|
|
|
|
module PCIE_EP(BUSMASTERENABLE, CRMDOHOTRESETN, CRMPWRSOFTRESETN, DLLTXPMDLLPOUTSTANDING, INTERRUPTDISABLE, IOSPACEENABLE, L0CFGLOOPBACKACK, L0DLLRXACKOUTSTANDING, L0DLLTXNONFCOUTSTANDING, L0DLLTXOUTSTANDING, L0FIRSTCFGWRITEOCCURRED, L0MACENTEREDL0, L0MACLINKTRAINING, L0MACLINKUP, L0MACNEWSTATEACK, L0MACRXL0SSTATE, L0MSIENABLE0, L0PMEACK, L0PMEEN, L0PMEREQOUT, L0PWRL1STATE
|
|
, L0PWRL23READYSTATE, L0PWRTURNOFFREQ, L0PWRTXL0SSTATE, L0RXDLLPM, L0STATSCFGOTHERRECEIVED, L0STATSCFGOTHERTRANSMITTED, L0STATSCFGRECEIVED, L0STATSCFGTRANSMITTED, L0STATSDLLPRECEIVED, L0STATSDLLPTRANSMITTED, L0STATSOSRECEIVED, L0STATSOSTRANSMITTED, L0STATSTLPRECEIVED, L0STATSTLPTRANSMITTED, L0UNLOCKRECEIVED, LLKRXEOFN, LLKRXEOPN, LLKRXSOFN, LLKRXSOPN, LLKRXSRCLASTREQN, LLKRXSRCRDYN
|
|
, LLKTXCONFIGREADYN, LLKTXDSTRDYN, MEMSPACEENABLE, MIMDLLBREN, MIMDLLBWEN, MIMRXBREN, MIMRXBWEN, MIMTXBREN, MIMTXBWEN, PARITYERRORRESPONSE, PIPEDESKEWLANESL0, PIPEDESKEWLANESL1, PIPEDESKEWLANESL2, PIPEDESKEWLANESL3, PIPEDESKEWLANESL4, PIPEDESKEWLANESL5, PIPEDESKEWLANESL6, PIPEDESKEWLANESL7, PIPERESETL0, PIPERESETL1, PIPERESETL2
|
|
, PIPERESETL3, PIPERESETL4, PIPERESETL5, PIPERESETL6, PIPERESETL7, PIPERXPOLARITYL0, PIPERXPOLARITYL1, PIPERXPOLARITYL2, PIPERXPOLARITYL3, PIPERXPOLARITYL4, PIPERXPOLARITYL5, PIPERXPOLARITYL6, PIPERXPOLARITYL7, PIPETXCOMPLIANCEL0, PIPETXCOMPLIANCEL1, PIPETXCOMPLIANCEL2, PIPETXCOMPLIANCEL3, PIPETXCOMPLIANCEL4, PIPETXCOMPLIANCEL5, PIPETXCOMPLIANCEL6, PIPETXCOMPLIANCEL7
|
|
, PIPETXDATAKL0, PIPETXDATAKL1, PIPETXDATAKL2, PIPETXDATAKL3, PIPETXDATAKL4, PIPETXDATAKL5, PIPETXDATAKL6, PIPETXDATAKL7, PIPETXDETECTRXLOOPBACKL0, PIPETXDETECTRXLOOPBACKL1, PIPETXDETECTRXLOOPBACKL2, PIPETXDETECTRXLOOPBACKL3, PIPETXDETECTRXLOOPBACKL4, PIPETXDETECTRXLOOPBACKL5, PIPETXDETECTRXLOOPBACKL6, PIPETXDETECTRXLOOPBACKL7, PIPETXELECIDLEL0, PIPETXELECIDLEL1, PIPETXELECIDLEL2, PIPETXELECIDLEL3, PIPETXELECIDLEL4
|
|
, PIPETXELECIDLEL5, PIPETXELECIDLEL6, PIPETXELECIDLEL7, SERRENABLE, URREPORTINGENABLE, MGMTSTATSCREDIT, MIMDLLBRADD, MIMDLLBWADD, L0COMPLETERID, MIMRXBRADD, MIMRXBWADD, MIMTXBRADD, MIMTXBWADD, LLKRXPREFERREDTYPE, MGMTPSO, L0PWRSTATE0, L0RXMACLINKERROR, LLKRXVALIDN, PIPEPOWERDOWNL0, PIPEPOWERDOWNL1, PIPEPOWERDOWNL2
|
|
, PIPEPOWERDOWNL3, PIPEPOWERDOWNL4, PIPEPOWERDOWNL5, PIPEPOWERDOWNL6, PIPEPOWERDOWNL7, L0MULTIMSGEN0, L0RXDLLPMTYPE, MAXPAYLOADSIZE, MAXREADREQUESTSIZE, MGMTRDATA, L0LTSSMSTATE, L0MACNEGOTIATEDLINKWIDTH, LLKRXDATA, MIMDLLBWDATA, MIMRXBWDATA, MIMTXBWDATA, L0DLLERRORVECTOR, L0DLLVCSTATUS, L0DLUPDOWN, LLKRXCHCOMPLETIONAVAILABLEN, LLKRXCHNONPOSTEDAVAILABLEN
|
|
, LLKRXCHPOSTEDAVAILABLEN, LLKTCSTATUS, LLKTXCHCOMPLETIONREADYN, LLKTXCHNONPOSTEDREADYN, LLKTXCHPOSTEDREADYN, PIPETXDATAL0, PIPETXDATAL1, PIPETXDATAL2, PIPETXDATAL3, PIPETXDATAL4, PIPETXDATAL5, PIPETXDATAL6, PIPETXDATAL7, LLKTXCHANSPACE, AUXPOWER, COMPLIANCEAVOID, CRMCORECLK, CRMCORECLKDLO, CRMCORECLKRXO, CRMCORECLKTXO, CRMLINKRSTN
|
|
, CRMMACRSTN, CRMMGMTRSTN, CRMNVRSTN, CRMURSTN, CRMUSERCFGRSTN, CRMUSERCLK, CRMUSERCLKRXO, CRMUSERCLKTXO, L0CFGDISABLESCRAMBLE, L0CFGLOOPBACKMASTER, L0LEGACYINTFUNCT0, L0PMEREQIN, L0SETCOMPLETERABORTERROR, L0SETCOMPLETIONTIMEOUTCORRERROR, L0SETCOMPLETIONTIMEOUTUNCORRERROR, L0SETDETECTEDCORRERROR, L0SETDETECTEDFATALERROR, L0SETDETECTEDNONFATALERROR, L0SETUNEXPECTEDCOMPLETIONCORRERROR, L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR
|
|
, L0SETUNSUPPORTEDREQUESTOTHERERROR, L0SETUSERDETECTEDPARITYERROR, L0SETUSERMASTERDATAPARITY, L0SETUSERRECEIVEDMASTERABORT, L0SETUSERRECEIVEDTARGETABORT, L0SETUSERSIGNALLEDTARGETABORT, L0SETUSERSYSTEMERROR, L0TRANSACTIONSPENDING, LLKRXDSTCONTREQN, LLKRXDSTREQN, LLKTXEOFN, LLKTXEOPN, LLKTXSOFN, LLKTXSOPN, LLKTXSRCDSCN, LLKTXSRCRDYN, MGMTRDEN, MGMTWREN, PIPEPHYSTATUSL0, PIPEPHYSTATUSL1, PIPEPHYSTATUSL2
|
|
, PIPEPHYSTATUSL3, PIPEPHYSTATUSL4, PIPEPHYSTATUSL5, PIPEPHYSTATUSL6, PIPEPHYSTATUSL7, PIPERXCHANISALIGNEDL0, PIPERXCHANISALIGNEDL1, PIPERXCHANISALIGNEDL2, PIPERXCHANISALIGNEDL3, PIPERXCHANISALIGNEDL4, PIPERXCHANISALIGNEDL5, PIPERXCHANISALIGNEDL6, PIPERXCHANISALIGNEDL7, PIPERXDATAKL0, PIPERXDATAKL1, PIPERXDATAKL2, PIPERXDATAKL3, PIPERXDATAKL4, PIPERXDATAKL5, PIPERXDATAKL6, PIPERXDATAKL7
|
|
, PIPERXELECIDLEL0, PIPERXELECIDLEL1, PIPERXELECIDLEL2, PIPERXELECIDLEL3, PIPERXELECIDLEL4, PIPERXELECIDLEL5, PIPERXELECIDLEL6, PIPERXELECIDLEL7, PIPERXVALIDL0, PIPERXVALIDL1, PIPERXVALIDL2, PIPERXVALIDL3, PIPERXVALIDL4, PIPERXVALIDL5, PIPERXVALIDL6, PIPERXVALIDL7, MGMTADDR, L0PACKETHEADERFROMUSER, LLKRXCHFIFO, LLKTXCHFIFO, LLKTXENABLEN
|
|
, LLKRXCHTC, LLKTXCHTC, PIPERXSTATUSL0, PIPERXSTATUSL1, PIPERXSTATUSL2, PIPERXSTATUSL3, PIPERXSTATUSL4, PIPERXSTATUSL5, PIPERXSTATUSL6, PIPERXSTATUSL7, MGMTWDATA, L0MSIREQUEST0, MGMTBWREN, LLKTXDATA, MIMDLLBRDATA, MIMRXBRDATA, MIMTXBRDATA, MGMTSTATSCREDITSEL, PIPERXDATAL0, PIPERXDATAL1, PIPERXDATAL2
|
|
, PIPERXDATAL3, PIPERXDATAL4, PIPERXDATAL5, PIPERXDATAL6, PIPERXDATAL7);
|
|
parameter BAR0EXIST = "TRUE";
|
|
parameter BAR0PREFETCHABLE = "TRUE";
|
|
parameter BAR1EXIST = "FALSE";
|
|
parameter BAR1PREFETCHABLE = "FALSE";
|
|
parameter BAR2EXIST = "FALSE";
|
|
parameter BAR2PREFETCHABLE = "FALSE";
|
|
parameter BAR3EXIST = "FALSE";
|
|
parameter BAR3PREFETCHABLE = "FALSE";
|
|
parameter BAR4EXIST = "FALSE";
|
|
parameter BAR4PREFETCHABLE = "FALSE";
|
|
parameter BAR5EXIST = "FALSE";
|
|
parameter BAR5PREFETCHABLE = "FALSE";
|
|
parameter CLKDIVIDED = "FALSE";
|
|
parameter INFINITECOMPLETIONS = "TRUE";
|
|
parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE";
|
|
parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE";
|
|
parameter PMCAPABILITYD1SUPPORT = "FALSE";
|
|
parameter PMCAPABILITYD2SUPPORT = "FALSE";
|
|
parameter PMCAPABILITYDSI = "TRUE";
|
|
parameter RESETMODE = "FALSE";
|
|
parameter [10:0] VC0TOTALCREDITSCD = 11'h0;
|
|
parameter [10:0] VC0TOTALCREDITSPD = 11'h34;
|
|
parameter [10:0] VC1TOTALCREDITSCD = 11'h0;
|
|
parameter [10:0] VC1TOTALCREDITSPD = 11'h0;
|
|
parameter [11:0] AERBASEPTR = 12'h110;
|
|
parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138;
|
|
parameter [11:0] DSNBASEPTR = 12'h148;
|
|
parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154;
|
|
parameter [11:0] MSIBASEPTR = 12'h48;
|
|
parameter [11:0] PBBASEPTR = 12'h138;
|
|
parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148;
|
|
parameter [11:0] PMBASEPTR = 12'h40;
|
|
parameter [11:0] RETRYRAMSIZE = 12'h9;
|
|
parameter [11:0] VCBASEPTR = 12'h154;
|
|
parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0;
|
|
parameter [12:0] VC0RXFIFOBASEC = 13'h98;
|
|
parameter [12:0] VC0RXFIFOBASENP = 13'h80;
|
|
parameter [12:0] VC0RXFIFOBASEP = 13'h0;
|
|
parameter [12:0] VC0RXFIFOLIMITC = 13'h117;
|
|
parameter [12:0] VC0RXFIFOLIMITNP = 13'h97;
|
|
parameter [12:0] VC0RXFIFOLIMITP = 13'h7f;
|
|
parameter [12:0] VC0TXFIFOBASEC = 13'h98;
|
|
parameter [12:0] VC0TXFIFOBASENP = 13'h80;
|
|
parameter [12:0] VC0TXFIFOBASEP = 13'h0;
|
|
parameter [12:0] VC0TXFIFOLIMITC = 13'h117;
|
|
parameter [12:0] VC0TXFIFOLIMITNP = 13'h97;
|
|
parameter [12:0] VC0TXFIFOLIMITP = 13'h7f;
|
|
parameter [12:0] VC1RXFIFOBASEC = 13'h118;
|
|
parameter [12:0] VC1RXFIFOBASENP = 13'h118;
|
|
parameter [12:0] VC1RXFIFOBASEP = 13'h118;
|
|
parameter [12:0] VC1RXFIFOLIMITC = 13'h118;
|
|
parameter [12:0] VC1RXFIFOLIMITNP = 13'h118;
|
|
parameter [12:0] VC1RXFIFOLIMITP = 13'h118;
|
|
parameter [12:0] VC1TXFIFOBASEC = 13'h118;
|
|
parameter [12:0] VC1TXFIFOBASENP = 13'h118;
|
|
parameter [12:0] VC1TXFIFOBASEP = 13'h118;
|
|
parameter [12:0] VC1TXFIFOLIMITC = 13'h118;
|
|
parameter [12:0] VC1TXFIFOLIMITNP = 13'h118;
|
|
parameter [12:0] VC1TXFIFOLIMITP = 13'h118;
|
|
parameter [15:0] DEVICEID = 16'h5050;
|
|
parameter [15:0] SUBSYSTEMID = 16'h5050;
|
|
parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE;
|
|
parameter [15:0] VENDORID = 16'h10EE;
|
|
parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1;
|
|
parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0;
|
|
parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0;
|
|
parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0;
|
|
parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0;
|
|
parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0;
|
|
parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0;
|
|
parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0;
|
|
parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0;
|
|
parameter [23:0] CLASSCODE = 24'h058000;
|
|
parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0;
|
|
parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0;
|
|
parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0;
|
|
parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0;
|
|
parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0;
|
|
parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0;
|
|
parameter [31:0] CARDBUSCISPOINTER = 32'h0;
|
|
parameter [3:0] XPDEVICEPORTTYPE = 4'h0;
|
|
parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0;
|
|
parameter [5:0] BAR0MASKWIDTH = 6'h14;
|
|
parameter [5:0] BAR1MASKWIDTH = 6'h0;
|
|
parameter [5:0] BAR2MASKWIDTH = 6'h0;
|
|
parameter [5:0] BAR3MASKWIDTH = 6'h0;
|
|
parameter [5:0] BAR4MASKWIDTH = 6'h0;
|
|
parameter [5:0] BAR5MASKWIDTH = 6'h0;
|
|
parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01;
|
|
parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35;
|
|
parameter [6:0] VC0TOTALCREDITSCH = 7'h0;
|
|
parameter [6:0] VC0TOTALCREDITSNPH = 7'h08;
|
|
parameter [6:0] VC0TOTALCREDITSPH = 7'h08;
|
|
parameter [6:0] VC1TOTALCREDITSCH = 7'h0;
|
|
parameter [6:0] VC1TOTALCREDITSNPH = 7'h0;
|
|
parameter [6:0] VC1TOTALCREDITSPH = 7'h0;
|
|
parameter [7:0] ACTIVELANESIN = 8'h1;
|
|
parameter [7:0] CAPABILITIESPOINTER = 8'h40;
|
|
parameter [7:0] INTERRUPTPIN = 8'h0;
|
|
parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60;
|
|
parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0;
|
|
parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0;
|
|
parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0;
|
|
parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0;
|
|
parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0;
|
|
parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60;
|
|
parameter [7:0] PMDATA0 = 8'h0;
|
|
parameter [7:0] PMDATA1 = 8'h0;
|
|
parameter [7:0] PMDATA2 = 8'h0;
|
|
parameter [7:0] PMDATA3 = 8'h0;
|
|
parameter [7:0] PMDATA4 = 8'h0;
|
|
parameter [7:0] PMDATA5 = 8'h0;
|
|
parameter [7:0] PMDATA6 = 8'h0;
|
|
parameter [7:0] PMDATA7 = 8'h0;
|
|
parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0;
|
|
parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0;
|
|
parameter [7:0] REVISIONID = 8'h0;
|
|
parameter [7:0] XPBASEPTR = 8'h60;
|
|
parameter BAR0ADDRWIDTH = 0;
|
|
parameter BAR0IOMEMN = 0;
|
|
parameter BAR1ADDRWIDTH = 0;
|
|
parameter BAR1IOMEMN = 0;
|
|
parameter BAR2ADDRWIDTH = 0;
|
|
parameter BAR2IOMEMN = 0;
|
|
parameter BAR3ADDRWIDTH = 0;
|
|
parameter BAR3IOMEMN = 0;
|
|
parameter BAR4ADDRWIDTH = 0;
|
|
parameter BAR4IOMEMN = 0;
|
|
parameter BAR5IOMEMN = 0;
|
|
parameter L0SEXITLATENCY = 7;
|
|
parameter L0SEXITLATENCYCOMCLK = 7;
|
|
parameter L1EXITLATENCY = 7;
|
|
parameter L1EXITLATENCYCOMCLK = 7;
|
|
parameter LOWPRIORITYVCCOUNT = 0;
|
|
parameter PMDATASCALE0 = 0;
|
|
parameter PMDATASCALE1 = 0;
|
|
parameter PMDATASCALE2 = 0;
|
|
parameter PMDATASCALE3 = 0;
|
|
parameter PMDATASCALE4 = 0;
|
|
parameter PMDATASCALE5 = 0;
|
|
parameter PMDATASCALE6 = 0;
|
|
parameter PMDATASCALE7 = 0;
|
|
parameter RETRYRAMREADLATENCY = 3;
|
|
parameter RETRYRAMWRITELATENCY = 1;
|
|
parameter TLRAMREADLATENCY = 3;
|
|
parameter TLRAMWRITELATENCY = 1;
|
|
parameter TXTSNFTS = 255;
|
|
parameter TXTSNFTSCOMCLK = 255;
|
|
parameter XPMAXPAYLOAD = 0;
|
|
output BUSMASTERENABLE;
|
|
output CRMDOHOTRESETN;
|
|
output CRMPWRSOFTRESETN;
|
|
output DLLTXPMDLLPOUTSTANDING;
|
|
output INTERRUPTDISABLE;
|
|
output IOSPACEENABLE;
|
|
output L0CFGLOOPBACKACK;
|
|
output L0DLLRXACKOUTSTANDING;
|
|
output L0DLLTXNONFCOUTSTANDING;
|
|
output L0DLLTXOUTSTANDING;
|
|
output L0FIRSTCFGWRITEOCCURRED;
|
|
output L0MACENTEREDL0;
|
|
output L0MACLINKTRAINING;
|
|
output L0MACLINKUP;
|
|
output L0MACNEWSTATEACK;
|
|
output L0MACRXL0SSTATE;
|
|
output L0MSIENABLE0;
|
|
output L0PMEACK;
|
|
output L0PMEEN;
|
|
output L0PMEREQOUT;
|
|
output L0PWRL1STATE;
|
|
output L0PWRL23READYSTATE;
|
|
output L0PWRTURNOFFREQ;
|
|
output L0PWRTXL0SSTATE;
|
|
output L0RXDLLPM;
|
|
output L0STATSCFGOTHERRECEIVED;
|
|
output L0STATSCFGOTHERTRANSMITTED;
|
|
output L0STATSCFGRECEIVED;
|
|
output L0STATSCFGTRANSMITTED;
|
|
output L0STATSDLLPRECEIVED;
|
|
output L0STATSDLLPTRANSMITTED;
|
|
output L0STATSOSRECEIVED;
|
|
output L0STATSOSTRANSMITTED;
|
|
output L0STATSTLPRECEIVED;
|
|
output L0STATSTLPTRANSMITTED;
|
|
output L0UNLOCKRECEIVED;
|
|
output LLKRXEOFN;
|
|
output LLKRXEOPN;
|
|
output LLKRXSOFN;
|
|
output LLKRXSOPN;
|
|
output LLKRXSRCLASTREQN;
|
|
output LLKRXSRCRDYN;
|
|
output LLKTXCONFIGREADYN;
|
|
output LLKTXDSTRDYN;
|
|
output MEMSPACEENABLE;
|
|
output MIMDLLBREN;
|
|
output MIMDLLBWEN;
|
|
output MIMRXBREN;
|
|
output MIMRXBWEN;
|
|
output MIMTXBREN;
|
|
output MIMTXBWEN;
|
|
output PARITYERRORRESPONSE;
|
|
output PIPEDESKEWLANESL0;
|
|
output PIPEDESKEWLANESL1;
|
|
output PIPEDESKEWLANESL2;
|
|
output PIPEDESKEWLANESL3;
|
|
output PIPEDESKEWLANESL4;
|
|
output PIPEDESKEWLANESL5;
|
|
output PIPEDESKEWLANESL6;
|
|
output PIPEDESKEWLANESL7;
|
|
output PIPERESETL0;
|
|
output PIPERESETL1;
|
|
output PIPERESETL2;
|
|
output PIPERESETL3;
|
|
output PIPERESETL4;
|
|
output PIPERESETL5;
|
|
output PIPERESETL6;
|
|
output PIPERESETL7;
|
|
output PIPERXPOLARITYL0;
|
|
output PIPERXPOLARITYL1;
|
|
output PIPERXPOLARITYL2;
|
|
output PIPERXPOLARITYL3;
|
|
output PIPERXPOLARITYL4;
|
|
output PIPERXPOLARITYL5;
|
|
output PIPERXPOLARITYL6;
|
|
output PIPERXPOLARITYL7;
|
|
output PIPETXCOMPLIANCEL0;
|
|
output PIPETXCOMPLIANCEL1;
|
|
output PIPETXCOMPLIANCEL2;
|
|
output PIPETXCOMPLIANCEL3;
|
|
output PIPETXCOMPLIANCEL4;
|
|
output PIPETXCOMPLIANCEL5;
|
|
output PIPETXCOMPLIANCEL6;
|
|
output PIPETXCOMPLIANCEL7;
|
|
output PIPETXDATAKL0;
|
|
output PIPETXDATAKL1;
|
|
output PIPETXDATAKL2;
|
|
output PIPETXDATAKL3;
|
|
output PIPETXDATAKL4;
|
|
output PIPETXDATAKL5;
|
|
output PIPETXDATAKL6;
|
|
output PIPETXDATAKL7;
|
|
output PIPETXDETECTRXLOOPBACKL0;
|
|
output PIPETXDETECTRXLOOPBACKL1;
|
|
output PIPETXDETECTRXLOOPBACKL2;
|
|
output PIPETXDETECTRXLOOPBACKL3;
|
|
output PIPETXDETECTRXLOOPBACKL4;
|
|
output PIPETXDETECTRXLOOPBACKL5;
|
|
output PIPETXDETECTRXLOOPBACKL6;
|
|
output PIPETXDETECTRXLOOPBACKL7;
|
|
output PIPETXELECIDLEL0;
|
|
output PIPETXELECIDLEL1;
|
|
output PIPETXELECIDLEL2;
|
|
output PIPETXELECIDLEL3;
|
|
output PIPETXELECIDLEL4;
|
|
output PIPETXELECIDLEL5;
|
|
output PIPETXELECIDLEL6;
|
|
output PIPETXELECIDLEL7;
|
|
output SERRENABLE;
|
|
output URREPORTINGENABLE;
|
|
output [11:0] MGMTSTATSCREDIT;
|
|
output [11:0] MIMDLLBRADD;
|
|
output [11:0] MIMDLLBWADD;
|
|
output [12:0] L0COMPLETERID;
|
|
output [12:0] MIMRXBRADD;
|
|
output [12:0] MIMRXBWADD;
|
|
output [12:0] MIMTXBRADD;
|
|
output [12:0] MIMTXBWADD;
|
|
output [15:0] LLKRXPREFERREDTYPE;
|
|
output [16:0] MGMTPSO;
|
|
output [1:0] L0PWRSTATE0;
|
|
output [1:0] L0RXMACLINKERROR;
|
|
output [1:0] LLKRXVALIDN;
|
|
output [1:0] PIPEPOWERDOWNL0;
|
|
output [1:0] PIPEPOWERDOWNL1;
|
|
output [1:0] PIPEPOWERDOWNL2;
|
|
output [1:0] PIPEPOWERDOWNL3;
|
|
output [1:0] PIPEPOWERDOWNL4;
|
|
output [1:0] PIPEPOWERDOWNL5;
|
|
output [1:0] PIPEPOWERDOWNL6;
|
|
output [1:0] PIPEPOWERDOWNL7;
|
|
output [2:0] L0MULTIMSGEN0;
|
|
output [2:0] L0RXDLLPMTYPE;
|
|
output [2:0] MAXPAYLOADSIZE;
|
|
output [2:0] MAXREADREQUESTSIZE;
|
|
output [31:0] MGMTRDATA;
|
|
output [3:0] L0LTSSMSTATE;
|
|
output [3:0] L0MACNEGOTIATEDLINKWIDTH;
|
|
output [63:0] LLKRXDATA;
|
|
output [63:0] MIMDLLBWDATA;
|
|
output [63:0] MIMRXBWDATA;
|
|
output [63:0] MIMTXBWDATA;
|
|
output [6:0] L0DLLERRORVECTOR;
|
|
output [7:0] L0DLLVCSTATUS;
|
|
output [7:0] L0DLUPDOWN;
|
|
output [7:0] LLKRXCHCOMPLETIONAVAILABLEN;
|
|
output [7:0] LLKRXCHNONPOSTEDAVAILABLEN;
|
|
output [7:0] LLKRXCHPOSTEDAVAILABLEN;
|
|
output [7:0] LLKTCSTATUS;
|
|
output [7:0] LLKTXCHCOMPLETIONREADYN;
|
|
output [7:0] LLKTXCHNONPOSTEDREADYN;
|
|
output [7:0] LLKTXCHPOSTEDREADYN;
|
|
output [7:0] PIPETXDATAL0;
|
|
output [7:0] PIPETXDATAL1;
|
|
output [7:0] PIPETXDATAL2;
|
|
output [7:0] PIPETXDATAL3;
|
|
output [7:0] PIPETXDATAL4;
|
|
output [7:0] PIPETXDATAL5;
|
|
output [7:0] PIPETXDATAL6;
|
|
output [7:0] PIPETXDATAL7;
|
|
output [9:0] LLKTXCHANSPACE;
|
|
input AUXPOWER;
|
|
input COMPLIANCEAVOID;
|
|
input CRMCORECLK;
|
|
input CRMCORECLKDLO;
|
|
input CRMCORECLKRXO;
|
|
input CRMCORECLKTXO;
|
|
input CRMLINKRSTN;
|
|
input CRMMACRSTN;
|
|
input CRMMGMTRSTN;
|
|
input CRMNVRSTN;
|
|
input CRMURSTN;
|
|
input CRMUSERCFGRSTN;
|
|
input CRMUSERCLK;
|
|
input CRMUSERCLKRXO;
|
|
input CRMUSERCLKTXO;
|
|
input L0CFGDISABLESCRAMBLE;
|
|
input L0CFGLOOPBACKMASTER;
|
|
input L0LEGACYINTFUNCT0;
|
|
input L0PMEREQIN;
|
|
input L0SETCOMPLETERABORTERROR;
|
|
input L0SETCOMPLETIONTIMEOUTCORRERROR;
|
|
input L0SETCOMPLETIONTIMEOUTUNCORRERROR;
|
|
input L0SETDETECTEDCORRERROR;
|
|
input L0SETDETECTEDFATALERROR;
|
|
input L0SETDETECTEDNONFATALERROR;
|
|
input L0SETUNEXPECTEDCOMPLETIONCORRERROR;
|
|
input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR;
|
|
input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR;
|
|
input L0SETUNSUPPORTEDREQUESTOTHERERROR;
|
|
input L0SETUSERDETECTEDPARITYERROR;
|
|
input L0SETUSERMASTERDATAPARITY;
|
|
input L0SETUSERRECEIVEDMASTERABORT;
|
|
input L0SETUSERRECEIVEDTARGETABORT;
|
|
input L0SETUSERSIGNALLEDTARGETABORT;
|
|
input L0SETUSERSYSTEMERROR;
|
|
input L0TRANSACTIONSPENDING;
|
|
input LLKRXDSTCONTREQN;
|
|
input LLKRXDSTREQN;
|
|
input LLKTXEOFN;
|
|
input LLKTXEOPN;
|
|
input LLKTXSOFN;
|
|
input LLKTXSOPN;
|
|
input LLKTXSRCDSCN;
|
|
input LLKTXSRCRDYN;
|
|
input MGMTRDEN;
|
|
input MGMTWREN;
|
|
input PIPEPHYSTATUSL0;
|
|
input PIPEPHYSTATUSL1;
|
|
input PIPEPHYSTATUSL2;
|
|
input PIPEPHYSTATUSL3;
|
|
input PIPEPHYSTATUSL4;
|
|
input PIPEPHYSTATUSL5;
|
|
input PIPEPHYSTATUSL6;
|
|
input PIPEPHYSTATUSL7;
|
|
input PIPERXCHANISALIGNEDL0;
|
|
input PIPERXCHANISALIGNEDL1;
|
|
input PIPERXCHANISALIGNEDL2;
|
|
input PIPERXCHANISALIGNEDL3;
|
|
input PIPERXCHANISALIGNEDL4;
|
|
input PIPERXCHANISALIGNEDL5;
|
|
input PIPERXCHANISALIGNEDL6;
|
|
input PIPERXCHANISALIGNEDL7;
|
|
input PIPERXDATAKL0;
|
|
input PIPERXDATAKL1;
|
|
input PIPERXDATAKL2;
|
|
input PIPERXDATAKL3;
|
|
input PIPERXDATAKL4;
|
|
input PIPERXDATAKL5;
|
|
input PIPERXDATAKL6;
|
|
input PIPERXDATAKL7;
|
|
input PIPERXELECIDLEL0;
|
|
input PIPERXELECIDLEL1;
|
|
input PIPERXELECIDLEL2;
|
|
input PIPERXELECIDLEL3;
|
|
input PIPERXELECIDLEL4;
|
|
input PIPERXELECIDLEL5;
|
|
input PIPERXELECIDLEL6;
|
|
input PIPERXELECIDLEL7;
|
|
input PIPERXVALIDL0;
|
|
input PIPERXVALIDL1;
|
|
input PIPERXVALIDL2;
|
|
input PIPERXVALIDL3;
|
|
input PIPERXVALIDL4;
|
|
input PIPERXVALIDL5;
|
|
input PIPERXVALIDL6;
|
|
input PIPERXVALIDL7;
|
|
input [10:0] MGMTADDR;
|
|
input [127:0] L0PACKETHEADERFROMUSER;
|
|
input [1:0] LLKRXCHFIFO;
|
|
input [1:0] LLKTXCHFIFO;
|
|
input [1:0] LLKTXENABLEN;
|
|
input [2:0] LLKRXCHTC;
|
|
input [2:0] LLKTXCHTC;
|
|
input [2:0] PIPERXSTATUSL0;
|
|
input [2:0] PIPERXSTATUSL1;
|
|
input [2:0] PIPERXSTATUSL2;
|
|
input [2:0] PIPERXSTATUSL3;
|
|
input [2:0] PIPERXSTATUSL4;
|
|
input [2:0] PIPERXSTATUSL5;
|
|
input [2:0] PIPERXSTATUSL6;
|
|
input [2:0] PIPERXSTATUSL7;
|
|
input [31:0] MGMTWDATA;
|
|
input [3:0] L0MSIREQUEST0;
|
|
input [3:0] MGMTBWREN;
|
|
input [63:0] LLKTXDATA;
|
|
input [63:0] MIMDLLBRDATA;
|
|
input [63:0] MIMRXBRDATA;
|
|
input [63:0] MIMTXBRDATA;
|
|
input [6:0] MGMTSTATSCREDITSEL;
|
|
input [7:0] PIPERXDATAL0;
|
|
input [7:0] PIPERXDATAL1;
|
|
input [7:0] PIPERXDATAL2;
|
|
input [7:0] PIPERXDATAL3;
|
|
input [7:0] PIPERXDATAL4;
|
|
input [7:0] PIPERXDATAL5;
|
|
input [7:0] PIPERXDATAL6;
|
|
input [7:0] PIPERXDATAL7;
|
|
endmodule
|
|
|
|
module PCIE_2_0(CFGAERECRCCHECKEN, CFGAERECRCGENEN, CFGCOMMANDBUSMASTERENABLE, CFGCOMMANDINTERRUPTDISABLE, CFGCOMMANDIOENABLE, CFGCOMMANDMEMENABLE, CFGCOMMANDSERREN, CFGDEVCONTROL2CPLTIMEOUTDIS, CFGDEVCONTROLAUXPOWEREN, CFGDEVCONTROLCORRERRREPORTINGEN, CFGDEVCONTROLENABLERO, CFGDEVCONTROLEXTTAGEN, CFGDEVCONTROLFATALERRREPORTINGEN, CFGDEVCONTROLNONFATALREPORTINGEN, CFGDEVCONTROLNOSNOOPEN, CFGDEVCONTROLPHANTOMEN, CFGDEVCONTROLURERRREPORTINGEN, CFGDEVSTATUSCORRERRDETECTED, CFGDEVSTATUSFATALERRDETECTED, CFGDEVSTATUSNONFATALERRDETECTED, CFGDEVSTATUSURDETECTED
|
|
, CFGERRAERHEADERLOGSETN, CFGERRCPLRDYN, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXFM, CFGINTERRUPTRDYN, CFGLINKCONTROLAUTOBANDWIDTHINTEN, CFGLINKCONTROLBANDWIDTHINTEN, CFGLINKCONTROLCLOCKPMEN, CFGLINKCONTROLCOMMONCLOCK, CFGLINKCONTROLEXTENDEDSYNC, CFGLINKCONTROLHWAUTOWIDTHDIS, CFGLINKCONTROLLINKDISABLE, CFGLINKCONTROLRCB, CFGLINKCONTROLRETRAINLINK, CFGLINKSTATUSAUTOBANDWIDTHSTATUS, CFGLINKSTATUSBANDWITHSTATUS, CFGLINKSTATUSDLLACTIVE, CFGLINKSTATUSLINKTRAINING, CFGMSGRECEIVED, CFGMSGRECEIVEDASSERTINTA
|
|
, CFGMSGRECEIVEDASSERTINTB, CFGMSGRECEIVEDASSERTINTC, CFGMSGRECEIVEDASSERTINTD, CFGMSGRECEIVEDDEASSERTINTA, CFGMSGRECEIVEDDEASSERTINTB, CFGMSGRECEIVEDDEASSERTINTC, CFGMSGRECEIVEDDEASSERTINTD, CFGMSGRECEIVEDERRCOR, CFGMSGRECEIVEDERRFATAL, CFGMSGRECEIVEDERRNONFATAL, CFGMSGRECEIVEDPMASNAK, CFGMSGRECEIVEDPMETO, CFGMSGRECEIVEDPMETOACK, CFGMSGRECEIVEDPMPME, CFGMSGRECEIVEDSETSLOTPOWERLIMIT, CFGMSGRECEIVEDUNLOCK, CFGPMCSRPMEEN, CFGPMCSRPMESTATUS, CFGPMRCVASREQL1N, CFGPMRCVENTERL1N, CFGPMRCVENTERL23N
|
|
, CFGPMRCVREQACKN, CFGRDWRDONEN, CFGSLOTCONTROLELECTROMECHILCTLPULSE, CFGTRANSACTION, CFGTRANSACTIONTYPE, DBGSCLRA, DBGSCLRB, DBGSCLRC, DBGSCLRD, DBGSCLRE, DBGSCLRF, DBGSCLRG, DBGSCLRH, DBGSCLRI, DBGSCLRJ, DBGSCLRK, DRPDRDY, LL2BADDLLPERRN, LL2BADTLPERRN, LL2PROTOCOLERRN, LL2REPLAYROERRN
|
|
, LL2REPLAYTOERRN, LL2SUSPENDOKN, LL2TFCINIT1SEQN, LL2TFCINIT2SEQN, LNKCLKEN, MIMRXRCE, MIMRXREN, MIMRXWEN, MIMTXRCE, MIMTXREN, MIMTXWEN, PIPERX0POLARITY, PIPERX1POLARITY, PIPERX2POLARITY, PIPERX3POLARITY, PIPERX4POLARITY, PIPERX5POLARITY, PIPERX6POLARITY, PIPERX7POLARITY, PIPETX0COMPLIANCE, PIPETX0ELECIDLE
|
|
, PIPETX1COMPLIANCE, PIPETX1ELECIDLE, PIPETX2COMPLIANCE, PIPETX2ELECIDLE, PIPETX3COMPLIANCE, PIPETX3ELECIDLE, PIPETX4COMPLIANCE, PIPETX4ELECIDLE, PIPETX5COMPLIANCE, PIPETX5ELECIDLE, PIPETX6COMPLIANCE, PIPETX6ELECIDLE, PIPETX7COMPLIANCE, PIPETX7ELECIDLE, PIPETXDEEMPH, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PL2LINKUPN, PL2RECEIVERERRN, PL2RECOVERYN
|
|
, PL2RXELECIDLE, PL2SUSPENDOK, PLLINKGEN2CAP, PLLINKPARTNERGEN2SUPPORTED, PLLINKUPCFGCAP, PLPHYLNKUPN, PLRECEIVEDHOTRST, PLSELLNKRATE, RECEIVEDFUNCLVLRSTN, TL2ASPMSUSPENDCREDITCHECKOKN, TL2ASPMSUSPENDREQN, TL2PPMSUSPENDOKN, TRNLNKUPN, TRNRDLLPSRCRDYN, TRNRECRCERRN, TRNREOFN, TRNRERRFWDN, TRNRREMN, TRNRSOFN, TRNRSRCDSCN, TRNRSRCRDYN
|
|
, TRNTCFGREQN, TRNTDLLPDSTRDYN, TRNTDSTRDYN, TRNTERRDROPN, USERRSTN, DBGVECC, PLDBGVEC, TRNFCCPLD, TRNFCNPD, TRNFCPD, MIMRXRADDR, MIMRXWADDR, MIMTXRADDR, MIMTXWADDR, CFGMSGDATA, DRPDO, PIPETX0DATA, PIPETX1DATA, PIPETX2DATA, PIPETX3DATA, PIPETX4DATA
|
|
, PIPETX5DATA, PIPETX6DATA, PIPETX7DATA, CFGLINKCONTROLASPMCONTROL, CFGLINKSTATUSCURRENTSPEED, CFGPMCSRPOWERSTATE, PIPETX0CHARISK, PIPETX0POWERDOWN, PIPETX1CHARISK, PIPETX1POWERDOWN, PIPETX2CHARISK, PIPETX2POWERDOWN, PIPETX3CHARISK, PIPETX3POWERDOWN, PIPETX4CHARISK, PIPETX4POWERDOWN, PIPETX5CHARISK, PIPETX5POWERDOWN, PIPETX6CHARISK, PIPETX6POWERDOWN, PIPETX7CHARISK
|
|
, PIPETX7POWERDOWN, PLLANEREVERSALMODE, PLRXPMSTATE, PLSELLNKWIDTH, CFGDEVCONTROLMAXPAYLOAD, CFGDEVCONTROLMAXREADREQ, CFGINTERRUPTMMENABLE, CFGPCIELINKSTATE, PIPETXMARGIN, PLINITIALLINKWIDTH, PLTXPMSTATE, CFGDO, TRNRDLLPDATA, CFGDEVCONTROL2CPLTIMEOUTVAL, CFGLINKSTATUSNEGOTIATEDWIDTH, PLLTSSMSTATE, TRNTBUFAV, DBGVECA, DBGVECB, TRNRD, MIMRXWDATA
|
|
, MIMTXWDATA, CFGTRANSACTIONADDR, CFGVCTCVCMAP, TRNRBARHITN, CFGINTERRUPTDO, TRNFCCPLH, TRNFCNPH, TRNFCPH, CFGERRACSN, CFGERRCORN, CFGERRCPLABORTN, CFGERRCPLTIMEOUTN, CFGERRCPLUNEXPECTN, CFGERRECRCN, CFGERRLOCKEDN, CFGERRPOSTEDN, CFGERRURN, CFGINTERRUPTASSERTN, CFGINTERRUPTN, CFGPMDIRECTASPML1N, CFGPMSENDPMACKN
|
|
, CFGPMSENDPMETON, CFGPMSENDPMNAKN, CFGPMTURNOFFOKN, CFGPMWAKEN, CFGRDENN, CFGTRNPENDINGN, CFGWRENN, CFGWRREADONLYN, CFGWRRW1CASRWN, CMRSTN, CMSTICKYRSTN, DBGSUBMODE, DLRSTN, DRPCLK, DRPDEN, DRPDWE, FUNCLVLRSTN, LL2SENDASREQL1N, LL2SENDENTERL1N, LL2SENDENTERL23N, LL2SUSPENDNOWN
|
|
, LL2TLPRCVN, PIPECLK, PIPERX0CHANISALIGNED, PIPERX0ELECIDLE, PIPERX0PHYSTATUS, PIPERX0VALID, PIPERX1CHANISALIGNED, PIPERX1ELECIDLE, PIPERX1PHYSTATUS, PIPERX1VALID, PIPERX2CHANISALIGNED, PIPERX2ELECIDLE, PIPERX2PHYSTATUS, PIPERX2VALID, PIPERX3CHANISALIGNED, PIPERX3ELECIDLE, PIPERX3PHYSTATUS, PIPERX3VALID, PIPERX4CHANISALIGNED, PIPERX4ELECIDLE, PIPERX4PHYSTATUS
|
|
, PIPERX4VALID, PIPERX5CHANISALIGNED, PIPERX5ELECIDLE, PIPERX5PHYSTATUS, PIPERX5VALID, PIPERX6CHANISALIGNED, PIPERX6ELECIDLE, PIPERX6PHYSTATUS, PIPERX6VALID, PIPERX7CHANISALIGNED, PIPERX7ELECIDLE, PIPERX7PHYSTATUS, PIPERX7VALID, PLDIRECTEDLINKAUTON, PLDIRECTEDLINKSPEED, PLDOWNSTREAMDEEMPHSOURCE, PLRSTN, PLTRANSMITHOTRST, PLUPSTREAMPREFERDEEMPH, SYSRSTN, TL2ASPMSUSPENDCREDITCHECKN
|
|
, TL2PPMSUSPENDREQN, TLRSTN, TRNRDSTRDYN, TRNRNPOKN, TRNTCFGGNTN, TRNTDLLPSRCRDYN, TRNTECRCGENN, TRNTEOFN, TRNTERRFWDN, TRNTREMN, TRNTSOFN, TRNTSRCDSCN, TRNTSRCRDYN, TRNTSTRN, USERCLK, CFGERRAERHEADERLOG, DRPDI, PIPERX0DATA, PIPERX1DATA, PIPERX2DATA, PIPERX3DATA
|
|
, PIPERX4DATA, PIPERX5DATA, PIPERX6DATA, PIPERX7DATA, DBGMODE, PIPERX0CHARISK, PIPERX1CHARISK, PIPERX2CHARISK, PIPERX3CHARISK, PIPERX4CHARISK, PIPERX5CHARISK, PIPERX6CHARISK, PIPERX7CHARISK, PLDIRECTEDLINKCHANGE, PLDIRECTEDLINKWIDTH, CFGDSFUNCTIONNUMBER, PIPERX0STATUS, PIPERX1STATUS, PIPERX2STATUS, PIPERX3STATUS, PIPERX4STATUS
|
|
, PIPERX5STATUS, PIPERX6STATUS, PIPERX7STATUS, PLDBGMODE, TRNFCSEL, CFGDI, TRNTDLLPDATA, CFGBYTEENN, CFGERRTLPCPLHEADER, CFGDSDEVICENUMBER, PL2DIRECTEDLSTATE, CFGDSN, TRNTD, MIMRXRDATA, MIMTXRDATA, CFGDSBUSNUMBER, CFGINTERRUPTDI, CFGPORTNUMBER, DRPDADDR, CFGDWADDR);
|
|
parameter [11:0] AER_BASE_PTR = 12'h128;
|
|
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
|
|
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
|
|
parameter [15:0] AER_CAP_ID = 16'h0001;
|
|
parameter [4:0] AER_CAP_INT_MSG_NUM_MSI = 5'h0A;
|
|
parameter [4:0] AER_CAP_INT_MSG_NUM_MSIX = 5'h15;
|
|
parameter [11:0] AER_CAP_NEXTPTR = 12'h160;
|
|
parameter AER_CAP_ON = "FALSE";
|
|
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE";
|
|
parameter [3:0] AER_CAP_VERSION = 4'h1;
|
|
parameter ALLOW_X8_GEN2 = "FALSE";
|
|
parameter [31:0] BAR0 = 32'hFFFFFF00;
|
|
parameter [31:0] BAR1 = 32'hFFFF0000;
|
|
parameter [31:0] BAR2 = 32'hFFFF000C;
|
|
parameter [31:0] BAR3 = 32'hFFFFFFFF;
|
|
parameter [31:0] BAR4 = 32'h00000000;
|
|
parameter [31:0] BAR5 = 32'h00000000;
|
|
parameter [7:0] CAPABILITIES_PTR = 8'h40;
|
|
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000;
|
|
parameter [23:0] CLASS_CODE = 24'h000000;
|
|
parameter CMD_INTX_IMPLEMENTED = "TRUE";
|
|
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE";
|
|
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0;
|
|
parameter [6:0] CRM_MODULE_RSTS = 7'h00;
|
|
parameter [15:0] DEVICE_ID = 16'h0007;
|
|
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE";
|
|
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE";
|
|
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
|
|
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0;
|
|
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
|
|
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE";
|
|
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2;
|
|
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0;
|
|
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE";
|
|
parameter integer DEV_CAP_RSVD_14_12 = 0;
|
|
parameter integer DEV_CAP_RSVD_17_16 = 0;
|
|
parameter integer DEV_CAP_RSVD_31_29 = 0;
|
|
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE";
|
|
parameter DISABLE_ASPM_L1_TIMER = "FALSE";
|
|
parameter DISABLE_BAR_FILTERING = "FALSE";
|
|
parameter DISABLE_ID_CHECK = "FALSE";
|
|
parameter DISABLE_LANE_REVERSAL = "FALSE";
|
|
parameter DISABLE_RX_TC_FILTER = "FALSE";
|
|
parameter DISABLE_SCRAMBLING = "FALSE";
|
|
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
|
|
parameter [11:0] DSN_BASE_PTR = 12'h100;
|
|
parameter [15:0] DSN_CAP_ID = 16'h0003;
|
|
parameter [11:0] DSN_CAP_NEXTPTR = 12'h000;
|
|
parameter DSN_CAP_ON = "TRUE";
|
|
parameter [3:0] DSN_CAP_VERSION = 4'h1;
|
|
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000;
|
|
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
|
|
parameter ENTER_RVRY_EI_L0 = "TRUE";
|
|
parameter EXIT_LOOPBACK_ON_EI = "TRUE";
|
|
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001;
|
|
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F;
|
|
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF;
|
|
parameter [7:0] HEADER_TYPE = 8'h00;
|
|
parameter [4:0] INFER_EI = 5'h00;
|
|
parameter [7:0] INTERRUPT_PIN = 8'h01;
|
|
parameter IS_SWITCH = "FALSE";
|
|
parameter [9:0] LAST_CONFIG_DWORD = 10'h042;
|
|
parameter integer LINK_CAP_ASPM_SUPPORT = 1;
|
|
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE";
|
|
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE";
|
|
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
|
|
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE";
|
|
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1;
|
|
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08;
|
|
parameter integer LINK_CAP_RSVD_23_22 = 0;
|
|
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE";
|
|
parameter integer LINK_CONTROL_RCB = 0;
|
|
parameter LINK_CTRL2_DEEMPHASIS = "FALSE";
|
|
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE";
|
|
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2;
|
|
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
|
|
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000;
|
|
parameter LL_ACK_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
|
|
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000;
|
|
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
|
|
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01;
|
|
parameter [7:0] MSIX_BASE_PTR = 8'h9C;
|
|
parameter [7:0] MSIX_CAP_ID = 8'h11;
|
|
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter MSIX_CAP_ON = "FALSE";
|
|
parameter integer MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] MSI_BASE_PTR = 8'h48;
|
|
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE";
|
|
parameter [7:0] MSI_CAP_ID = 8'h05;
|
|
parameter integer MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0;
|
|
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60;
|
|
parameter MSI_CAP_ON = "FALSE";
|
|
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE";
|
|
parameter integer N_FTS_COMCLK_GEN1 = 255;
|
|
parameter integer N_FTS_COMCLK_GEN2 = 255;
|
|
parameter integer N_FTS_GEN1 = 255;
|
|
parameter integer N_FTS_GEN2 = 255;
|
|
parameter [7:0] PCIE_BASE_PTR = 8'h60;
|
|
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10;
|
|
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2;
|
|
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0;
|
|
parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'h00;
|
|
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter PCIE_CAP_ON = "TRUE";
|
|
parameter integer PCIE_CAP_RSVD_15_14 = 0;
|
|
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
|
|
parameter integer PCIE_REVISION = 2;
|
|
parameter integer PGL0_LANE = 0;
|
|
parameter integer PGL1_LANE = 1;
|
|
parameter integer PGL2_LANE = 2;
|
|
parameter integer PGL3_LANE = 3;
|
|
parameter integer PGL4_LANE = 4;
|
|
parameter integer PGL5_LANE = 5;
|
|
parameter integer PGL6_LANE = 6;
|
|
parameter integer PGL7_LANE = 7;
|
|
parameter integer PL_AUTO_CONFIG = 0;
|
|
parameter PL_FAST_TRAIN = "FALSE";
|
|
parameter [7:0] PM_BASE_PTR = 8'h40;
|
|
parameter integer PM_CAP_AUXCURRENT = 0;
|
|
parameter PM_CAP_D1SUPPORT = "TRUE";
|
|
parameter PM_CAP_D2SUPPORT = "TRUE";
|
|
parameter PM_CAP_DSI = "FALSE";
|
|
parameter [7:0] PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PM_CAP_NEXTPTR = 8'h48;
|
|
parameter PM_CAP_ON = "TRUE";
|
|
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F;
|
|
parameter PM_CAP_PME_CLOCK = "FALSE";
|
|
parameter integer PM_CAP_RSVD_04 = 0;
|
|
parameter integer PM_CAP_VERSION = 3;
|
|
parameter PM_CSR_B2B3 = "FALSE";
|
|
parameter PM_CSR_BPCCEN = "FALSE";
|
|
parameter PM_CSR_NOSOFTRST = "TRUE";
|
|
parameter [7:0] PM_DATA0 = 8'h01;
|
|
parameter [7:0] PM_DATA1 = 8'h01;
|
|
parameter [7:0] PM_DATA2 = 8'h01;
|
|
parameter [7:0] PM_DATA3 = 8'h01;
|
|
parameter [7:0] PM_DATA4 = 8'h01;
|
|
parameter [7:0] PM_DATA5 = 8'h01;
|
|
parameter [7:0] PM_DATA6 = 8'h01;
|
|
parameter [7:0] PM_DATA7 = 8'h01;
|
|
parameter [1:0] PM_DATA_SCALE0 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE1 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE2 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE3 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE4 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE5 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE6 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE7 = 2'h1;
|
|
parameter integer RECRC_CHK = 0;
|
|
parameter RECRC_CHK_TRIM = "FALSE";
|
|
parameter [7:0] REVISION_ID = 8'h00;
|
|
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE";
|
|
parameter SELECT_DLL_IF = "FALSE";
|
|
parameter SIM_VERSION = "1.0";
|
|
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE";
|
|
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE";
|
|
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE";
|
|
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000;
|
|
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
|
|
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0;
|
|
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00;
|
|
parameter integer SPARE_BIT0 = 0;
|
|
parameter integer SPARE_BIT1 = 0;
|
|
parameter integer SPARE_BIT2 = 0;
|
|
parameter integer SPARE_BIT3 = 0;
|
|
parameter integer SPARE_BIT4 = 0;
|
|
parameter integer SPARE_BIT5 = 0;
|
|
parameter integer SPARE_BIT6 = 0;
|
|
parameter integer SPARE_BIT7 = 0;
|
|
parameter integer SPARE_BIT8 = 0;
|
|
parameter [7:0] SPARE_BYTE0 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE1 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE2 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE3 = 8'h00;
|
|
parameter [31:0] SPARE_WORD0 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD1 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD2 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD3 = 32'h00000000;
|
|
parameter [15:0] SUBSYSTEM_ID = 16'h0007;
|
|
parameter [15:0] SUBSYSTEM_VENDOR_ID = 16'h10EE;
|
|
parameter TL_RBYPASS = "FALSE";
|
|
parameter integer TL_RX_RAM_RADDR_LATENCY = 0;
|
|
parameter integer TL_RX_RAM_RDATA_LATENCY = 2;
|
|
parameter integer TL_RX_RAM_WRITE_LATENCY = 0;
|
|
parameter TL_TFC_DISABLE = "FALSE";
|
|
parameter TL_TX_CHECKS_DISABLE = "FALSE";
|
|
parameter integer TL_TX_RAM_RADDR_LATENCY = 0;
|
|
parameter integer TL_TX_RAM_RDATA_LATENCY = 2;
|
|
parameter integer TL_TX_RAM_WRITE_LATENCY = 0;
|
|
parameter UPCONFIG_CAPABLE = "TRUE";
|
|
parameter UPSTREAM_FACING = "TRUE";
|
|
parameter UR_INV_REQ = "TRUE";
|
|
parameter integer USER_CLK_FREQ = 3;
|
|
parameter VC0_CPL_INFINITE = "TRUE";
|
|
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF;
|
|
parameter integer VC0_TOTAL_CREDITS_CD = 127;
|
|
parameter integer VC0_TOTAL_CREDITS_CH = 31;
|
|
parameter integer VC0_TOTAL_CREDITS_NPH = 12;
|
|
parameter integer VC0_TOTAL_CREDITS_PD = 288;
|
|
parameter integer VC0_TOTAL_CREDITS_PH = 32;
|
|
parameter integer VC0_TX_LASTPACKET = 31;
|
|
parameter [11:0] VC_BASE_PTR = 12'h10C;
|
|
parameter [15:0] VC_CAP_ID = 16'h0002;
|
|
parameter [11:0] VC_CAP_NEXTPTR = 12'h000;
|
|
parameter VC_CAP_ON = "FALSE";
|
|
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE";
|
|
parameter [3:0] VC_CAP_VERSION = 4'h1;
|
|
parameter [15:0] VENDOR_ID = 16'h10EE;
|
|
parameter [11:0] VSEC_BASE_PTR = 12'h160;
|
|
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234;
|
|
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018;
|
|
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1;
|
|
parameter [15:0] VSEC_CAP_ID = 16'h000B;
|
|
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE";
|
|
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000;
|
|
parameter VSEC_CAP_ON = "FALSE";
|
|
parameter [3:0] VSEC_CAP_VERSION = 4'h1;
|
|
output CFGAERECRCCHECKEN;
|
|
output CFGAERECRCGENEN;
|
|
output CFGCOMMANDBUSMASTERENABLE;
|
|
output CFGCOMMANDINTERRUPTDISABLE;
|
|
output CFGCOMMANDIOENABLE;
|
|
output CFGCOMMANDMEMENABLE;
|
|
output CFGCOMMANDSERREN;
|
|
output CFGDEVCONTROL2CPLTIMEOUTDIS;
|
|
output CFGDEVCONTROLAUXPOWEREN;
|
|
output CFGDEVCONTROLCORRERRREPORTINGEN;
|
|
output CFGDEVCONTROLENABLERO;
|
|
output CFGDEVCONTROLEXTTAGEN;
|
|
output CFGDEVCONTROLFATALERRREPORTINGEN;
|
|
output CFGDEVCONTROLNONFATALREPORTINGEN;
|
|
output CFGDEVCONTROLNOSNOOPEN;
|
|
output CFGDEVCONTROLPHANTOMEN;
|
|
output CFGDEVCONTROLURERRREPORTINGEN;
|
|
output CFGDEVSTATUSCORRERRDETECTED;
|
|
output CFGDEVSTATUSFATALERRDETECTED;
|
|
output CFGDEVSTATUSNONFATALERRDETECTED;
|
|
output CFGDEVSTATUSURDETECTED;
|
|
output CFGERRAERHEADERLOGSETN;
|
|
output CFGERRCPLRDYN;
|
|
output CFGINTERRUPTMSIENABLE;
|
|
output CFGINTERRUPTMSIXENABLE;
|
|
output CFGINTERRUPTMSIXFM;
|
|
output CFGINTERRUPTRDYN;
|
|
output CFGLINKCONTROLAUTOBANDWIDTHINTEN;
|
|
output CFGLINKCONTROLBANDWIDTHINTEN;
|
|
output CFGLINKCONTROLCLOCKPMEN;
|
|
output CFGLINKCONTROLCOMMONCLOCK;
|
|
output CFGLINKCONTROLEXTENDEDSYNC;
|
|
output CFGLINKCONTROLHWAUTOWIDTHDIS;
|
|
output CFGLINKCONTROLLINKDISABLE;
|
|
output CFGLINKCONTROLRCB;
|
|
output CFGLINKCONTROLRETRAINLINK;
|
|
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
|
|
output CFGLINKSTATUSBANDWITHSTATUS;
|
|
output CFGLINKSTATUSDLLACTIVE;
|
|
output CFGLINKSTATUSLINKTRAINING;
|
|
output CFGMSGRECEIVED;
|
|
output CFGMSGRECEIVEDASSERTINTA;
|
|
output CFGMSGRECEIVEDASSERTINTB;
|
|
output CFGMSGRECEIVEDASSERTINTC;
|
|
output CFGMSGRECEIVEDASSERTINTD;
|
|
output CFGMSGRECEIVEDDEASSERTINTA;
|
|
output CFGMSGRECEIVEDDEASSERTINTB;
|
|
output CFGMSGRECEIVEDDEASSERTINTC;
|
|
output CFGMSGRECEIVEDDEASSERTINTD;
|
|
output CFGMSGRECEIVEDERRCOR;
|
|
output CFGMSGRECEIVEDERRFATAL;
|
|
output CFGMSGRECEIVEDERRNONFATAL;
|
|
output CFGMSGRECEIVEDPMASNAK;
|
|
output CFGMSGRECEIVEDPMETO;
|
|
output CFGMSGRECEIVEDPMETOACK;
|
|
output CFGMSGRECEIVEDPMPME;
|
|
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
|
|
output CFGMSGRECEIVEDUNLOCK;
|
|
output CFGPMCSRPMEEN;
|
|
output CFGPMCSRPMESTATUS;
|
|
output CFGPMRCVASREQL1N;
|
|
output CFGPMRCVENTERL1N;
|
|
output CFGPMRCVENTERL23N;
|
|
output CFGPMRCVREQACKN;
|
|
output CFGRDWRDONEN;
|
|
output CFGSLOTCONTROLELECTROMECHILCTLPULSE;
|
|
output CFGTRANSACTION;
|
|
output CFGTRANSACTIONTYPE;
|
|
output DBGSCLRA;
|
|
output DBGSCLRB;
|
|
output DBGSCLRC;
|
|
output DBGSCLRD;
|
|
output DBGSCLRE;
|
|
output DBGSCLRF;
|
|
output DBGSCLRG;
|
|
output DBGSCLRH;
|
|
output DBGSCLRI;
|
|
output DBGSCLRJ;
|
|
output DBGSCLRK;
|
|
output DRPDRDY;
|
|
output LL2BADDLLPERRN;
|
|
output LL2BADTLPERRN;
|
|
output LL2PROTOCOLERRN;
|
|
output LL2REPLAYROERRN;
|
|
output LL2REPLAYTOERRN;
|
|
output LL2SUSPENDOKN;
|
|
output LL2TFCINIT1SEQN;
|
|
output LL2TFCINIT2SEQN;
|
|
output LNKCLKEN;
|
|
output MIMRXRCE;
|
|
output MIMRXREN;
|
|
output MIMRXWEN;
|
|
output MIMTXRCE;
|
|
output MIMTXREN;
|
|
output MIMTXWEN;
|
|
output PIPERX0POLARITY;
|
|
output PIPERX1POLARITY;
|
|
output PIPERX2POLARITY;
|
|
output PIPERX3POLARITY;
|
|
output PIPERX4POLARITY;
|
|
output PIPERX5POLARITY;
|
|
output PIPERX6POLARITY;
|
|
output PIPERX7POLARITY;
|
|
output PIPETX0COMPLIANCE;
|
|
output PIPETX0ELECIDLE;
|
|
output PIPETX1COMPLIANCE;
|
|
output PIPETX1ELECIDLE;
|
|
output PIPETX2COMPLIANCE;
|
|
output PIPETX2ELECIDLE;
|
|
output PIPETX3COMPLIANCE;
|
|
output PIPETX3ELECIDLE;
|
|
output PIPETX4COMPLIANCE;
|
|
output PIPETX4ELECIDLE;
|
|
output PIPETX5COMPLIANCE;
|
|
output PIPETX5ELECIDLE;
|
|
output PIPETX6COMPLIANCE;
|
|
output PIPETX6ELECIDLE;
|
|
output PIPETX7COMPLIANCE;
|
|
output PIPETX7ELECIDLE;
|
|
output PIPETXDEEMPH;
|
|
output PIPETXRATE;
|
|
output PIPETXRCVRDET;
|
|
output PIPETXRESET;
|
|
output PL2LINKUPN;
|
|
output PL2RECEIVERERRN;
|
|
output PL2RECOVERYN;
|
|
output PL2RXELECIDLE;
|
|
output PL2SUSPENDOK;
|
|
output PLLINKGEN2CAP;
|
|
output PLLINKPARTNERGEN2SUPPORTED;
|
|
output PLLINKUPCFGCAP;
|
|
output PLPHYLNKUPN;
|
|
output PLRECEIVEDHOTRST;
|
|
output PLSELLNKRATE;
|
|
output RECEIVEDFUNCLVLRSTN;
|
|
output TL2ASPMSUSPENDCREDITCHECKOKN;
|
|
output TL2ASPMSUSPENDREQN;
|
|
output TL2PPMSUSPENDOKN;
|
|
output TRNLNKUPN;
|
|
output TRNRDLLPSRCRDYN;
|
|
output TRNRECRCERRN;
|
|
output TRNREOFN;
|
|
output TRNRERRFWDN;
|
|
output TRNRREMN;
|
|
output TRNRSOFN;
|
|
output TRNRSRCDSCN;
|
|
output TRNRSRCRDYN;
|
|
output TRNTCFGREQN;
|
|
output TRNTDLLPDSTRDYN;
|
|
output TRNTDSTRDYN;
|
|
output TRNTERRDROPN;
|
|
output USERRSTN;
|
|
output [11:0] DBGVECC;
|
|
output [11:0] PLDBGVEC;
|
|
output [11:0] TRNFCCPLD;
|
|
output [11:0] TRNFCNPD;
|
|
output [11:0] TRNFCPD;
|
|
output [12:0] MIMRXRADDR;
|
|
output [12:0] MIMRXWADDR;
|
|
output [12:0] MIMTXRADDR;
|
|
output [12:0] MIMTXWADDR;
|
|
output [15:0] CFGMSGDATA;
|
|
output [15:0] DRPDO;
|
|
output [15:0] PIPETX0DATA;
|
|
output [15:0] PIPETX1DATA;
|
|
output [15:0] PIPETX2DATA;
|
|
output [15:0] PIPETX3DATA;
|
|
output [15:0] PIPETX4DATA;
|
|
output [15:0] PIPETX5DATA;
|
|
output [15:0] PIPETX6DATA;
|
|
output [15:0] PIPETX7DATA;
|
|
output [1:0] CFGLINKCONTROLASPMCONTROL;
|
|
output [1:0] CFGLINKSTATUSCURRENTSPEED;
|
|
output [1:0] CFGPMCSRPOWERSTATE;
|
|
output [1:0] PIPETX0CHARISK;
|
|
output [1:0] PIPETX0POWERDOWN;
|
|
output [1:0] PIPETX1CHARISK;
|
|
output [1:0] PIPETX1POWERDOWN;
|
|
output [1:0] PIPETX2CHARISK;
|
|
output [1:0] PIPETX2POWERDOWN;
|
|
output [1:0] PIPETX3CHARISK;
|
|
output [1:0] PIPETX3POWERDOWN;
|
|
output [1:0] PIPETX4CHARISK;
|
|
output [1:0] PIPETX4POWERDOWN;
|
|
output [1:0] PIPETX5CHARISK;
|
|
output [1:0] PIPETX5POWERDOWN;
|
|
output [1:0] PIPETX6CHARISK;
|
|
output [1:0] PIPETX6POWERDOWN;
|
|
output [1:0] PIPETX7CHARISK;
|
|
output [1:0] PIPETX7POWERDOWN;
|
|
output [1:0] PLLANEREVERSALMODE;
|
|
output [1:0] PLRXPMSTATE;
|
|
output [1:0] PLSELLNKWIDTH;
|
|
output [2:0] CFGDEVCONTROLMAXPAYLOAD;
|
|
output [2:0] CFGDEVCONTROLMAXREADREQ;
|
|
output [2:0] CFGINTERRUPTMMENABLE;
|
|
output [2:0] CFGPCIELINKSTATE;
|
|
output [2:0] PIPETXMARGIN;
|
|
output [2:0] PLINITIALLINKWIDTH;
|
|
output [2:0] PLTXPMSTATE;
|
|
output [31:0] CFGDO;
|
|
output [31:0] TRNRDLLPDATA;
|
|
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL;
|
|
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH;
|
|
output [5:0] PLLTSSMSTATE;
|
|
output [5:0] TRNTBUFAV;
|
|
output [63:0] DBGVECA;
|
|
output [63:0] DBGVECB;
|
|
output [63:0] TRNRD;
|
|
output [67:0] MIMRXWDATA;
|
|
output [68:0] MIMTXWDATA;
|
|
output [6:0] CFGTRANSACTIONADDR;
|
|
output [6:0] CFGVCTCVCMAP;
|
|
output [6:0] TRNRBARHITN;
|
|
output [7:0] CFGINTERRUPTDO;
|
|
output [7:0] TRNFCCPLH;
|
|
output [7:0] TRNFCNPH;
|
|
output [7:0] TRNFCPH;
|
|
input CFGERRACSN;
|
|
input CFGERRCORN;
|
|
input CFGERRCPLABORTN;
|
|
input CFGERRCPLTIMEOUTN;
|
|
input CFGERRCPLUNEXPECTN;
|
|
input CFGERRECRCN;
|
|
input CFGERRLOCKEDN;
|
|
input CFGERRPOSTEDN;
|
|
input CFGERRURN;
|
|
input CFGINTERRUPTASSERTN;
|
|
input CFGINTERRUPTN;
|
|
input CFGPMDIRECTASPML1N;
|
|
input CFGPMSENDPMACKN;
|
|
input CFGPMSENDPMETON;
|
|
input CFGPMSENDPMNAKN;
|
|
input CFGPMTURNOFFOKN;
|
|
input CFGPMWAKEN;
|
|
input CFGRDENN;
|
|
input CFGTRNPENDINGN;
|
|
input CFGWRENN;
|
|
input CFGWRREADONLYN;
|
|
input CFGWRRW1CASRWN;
|
|
input CMRSTN;
|
|
input CMSTICKYRSTN;
|
|
input DBGSUBMODE;
|
|
input DLRSTN;
|
|
input DRPCLK;
|
|
input DRPDEN;
|
|
input DRPDWE;
|
|
input FUNCLVLRSTN;
|
|
input LL2SENDASREQL1N;
|
|
input LL2SENDENTERL1N;
|
|
input LL2SENDENTERL23N;
|
|
input LL2SUSPENDNOWN;
|
|
input LL2TLPRCVN;
|
|
input PIPECLK;
|
|
input PIPERX0CHANISALIGNED;
|
|
input PIPERX0ELECIDLE;
|
|
input PIPERX0PHYSTATUS;
|
|
input PIPERX0VALID;
|
|
input PIPERX1CHANISALIGNED;
|
|
input PIPERX1ELECIDLE;
|
|
input PIPERX1PHYSTATUS;
|
|
input PIPERX1VALID;
|
|
input PIPERX2CHANISALIGNED;
|
|
input PIPERX2ELECIDLE;
|
|
input PIPERX2PHYSTATUS;
|
|
input PIPERX2VALID;
|
|
input PIPERX3CHANISALIGNED;
|
|
input PIPERX3ELECIDLE;
|
|
input PIPERX3PHYSTATUS;
|
|
input PIPERX3VALID;
|
|
input PIPERX4CHANISALIGNED;
|
|
input PIPERX4ELECIDLE;
|
|
input PIPERX4PHYSTATUS;
|
|
input PIPERX4VALID;
|
|
input PIPERX5CHANISALIGNED;
|
|
input PIPERX5ELECIDLE;
|
|
input PIPERX5PHYSTATUS;
|
|
input PIPERX5VALID;
|
|
input PIPERX6CHANISALIGNED;
|
|
input PIPERX6ELECIDLE;
|
|
input PIPERX6PHYSTATUS;
|
|
input PIPERX6VALID;
|
|
input PIPERX7CHANISALIGNED;
|
|
input PIPERX7ELECIDLE;
|
|
input PIPERX7PHYSTATUS;
|
|
input PIPERX7VALID;
|
|
input PLDIRECTEDLINKAUTON;
|
|
input PLDIRECTEDLINKSPEED;
|
|
input PLDOWNSTREAMDEEMPHSOURCE;
|
|
input PLRSTN;
|
|
input PLTRANSMITHOTRST;
|
|
input PLUPSTREAMPREFERDEEMPH;
|
|
input SYSRSTN;
|
|
input TL2ASPMSUSPENDCREDITCHECKN;
|
|
input TL2PPMSUSPENDREQN;
|
|
input TLRSTN;
|
|
input TRNRDSTRDYN;
|
|
input TRNRNPOKN;
|
|
input TRNTCFGGNTN;
|
|
input TRNTDLLPSRCRDYN;
|
|
input TRNTECRCGENN;
|
|
input TRNTEOFN;
|
|
input TRNTERRFWDN;
|
|
input TRNTREMN;
|
|
input TRNTSOFN;
|
|
input TRNTSRCDSCN;
|
|
input TRNTSRCRDYN;
|
|
input TRNTSTRN;
|
|
input USERCLK;
|
|
input [127:0] CFGERRAERHEADERLOG;
|
|
input [15:0] DRPDI;
|
|
input [15:0] PIPERX0DATA;
|
|
input [15:0] PIPERX1DATA;
|
|
input [15:0] PIPERX2DATA;
|
|
input [15:0] PIPERX3DATA;
|
|
input [15:0] PIPERX4DATA;
|
|
input [15:0] PIPERX5DATA;
|
|
input [15:0] PIPERX6DATA;
|
|
input [15:0] PIPERX7DATA;
|
|
input [1:0] DBGMODE;
|
|
input [1:0] PIPERX0CHARISK;
|
|
input [1:0] PIPERX1CHARISK;
|
|
input [1:0] PIPERX2CHARISK;
|
|
input [1:0] PIPERX3CHARISK;
|
|
input [1:0] PIPERX4CHARISK;
|
|
input [1:0] PIPERX5CHARISK;
|
|
input [1:0] PIPERX6CHARISK;
|
|
input [1:0] PIPERX7CHARISK;
|
|
input [1:0] PLDIRECTEDLINKCHANGE;
|
|
input [1:0] PLDIRECTEDLINKWIDTH;
|
|
input [2:0] CFGDSFUNCTIONNUMBER;
|
|
input [2:0] PIPERX0STATUS;
|
|
input [2:0] PIPERX1STATUS;
|
|
input [2:0] PIPERX2STATUS;
|
|
input [2:0] PIPERX3STATUS;
|
|
input [2:0] PIPERX4STATUS;
|
|
input [2:0] PIPERX5STATUS;
|
|
input [2:0] PIPERX6STATUS;
|
|
input [2:0] PIPERX7STATUS;
|
|
input [2:0] PLDBGMODE;
|
|
input [2:0] TRNFCSEL;
|
|
input [31:0] CFGDI;
|
|
input [31:0] TRNTDLLPDATA;
|
|
input [3:0] CFGBYTEENN;
|
|
input [47:0] CFGERRTLPCPLHEADER;
|
|
input [4:0] CFGDSDEVICENUMBER;
|
|
input [4:0] PL2DIRECTEDLSTATE;
|
|
input [63:0] CFGDSN;
|
|
input [63:0] TRNTD;
|
|
input [67:0] MIMRXRDATA;
|
|
input [68:0] MIMTXRDATA;
|
|
input [7:0] CFGDSBUSNUMBER;
|
|
input [7:0] CFGINTERRUPTDI;
|
|
input [7:0] CFGPORTNUMBER;
|
|
input [8:0] DRPDADDR;
|
|
input [9:0] CFGDWADDR;
|
|
endmodule
|
|
|
|
module PCIE_2_1(CFGAERECRCCHECKEN, CFGAERECRCGENEN, CFGAERROOTERRCORRERRRECEIVED, CFGAERROOTERRCORRERRREPORTINGEN, CFGAERROOTERRFATALERRRECEIVED, CFGAERROOTERRFATALERRREPORTINGEN, CFGAERROOTERRNONFATALERRRECEIVED, CFGAERROOTERRNONFATALERRREPORTINGEN, CFGBRIDGESERREN, CFGCOMMANDBUSMASTERENABLE, CFGCOMMANDINTERRUPTDISABLE, CFGCOMMANDIOENABLE, CFGCOMMANDMEMENABLE, CFGCOMMANDSERREN, CFGDEVCONTROL2ARIFORWARDEN, CFGDEVCONTROL2ATOMICEGRESSBLOCK, CFGDEVCONTROL2ATOMICREQUESTEREN, CFGDEVCONTROL2CPLTIMEOUTDIS, CFGDEVCONTROL2IDOCPLEN, CFGDEVCONTROL2IDOREQEN, CFGDEVCONTROL2LTREN
|
|
, CFGDEVCONTROL2TLPPREFIXBLOCK, CFGDEVCONTROLAUXPOWEREN, CFGDEVCONTROLCORRERRREPORTINGEN, CFGDEVCONTROLENABLERO, CFGDEVCONTROLEXTTAGEN, CFGDEVCONTROLFATALERRREPORTINGEN, CFGDEVCONTROLNONFATALREPORTINGEN, CFGDEVCONTROLNOSNOOPEN, CFGDEVCONTROLPHANTOMEN, CFGDEVCONTROLURERRREPORTINGEN, CFGDEVSTATUSCORRERRDETECTED, CFGDEVSTATUSFATALERRDETECTED, CFGDEVSTATUSNONFATALERRDETECTED, CFGDEVSTATUSURDETECTED, CFGERRAERHEADERLOGSETN, CFGERRCPLRDYN, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXFM, CFGINTERRUPTRDYN, CFGLINKCONTROLAUTOBANDWIDTHINTEN
|
|
, CFGLINKCONTROLBANDWIDTHINTEN, CFGLINKCONTROLCLOCKPMEN, CFGLINKCONTROLCOMMONCLOCK, CFGLINKCONTROLEXTENDEDSYNC, CFGLINKCONTROLHWAUTOWIDTHDIS, CFGLINKCONTROLLINKDISABLE, CFGLINKCONTROLRCB, CFGLINKCONTROLRETRAINLINK, CFGLINKSTATUSAUTOBANDWIDTHSTATUS, CFGLINKSTATUSBANDWIDTHSTATUS, CFGLINKSTATUSDLLACTIVE, CFGLINKSTATUSLINKTRAINING, CFGMGMTRDWRDONEN, CFGMSGRECEIVED, CFGMSGRECEIVEDASSERTINTA, CFGMSGRECEIVEDASSERTINTB, CFGMSGRECEIVEDASSERTINTC, CFGMSGRECEIVEDASSERTINTD, CFGMSGRECEIVEDDEASSERTINTA, CFGMSGRECEIVEDDEASSERTINTB, CFGMSGRECEIVEDDEASSERTINTC
|
|
, CFGMSGRECEIVEDDEASSERTINTD, CFGMSGRECEIVEDERRCOR, CFGMSGRECEIVEDERRFATAL, CFGMSGRECEIVEDERRNONFATAL, CFGMSGRECEIVEDPMASNAK, CFGMSGRECEIVEDPMETO, CFGMSGRECEIVEDPMETOACK, CFGMSGRECEIVEDPMPME, CFGMSGRECEIVEDSETSLOTPOWERLIMIT, CFGMSGRECEIVEDUNLOCK, CFGPMCSRPMEEN, CFGPMCSRPMESTATUS, CFGPMRCVASREQL1N, CFGPMRCVENTERL1N, CFGPMRCVENTERL23N, CFGPMRCVREQACKN, CFGROOTCONTROLPMEINTEN, CFGROOTCONTROLSYSERRCORRERREN, CFGROOTCONTROLSYSERRFATALERREN, CFGROOTCONTROLSYSERRNONFATALERREN, CFGSLOTCONTROLELECTROMECHILCTLPULSE
|
|
, CFGTRANSACTION, CFGTRANSACTIONTYPE, DBGSCLRA, DBGSCLRB, DBGSCLRC, DBGSCLRD, DBGSCLRE, DBGSCLRF, DBGSCLRG, DBGSCLRH, DBGSCLRI, DBGSCLRJ, DBGSCLRK, DRPRDY, LL2BADDLLPERR, LL2BADTLPERR, LL2PROTOCOLERR, LL2RECEIVERERR, LL2REPLAYROERR, LL2REPLAYTOERR, LL2SUSPENDOK
|
|
, LL2TFCINIT1SEQ, LL2TFCINIT2SEQ, LL2TXIDLE, LNKCLKEN, MIMRXREN, MIMRXWEN, MIMTXREN, MIMTXWEN, PIPERX0POLARITY, PIPERX1POLARITY, PIPERX2POLARITY, PIPERX3POLARITY, PIPERX4POLARITY, PIPERX5POLARITY, PIPERX6POLARITY, PIPERX7POLARITY, PIPETX0COMPLIANCE, PIPETX0ELECIDLE, PIPETX1COMPLIANCE, PIPETX1ELECIDLE, PIPETX2COMPLIANCE
|
|
, PIPETX2ELECIDLE, PIPETX3COMPLIANCE, PIPETX3ELECIDLE, PIPETX4COMPLIANCE, PIPETX4ELECIDLE, PIPETX5COMPLIANCE, PIPETX5ELECIDLE, PIPETX6COMPLIANCE, PIPETX6ELECIDLE, PIPETX7COMPLIANCE, PIPETX7ELECIDLE, PIPETXDEEMPH, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PL2L0REQ, PL2LINKUP, PL2RECEIVERERR, PL2RECOVERY, PL2RXELECIDLE, PL2SUSPENDOK
|
|
, PLDIRECTEDCHANGEDONE, PLLINKGEN2CAP, PLLINKPARTNERGEN2SUPPORTED, PLLINKUPCFGCAP, PLPHYLNKUPN, PLRECEIVEDHOTRST, PLSELLNKRATE, RECEIVEDFUNCLVLRSTN, TL2ASPMSUSPENDCREDITCHECKOK, TL2ASPMSUSPENDREQ, TL2ERRFCPE, TL2ERRMALFORMED, TL2ERRRXOVERFLOW, TL2PPMSUSPENDOK, TRNLNKUP, TRNRECRCERR, TRNREOF, TRNRERRFWD, TRNRSOF, TRNRSRCDSC, TRNRSRCRDY
|
|
, TRNTCFGREQ, TRNTDLLPDSTRDY, TRNTERRDROP, USERRSTN, DBGVECC, PLDBGVEC, TRNFCCPLD, TRNFCNPD, TRNFCPD, TRNRD, MIMRXRADDR, MIMRXWADDR, MIMTXRADDR, MIMTXWADDR, CFGMSGDATA, DRPDO, PIPETX0DATA, PIPETX1DATA, PIPETX2DATA, PIPETX3DATA, PIPETX4DATA
|
|
, PIPETX5DATA, PIPETX6DATA, PIPETX7DATA, CFGLINKCONTROLASPMCONTROL, CFGLINKSTATUSCURRENTSPEED, CFGPMCSRPOWERSTATE, PIPETX0CHARISK, PIPETX0POWERDOWN, PIPETX1CHARISK, PIPETX1POWERDOWN, PIPETX2CHARISK, PIPETX2POWERDOWN, PIPETX3CHARISK, PIPETX3POWERDOWN, PIPETX4CHARISK, PIPETX4POWERDOWN, PIPETX5CHARISK, PIPETX5POWERDOWN, PIPETX6CHARISK, PIPETX6POWERDOWN, PIPETX7CHARISK
|
|
, PIPETX7POWERDOWN, PL2RXPMSTATE, PLLANEREVERSALMODE, PLRXPMSTATE, PLSELLNKWIDTH, TRNRDLLPSRCRDY, TRNRREM, CFGDEVCONTROLMAXPAYLOAD, CFGDEVCONTROLMAXREADREQ, CFGINTERRUPTMMENABLE, CFGPCIELINKSTATE, PIPETXMARGIN, PLINITIALLINKWIDTH, PLTXPMSTATE, CFGMGMTDO, CFGDEVCONTROL2CPLTIMEOUTVAL, CFGLINKSTATUSNEGOTIATEDWIDTH, TRNTDSTRDY, LL2LINKSTATUS, PLLTSSMSTATE, TRNTBUFAV
|
|
, DBGVECA, DBGVECB, TL2ERRHDR, TRNRDLLPDATA, MIMRXWDATA, MIMTXWDATA, CFGTRANSACTIONADDR, CFGVCTCVCMAP, CFGINTERRUPTDO, TRNFCCPLH, TRNFCNPH, TRNFCPH, TRNRBARHIT, CFGERRACSN, CFGERRATOMICEGRESSBLOCKEDN, CFGERRCORN, CFGERRCPLABORTN, CFGERRCPLTIMEOUTN, CFGERRCPLUNEXPECTN, CFGERRECRCN, CFGERRINTERNALCORN
|
|
, CFGERRINTERNALUNCORN, CFGERRLOCKEDN, CFGERRMALFORMEDN, CFGERRMCBLOCKEDN, CFGERRNORECOVERYN, CFGERRPOISONEDN, CFGERRPOSTEDN, CFGERRURN, CFGFORCECOMMONCLOCKOFF, CFGFORCEEXTENDEDSYNCON, CFGINTERRUPTASSERTN, CFGINTERRUPTN, CFGINTERRUPTSTATN, CFGMGMTRDENN, CFGMGMTWRENN, CFGMGMTWRREADONLYN, CFGMGMTWRRW1CASRWN, CFGPMFORCESTATEENN, CFGPMHALTASPML0SN, CFGPMHALTASPML1N, CFGPMSENDPMETON
|
|
, CFGPMTURNOFFOKN, CFGPMWAKEN, CFGTRNPENDINGN, CMRSTN, CMSTICKYRSTN, DBGSUBMODE, DLRSTN, DRPCLK, DRPEN, DRPWE, FUNCLVLRSTN, LL2SENDASREQL1, LL2SENDENTERL1, LL2SENDENTERL23, LL2SENDPMACK, LL2SUSPENDNOW, LL2TLPRCV, PIPECLK, PIPERX0CHANISALIGNED, PIPERX0ELECIDLE, PIPERX0PHYSTATUS
|
|
, PIPERX0VALID, PIPERX1CHANISALIGNED, PIPERX1ELECIDLE, PIPERX1PHYSTATUS, PIPERX1VALID, PIPERX2CHANISALIGNED, PIPERX2ELECIDLE, PIPERX2PHYSTATUS, PIPERX2VALID, PIPERX3CHANISALIGNED, PIPERX3ELECIDLE, PIPERX3PHYSTATUS, PIPERX3VALID, PIPERX4CHANISALIGNED, PIPERX4ELECIDLE, PIPERX4PHYSTATUS, PIPERX4VALID, PIPERX5CHANISALIGNED, PIPERX5ELECIDLE, PIPERX5PHYSTATUS, PIPERX5VALID
|
|
, PIPERX6CHANISALIGNED, PIPERX6ELECIDLE, PIPERX6PHYSTATUS, PIPERX6VALID, PIPERX7CHANISALIGNED, PIPERX7ELECIDLE, PIPERX7PHYSTATUS, PIPERX7VALID, PLDIRECTEDLINKAUTON, PLDIRECTEDLINKSPEED, PLDIRECTEDLTSSMNEWVLD, PLDIRECTEDLTSSMSTALL, PLDOWNSTREAMDEEMPHSOURCE, PLRSTN, PLTRANSMITHOTRST, PLUPSTREAMPREFERDEEMPH, SYSRSTN, TL2ASPMSUSPENDCREDITCHECK, TL2PPMSUSPENDREQ, TLRSTN, TRNRDSTRDY
|
|
, TRNRFCPRET, TRNRNPOK, TRNRNPREQ, TRNTCFGGNT, TRNTDLLPSRCRDY, TRNTECRCGEN, TRNTEOF, TRNTERRFWD, TRNTSOF, TRNTSRCDSC, TRNTSRCRDY, TRNTSTR, USERCLK2, USERCLK, CFGERRAERHEADERLOG, TRNTD, CFGDEVID, CFGSUBSYSID, CFGSUBSYSVENDID, CFGVENDID, DRPDI
|
|
, PIPERX0DATA, PIPERX1DATA, PIPERX2DATA, PIPERX3DATA, PIPERX4DATA, PIPERX5DATA, PIPERX6DATA, PIPERX7DATA, CFGPMFORCESTATE, DBGMODE, PIPERX0CHARISK, PIPERX1CHARISK, PIPERX2CHARISK, PIPERX3CHARISK, PIPERX4CHARISK, PIPERX5CHARISK, PIPERX6CHARISK, PIPERX7CHARISK, PLDIRECTEDLINKCHANGE, PLDIRECTEDLINKWIDTH, TRNTREM
|
|
, CFGDSFUNCTIONNUMBER, CFGFORCEMPS, PIPERX0STATUS, PIPERX1STATUS, PIPERX2STATUS, PIPERX3STATUS, PIPERX4STATUS, PIPERX5STATUS, PIPERX6STATUS, PIPERX7STATUS, PLDBGMODE, TRNFCSEL, CFGMGMTDI, TRNTDLLPDATA, CFGMGMTBYTEENN, CFGERRTLPCPLHEADER, CFGAERINTERRUPTMSGNUM, CFGDSDEVICENUMBER, CFGPCIECAPINTERRUPTMSGNUM, PL2DIRECTEDLSTATE, PLDIRECTEDLTSSMNEW
|
|
, CFGDSN, MIMRXRDATA, MIMTXRDATA, CFGDSBUSNUMBER, CFGINTERRUPTDI, CFGPORTNUMBER, CFGREVID, DRPADDR, CFGMGMTDWADDR);
|
|
parameter [11:0] AER_BASE_PTR = 12'h140;
|
|
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
|
|
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
|
|
parameter [15:0] AER_CAP_ID = 16'h0001;
|
|
parameter AER_CAP_MULTIHEADER = "FALSE";
|
|
parameter [11:0] AER_CAP_NEXTPTR = 12'h178;
|
|
parameter AER_CAP_ON = "FALSE";
|
|
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000;
|
|
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE";
|
|
parameter [3:0] AER_CAP_VERSION = 4'h2;
|
|
parameter ALLOW_X8_GEN2 = "FALSE";
|
|
parameter [31:0] BAR0 = 32'hFFFFFF00;
|
|
parameter [31:0] BAR1 = 32'hFFFF0000;
|
|
parameter [31:0] BAR2 = 32'hFFFF000C;
|
|
parameter [31:0] BAR3 = 32'hFFFFFFFF;
|
|
parameter [31:0] BAR4 = 32'h00000000;
|
|
parameter [31:0] BAR5 = 32'h00000000;
|
|
parameter [7:0] CAPABILITIES_PTR = 8'h40;
|
|
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000;
|
|
parameter integer CFG_ECRC_ERR_CPLSTAT = 0;
|
|
parameter [23:0] CLASS_CODE = 24'h000000;
|
|
parameter CMD_INTX_IMPLEMENTED = "TRUE";
|
|
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE";
|
|
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0;
|
|
parameter [6:0] CRM_MODULE_RSTS = 7'h00;
|
|
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE";
|
|
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE";
|
|
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE";
|
|
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE";
|
|
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE";
|
|
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE";
|
|
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE";
|
|
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE";
|
|
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0;
|
|
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE";
|
|
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0;
|
|
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE";
|
|
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE";
|
|
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
|
|
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0;
|
|
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
|
|
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE";
|
|
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2;
|
|
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0;
|
|
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE";
|
|
parameter integer DEV_CAP_RSVD_14_12 = 0;
|
|
parameter integer DEV_CAP_RSVD_17_16 = 0;
|
|
parameter integer DEV_CAP_RSVD_31_29 = 0;
|
|
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE";
|
|
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE";
|
|
parameter DISABLE_ASPM_L1_TIMER = "FALSE";
|
|
parameter DISABLE_BAR_FILTERING = "FALSE";
|
|
parameter DISABLE_ERR_MSG = "FALSE";
|
|
parameter DISABLE_ID_CHECK = "FALSE";
|
|
parameter DISABLE_LANE_REVERSAL = "FALSE";
|
|
parameter DISABLE_LOCKED_FILTER = "FALSE";
|
|
parameter DISABLE_PPM_FILTER = "FALSE";
|
|
parameter DISABLE_RX_POISONED_RESP = "FALSE";
|
|
parameter DISABLE_RX_TC_FILTER = "FALSE";
|
|
parameter DISABLE_SCRAMBLING = "FALSE";
|
|
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
|
|
parameter [11:0] DSN_BASE_PTR = 12'h100;
|
|
parameter [15:0] DSN_CAP_ID = 16'h0003;
|
|
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter DSN_CAP_ON = "TRUE";
|
|
parameter [3:0] DSN_CAP_VERSION = 4'h1;
|
|
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000;
|
|
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
|
|
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE";
|
|
parameter ENTER_RVRY_EI_L0 = "TRUE";
|
|
parameter EXIT_LOOPBACK_ON_EI = "TRUE";
|
|
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001;
|
|
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F;
|
|
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF;
|
|
parameter [7:0] HEADER_TYPE = 8'h00;
|
|
parameter [4:0] INFER_EI = 5'h00;
|
|
parameter [7:0] INTERRUPT_PIN = 8'h01;
|
|
parameter INTERRUPT_STAT_AUTO = "TRUE";
|
|
parameter IS_SWITCH = "FALSE";
|
|
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF;
|
|
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE";
|
|
parameter integer LINK_CAP_ASPM_SUPPORT = 1;
|
|
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE";
|
|
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE";
|
|
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
|
|
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE";
|
|
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1;
|
|
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08;
|
|
parameter integer LINK_CAP_RSVD_23 = 0;
|
|
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE";
|
|
parameter integer LINK_CONTROL_RCB = 0;
|
|
parameter LINK_CTRL2_DEEMPHASIS = "FALSE";
|
|
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE";
|
|
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2;
|
|
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
|
|
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000;
|
|
parameter LL_ACK_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
|
|
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000;
|
|
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
|
|
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01;
|
|
parameter MPS_FORCE = "FALSE";
|
|
parameter [7:0] MSIX_BASE_PTR = 8'h9C;
|
|
parameter [7:0] MSIX_CAP_ID = 8'h11;
|
|
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter MSIX_CAP_ON = "FALSE";
|
|
parameter integer MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] MSI_BASE_PTR = 8'h48;
|
|
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE";
|
|
parameter [7:0] MSI_CAP_ID = 8'h05;
|
|
parameter integer MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0;
|
|
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60;
|
|
parameter MSI_CAP_ON = "FALSE";
|
|
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE";
|
|
parameter integer N_FTS_COMCLK_GEN1 = 255;
|
|
parameter integer N_FTS_COMCLK_GEN2 = 255;
|
|
parameter integer N_FTS_GEN1 = 255;
|
|
parameter integer N_FTS_GEN2 = 255;
|
|
parameter [7:0] PCIE_BASE_PTR = 8'h60;
|
|
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10;
|
|
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2;
|
|
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0;
|
|
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C;
|
|
parameter PCIE_CAP_ON = "TRUE";
|
|
parameter integer PCIE_CAP_RSVD_15_14 = 0;
|
|
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
|
|
parameter integer PCIE_REVISION = 2;
|
|
parameter integer PL_AUTO_CONFIG = 0;
|
|
parameter PL_FAST_TRAIN = "FALSE";
|
|
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000;
|
|
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE";
|
|
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0;
|
|
parameter PM_ASPM_FASTEXIT = "FALSE";
|
|
parameter [7:0] PM_BASE_PTR = 8'h40;
|
|
parameter integer PM_CAP_AUXCURRENT = 0;
|
|
parameter PM_CAP_D1SUPPORT = "TRUE";
|
|
parameter PM_CAP_D2SUPPORT = "TRUE";
|
|
parameter PM_CAP_DSI = "FALSE";
|
|
parameter [7:0] PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PM_CAP_NEXTPTR = 8'h48;
|
|
parameter PM_CAP_ON = "TRUE";
|
|
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F;
|
|
parameter PM_CAP_PME_CLOCK = "FALSE";
|
|
parameter integer PM_CAP_RSVD_04 = 0;
|
|
parameter integer PM_CAP_VERSION = 3;
|
|
parameter PM_CSR_B2B3 = "FALSE";
|
|
parameter PM_CSR_BPCCEN = "FALSE";
|
|
parameter PM_CSR_NOSOFTRST = "TRUE";
|
|
parameter [7:0] PM_DATA0 = 8'h01;
|
|
parameter [7:0] PM_DATA1 = 8'h01;
|
|
parameter [7:0] PM_DATA2 = 8'h01;
|
|
parameter [7:0] PM_DATA3 = 8'h01;
|
|
parameter [7:0] PM_DATA4 = 8'h01;
|
|
parameter [7:0] PM_DATA5 = 8'h01;
|
|
parameter [7:0] PM_DATA6 = 8'h01;
|
|
parameter [7:0] PM_DATA7 = 8'h01;
|
|
parameter [1:0] PM_DATA_SCALE0 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE1 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE2 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE3 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE4 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE5 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE6 = 2'h1;
|
|
parameter [1:0] PM_DATA_SCALE7 = 2'h1;
|
|
parameter PM_MF = "FALSE";
|
|
parameter [11:0] RBAR_BASE_PTR = 12'h178;
|
|
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00;
|
|
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00;
|
|
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00;
|
|
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00;
|
|
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00;
|
|
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00;
|
|
parameter [15:0] RBAR_CAP_ID = 16'h0015;
|
|
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0;
|
|
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0;
|
|
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0;
|
|
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0;
|
|
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0;
|
|
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0;
|
|
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000;
|
|
parameter RBAR_CAP_ON = "FALSE";
|
|
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000;
|
|
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000;
|
|
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000;
|
|
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000;
|
|
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000;
|
|
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000;
|
|
parameter [3:0] RBAR_CAP_VERSION = 4'h1;
|
|
parameter [2:0] RBAR_NUM = 3'h1;
|
|
parameter integer RECRC_CHK = 0;
|
|
parameter RECRC_CHK_TRIM = "FALSE";
|
|
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE";
|
|
parameter [1:0] RP_AUTO_SPD = 2'h1;
|
|
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F;
|
|
parameter SELECT_DLL_IF = "FALSE";
|
|
parameter SIM_VERSION = "1.0";
|
|
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE";
|
|
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE";
|
|
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE";
|
|
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000;
|
|
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE";
|
|
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
|
|
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0;
|
|
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00;
|
|
parameter integer SPARE_BIT0 = 0;
|
|
parameter integer SPARE_BIT1 = 0;
|
|
parameter integer SPARE_BIT2 = 0;
|
|
parameter integer SPARE_BIT3 = 0;
|
|
parameter integer SPARE_BIT4 = 0;
|
|
parameter integer SPARE_BIT5 = 0;
|
|
parameter integer SPARE_BIT6 = 0;
|
|
parameter integer SPARE_BIT7 = 0;
|
|
parameter integer SPARE_BIT8 = 0;
|
|
parameter [7:0] SPARE_BYTE0 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE1 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE2 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE3 = 8'h00;
|
|
parameter [31:0] SPARE_WORD0 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD1 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD2 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD3 = 32'h00000000;
|
|
parameter SSL_MESSAGE_AUTO = "FALSE";
|
|
parameter TECRC_EP_INV = "FALSE";
|
|
parameter TL_RBYPASS = "FALSE";
|
|
parameter integer TL_RX_RAM_RADDR_LATENCY = 0;
|
|
parameter integer TL_RX_RAM_RDATA_LATENCY = 2;
|
|
parameter integer TL_RX_RAM_WRITE_LATENCY = 0;
|
|
parameter TL_TFC_DISABLE = "FALSE";
|
|
parameter TL_TX_CHECKS_DISABLE = "FALSE";
|
|
parameter integer TL_TX_RAM_RADDR_LATENCY = 0;
|
|
parameter integer TL_TX_RAM_RDATA_LATENCY = 2;
|
|
parameter integer TL_TX_RAM_WRITE_LATENCY = 0;
|
|
parameter TRN_DW = "FALSE";
|
|
parameter TRN_NP_FC = "FALSE";
|
|
parameter UPCONFIG_CAPABLE = "TRUE";
|
|
parameter UPSTREAM_FACING = "TRUE";
|
|
parameter UR_ATOMIC = "TRUE";
|
|
parameter UR_CFG1 = "TRUE";
|
|
parameter UR_INV_REQ = "TRUE";
|
|
parameter UR_PRS_RESPONSE = "TRUE";
|
|
parameter USER_CLK2_DIV2 = "FALSE";
|
|
parameter integer USER_CLK_FREQ = 3;
|
|
parameter USE_RID_PINS = "FALSE";
|
|
parameter VC0_CPL_INFINITE = "TRUE";
|
|
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF;
|
|
parameter integer VC0_TOTAL_CREDITS_CD = 127;
|
|
parameter integer VC0_TOTAL_CREDITS_CH = 31;
|
|
parameter integer VC0_TOTAL_CREDITS_NPD = 24;
|
|
parameter integer VC0_TOTAL_CREDITS_NPH = 12;
|
|
parameter integer VC0_TOTAL_CREDITS_PD = 288;
|
|
parameter integer VC0_TOTAL_CREDITS_PH = 32;
|
|
parameter integer VC0_TX_LASTPACKET = 31;
|
|
parameter [11:0] VC_BASE_PTR = 12'h10C;
|
|
parameter [15:0] VC_CAP_ID = 16'h0002;
|
|
parameter [11:0] VC_CAP_NEXTPTR = 12'h000;
|
|
parameter VC_CAP_ON = "FALSE";
|
|
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE";
|
|
parameter [3:0] VC_CAP_VERSION = 4'h1;
|
|
parameter [11:0] VSEC_BASE_PTR = 12'h128;
|
|
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234;
|
|
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018;
|
|
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1;
|
|
parameter [15:0] VSEC_CAP_ID = 16'h000B;
|
|
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE";
|
|
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140;
|
|
parameter VSEC_CAP_ON = "FALSE";
|
|
parameter [3:0] VSEC_CAP_VERSION = 4'h1;
|
|
output CFGAERECRCCHECKEN;
|
|
output CFGAERECRCGENEN;
|
|
output CFGAERROOTERRCORRERRRECEIVED;
|
|
output CFGAERROOTERRCORRERRREPORTINGEN;
|
|
output CFGAERROOTERRFATALERRRECEIVED;
|
|
output CFGAERROOTERRFATALERRREPORTINGEN;
|
|
output CFGAERROOTERRNONFATALERRRECEIVED;
|
|
output CFGAERROOTERRNONFATALERRREPORTINGEN;
|
|
output CFGBRIDGESERREN;
|
|
output CFGCOMMANDBUSMASTERENABLE;
|
|
output CFGCOMMANDINTERRUPTDISABLE;
|
|
output CFGCOMMANDIOENABLE;
|
|
output CFGCOMMANDMEMENABLE;
|
|
output CFGCOMMANDSERREN;
|
|
output CFGDEVCONTROL2ARIFORWARDEN;
|
|
output CFGDEVCONTROL2ATOMICEGRESSBLOCK;
|
|
output CFGDEVCONTROL2ATOMICREQUESTEREN;
|
|
output CFGDEVCONTROL2CPLTIMEOUTDIS;
|
|
output CFGDEVCONTROL2IDOCPLEN;
|
|
output CFGDEVCONTROL2IDOREQEN;
|
|
output CFGDEVCONTROL2LTREN;
|
|
output CFGDEVCONTROL2TLPPREFIXBLOCK;
|
|
output CFGDEVCONTROLAUXPOWEREN;
|
|
output CFGDEVCONTROLCORRERRREPORTINGEN;
|
|
output CFGDEVCONTROLENABLERO;
|
|
output CFGDEVCONTROLEXTTAGEN;
|
|
output CFGDEVCONTROLFATALERRREPORTINGEN;
|
|
output CFGDEVCONTROLNONFATALREPORTINGEN;
|
|
output CFGDEVCONTROLNOSNOOPEN;
|
|
output CFGDEVCONTROLPHANTOMEN;
|
|
output CFGDEVCONTROLURERRREPORTINGEN;
|
|
output CFGDEVSTATUSCORRERRDETECTED;
|
|
output CFGDEVSTATUSFATALERRDETECTED;
|
|
output CFGDEVSTATUSNONFATALERRDETECTED;
|
|
output CFGDEVSTATUSURDETECTED;
|
|
output CFGERRAERHEADERLOGSETN;
|
|
output CFGERRCPLRDYN;
|
|
output CFGINTERRUPTMSIENABLE;
|
|
output CFGINTERRUPTMSIXENABLE;
|
|
output CFGINTERRUPTMSIXFM;
|
|
output CFGINTERRUPTRDYN;
|
|
output CFGLINKCONTROLAUTOBANDWIDTHINTEN;
|
|
output CFGLINKCONTROLBANDWIDTHINTEN;
|
|
output CFGLINKCONTROLCLOCKPMEN;
|
|
output CFGLINKCONTROLCOMMONCLOCK;
|
|
output CFGLINKCONTROLEXTENDEDSYNC;
|
|
output CFGLINKCONTROLHWAUTOWIDTHDIS;
|
|
output CFGLINKCONTROLLINKDISABLE;
|
|
output CFGLINKCONTROLRCB;
|
|
output CFGLINKCONTROLRETRAINLINK;
|
|
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
|
|
output CFGLINKSTATUSBANDWIDTHSTATUS;
|
|
output CFGLINKSTATUSDLLACTIVE;
|
|
output CFGLINKSTATUSLINKTRAINING;
|
|
output CFGMGMTRDWRDONEN;
|
|
output CFGMSGRECEIVED;
|
|
output CFGMSGRECEIVEDASSERTINTA;
|
|
output CFGMSGRECEIVEDASSERTINTB;
|
|
output CFGMSGRECEIVEDASSERTINTC;
|
|
output CFGMSGRECEIVEDASSERTINTD;
|
|
output CFGMSGRECEIVEDDEASSERTINTA;
|
|
output CFGMSGRECEIVEDDEASSERTINTB;
|
|
output CFGMSGRECEIVEDDEASSERTINTC;
|
|
output CFGMSGRECEIVEDDEASSERTINTD;
|
|
output CFGMSGRECEIVEDERRCOR;
|
|
output CFGMSGRECEIVEDERRFATAL;
|
|
output CFGMSGRECEIVEDERRNONFATAL;
|
|
output CFGMSGRECEIVEDPMASNAK;
|
|
output CFGMSGRECEIVEDPMETO;
|
|
output CFGMSGRECEIVEDPMETOACK;
|
|
output CFGMSGRECEIVEDPMPME;
|
|
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
|
|
output CFGMSGRECEIVEDUNLOCK;
|
|
output CFGPMCSRPMEEN;
|
|
output CFGPMCSRPMESTATUS;
|
|
output CFGPMRCVASREQL1N;
|
|
output CFGPMRCVENTERL1N;
|
|
output CFGPMRCVENTERL23N;
|
|
output CFGPMRCVREQACKN;
|
|
output CFGROOTCONTROLPMEINTEN;
|
|
output CFGROOTCONTROLSYSERRCORRERREN;
|
|
output CFGROOTCONTROLSYSERRFATALERREN;
|
|
output CFGROOTCONTROLSYSERRNONFATALERREN;
|
|
output CFGSLOTCONTROLELECTROMECHILCTLPULSE;
|
|
output CFGTRANSACTION;
|
|
output CFGTRANSACTIONTYPE;
|
|
output DBGSCLRA;
|
|
output DBGSCLRB;
|
|
output DBGSCLRC;
|
|
output DBGSCLRD;
|
|
output DBGSCLRE;
|
|
output DBGSCLRF;
|
|
output DBGSCLRG;
|
|
output DBGSCLRH;
|
|
output DBGSCLRI;
|
|
output DBGSCLRJ;
|
|
output DBGSCLRK;
|
|
output DRPRDY;
|
|
output LL2BADDLLPERR;
|
|
output LL2BADTLPERR;
|
|
output LL2PROTOCOLERR;
|
|
output LL2RECEIVERERR;
|
|
output LL2REPLAYROERR;
|
|
output LL2REPLAYTOERR;
|
|
output LL2SUSPENDOK;
|
|
output LL2TFCINIT1SEQ;
|
|
output LL2TFCINIT2SEQ;
|
|
output LL2TXIDLE;
|
|
output LNKCLKEN;
|
|
output MIMRXREN;
|
|
output MIMRXWEN;
|
|
output MIMTXREN;
|
|
output MIMTXWEN;
|
|
output PIPERX0POLARITY;
|
|
output PIPERX1POLARITY;
|
|
output PIPERX2POLARITY;
|
|
output PIPERX3POLARITY;
|
|
output PIPERX4POLARITY;
|
|
output PIPERX5POLARITY;
|
|
output PIPERX6POLARITY;
|
|
output PIPERX7POLARITY;
|
|
output PIPETX0COMPLIANCE;
|
|
output PIPETX0ELECIDLE;
|
|
output PIPETX1COMPLIANCE;
|
|
output PIPETX1ELECIDLE;
|
|
output PIPETX2COMPLIANCE;
|
|
output PIPETX2ELECIDLE;
|
|
output PIPETX3COMPLIANCE;
|
|
output PIPETX3ELECIDLE;
|
|
output PIPETX4COMPLIANCE;
|
|
output PIPETX4ELECIDLE;
|
|
output PIPETX5COMPLIANCE;
|
|
output PIPETX5ELECIDLE;
|
|
output PIPETX6COMPLIANCE;
|
|
output PIPETX6ELECIDLE;
|
|
output PIPETX7COMPLIANCE;
|
|
output PIPETX7ELECIDLE;
|
|
output PIPETXDEEMPH;
|
|
output PIPETXRATE;
|
|
output PIPETXRCVRDET;
|
|
output PIPETXRESET;
|
|
output PL2L0REQ;
|
|
output PL2LINKUP;
|
|
output PL2RECEIVERERR;
|
|
output PL2RECOVERY;
|
|
output PL2RXELECIDLE;
|
|
output PL2SUSPENDOK;
|
|
output PLDIRECTEDCHANGEDONE;
|
|
output PLLINKGEN2CAP;
|
|
output PLLINKPARTNERGEN2SUPPORTED;
|
|
output PLLINKUPCFGCAP;
|
|
output PLPHYLNKUPN;
|
|
output PLRECEIVEDHOTRST;
|
|
output PLSELLNKRATE;
|
|
output RECEIVEDFUNCLVLRSTN;
|
|
output TL2ASPMSUSPENDCREDITCHECKOK;
|
|
output TL2ASPMSUSPENDREQ;
|
|
output TL2ERRFCPE;
|
|
output TL2ERRMALFORMED;
|
|
output TL2ERRRXOVERFLOW;
|
|
output TL2PPMSUSPENDOK;
|
|
output TRNLNKUP;
|
|
output TRNRECRCERR;
|
|
output TRNREOF;
|
|
output TRNRERRFWD;
|
|
output TRNRSOF;
|
|
output TRNRSRCDSC;
|
|
output TRNRSRCRDY;
|
|
output TRNTCFGREQ;
|
|
output TRNTDLLPDSTRDY;
|
|
output TRNTERRDROP;
|
|
output USERRSTN;
|
|
output [11:0] DBGVECC;
|
|
output [11:0] PLDBGVEC;
|
|
output [11:0] TRNFCCPLD;
|
|
output [11:0] TRNFCNPD;
|
|
output [11:0] TRNFCPD;
|
|
output [127:0] TRNRD;
|
|
output [12:0] MIMRXRADDR;
|
|
output [12:0] MIMRXWADDR;
|
|
output [12:0] MIMTXRADDR;
|
|
output [12:0] MIMTXWADDR;
|
|
output [15:0] CFGMSGDATA;
|
|
output [15:0] DRPDO;
|
|
output [15:0] PIPETX0DATA;
|
|
output [15:0] PIPETX1DATA;
|
|
output [15:0] PIPETX2DATA;
|
|
output [15:0] PIPETX3DATA;
|
|
output [15:0] PIPETX4DATA;
|
|
output [15:0] PIPETX5DATA;
|
|
output [15:0] PIPETX6DATA;
|
|
output [15:0] PIPETX7DATA;
|
|
output [1:0] CFGLINKCONTROLASPMCONTROL;
|
|
output [1:0] CFGLINKSTATUSCURRENTSPEED;
|
|
output [1:0] CFGPMCSRPOWERSTATE;
|
|
output [1:0] PIPETX0CHARISK;
|
|
output [1:0] PIPETX0POWERDOWN;
|
|
output [1:0] PIPETX1CHARISK;
|
|
output [1:0] PIPETX1POWERDOWN;
|
|
output [1:0] PIPETX2CHARISK;
|
|
output [1:0] PIPETX2POWERDOWN;
|
|
output [1:0] PIPETX3CHARISK;
|
|
output [1:0] PIPETX3POWERDOWN;
|
|
output [1:0] PIPETX4CHARISK;
|
|
output [1:0] PIPETX4POWERDOWN;
|
|
output [1:0] PIPETX5CHARISK;
|
|
output [1:0] PIPETX5POWERDOWN;
|
|
output [1:0] PIPETX6CHARISK;
|
|
output [1:0] PIPETX6POWERDOWN;
|
|
output [1:0] PIPETX7CHARISK;
|
|
output [1:0] PIPETX7POWERDOWN;
|
|
output [1:0] PL2RXPMSTATE;
|
|
output [1:0] PLLANEREVERSALMODE;
|
|
output [1:0] PLRXPMSTATE;
|
|
output [1:0] PLSELLNKWIDTH;
|
|
output [1:0] TRNRDLLPSRCRDY;
|
|
output [1:0] TRNRREM;
|
|
output [2:0] CFGDEVCONTROLMAXPAYLOAD;
|
|
output [2:0] CFGDEVCONTROLMAXREADREQ;
|
|
output [2:0] CFGINTERRUPTMMENABLE;
|
|
output [2:0] CFGPCIELINKSTATE;
|
|
output [2:0] PIPETXMARGIN;
|
|
output [2:0] PLINITIALLINKWIDTH;
|
|
output [2:0] PLTXPMSTATE;
|
|
output [31:0] CFGMGMTDO;
|
|
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL;
|
|
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH;
|
|
output [3:0] TRNTDSTRDY;
|
|
output [4:0] LL2LINKSTATUS;
|
|
output [5:0] PLLTSSMSTATE;
|
|
output [5:0] TRNTBUFAV;
|
|
output [63:0] DBGVECA;
|
|
output [63:0] DBGVECB;
|
|
output [63:0] TL2ERRHDR;
|
|
output [63:0] TRNRDLLPDATA;
|
|
output [67:0] MIMRXWDATA;
|
|
output [68:0] MIMTXWDATA;
|
|
output [6:0] CFGTRANSACTIONADDR;
|
|
output [6:0] CFGVCTCVCMAP;
|
|
output [7:0] CFGINTERRUPTDO;
|
|
output [7:0] TRNFCCPLH;
|
|
output [7:0] TRNFCNPH;
|
|
output [7:0] TRNFCPH;
|
|
output [7:0] TRNRBARHIT;
|
|
input CFGERRACSN;
|
|
input CFGERRATOMICEGRESSBLOCKEDN;
|
|
input CFGERRCORN;
|
|
input CFGERRCPLABORTN;
|
|
input CFGERRCPLTIMEOUTN;
|
|
input CFGERRCPLUNEXPECTN;
|
|
input CFGERRECRCN;
|
|
input CFGERRINTERNALCORN;
|
|
input CFGERRINTERNALUNCORN;
|
|
input CFGERRLOCKEDN;
|
|
input CFGERRMALFORMEDN;
|
|
input CFGERRMCBLOCKEDN;
|
|
input CFGERRNORECOVERYN;
|
|
input CFGERRPOISONEDN;
|
|
input CFGERRPOSTEDN;
|
|
input CFGERRURN;
|
|
input CFGFORCECOMMONCLOCKOFF;
|
|
input CFGFORCEEXTENDEDSYNCON;
|
|
input CFGINTERRUPTASSERTN;
|
|
input CFGINTERRUPTN;
|
|
input CFGINTERRUPTSTATN;
|
|
input CFGMGMTRDENN;
|
|
input CFGMGMTWRENN;
|
|
input CFGMGMTWRREADONLYN;
|
|
input CFGMGMTWRRW1CASRWN;
|
|
input CFGPMFORCESTATEENN;
|
|
input CFGPMHALTASPML0SN;
|
|
input CFGPMHALTASPML1N;
|
|
input CFGPMSENDPMETON;
|
|
input CFGPMTURNOFFOKN;
|
|
input CFGPMWAKEN;
|
|
input CFGTRNPENDINGN;
|
|
input CMRSTN;
|
|
input CMSTICKYRSTN;
|
|
input DBGSUBMODE;
|
|
input DLRSTN;
|
|
input DRPCLK;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input FUNCLVLRSTN;
|
|
input LL2SENDASREQL1;
|
|
input LL2SENDENTERL1;
|
|
input LL2SENDENTERL23;
|
|
input LL2SENDPMACK;
|
|
input LL2SUSPENDNOW;
|
|
input LL2TLPRCV;
|
|
input PIPECLK;
|
|
input PIPERX0CHANISALIGNED;
|
|
input PIPERX0ELECIDLE;
|
|
input PIPERX0PHYSTATUS;
|
|
input PIPERX0VALID;
|
|
input PIPERX1CHANISALIGNED;
|
|
input PIPERX1ELECIDLE;
|
|
input PIPERX1PHYSTATUS;
|
|
input PIPERX1VALID;
|
|
input PIPERX2CHANISALIGNED;
|
|
input PIPERX2ELECIDLE;
|
|
input PIPERX2PHYSTATUS;
|
|
input PIPERX2VALID;
|
|
input PIPERX3CHANISALIGNED;
|
|
input PIPERX3ELECIDLE;
|
|
input PIPERX3PHYSTATUS;
|
|
input PIPERX3VALID;
|
|
input PIPERX4CHANISALIGNED;
|
|
input PIPERX4ELECIDLE;
|
|
input PIPERX4PHYSTATUS;
|
|
input PIPERX4VALID;
|
|
input PIPERX5CHANISALIGNED;
|
|
input PIPERX5ELECIDLE;
|
|
input PIPERX5PHYSTATUS;
|
|
input PIPERX5VALID;
|
|
input PIPERX6CHANISALIGNED;
|
|
input PIPERX6ELECIDLE;
|
|
input PIPERX6PHYSTATUS;
|
|
input PIPERX6VALID;
|
|
input PIPERX7CHANISALIGNED;
|
|
input PIPERX7ELECIDLE;
|
|
input PIPERX7PHYSTATUS;
|
|
input PIPERX7VALID;
|
|
input PLDIRECTEDLINKAUTON;
|
|
input PLDIRECTEDLINKSPEED;
|
|
input PLDIRECTEDLTSSMNEWVLD;
|
|
input PLDIRECTEDLTSSMSTALL;
|
|
input PLDOWNSTREAMDEEMPHSOURCE;
|
|
input PLRSTN;
|
|
input PLTRANSMITHOTRST;
|
|
input PLUPSTREAMPREFERDEEMPH;
|
|
input SYSRSTN;
|
|
input TL2ASPMSUSPENDCREDITCHECK;
|
|
input TL2PPMSUSPENDREQ;
|
|
input TLRSTN;
|
|
input TRNRDSTRDY;
|
|
input TRNRFCPRET;
|
|
input TRNRNPOK;
|
|
input TRNRNPREQ;
|
|
input TRNTCFGGNT;
|
|
input TRNTDLLPSRCRDY;
|
|
input TRNTECRCGEN;
|
|
input TRNTEOF;
|
|
input TRNTERRFWD;
|
|
input TRNTSOF;
|
|
input TRNTSRCDSC;
|
|
input TRNTSRCRDY;
|
|
input TRNTSTR;
|
|
input USERCLK2;
|
|
input USERCLK;
|
|
input [127:0] CFGERRAERHEADERLOG;
|
|
input [127:0] TRNTD;
|
|
input [15:0] CFGDEVID;
|
|
input [15:0] CFGSUBSYSID;
|
|
input [15:0] CFGSUBSYSVENDID;
|
|
input [15:0] CFGVENDID;
|
|
input [15:0] DRPDI;
|
|
input [15:0] PIPERX0DATA;
|
|
input [15:0] PIPERX1DATA;
|
|
input [15:0] PIPERX2DATA;
|
|
input [15:0] PIPERX3DATA;
|
|
input [15:0] PIPERX4DATA;
|
|
input [15:0] PIPERX5DATA;
|
|
input [15:0] PIPERX6DATA;
|
|
input [15:0] PIPERX7DATA;
|
|
input [1:0] CFGPMFORCESTATE;
|
|
input [1:0] DBGMODE;
|
|
input [1:0] PIPERX0CHARISK;
|
|
input [1:0] PIPERX1CHARISK;
|
|
input [1:0] PIPERX2CHARISK;
|
|
input [1:0] PIPERX3CHARISK;
|
|
input [1:0] PIPERX4CHARISK;
|
|
input [1:0] PIPERX5CHARISK;
|
|
input [1:0] PIPERX6CHARISK;
|
|
input [1:0] PIPERX7CHARISK;
|
|
input [1:0] PLDIRECTEDLINKCHANGE;
|
|
input [1:0] PLDIRECTEDLINKWIDTH;
|
|
input [1:0] TRNTREM;
|
|
input [2:0] CFGDSFUNCTIONNUMBER;
|
|
input [2:0] CFGFORCEMPS;
|
|
input [2:0] PIPERX0STATUS;
|
|
input [2:0] PIPERX1STATUS;
|
|
input [2:0] PIPERX2STATUS;
|
|
input [2:0] PIPERX3STATUS;
|
|
input [2:0] PIPERX4STATUS;
|
|
input [2:0] PIPERX5STATUS;
|
|
input [2:0] PIPERX6STATUS;
|
|
input [2:0] PIPERX7STATUS;
|
|
input [2:0] PLDBGMODE;
|
|
input [2:0] TRNFCSEL;
|
|
input [31:0] CFGMGMTDI;
|
|
input [31:0] TRNTDLLPDATA;
|
|
input [3:0] CFGMGMTBYTEENN;
|
|
input [47:0] CFGERRTLPCPLHEADER;
|
|
input [4:0] CFGAERINTERRUPTMSGNUM;
|
|
input [4:0] CFGDSDEVICENUMBER;
|
|
input [4:0] CFGPCIECAPINTERRUPTMSGNUM;
|
|
input [4:0] PL2DIRECTEDLSTATE;
|
|
input [5:0] PLDIRECTEDLTSSMNEW;
|
|
input [63:0] CFGDSN;
|
|
input [67:0] MIMRXRDATA;
|
|
input [68:0] MIMTXRDATA;
|
|
input [7:0] CFGDSBUSNUMBER;
|
|
input [7:0] CFGINTERRUPTDI;
|
|
input [7:0] CFGPORTNUMBER;
|
|
input [7:0] CFGREVID;
|
|
input [8:0] DRPADDR;
|
|
input [9:0] CFGMGMTDWADDR;
|
|
endmodule
|
|
|
|
module PCIE_3_0(CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTREADRECEIVED, CFGEXTWRITERECEIVED, CFGHOTRESETOUT, CFGINPUTUPDATEDONE, CFGINTERRUPTAOUTPUT, CFGINTERRUPTBOUTPUT, CFGINTERRUPTCOUTPUT, CFGINTERRUPTDOUTPUT, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIXFAIL, CFGINTERRUPTMSIXSENT, CFGINTERRUPTSENT, CFGLOCALERROR, CFGLTRENABLE, CFGMCUPDATEDONE, CFGMGMTREADWRITEDONE
|
|
, CFGMSGRECEIVED, CFGMSGTRANSMITDONE, CFGPERFUNCTIONUPDATEDONE, CFGPHYLINKDOWN, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGTPHSTTREADENABLE, CFGTPHSTTWRITEENABLE, DRPRDY, MAXISCQTLAST, MAXISCQTVALID, MAXISRCTLAST, MAXISRCTVALID, PCIERQSEQNUMVLD, PCIERQTAGVLD, PIPERX0POLARITY, PIPERX1POLARITY, PIPERX2POLARITY, PIPERX3POLARITY, PIPERX4POLARITY, PIPERX5POLARITY
|
|
, PIPERX6POLARITY, PIPERX7POLARITY, PIPETX0COMPLIANCE, PIPETX0DATAVALID, PIPETX0ELECIDLE, PIPETX0STARTBLOCK, PIPETX1COMPLIANCE, PIPETX1DATAVALID, PIPETX1ELECIDLE, PIPETX1STARTBLOCK, PIPETX2COMPLIANCE, PIPETX2DATAVALID, PIPETX2ELECIDLE, PIPETX2STARTBLOCK, PIPETX3COMPLIANCE, PIPETX3DATAVALID, PIPETX3ELECIDLE, PIPETX3STARTBLOCK, PIPETX4COMPLIANCE, PIPETX4DATAVALID, PIPETX4ELECIDLE
|
|
, PIPETX4STARTBLOCK, PIPETX5COMPLIANCE, PIPETX5DATAVALID, PIPETX5ELECIDLE, PIPETX5STARTBLOCK, PIPETX6COMPLIANCE, PIPETX6DATAVALID, PIPETX6ELECIDLE, PIPETX6STARTBLOCK, PIPETX7COMPLIANCE, PIPETX7DATAVALID, PIPETX7ELECIDLE, PIPETX7STARTBLOCK, PIPETXDEEMPH, PIPETXRCVRDET, PIPETXRESET, PIPETXSWING, PLEQINPROGRESS, CFGFCCPLD, CFGFCNPD, CFGFCPD
|
|
, CFGVFSTATUS, MIREPLAYRAMWRITEDATA, MIREQUESTRAMWRITEDATA, CFGPERFUNCSTATUSDATA, DBGDATAOUT, DRPDO, CFGVFPOWERSTATE, CFGVFTPHSTMODE, CFGDPASUBSTATECHANGE, CFGFLRINPROCESS, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXMASK, CFGLINKPOWERSTATE, CFGOBFFENABLE, CFGPHYLINKSTATUS, CFGRCBSTATUS, CFGTPHREQUESTERENABLE, MIREPLAYRAMREADENABLE, MIREPLAYRAMWRITEENABLE, PCIERQTAGAV
|
|
, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX0EQCONTROL, PIPERX1EQCONTROL, PIPERX2EQCONTROL, PIPERX3EQCONTROL, PIPERX4EQCONTROL, PIPERX5EQCONTROL, PIPERX6EQCONTROL, PIPERX7EQCONTROL, PIPETX0CHARISK, PIPETX0EQCONTROL, PIPETX0POWERDOWN, PIPETX0SYNCHEADER, PIPETX1CHARISK, PIPETX1EQCONTROL, PIPETX1POWERDOWN, PIPETX1SYNCHEADER, PIPETX2CHARISK, PIPETX2EQCONTROL, PIPETX2POWERDOWN
|
|
, PIPETX2SYNCHEADER, PIPETX3CHARISK, PIPETX3EQCONTROL, PIPETX3POWERDOWN, PIPETX3SYNCHEADER, PIPETX4CHARISK, PIPETX4EQCONTROL, PIPETX4POWERDOWN, PIPETX4SYNCHEADER, PIPETX5CHARISK, PIPETX5EQCONTROL, PIPETX5POWERDOWN, PIPETX5SYNCHEADER, PIPETX6CHARISK, PIPETX6EQCONTROL, PIPETX6POWERDOWN, PIPETX6SYNCHEADER, PIPETX7CHARISK, PIPETX7EQCONTROL, PIPETX7POWERDOWN, PIPETX7SYNCHEADER
|
|
, PIPETXRATE, PLEQPHASE, MAXISCQTDATA, MAXISRCTDATA, CFGCURRENTSPEED, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGTPHFUNCTIONNUM, PIPERX0EQPRESET, PIPERX1EQPRESET, PIPERX2EQPRESET, PIPERX3EQPRESET, PIPERX4EQPRESET, PIPERX5EQPRESET, PIPERX6EQPRESET, PIPERX7EQPRESET, PIPETXMARGIN, CFGEXTWRITEDATA, CFGINTERRUPTMSIDATA, CFGMGMTREADDATA, CFGTPHSTTWRITEDATA
|
|
, PIPETX0DATA, PIPETX1DATA, PIPETX2DATA, PIPETX3DATA, PIPETX4DATA, PIPETX5DATA, PIPETX6DATA, PIPETX7DATA, CFGEXTWRITEBYTEENABLE, CFGNEGOTIATEDWIDTH, CFGTPHSTTWRITEBYTEVALID, MICOMPLETIONRAMREADENABLEL, MICOMPLETIONRAMREADENABLEU, MICOMPLETIONRAMWRITEENABLEL, MICOMPLETIONRAMWRITEENABLEU, MIREQUESTRAMREADENABLE, MIREQUESTRAMWRITEENABLE, PCIERQSEQNUM, PIPERX0EQLPTXPRESET, PIPERX1EQLPTXPRESET, PIPERX2EQLPTXPRESET
|
|
, PIPERX3EQLPTXPRESET, PIPERX4EQLPTXPRESET, PIPERX5EQLPTXPRESET, PIPERX6EQLPTXPRESET, PIPERX7EQLPTXPRESET, PIPETX0EQPRESET, PIPETX1EQPRESET, PIPETX2EQPRESET, PIPETX3EQPRESET, PIPETX4EQPRESET, PIPETX5EQPRESET, PIPETX6EQPRESET, PIPETX7EQPRESET, SAXISCCTREADY, SAXISRQTREADY, CFGMSGRECEIVEDTYPE, CFGTPHSTTADDRESS, CFGFUNCTIONPOWERSTATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSIVFENABLE, CFGINTERRUPTMSIXVFENABLE
|
|
, CFGINTERRUPTMSIXVFMASK, CFGLTSSMSTATE, CFGTPHSTMODE, CFGVFFLRINPROCESS, CFGVFTPHREQUESTERENABLE, PCIECQNPREQCOUNT, PCIERQTAG, PIPERX0EQLPLFFS, PIPERX1EQLPLFFS, PIPERX2EQLPLFFS, PIPERX3EQLPLFFS, PIPERX4EQLPLFFS, PIPERX5EQLPLFFS, PIPERX6EQLPLFFS, PIPERX7EQLPLFFS, PIPETX0EQDEEMPH, PIPETX1EQDEEMPH, PIPETX2EQDEEMPH, PIPETX3EQDEEMPH, PIPETX4EQDEEMPH, PIPETX5EQDEEMPH
|
|
, PIPETX6EQDEEMPH, PIPETX7EQDEEMPH, MICOMPLETIONRAMWRITEDATAL, MICOMPLETIONRAMWRITEDATAU, MAXISRCTUSER, CFGEXTFUNCTIONNUMBER, CFGFCCPLH, CFGFCNPH, CFGFCPH, CFGFUNCTIONSTATUS, CFGMSGRECEIVEDDATA, MAXISCQTKEEP, MAXISRCTKEEP, PLGEN3PCSRXSLIDE, MAXISCQTUSER, MIREPLAYRAMADDRESS, MIREQUESTRAMREADADDRESSA, MIREQUESTRAMREADADDRESSB, MIREQUESTRAMWRITEADDRESSA, MIREQUESTRAMWRITEADDRESSB, CFGEXTREGISTERNUMBER
|
|
, MICOMPLETIONRAMREADADDRESSAL, MICOMPLETIONRAMREADADDRESSAU, MICOMPLETIONRAMREADADDRESSBL, MICOMPLETIONRAMREADADDRESSBU, MICOMPLETIONRAMWRITEADDRESSAL, MICOMPLETIONRAMWRITEADDRESSAU, MICOMPLETIONRAMWRITEADDRESSBL, MICOMPLETIONRAMWRITEADDRESSBU, CFGCONFIGSPACEENABLE, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATAVALID, CFGHOTRESETIN, CFGINPUTUPDATEREQUEST, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSIXINT, CFGLINKTRAININGENABLE, CFGMCUPDATEREQUEST, CFGMGMTREAD, CFGMGMTTYPE1CFGREGACCESS, CFGMGMTWRITE
|
|
, CFGMSGTRANSMIT, CFGPERFUNCTIONOUTPUTREQUEST, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY, CFGTPHSTTREADDATAVALID, CORECLK, CORECLKMICOMPLETIONRAML, CORECLKMICOMPLETIONRAMU, CORECLKMIREPLAYRAM, CORECLKMIREQUESTRAM, DRPCLK, DRPEN, DRPWE, MGMTRESETN, MGMTSTICKYRESETN, PCIECQNPREQ, PIPECLK, PIPERESETN, PIPERX0DATAVALID, PIPERX0ELECIDLE, PIPERX0EQDONE
|
|
, PIPERX0EQLPADAPTDONE, PIPERX0EQLPLFFSSEL, PIPERX0PHYSTATUS, PIPERX0STARTBLOCK, PIPERX0VALID, PIPERX1DATAVALID, PIPERX1ELECIDLE, PIPERX1EQDONE, PIPERX1EQLPADAPTDONE, PIPERX1EQLPLFFSSEL, PIPERX1PHYSTATUS, PIPERX1STARTBLOCK, PIPERX1VALID, PIPERX2DATAVALID, PIPERX2ELECIDLE, PIPERX2EQDONE, PIPERX2EQLPADAPTDONE, PIPERX2EQLPLFFSSEL, PIPERX2PHYSTATUS, PIPERX2STARTBLOCK, PIPERX2VALID
|
|
, PIPERX3DATAVALID, PIPERX3ELECIDLE, PIPERX3EQDONE, PIPERX3EQLPADAPTDONE, PIPERX3EQLPLFFSSEL, PIPERX3PHYSTATUS, PIPERX3STARTBLOCK, PIPERX3VALID, PIPERX4DATAVALID, PIPERX4ELECIDLE, PIPERX4EQDONE, PIPERX4EQLPADAPTDONE, PIPERX4EQLPLFFSSEL, PIPERX4PHYSTATUS, PIPERX4STARTBLOCK, PIPERX4VALID, PIPERX5DATAVALID, PIPERX5ELECIDLE, PIPERX5EQDONE, PIPERX5EQLPADAPTDONE, PIPERX5EQLPLFFSSEL
|
|
, PIPERX5PHYSTATUS, PIPERX5STARTBLOCK, PIPERX5VALID, PIPERX6DATAVALID, PIPERX6ELECIDLE, PIPERX6EQDONE, PIPERX6EQLPADAPTDONE, PIPERX6EQLPLFFSSEL, PIPERX6PHYSTATUS, PIPERX6STARTBLOCK, PIPERX6VALID, PIPERX7DATAVALID, PIPERX7ELECIDLE, PIPERX7EQDONE, PIPERX7EQLPADAPTDONE, PIPERX7EQLPLFFSSEL, PIPERX7PHYSTATUS, PIPERX7STARTBLOCK, PIPERX7VALID, PIPETX0EQDONE, PIPETX1EQDONE
|
|
, PIPETX2EQDONE, PIPETX3EQDONE, PIPETX4EQDONE, PIPETX5EQDONE, PIPETX6EQDONE, PIPETX7EQDONE, PLDISABLESCRAMBLER, PLEQRESETEIEOSCOUNT, PLGEN3PCSDISABLE, RECCLK, RESETN, SAXISCCTLAST, SAXISCCTVALID, SAXISRQTLAST, SAXISRQTVALID, USERCLK, DRPADDR, MICOMPLETIONRAMREADDATA, MIREPLAYRAMREADDATA, MIREQUESTRAMREADDATA, CFGDEVID
|
|
, CFGSUBSYSID, CFGSUBSYSVENDID, CFGVENDID, DRPDI, PIPERX0EQLPNEWTXCOEFFORPRESET, PIPERX1EQLPNEWTXCOEFFORPRESET, PIPERX2EQLPNEWTXCOEFFORPRESET, PIPERX3EQLPNEWTXCOEFFORPRESET, PIPERX4EQLPNEWTXCOEFFORPRESET, PIPERX5EQLPNEWTXCOEFFORPRESET, PIPERX6EQLPNEWTXCOEFFORPRESET, PIPERX7EQLPNEWTXCOEFFORPRESET, PIPETX0EQCOEFF, PIPETX1EQCOEFF, PIPETX2EQCOEFF, PIPETX3EQCOEFF, PIPETX4EQCOEFF, PIPETX5EQCOEFF, PIPETX6EQCOEFF, PIPETX7EQCOEFF, CFGMGMTADDR
|
|
, CFGFLRDONE, CFGINTERRUPTMSITPHTYPE, CFGINTERRUPTPENDING, PIPERX0CHARISK, PIPERX0SYNCHEADER, PIPERX1CHARISK, PIPERX1SYNCHEADER, PIPERX2CHARISK, PIPERX2SYNCHEADER, PIPERX3CHARISK, PIPERX3SYNCHEADER, PIPERX4CHARISK, PIPERX4SYNCHEADER, PIPERX5CHARISK, PIPERX5SYNCHEADER, PIPERX6CHARISK, PIPERX6SYNCHEADER, PIPERX7CHARISK, PIPERX7SYNCHEADER, MAXISCQTREADY, MAXISRCTREADY
|
|
, SAXISCCTDATA, SAXISRQTDATA, CFGDSFUNCTIONNUMBER, CFGFCSEL, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGMSGTRANSMITTYPE, CFGPERFUNCSTATUSCONTROL, CFGPERFUNCTIONNUMBER, PIPERX0STATUS, PIPERX1STATUS, PIPERX2STATUS, PIPERX3STATUS, PIPERX4STATUS, PIPERX5STATUS, PIPERX6STATUS, PIPERX7STATUS, CFGEXTREADDATA, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIXDATA, CFGMGMTWRITEDATA
|
|
, CFGMSGTRANSMITDATA, CFGTPHSTTREADDATA, PIPERX0DATA, PIPERX1DATA, PIPERX2DATA, PIPERX3DATA, PIPERX4DATA, PIPERX5DATA, PIPERX6DATA, PIPERX7DATA, SAXISCCTUSER, CFGINTERRUPTINT, CFGINTERRUPTMSISELECT, CFGMGMTBYTEENABLE, CFGDSDEVICENUMBER, SAXISRQTUSER, CFGVFFLRDONE, PIPEEQFS, PIPEEQLF, CFGDSN, CFGINTERRUPTMSIPENDINGSTATUS
|
|
, CFGINTERRUPTMSIXADDRESS, CFGDSBUSNUMBER, CFGDSPORTNUMBER, CFGREVID, PLGEN3PCSRXSYNCDONE, SAXISCCTKEEP, SAXISRQTKEEP, CFGINTERRUPTMSITPHSTTAG);
|
|
parameter ARI_CAP_ENABLE = "FALSE";
|
|
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE";
|
|
parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE";
|
|
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
|
|
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
|
|
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
|
|
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE";
|
|
parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE";
|
|
parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE";
|
|
parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
|
|
parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
|
|
parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
|
|
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
|
|
parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1;
|
|
parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE";
|
|
parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
|
|
parameter LL_ACK_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
|
|
parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000;
|
|
parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
|
|
parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000;
|
|
parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
|
|
parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000;
|
|
parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
|
|
parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000;
|
|
parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
|
|
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
|
|
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
|
|
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA;
|
|
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
|
|
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
|
|
parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
|
|
parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
|
|
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
|
|
parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF0_BIST_REGISTER = 8'h00;
|
|
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50;
|
|
parameter [23:0] PF0_CLASS_CODE = 24'h000000;
|
|
parameter [15:0] PF0_DEVICE_ID = 16'h0000;
|
|
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
|
|
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
|
|
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
|
|
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
|
|
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
|
|
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
|
|
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
|
|
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
|
|
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
|
|
parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
|
|
parameter [3:0] PF0_DPA_CAP_VER = 4'h1;
|
|
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [7:0] PF0_INTERRUPT_LINE = 8'h00;
|
|
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
|
|
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
|
|
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
|
|
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
|
|
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
|
|
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
|
|
parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
|
|
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000;
|
|
parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
|
|
parameter [3:0] PF0_PB_CAP_VER = 4'h1;
|
|
parameter [7:0] PF0_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
|
|
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
|
|
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
|
|
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
|
|
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
|
|
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
|
|
parameter PF0_RBAR_CAP_ENABLE = "FALSE";
|
|
parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0;
|
|
parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0;
|
|
parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0;
|
|
parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000;
|
|
parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000;
|
|
parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000;
|
|
parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000;
|
|
parameter [3:0] PF0_RBAR_CAP_VER = 4'h1;
|
|
parameter [2:0] PF0_RBAR_NUM = 3'h1;
|
|
parameter [7:0] PF0_REVISION_ID = 8'h00;
|
|
parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000;
|
|
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter PF0_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
|
|
parameter [3:0] PF0_VC_CAP_VER = 4'h1;
|
|
parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
|
|
parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
|
|
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF1_BIST_REGISTER = 8'h00;
|
|
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50;
|
|
parameter [23:0] PF1_CLASS_CODE = 24'h000000;
|
|
parameter [15:0] PF1_DEVICE_ID = 16'h0000;
|
|
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
|
|
parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
|
|
parameter [3:0] PF1_DPA_CAP_VER = 4'h1;
|
|
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [7:0] PF1_INTERRUPT_LINE = 8'h00;
|
|
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000;
|
|
parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
|
|
parameter [3:0] PF1_PB_CAP_VER = 4'h1;
|
|
parameter [7:0] PF1_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3;
|
|
parameter PF1_RBAR_CAP_ENABLE = "FALSE";
|
|
parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0;
|
|
parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0;
|
|
parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0;
|
|
parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000;
|
|
parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000;
|
|
parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000;
|
|
parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000;
|
|
parameter [3:0] PF1_RBAR_CAP_VER = 4'h1;
|
|
parameter [2:0] PF1_RBAR_NUM = 3'h1;
|
|
parameter [7:0] PF1_REVISION_ID = 8'h00;
|
|
parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000;
|
|
parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter PF1_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] PF1_TPHR_CAP_VER = 4'h1;
|
|
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
|
|
parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE";
|
|
parameter PL_DISABLE_SCRAMBLING = "FALSE";
|
|
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
|
|
parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE";
|
|
parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE";
|
|
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
|
|
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
|
|
parameter PL_EQ_BYPASS_PHASE23 = "FALSE";
|
|
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
|
|
parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00;
|
|
parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4;
|
|
parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8;
|
|
parameter integer PL_N_FTS_COMCLK_GEN1 = 255;
|
|
parameter integer PL_N_FTS_COMCLK_GEN2 = 255;
|
|
parameter integer PL_N_FTS_COMCLK_GEN3 = 255;
|
|
parameter integer PL_N_FTS_GEN1 = 255;
|
|
parameter integer PL_N_FTS_GEN2 = 255;
|
|
parameter integer PL_N_FTS_GEN3 = 255;
|
|
parameter PL_SIM_FAST_LINK_TRAINING = "FALSE";
|
|
parameter PL_UPSTREAM_FACING = "TRUE";
|
|
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC;
|
|
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000;
|
|
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
|
|
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000;
|
|
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0;
|
|
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064;
|
|
parameter SIM_VERSION = "1.0";
|
|
parameter integer SPARE_BIT0 = 0;
|
|
parameter integer SPARE_BIT1 = 0;
|
|
parameter integer SPARE_BIT2 = 0;
|
|
parameter integer SPARE_BIT3 = 0;
|
|
parameter integer SPARE_BIT4 = 0;
|
|
parameter integer SPARE_BIT5 = 0;
|
|
parameter integer SPARE_BIT6 = 0;
|
|
parameter integer SPARE_BIT7 = 0;
|
|
parameter integer SPARE_BIT8 = 0;
|
|
parameter [7:0] SPARE_BYTE0 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE1 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE2 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE3 = 8'h00;
|
|
parameter [31:0] SPARE_WORD0 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD1 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD2 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD3 = 32'h00000000;
|
|
parameter SRIOV_CAP_ENABLE = "FALSE";
|
|
parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
|
|
parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000;
|
|
parameter [11:0] TL_CREDITS_CD = 12'h3E0;
|
|
parameter [7:0] TL_CREDITS_CH = 8'h20;
|
|
parameter [11:0] TL_CREDITS_NPD = 12'h028;
|
|
parameter [7:0] TL_CREDITS_NPH = 8'h20;
|
|
parameter [11:0] TL_CREDITS_PD = 12'h198;
|
|
parameter [7:0] TL_CREDITS_PH = 8'h20;
|
|
parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE";
|
|
parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
|
|
parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
|
|
parameter TL_LEGACY_MODE_ENABLE = "FALSE";
|
|
parameter TL_PF_ENABLE_REG = "FALSE";
|
|
parameter TL_TAG_MGMT_ENABLE = "TRUE";
|
|
parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50;
|
|
parameter integer VF0_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF0_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF0_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF0_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF0_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF1_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF1_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF1_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF1_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF1_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF2_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF2_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF2_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF2_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF2_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF3_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF3_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF3_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF3_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF3_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF4_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF4_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF4_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF4_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF4_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF5_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF5_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF5_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF5_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF5_TPHR_CAP_VER = 4'h1;
|
|
output CFGERRCOROUT;
|
|
output CFGERRFATALOUT;
|
|
output CFGERRNONFATALOUT;
|
|
output CFGEXTREADRECEIVED;
|
|
output CFGEXTWRITERECEIVED;
|
|
output CFGHOTRESETOUT;
|
|
output CFGINPUTUPDATEDONE;
|
|
output CFGINTERRUPTAOUTPUT;
|
|
output CFGINTERRUPTBOUTPUT;
|
|
output CFGINTERRUPTCOUTPUT;
|
|
output CFGINTERRUPTDOUTPUT;
|
|
output CFGINTERRUPTMSIFAIL;
|
|
output CFGINTERRUPTMSIMASKUPDATE;
|
|
output CFGINTERRUPTMSISENT;
|
|
output CFGINTERRUPTMSIXFAIL;
|
|
output CFGINTERRUPTMSIXSENT;
|
|
output CFGINTERRUPTSENT;
|
|
output CFGLOCALERROR;
|
|
output CFGLTRENABLE;
|
|
output CFGMCUPDATEDONE;
|
|
output CFGMGMTREADWRITEDONE;
|
|
output CFGMSGRECEIVED;
|
|
output CFGMSGTRANSMITDONE;
|
|
output CFGPERFUNCTIONUPDATEDONE;
|
|
output CFGPHYLINKDOWN;
|
|
output CFGPLSTATUSCHANGE;
|
|
output CFGPOWERSTATECHANGEINTERRUPT;
|
|
output CFGTPHSTTREADENABLE;
|
|
output CFGTPHSTTWRITEENABLE;
|
|
output DRPRDY;
|
|
output MAXISCQTLAST;
|
|
output MAXISCQTVALID;
|
|
output MAXISRCTLAST;
|
|
output MAXISRCTVALID;
|
|
output PCIERQSEQNUMVLD;
|
|
output PCIERQTAGVLD;
|
|
output PIPERX0POLARITY;
|
|
output PIPERX1POLARITY;
|
|
output PIPERX2POLARITY;
|
|
output PIPERX3POLARITY;
|
|
output PIPERX4POLARITY;
|
|
output PIPERX5POLARITY;
|
|
output PIPERX6POLARITY;
|
|
output PIPERX7POLARITY;
|
|
output PIPETX0COMPLIANCE;
|
|
output PIPETX0DATAVALID;
|
|
output PIPETX0ELECIDLE;
|
|
output PIPETX0STARTBLOCK;
|
|
output PIPETX1COMPLIANCE;
|
|
output PIPETX1DATAVALID;
|
|
output PIPETX1ELECIDLE;
|
|
output PIPETX1STARTBLOCK;
|
|
output PIPETX2COMPLIANCE;
|
|
output PIPETX2DATAVALID;
|
|
output PIPETX2ELECIDLE;
|
|
output PIPETX2STARTBLOCK;
|
|
output PIPETX3COMPLIANCE;
|
|
output PIPETX3DATAVALID;
|
|
output PIPETX3ELECIDLE;
|
|
output PIPETX3STARTBLOCK;
|
|
output PIPETX4COMPLIANCE;
|
|
output PIPETX4DATAVALID;
|
|
output PIPETX4ELECIDLE;
|
|
output PIPETX4STARTBLOCK;
|
|
output PIPETX5COMPLIANCE;
|
|
output PIPETX5DATAVALID;
|
|
output PIPETX5ELECIDLE;
|
|
output PIPETX5STARTBLOCK;
|
|
output PIPETX6COMPLIANCE;
|
|
output PIPETX6DATAVALID;
|
|
output PIPETX6ELECIDLE;
|
|
output PIPETX6STARTBLOCK;
|
|
output PIPETX7COMPLIANCE;
|
|
output PIPETX7DATAVALID;
|
|
output PIPETX7ELECIDLE;
|
|
output PIPETX7STARTBLOCK;
|
|
output PIPETXDEEMPH;
|
|
output PIPETXRCVRDET;
|
|
output PIPETXRESET;
|
|
output PIPETXSWING;
|
|
output PLEQINPROGRESS;
|
|
output [11:0] CFGFCCPLD;
|
|
output [11:0] CFGFCNPD;
|
|
output [11:0] CFGFCPD;
|
|
output [11:0] CFGVFSTATUS;
|
|
output [143:0] MIREPLAYRAMWRITEDATA;
|
|
output [143:0] MIREQUESTRAMWRITEDATA;
|
|
output [15:0] CFGPERFUNCSTATUSDATA;
|
|
output [15:0] DBGDATAOUT;
|
|
output [15:0] DRPDO;
|
|
output [17:0] CFGVFPOWERSTATE;
|
|
output [17:0] CFGVFTPHSTMODE;
|
|
output [1:0] CFGDPASUBSTATECHANGE;
|
|
output [1:0] CFGFLRINPROCESS;
|
|
output [1:0] CFGINTERRUPTMSIENABLE;
|
|
output [1:0] CFGINTERRUPTMSIXENABLE;
|
|
output [1:0] CFGINTERRUPTMSIXMASK;
|
|
output [1:0] CFGLINKPOWERSTATE;
|
|
output [1:0] CFGOBFFENABLE;
|
|
output [1:0] CFGPHYLINKSTATUS;
|
|
output [1:0] CFGRCBSTATUS;
|
|
output [1:0] CFGTPHREQUESTERENABLE;
|
|
output [1:0] MIREPLAYRAMREADENABLE;
|
|
output [1:0] MIREPLAYRAMWRITEENABLE;
|
|
output [1:0] PCIERQTAGAV;
|
|
output [1:0] PCIETFCNPDAV;
|
|
output [1:0] PCIETFCNPHAV;
|
|
output [1:0] PIPERX0EQCONTROL;
|
|
output [1:0] PIPERX1EQCONTROL;
|
|
output [1:0] PIPERX2EQCONTROL;
|
|
output [1:0] PIPERX3EQCONTROL;
|
|
output [1:0] PIPERX4EQCONTROL;
|
|
output [1:0] PIPERX5EQCONTROL;
|
|
output [1:0] PIPERX6EQCONTROL;
|
|
output [1:0] PIPERX7EQCONTROL;
|
|
output [1:0] PIPETX0CHARISK;
|
|
output [1:0] PIPETX0EQCONTROL;
|
|
output [1:0] PIPETX0POWERDOWN;
|
|
output [1:0] PIPETX0SYNCHEADER;
|
|
output [1:0] PIPETX1CHARISK;
|
|
output [1:0] PIPETX1EQCONTROL;
|
|
output [1:0] PIPETX1POWERDOWN;
|
|
output [1:0] PIPETX1SYNCHEADER;
|
|
output [1:0] PIPETX2CHARISK;
|
|
output [1:0] PIPETX2EQCONTROL;
|
|
output [1:0] PIPETX2POWERDOWN;
|
|
output [1:0] PIPETX2SYNCHEADER;
|
|
output [1:0] PIPETX3CHARISK;
|
|
output [1:0] PIPETX3EQCONTROL;
|
|
output [1:0] PIPETX3POWERDOWN;
|
|
output [1:0] PIPETX3SYNCHEADER;
|
|
output [1:0] PIPETX4CHARISK;
|
|
output [1:0] PIPETX4EQCONTROL;
|
|
output [1:0] PIPETX4POWERDOWN;
|
|
output [1:0] PIPETX4SYNCHEADER;
|
|
output [1:0] PIPETX5CHARISK;
|
|
output [1:0] PIPETX5EQCONTROL;
|
|
output [1:0] PIPETX5POWERDOWN;
|
|
output [1:0] PIPETX5SYNCHEADER;
|
|
output [1:0] PIPETX6CHARISK;
|
|
output [1:0] PIPETX6EQCONTROL;
|
|
output [1:0] PIPETX6POWERDOWN;
|
|
output [1:0] PIPETX6SYNCHEADER;
|
|
output [1:0] PIPETX7CHARISK;
|
|
output [1:0] PIPETX7EQCONTROL;
|
|
output [1:0] PIPETX7POWERDOWN;
|
|
output [1:0] PIPETX7SYNCHEADER;
|
|
output [1:0] PIPETXRATE;
|
|
output [1:0] PLEQPHASE;
|
|
output [255:0] MAXISCQTDATA;
|
|
output [255:0] MAXISRCTDATA;
|
|
output [2:0] CFGCURRENTSPEED;
|
|
output [2:0] CFGMAXPAYLOAD;
|
|
output [2:0] CFGMAXREADREQ;
|
|
output [2:0] CFGTPHFUNCTIONNUM;
|
|
output [2:0] PIPERX0EQPRESET;
|
|
output [2:0] PIPERX1EQPRESET;
|
|
output [2:0] PIPERX2EQPRESET;
|
|
output [2:0] PIPERX3EQPRESET;
|
|
output [2:0] PIPERX4EQPRESET;
|
|
output [2:0] PIPERX5EQPRESET;
|
|
output [2:0] PIPERX6EQPRESET;
|
|
output [2:0] PIPERX7EQPRESET;
|
|
output [2:0] PIPETXMARGIN;
|
|
output [31:0] CFGEXTWRITEDATA;
|
|
output [31:0] CFGINTERRUPTMSIDATA;
|
|
output [31:0] CFGMGMTREADDATA;
|
|
output [31:0] CFGTPHSTTWRITEDATA;
|
|
output [31:0] PIPETX0DATA;
|
|
output [31:0] PIPETX1DATA;
|
|
output [31:0] PIPETX2DATA;
|
|
output [31:0] PIPETX3DATA;
|
|
output [31:0] PIPETX4DATA;
|
|
output [31:0] PIPETX5DATA;
|
|
output [31:0] PIPETX6DATA;
|
|
output [31:0] PIPETX7DATA;
|
|
output [3:0] CFGEXTWRITEBYTEENABLE;
|
|
output [3:0] CFGNEGOTIATEDWIDTH;
|
|
output [3:0] CFGTPHSTTWRITEBYTEVALID;
|
|
output [3:0] MICOMPLETIONRAMREADENABLEL;
|
|
output [3:0] MICOMPLETIONRAMREADENABLEU;
|
|
output [3:0] MICOMPLETIONRAMWRITEENABLEL;
|
|
output [3:0] MICOMPLETIONRAMWRITEENABLEU;
|
|
output [3:0] MIREQUESTRAMREADENABLE;
|
|
output [3:0] MIREQUESTRAMWRITEENABLE;
|
|
output [3:0] PCIERQSEQNUM;
|
|
output [3:0] PIPERX0EQLPTXPRESET;
|
|
output [3:0] PIPERX1EQLPTXPRESET;
|
|
output [3:0] PIPERX2EQLPTXPRESET;
|
|
output [3:0] PIPERX3EQLPTXPRESET;
|
|
output [3:0] PIPERX4EQLPTXPRESET;
|
|
output [3:0] PIPERX5EQLPTXPRESET;
|
|
output [3:0] PIPERX6EQLPTXPRESET;
|
|
output [3:0] PIPERX7EQLPTXPRESET;
|
|
output [3:0] PIPETX0EQPRESET;
|
|
output [3:0] PIPETX1EQPRESET;
|
|
output [3:0] PIPETX2EQPRESET;
|
|
output [3:0] PIPETX3EQPRESET;
|
|
output [3:0] PIPETX4EQPRESET;
|
|
output [3:0] PIPETX5EQPRESET;
|
|
output [3:0] PIPETX6EQPRESET;
|
|
output [3:0] PIPETX7EQPRESET;
|
|
output [3:0] SAXISCCTREADY;
|
|
output [3:0] SAXISRQTREADY;
|
|
output [4:0] CFGMSGRECEIVEDTYPE;
|
|
output [4:0] CFGTPHSTTADDRESS;
|
|
output [5:0] CFGFUNCTIONPOWERSTATE;
|
|
output [5:0] CFGINTERRUPTMSIMMENABLE;
|
|
output [5:0] CFGINTERRUPTMSIVFENABLE;
|
|
output [5:0] CFGINTERRUPTMSIXVFENABLE;
|
|
output [5:0] CFGINTERRUPTMSIXVFMASK;
|
|
output [5:0] CFGLTSSMSTATE;
|
|
output [5:0] CFGTPHSTMODE;
|
|
output [5:0] CFGVFFLRINPROCESS;
|
|
output [5:0] CFGVFTPHREQUESTERENABLE;
|
|
output [5:0] PCIECQNPREQCOUNT;
|
|
output [5:0] PCIERQTAG;
|
|
output [5:0] PIPERX0EQLPLFFS;
|
|
output [5:0] PIPERX1EQLPLFFS;
|
|
output [5:0] PIPERX2EQLPLFFS;
|
|
output [5:0] PIPERX3EQLPLFFS;
|
|
output [5:0] PIPERX4EQLPLFFS;
|
|
output [5:0] PIPERX5EQLPLFFS;
|
|
output [5:0] PIPERX6EQLPLFFS;
|
|
output [5:0] PIPERX7EQLPLFFS;
|
|
output [5:0] PIPETX0EQDEEMPH;
|
|
output [5:0] PIPETX1EQDEEMPH;
|
|
output [5:0] PIPETX2EQDEEMPH;
|
|
output [5:0] PIPETX3EQDEEMPH;
|
|
output [5:0] PIPETX4EQDEEMPH;
|
|
output [5:0] PIPETX5EQDEEMPH;
|
|
output [5:0] PIPETX6EQDEEMPH;
|
|
output [5:0] PIPETX7EQDEEMPH;
|
|
output [71:0] MICOMPLETIONRAMWRITEDATAL;
|
|
output [71:0] MICOMPLETIONRAMWRITEDATAU;
|
|
output [74:0] MAXISRCTUSER;
|
|
output [7:0] CFGEXTFUNCTIONNUMBER;
|
|
output [7:0] CFGFCCPLH;
|
|
output [7:0] CFGFCNPH;
|
|
output [7:0] CFGFCPH;
|
|
output [7:0] CFGFUNCTIONSTATUS;
|
|
output [7:0] CFGMSGRECEIVEDDATA;
|
|
output [7:0] MAXISCQTKEEP;
|
|
output [7:0] MAXISRCTKEEP;
|
|
output [7:0] PLGEN3PCSRXSLIDE;
|
|
output [84:0] MAXISCQTUSER;
|
|
output [8:0] MIREPLAYRAMADDRESS;
|
|
output [8:0] MIREQUESTRAMREADADDRESSA;
|
|
output [8:0] MIREQUESTRAMREADADDRESSB;
|
|
output [8:0] MIREQUESTRAMWRITEADDRESSA;
|
|
output [8:0] MIREQUESTRAMWRITEADDRESSB;
|
|
output [9:0] CFGEXTREGISTERNUMBER;
|
|
output [9:0] MICOMPLETIONRAMREADADDRESSAL;
|
|
output [9:0] MICOMPLETIONRAMREADADDRESSAU;
|
|
output [9:0] MICOMPLETIONRAMREADADDRESSBL;
|
|
output [9:0] MICOMPLETIONRAMREADADDRESSBU;
|
|
output [9:0] MICOMPLETIONRAMWRITEADDRESSAL;
|
|
output [9:0] MICOMPLETIONRAMWRITEADDRESSAU;
|
|
output [9:0] MICOMPLETIONRAMWRITEADDRESSBL;
|
|
output [9:0] MICOMPLETIONRAMWRITEADDRESSBU;
|
|
input CFGCONFIGSPACEENABLE;
|
|
input CFGERRCORIN;
|
|
input CFGERRUNCORIN;
|
|
input CFGEXTREADDATAVALID;
|
|
input CFGHOTRESETIN;
|
|
input CFGINPUTUPDATEREQUEST;
|
|
input CFGINTERRUPTMSITPHPRESENT;
|
|
input CFGINTERRUPTMSIXINT;
|
|
input CFGLINKTRAININGENABLE;
|
|
input CFGMCUPDATEREQUEST;
|
|
input CFGMGMTREAD;
|
|
input CFGMGMTTYPE1CFGREGACCESS;
|
|
input CFGMGMTWRITE;
|
|
input CFGMSGTRANSMIT;
|
|
input CFGPERFUNCTIONOUTPUTREQUEST;
|
|
input CFGPOWERSTATECHANGEACK;
|
|
input CFGREQPMTRANSITIONL23READY;
|
|
input CFGTPHSTTREADDATAVALID;
|
|
input CORECLK;
|
|
input CORECLKMICOMPLETIONRAML;
|
|
input CORECLKMICOMPLETIONRAMU;
|
|
input CORECLKMIREPLAYRAM;
|
|
input CORECLKMIREQUESTRAM;
|
|
input DRPCLK;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input MGMTRESETN;
|
|
input MGMTSTICKYRESETN;
|
|
input PCIECQNPREQ;
|
|
input PIPECLK;
|
|
input PIPERESETN;
|
|
input PIPERX0DATAVALID;
|
|
input PIPERX0ELECIDLE;
|
|
input PIPERX0EQDONE;
|
|
input PIPERX0EQLPADAPTDONE;
|
|
input PIPERX0EQLPLFFSSEL;
|
|
input PIPERX0PHYSTATUS;
|
|
input PIPERX0STARTBLOCK;
|
|
input PIPERX0VALID;
|
|
input PIPERX1DATAVALID;
|
|
input PIPERX1ELECIDLE;
|
|
input PIPERX1EQDONE;
|
|
input PIPERX1EQLPADAPTDONE;
|
|
input PIPERX1EQLPLFFSSEL;
|
|
input PIPERX1PHYSTATUS;
|
|
input PIPERX1STARTBLOCK;
|
|
input PIPERX1VALID;
|
|
input PIPERX2DATAVALID;
|
|
input PIPERX2ELECIDLE;
|
|
input PIPERX2EQDONE;
|
|
input PIPERX2EQLPADAPTDONE;
|
|
input PIPERX2EQLPLFFSSEL;
|
|
input PIPERX2PHYSTATUS;
|
|
input PIPERX2STARTBLOCK;
|
|
input PIPERX2VALID;
|
|
input PIPERX3DATAVALID;
|
|
input PIPERX3ELECIDLE;
|
|
input PIPERX3EQDONE;
|
|
input PIPERX3EQLPADAPTDONE;
|
|
input PIPERX3EQLPLFFSSEL;
|
|
input PIPERX3PHYSTATUS;
|
|
input PIPERX3STARTBLOCK;
|
|
input PIPERX3VALID;
|
|
input PIPERX4DATAVALID;
|
|
input PIPERX4ELECIDLE;
|
|
input PIPERX4EQDONE;
|
|
input PIPERX4EQLPADAPTDONE;
|
|
input PIPERX4EQLPLFFSSEL;
|
|
input PIPERX4PHYSTATUS;
|
|
input PIPERX4STARTBLOCK;
|
|
input PIPERX4VALID;
|
|
input PIPERX5DATAVALID;
|
|
input PIPERX5ELECIDLE;
|
|
input PIPERX5EQDONE;
|
|
input PIPERX5EQLPADAPTDONE;
|
|
input PIPERX5EQLPLFFSSEL;
|
|
input PIPERX5PHYSTATUS;
|
|
input PIPERX5STARTBLOCK;
|
|
input PIPERX5VALID;
|
|
input PIPERX6DATAVALID;
|
|
input PIPERX6ELECIDLE;
|
|
input PIPERX6EQDONE;
|
|
input PIPERX6EQLPADAPTDONE;
|
|
input PIPERX6EQLPLFFSSEL;
|
|
input PIPERX6PHYSTATUS;
|
|
input PIPERX6STARTBLOCK;
|
|
input PIPERX6VALID;
|
|
input PIPERX7DATAVALID;
|
|
input PIPERX7ELECIDLE;
|
|
input PIPERX7EQDONE;
|
|
input PIPERX7EQLPADAPTDONE;
|
|
input PIPERX7EQLPLFFSSEL;
|
|
input PIPERX7PHYSTATUS;
|
|
input PIPERX7STARTBLOCK;
|
|
input PIPERX7VALID;
|
|
input PIPETX0EQDONE;
|
|
input PIPETX1EQDONE;
|
|
input PIPETX2EQDONE;
|
|
input PIPETX3EQDONE;
|
|
input PIPETX4EQDONE;
|
|
input PIPETX5EQDONE;
|
|
input PIPETX6EQDONE;
|
|
input PIPETX7EQDONE;
|
|
input PLDISABLESCRAMBLER;
|
|
input PLEQRESETEIEOSCOUNT;
|
|
input PLGEN3PCSDISABLE;
|
|
input RECCLK;
|
|
input RESETN;
|
|
input SAXISCCTLAST;
|
|
input SAXISCCTVALID;
|
|
input SAXISRQTLAST;
|
|
input SAXISRQTVALID;
|
|
input USERCLK;
|
|
input [10:0] DRPADDR;
|
|
input [143:0] MICOMPLETIONRAMREADDATA;
|
|
input [143:0] MIREPLAYRAMREADDATA;
|
|
input [143:0] MIREQUESTRAMREADDATA;
|
|
input [15:0] CFGDEVID;
|
|
input [15:0] CFGSUBSYSID;
|
|
input [15:0] CFGSUBSYSVENDID;
|
|
input [15:0] CFGVENDID;
|
|
input [15:0] DRPDI;
|
|
input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET;
|
|
input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET;
|
|
input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET;
|
|
input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET;
|
|
input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET;
|
|
input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET;
|
|
input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET;
|
|
input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET;
|
|
input [17:0] PIPETX0EQCOEFF;
|
|
input [17:0] PIPETX1EQCOEFF;
|
|
input [17:0] PIPETX2EQCOEFF;
|
|
input [17:0] PIPETX3EQCOEFF;
|
|
input [17:0] PIPETX4EQCOEFF;
|
|
input [17:0] PIPETX5EQCOEFF;
|
|
input [17:0] PIPETX6EQCOEFF;
|
|
input [17:0] PIPETX7EQCOEFF;
|
|
input [18:0] CFGMGMTADDR;
|
|
input [1:0] CFGFLRDONE;
|
|
input [1:0] CFGINTERRUPTMSITPHTYPE;
|
|
input [1:0] CFGINTERRUPTPENDING;
|
|
input [1:0] PIPERX0CHARISK;
|
|
input [1:0] PIPERX0SYNCHEADER;
|
|
input [1:0] PIPERX1CHARISK;
|
|
input [1:0] PIPERX1SYNCHEADER;
|
|
input [1:0] PIPERX2CHARISK;
|
|
input [1:0] PIPERX2SYNCHEADER;
|
|
input [1:0] PIPERX3CHARISK;
|
|
input [1:0] PIPERX3SYNCHEADER;
|
|
input [1:0] PIPERX4CHARISK;
|
|
input [1:0] PIPERX4SYNCHEADER;
|
|
input [1:0] PIPERX5CHARISK;
|
|
input [1:0] PIPERX5SYNCHEADER;
|
|
input [1:0] PIPERX6CHARISK;
|
|
input [1:0] PIPERX6SYNCHEADER;
|
|
input [1:0] PIPERX7CHARISK;
|
|
input [1:0] PIPERX7SYNCHEADER;
|
|
input [21:0] MAXISCQTREADY;
|
|
input [21:0] MAXISRCTREADY;
|
|
input [255:0] SAXISCCTDATA;
|
|
input [255:0] SAXISRQTDATA;
|
|
input [2:0] CFGDSFUNCTIONNUMBER;
|
|
input [2:0] CFGFCSEL;
|
|
input [2:0] CFGINTERRUPTMSIATTR;
|
|
input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
|
|
input [2:0] CFGMSGTRANSMITTYPE;
|
|
input [2:0] CFGPERFUNCSTATUSCONTROL;
|
|
input [2:0] CFGPERFUNCTIONNUMBER;
|
|
input [2:0] PIPERX0STATUS;
|
|
input [2:0] PIPERX1STATUS;
|
|
input [2:0] PIPERX2STATUS;
|
|
input [2:0] PIPERX3STATUS;
|
|
input [2:0] PIPERX4STATUS;
|
|
input [2:0] PIPERX5STATUS;
|
|
input [2:0] PIPERX6STATUS;
|
|
input [2:0] PIPERX7STATUS;
|
|
input [31:0] CFGEXTREADDATA;
|
|
input [31:0] CFGINTERRUPTMSIINT;
|
|
input [31:0] CFGINTERRUPTMSIXDATA;
|
|
input [31:0] CFGMGMTWRITEDATA;
|
|
input [31:0] CFGMSGTRANSMITDATA;
|
|
input [31:0] CFGTPHSTTREADDATA;
|
|
input [31:0] PIPERX0DATA;
|
|
input [31:0] PIPERX1DATA;
|
|
input [31:0] PIPERX2DATA;
|
|
input [31:0] PIPERX3DATA;
|
|
input [31:0] PIPERX4DATA;
|
|
input [31:0] PIPERX5DATA;
|
|
input [31:0] PIPERX6DATA;
|
|
input [31:0] PIPERX7DATA;
|
|
input [32:0] SAXISCCTUSER;
|
|
input [3:0] CFGINTERRUPTINT;
|
|
input [3:0] CFGINTERRUPTMSISELECT;
|
|
input [3:0] CFGMGMTBYTEENABLE;
|
|
input [4:0] CFGDSDEVICENUMBER;
|
|
input [59:0] SAXISRQTUSER;
|
|
input [5:0] CFGVFFLRDONE;
|
|
input [5:0] PIPEEQFS;
|
|
input [5:0] PIPEEQLF;
|
|
input [63:0] CFGDSN;
|
|
input [63:0] CFGINTERRUPTMSIPENDINGSTATUS;
|
|
input [63:0] CFGINTERRUPTMSIXADDRESS;
|
|
input [7:0] CFGDSBUSNUMBER;
|
|
input [7:0] CFGDSPORTNUMBER;
|
|
input [7:0] CFGREVID;
|
|
input [7:0] PLGEN3PCSRXSYNCDONE;
|
|
input [7:0] SAXISCCTKEEP;
|
|
input [7:0] SAXISRQTKEEP;
|
|
input [8:0] CFGINTERRUPTMSITPHSTTAG;
|
|
endmodule
|
|
|
|
module PCIE_3_1(CFGCURRENTSPEED, CFGDPASUBSTATECHANGE, CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTFUNCTIONNUMBER, CFGEXTREADRECEIVED, CFGEXTREGISTERNUMBER, CFGEXTWRITEBYTEENABLE, CFGEXTWRITEDATA, CFGEXTWRITERECEIVED, CFGFCCPLD, CFGFCCPLH, CFGFCNPD, CFGFCNPH, CFGFCPD, CFGFCPH, CFGFLRINPROCESS, CFGFUNCTIONPOWERSTATE, CFGFUNCTIONSTATUS, CFGHOTRESETOUT
|
|
, CFGINTERRUPTMSIDATA, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIVFENABLE, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXFAIL, CFGINTERRUPTMSIXMASK, CFGINTERRUPTMSIXSENT, CFGINTERRUPTMSIXVFENABLE, CFGINTERRUPTMSIXVFMASK, CFGINTERRUPTSENT, CFGLINKPOWERSTATE, CFGLOCALERROR, CFGLTRENABLE, CFGLTSSMSTATE, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGMGMTREADDATA
|
|
, CFGMGMTREADWRITEDONE, CFGMSGRECEIVED, CFGMSGRECEIVEDDATA, CFGMSGRECEIVEDTYPE, CFGMSGTRANSMITDONE, CFGNEGOTIATEDWIDTH, CFGOBFFENABLE, CFGPERFUNCSTATUSDATA, CFGPERFUNCTIONUPDATEDONE, CFGPHYLINKDOWN, CFGPHYLINKSTATUS, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGRCBSTATUS, CFGTPHFUNCTIONNUM, CFGTPHREQUESTERENABLE, CFGTPHSTMODE, CFGTPHSTTADDRESS, CFGTPHSTTREADENABLE, CFGTPHSTTWRITEBYTEVALID, CFGTPHSTTWRITEDATA
|
|
, CFGTPHSTTWRITEENABLE, CFGVFFLRINPROCESS, CFGVFPOWERSTATE, CFGVFSTATUS, CFGVFTPHREQUESTERENABLE, CFGVFTPHSTMODE, CONFMCAPDESIGNSWITCH, CONFMCAPEOS, CONFMCAPINUSEBYPCIE, CONFREQREADY, CONFRESPRDATA, CONFRESPVALID, DBGDATAOUT, DBGMCAPCSB, DBGMCAPDATA, DBGMCAPEOS, DBGMCAPERROR, DBGMCAPMODE, DBGMCAPRDATAVALID, DBGMCAPRDWRB, DBGMCAPRESET
|
|
, DBGPLDATABLOCKRECEIVEDAFTEREDS, DBGPLGEN3FRAMINGERRORDETECTED, DBGPLGEN3SYNCHEADERERRORDETECTED, DBGPLINFERREDRXELECTRICALIDLE, DRPDO, DRPRDY, LL2LMMASTERTLPSENT0, LL2LMMASTERTLPSENT1, LL2LMMASTERTLPSENTTLPID0, LL2LMMASTERTLPSENTTLPID1, LL2LMMAXISRXTDATA, LL2LMMAXISRXTUSER, LL2LMMAXISRXTVALID, LL2LMSAXISTXTREADY, MAXISCQTDATA, MAXISCQTKEEP, MAXISCQTLAST, MAXISCQTUSER, MAXISCQTVALID, MAXISRCTDATA, MAXISRCTKEEP
|
|
, MAXISRCTLAST, MAXISRCTUSER, MAXISRCTVALID, MICOMPLETIONRAMREADADDRESSAL, MICOMPLETIONRAMREADADDRESSAU, MICOMPLETIONRAMREADADDRESSBL, MICOMPLETIONRAMREADADDRESSBU, MICOMPLETIONRAMREADENABLEL, MICOMPLETIONRAMREADENABLEU, MICOMPLETIONRAMWRITEADDRESSAL, MICOMPLETIONRAMWRITEADDRESSAU, MICOMPLETIONRAMWRITEADDRESSBL, MICOMPLETIONRAMWRITEADDRESSBU, MICOMPLETIONRAMWRITEDATAL, MICOMPLETIONRAMWRITEDATAU, MICOMPLETIONRAMWRITEENABLEL, MICOMPLETIONRAMWRITEENABLEU, MIREPLAYRAMADDRESS, MIREPLAYRAMREADENABLE, MIREPLAYRAMWRITEDATA, MIREPLAYRAMWRITEENABLE
|
|
, MIREQUESTRAMREADADDRESSA, MIREQUESTRAMREADADDRESSB, MIREQUESTRAMREADENABLE, MIREQUESTRAMWRITEADDRESSA, MIREQUESTRAMWRITEADDRESSB, MIREQUESTRAMWRITEDATA, MIREQUESTRAMWRITEENABLE, PCIECQNPREQCOUNT, PCIEPERST0B, PCIEPERST1B, PCIERQSEQNUM, PCIERQSEQNUMVLD, PCIERQTAG, PCIERQTAGAV, PCIERQTAGVLD, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX0EQCONTROL, PIPERX0EQLPLFFS, PIPERX0EQLPTXPRESET, PIPERX0EQPRESET
|
|
, PIPERX0POLARITY, PIPERX1EQCONTROL, PIPERX1EQLPLFFS, PIPERX1EQLPTXPRESET, PIPERX1EQPRESET, PIPERX1POLARITY, PIPERX2EQCONTROL, PIPERX2EQLPLFFS, PIPERX2EQLPTXPRESET, PIPERX2EQPRESET, PIPERX2POLARITY, PIPERX3EQCONTROL, PIPERX3EQLPLFFS, PIPERX3EQLPTXPRESET, PIPERX3EQPRESET, PIPERX3POLARITY, PIPERX4EQCONTROL, PIPERX4EQLPLFFS, PIPERX4EQLPTXPRESET, PIPERX4EQPRESET, PIPERX4POLARITY
|
|
, PIPERX5EQCONTROL, PIPERX5EQLPLFFS, PIPERX5EQLPTXPRESET, PIPERX5EQPRESET, PIPERX5POLARITY, PIPERX6EQCONTROL, PIPERX6EQLPLFFS, PIPERX6EQLPTXPRESET, PIPERX6EQPRESET, PIPERX6POLARITY, PIPERX7EQCONTROL, PIPERX7EQLPLFFS, PIPERX7EQLPTXPRESET, PIPERX7EQPRESET, PIPERX7POLARITY, PIPETX0CHARISK, PIPETX0COMPLIANCE, PIPETX0DATA, PIPETX0DATAVALID, PIPETX0DEEMPH, PIPETX0ELECIDLE
|
|
, PIPETX0EQCONTROL, PIPETX0EQDEEMPH, PIPETX0EQPRESET, PIPETX0MARGIN, PIPETX0POWERDOWN, PIPETX0RATE, PIPETX0RCVRDET, PIPETX0RESET, PIPETX0STARTBLOCK, PIPETX0SWING, PIPETX0SYNCHEADER, PIPETX1CHARISK, PIPETX1COMPLIANCE, PIPETX1DATA, PIPETX1DATAVALID, PIPETX1DEEMPH, PIPETX1ELECIDLE, PIPETX1EQCONTROL, PIPETX1EQDEEMPH, PIPETX1EQPRESET, PIPETX1MARGIN
|
|
, PIPETX1POWERDOWN, PIPETX1RATE, PIPETX1RCVRDET, PIPETX1RESET, PIPETX1STARTBLOCK, PIPETX1SWING, PIPETX1SYNCHEADER, PIPETX2CHARISK, PIPETX2COMPLIANCE, PIPETX2DATA, PIPETX2DATAVALID, PIPETX2DEEMPH, PIPETX2ELECIDLE, PIPETX2EQCONTROL, PIPETX2EQDEEMPH, PIPETX2EQPRESET, PIPETX2MARGIN, PIPETX2POWERDOWN, PIPETX2RATE, PIPETX2RCVRDET, PIPETX2RESET
|
|
, PIPETX2STARTBLOCK, PIPETX2SWING, PIPETX2SYNCHEADER, PIPETX3CHARISK, PIPETX3COMPLIANCE, PIPETX3DATA, PIPETX3DATAVALID, PIPETX3DEEMPH, PIPETX3ELECIDLE, PIPETX3EQCONTROL, PIPETX3EQDEEMPH, PIPETX3EQPRESET, PIPETX3MARGIN, PIPETX3POWERDOWN, PIPETX3RATE, PIPETX3RCVRDET, PIPETX3RESET, PIPETX3STARTBLOCK, PIPETX3SWING, PIPETX3SYNCHEADER, PIPETX4CHARISK
|
|
, PIPETX4COMPLIANCE, PIPETX4DATA, PIPETX4DATAVALID, PIPETX4DEEMPH, PIPETX4ELECIDLE, PIPETX4EQCONTROL, PIPETX4EQDEEMPH, PIPETX4EQPRESET, PIPETX4MARGIN, PIPETX4POWERDOWN, PIPETX4RATE, PIPETX4RCVRDET, PIPETX4RESET, PIPETX4STARTBLOCK, PIPETX4SWING, PIPETX4SYNCHEADER, PIPETX5CHARISK, PIPETX5COMPLIANCE, PIPETX5DATA, PIPETX5DATAVALID, PIPETX5DEEMPH
|
|
, PIPETX5ELECIDLE, PIPETX5EQCONTROL, PIPETX5EQDEEMPH, PIPETX5EQPRESET, PIPETX5MARGIN, PIPETX5POWERDOWN, PIPETX5RATE, PIPETX5RCVRDET, PIPETX5RESET, PIPETX5STARTBLOCK, PIPETX5SWING, PIPETX5SYNCHEADER, PIPETX6CHARISK, PIPETX6COMPLIANCE, PIPETX6DATA, PIPETX6DATAVALID, PIPETX6DEEMPH, PIPETX6ELECIDLE, PIPETX6EQCONTROL, PIPETX6EQDEEMPH, PIPETX6EQPRESET
|
|
, PIPETX6MARGIN, PIPETX6POWERDOWN, PIPETX6RATE, PIPETX6RCVRDET, PIPETX6RESET, PIPETX6STARTBLOCK, PIPETX6SWING, PIPETX6SYNCHEADER, PIPETX7CHARISK, PIPETX7COMPLIANCE, PIPETX7DATA, PIPETX7DATAVALID, PIPETX7DEEMPH, PIPETX7ELECIDLE, PIPETX7EQCONTROL, PIPETX7EQDEEMPH, PIPETX7EQPRESET, PIPETX7MARGIN, PIPETX7POWERDOWN, PIPETX7RATE, PIPETX7RCVRDET
|
|
, PIPETX7RESET, PIPETX7STARTBLOCK, PIPETX7SWING, PIPETX7SYNCHEADER, PLEQINPROGRESS, PLEQPHASE, SAXISCCTREADY, SAXISRQTREADY, SPAREOUT, CFGCONFIGSPACEENABLE, CFGDEVID, CFGDSBUSNUMBER, CFGDSDEVICENUMBER, CFGDSFUNCTIONNUMBER, CFGDSN, CFGDSPORTNUMBER, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATA, CFGEXTREADDATAVALID, CFGFCSEL
|
|
, CFGFLRDONE, CFGHOTRESETIN, CFGINTERRUPTINT, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIPENDINGSTATUS, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, CFGINTERRUPTMSISELECT, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSITPHSTTAG, CFGINTERRUPTMSITPHTYPE, CFGINTERRUPTMSIXADDRESS, CFGINTERRUPTMSIXDATA, CFGINTERRUPTMSIXINT, CFGINTERRUPTPENDING, CFGLINKTRAININGENABLE, CFGMGMTADDR, CFGMGMTBYTEENABLE, CFGMGMTREAD
|
|
, CFGMGMTTYPE1CFGREGACCESS, CFGMGMTWRITE, CFGMGMTWRITEDATA, CFGMSGTRANSMIT, CFGMSGTRANSMITDATA, CFGMSGTRANSMITTYPE, CFGPERFUNCSTATUSCONTROL, CFGPERFUNCTIONNUMBER, CFGPERFUNCTIONOUTPUTREQUEST, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY, CFGREVID, CFGSUBSYSID, CFGSUBSYSVENDID, CFGTPHSTTREADDATA, CFGTPHSTTREADDATAVALID, CFGVENDID, CFGVFFLRDONE, CONFMCAPREQUESTBYCONF, CONFREQDATA, CONFREQREGNUM
|
|
, CONFREQTYPE, CONFREQVALID, CORECLK, CORECLKMICOMPLETIONRAML, CORECLKMICOMPLETIONRAMU, CORECLKMIREPLAYRAM, CORECLKMIREQUESTRAM, DBGCFGLOCALMGMTREGOVERRIDE, DBGDATASEL, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, LL2LMSAXISTXTUSER, LL2LMSAXISTXTVALID, LL2LMTXTLPID0, LL2LMTXTLPID1, MAXISCQTREADY, MAXISRCTREADY, MCAPCLK
|
|
, MCAPPERST0B, MCAPPERST1B, MGMTRESETN, MGMTSTICKYRESETN, MICOMPLETIONRAMREADDATA, MIREPLAYRAMREADDATA, MIREQUESTRAMREADDATA, PCIECQNPREQ, PIPECLK, PIPEEQFS, PIPEEQLF, PIPERESETN, PIPERX0CHARISK, PIPERX0DATA, PIPERX0DATAVALID, PIPERX0ELECIDLE, PIPERX0EQDONE, PIPERX0EQLPADAPTDONE, PIPERX0EQLPLFFSSEL, PIPERX0EQLPNEWTXCOEFFORPRESET, PIPERX0PHYSTATUS
|
|
, PIPERX0STARTBLOCK, PIPERX0STATUS, PIPERX0SYNCHEADER, PIPERX0VALID, PIPERX1CHARISK, PIPERX1DATA, PIPERX1DATAVALID, PIPERX1ELECIDLE, PIPERX1EQDONE, PIPERX1EQLPADAPTDONE, PIPERX1EQLPLFFSSEL, PIPERX1EQLPNEWTXCOEFFORPRESET, PIPERX1PHYSTATUS, PIPERX1STARTBLOCK, PIPERX1STATUS, PIPERX1SYNCHEADER, PIPERX1VALID, PIPERX2CHARISK, PIPERX2DATA, PIPERX2DATAVALID, PIPERX2ELECIDLE
|
|
, PIPERX2EQDONE, PIPERX2EQLPADAPTDONE, PIPERX2EQLPLFFSSEL, PIPERX2EQLPNEWTXCOEFFORPRESET, PIPERX2PHYSTATUS, PIPERX2STARTBLOCK, PIPERX2STATUS, PIPERX2SYNCHEADER, PIPERX2VALID, PIPERX3CHARISK, PIPERX3DATA, PIPERX3DATAVALID, PIPERX3ELECIDLE, PIPERX3EQDONE, PIPERX3EQLPADAPTDONE, PIPERX3EQLPLFFSSEL, PIPERX3EQLPNEWTXCOEFFORPRESET, PIPERX3PHYSTATUS, PIPERX3STARTBLOCK, PIPERX3STATUS, PIPERX3SYNCHEADER
|
|
, PIPERX3VALID, PIPERX4CHARISK, PIPERX4DATA, PIPERX4DATAVALID, PIPERX4ELECIDLE, PIPERX4EQDONE, PIPERX4EQLPADAPTDONE, PIPERX4EQLPLFFSSEL, PIPERX4EQLPNEWTXCOEFFORPRESET, PIPERX4PHYSTATUS, PIPERX4STARTBLOCK, PIPERX4STATUS, PIPERX4SYNCHEADER, PIPERX4VALID, PIPERX5CHARISK, PIPERX5DATA, PIPERX5DATAVALID, PIPERX5ELECIDLE, PIPERX5EQDONE, PIPERX5EQLPADAPTDONE, PIPERX5EQLPLFFSSEL
|
|
, PIPERX5EQLPNEWTXCOEFFORPRESET, PIPERX5PHYSTATUS, PIPERX5STARTBLOCK, PIPERX5STATUS, PIPERX5SYNCHEADER, PIPERX5VALID, PIPERX6CHARISK, PIPERX6DATA, PIPERX6DATAVALID, PIPERX6ELECIDLE, PIPERX6EQDONE, PIPERX6EQLPADAPTDONE, PIPERX6EQLPLFFSSEL, PIPERX6EQLPNEWTXCOEFFORPRESET, PIPERX6PHYSTATUS, PIPERX6STARTBLOCK, PIPERX6STATUS, PIPERX6SYNCHEADER, PIPERX6VALID, PIPERX7CHARISK, PIPERX7DATA
|
|
, PIPERX7DATAVALID, PIPERX7ELECIDLE, PIPERX7EQDONE, PIPERX7EQLPADAPTDONE, PIPERX7EQLPLFFSSEL, PIPERX7EQLPNEWTXCOEFFORPRESET, PIPERX7PHYSTATUS, PIPERX7STARTBLOCK, PIPERX7STATUS, PIPERX7SYNCHEADER, PIPERX7VALID, PIPETX0EQCOEFF, PIPETX0EQDONE, PIPETX1EQCOEFF, PIPETX1EQDONE, PIPETX2EQCOEFF, PIPETX2EQDONE, PIPETX3EQCOEFF, PIPETX3EQDONE, PIPETX4EQCOEFF, PIPETX4EQDONE
|
|
, PIPETX5EQCOEFF, PIPETX5EQDONE, PIPETX6EQCOEFF, PIPETX6EQDONE, PIPETX7EQCOEFF, PIPETX7EQDONE, PLEQRESETEIEOSCOUNT, PLGEN2UPSTREAMPREFERDEEMPH, RESETN, SAXISCCTDATA, SAXISCCTKEEP, SAXISCCTLAST, SAXISCCTUSER, SAXISCCTVALID, SAXISRQTDATA, SAXISRQTKEEP, SAXISRQTLAST, SAXISRQTUSER, SAXISRQTVALID, SPAREIN, USERCLK
|
|
);
|
|
parameter ARI_CAP_ENABLE = "FALSE";
|
|
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE";
|
|
parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE";
|
|
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
|
|
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
|
|
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
|
|
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE";
|
|
parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE";
|
|
parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE";
|
|
parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
|
|
parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
|
|
parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
|
|
parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
|
|
parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE";
|
|
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
|
|
parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
|
|
parameter LL_ACK_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
|
|
parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000;
|
|
parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
|
|
parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000;
|
|
parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
|
|
parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000;
|
|
parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
|
|
parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000;
|
|
parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
|
|
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
|
|
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
|
|
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA;
|
|
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
|
|
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
|
|
parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000;
|
|
parameter MCAP_CONFIGURE_OVERRIDE = "FALSE";
|
|
parameter MCAP_ENABLE = "FALSE";
|
|
parameter MCAP_EOS_DESIGN_SWITCH = "FALSE";
|
|
parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000;
|
|
parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE";
|
|
parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE";
|
|
parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE";
|
|
parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE";
|
|
parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE";
|
|
parameter [15:0] MCAP_VSEC_ID = 16'h0000;
|
|
parameter [11:0] MCAP_VSEC_LEN = 12'h02C;
|
|
parameter [3:0] MCAP_VSEC_REV = 4'h0;
|
|
parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
|
|
parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
|
|
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
|
|
parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
|
|
parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00;
|
|
parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF0_BIST_REGISTER = 8'h00;
|
|
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50;
|
|
parameter [23:0] PF0_CLASS_CODE = 24'h000000;
|
|
parameter [15:0] PF0_DEVICE_ID = 16'h0000;
|
|
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE";
|
|
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
|
|
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
|
|
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
|
|
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
|
|
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
|
|
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
|
|
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
|
|
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
|
|
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
|
|
parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
|
|
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
|
|
parameter [3:0] PF0_DPA_CAP_VER = 4'h1;
|
|
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [7:0] PF0_INTERRUPT_LINE = 8'h00;
|
|
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
|
|
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
|
|
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
|
|
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
|
|
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
|
|
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
|
|
parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
|
|
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000;
|
|
parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000;
|
|
parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000;
|
|
parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000;
|
|
parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000;
|
|
parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
|
|
parameter [3:0] PF0_PB_CAP_VER = 4'h1;
|
|
parameter [7:0] PF0_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
|
|
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
|
|
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
|
|
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
|
|
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
|
|
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
|
|
parameter PF0_RBAR_CAP_ENABLE = "FALSE";
|
|
parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000;
|
|
parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000;
|
|
parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000;
|
|
parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000;
|
|
parameter [3:0] PF0_RBAR_CAP_VER = 4'h1;
|
|
parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0;
|
|
parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0;
|
|
parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0;
|
|
parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00;
|
|
parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00;
|
|
parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00;
|
|
parameter [2:0] PF0_RBAR_NUM = 3'h1;
|
|
parameter [7:0] PF0_REVISION_ID = 8'h00;
|
|
parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000;
|
|
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter PF0_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
|
|
parameter PF0_VC_CAP_ENABLE = "FALSE";
|
|
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
|
|
parameter [3:0] PF0_VC_CAP_VER = 4'h1;
|
|
parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
|
|
parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
|
|
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
|
|
parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00;
|
|
parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF1_BIST_REGISTER = 8'h00;
|
|
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50;
|
|
parameter [23:0] PF1_CLASS_CODE = 24'h000000;
|
|
parameter [15:0] PF1_DEVICE_ID = 16'h0000;
|
|
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
|
|
parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
|
|
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
|
|
parameter [3:0] PF1_DPA_CAP_VER = 4'h1;
|
|
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [7:0] PF1_INTERRUPT_LINE = 8'h00;
|
|
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000;
|
|
parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000;
|
|
parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000;
|
|
parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000;
|
|
parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000;
|
|
parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
|
|
parameter [3:0] PF1_PB_CAP_VER = 4'h1;
|
|
parameter [7:0] PF1_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3;
|
|
parameter PF1_RBAR_CAP_ENABLE = "FALSE";
|
|
parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000;
|
|
parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000;
|
|
parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000;
|
|
parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000;
|
|
parameter [3:0] PF1_RBAR_CAP_VER = 4'h1;
|
|
parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0;
|
|
parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0;
|
|
parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0;
|
|
parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00;
|
|
parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00;
|
|
parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00;
|
|
parameter [2:0] PF1_RBAR_NUM = 3'h1;
|
|
parameter [7:0] PF1_REVISION_ID = 8'h00;
|
|
parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000;
|
|
parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter PF1_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] PF1_TPHR_CAP_VER = 4'h1;
|
|
parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
|
|
parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
|
|
parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_BAR0_CONTROL = 3'h4;
|
|
parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00;
|
|
parameter [2:0] PF2_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF2_BIST_REGISTER = 8'h00;
|
|
parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50;
|
|
parameter [23:0] PF2_CLASS_CODE = 24'h000000;
|
|
parameter [15:0] PF2_DEVICE_ID = 16'h0000;
|
|
parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
|
|
parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
|
|
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
|
|
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
|
|
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
|
|
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
|
|
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
|
|
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
|
|
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
|
|
parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
|
|
parameter [3:0] PF2_DPA_CAP_VER = 4'h1;
|
|
parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF2_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [7:0] PF2_INTERRUPT_LINE = 8'h00;
|
|
parameter [2:0] PF2_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF2_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF2_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000;
|
|
parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000;
|
|
parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000;
|
|
parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000;
|
|
parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000;
|
|
parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
|
|
parameter [3:0] PF2_PB_CAP_VER = 4'h1;
|
|
parameter [7:0] PF2_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3;
|
|
parameter PF2_RBAR_CAP_ENABLE = "FALSE";
|
|
parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000;
|
|
parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000;
|
|
parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000;
|
|
parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000;
|
|
parameter [3:0] PF2_RBAR_CAP_VER = 4'h1;
|
|
parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0;
|
|
parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0;
|
|
parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0;
|
|
parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00;
|
|
parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00;
|
|
parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00;
|
|
parameter [2:0] PF2_RBAR_NUM = 3'h1;
|
|
parameter [7:0] PF2_REVISION_ID = 8'h00;
|
|
parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000;
|
|
parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter PF2_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] PF2_TPHR_CAP_VER = 4'h1;
|
|
parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
|
|
parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
|
|
parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_BAR0_CONTROL = 3'h4;
|
|
parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00;
|
|
parameter [2:0] PF3_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF3_BIST_REGISTER = 8'h00;
|
|
parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50;
|
|
parameter [23:0] PF3_CLASS_CODE = 24'h000000;
|
|
parameter [15:0] PF3_DEVICE_ID = 16'h0000;
|
|
parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
|
|
parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
|
|
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
|
|
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
|
|
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
|
|
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
|
|
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
|
|
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
|
|
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
|
|
parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
|
|
parameter [3:0] PF3_DPA_CAP_VER = 4'h1;
|
|
parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF3_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [7:0] PF3_INTERRUPT_LINE = 8'h00;
|
|
parameter [2:0] PF3_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF3_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF3_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000;
|
|
parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000;
|
|
parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000;
|
|
parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000;
|
|
parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000;
|
|
parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
|
|
parameter [3:0] PF3_PB_CAP_VER = 4'h1;
|
|
parameter [7:0] PF3_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3;
|
|
parameter PF3_RBAR_CAP_ENABLE = "FALSE";
|
|
parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000;
|
|
parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000;
|
|
parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000;
|
|
parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000;
|
|
parameter [3:0] PF3_RBAR_CAP_VER = 4'h1;
|
|
parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0;
|
|
parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0;
|
|
parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0;
|
|
parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00;
|
|
parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00;
|
|
parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00;
|
|
parameter [2:0] PF3_RBAR_NUM = 3'h1;
|
|
parameter [7:0] PF3_REVISION_ID = 8'h00;
|
|
parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000;
|
|
parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter PF3_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] PF3_TPHR_CAP_VER = 4'h1;
|
|
parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE";
|
|
parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE";
|
|
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
|
|
parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE";
|
|
parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "TRUE";
|
|
parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE";
|
|
parameter PL_DISABLE_SCRAMBLING = "FALSE";
|
|
parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE";
|
|
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
|
|
parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE";
|
|
parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE";
|
|
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
|
|
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
|
|
parameter PL_EQ_BYPASS_PHASE23 = "FALSE";
|
|
parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3;
|
|
parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4;
|
|
parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE";
|
|
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
|
|
parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00;
|
|
parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00;
|
|
parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4;
|
|
parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8;
|
|
parameter integer PL_N_FTS_COMCLK_GEN1 = 255;
|
|
parameter integer PL_N_FTS_COMCLK_GEN2 = 255;
|
|
parameter integer PL_N_FTS_COMCLK_GEN3 = 255;
|
|
parameter integer PL_N_FTS_GEN1 = 255;
|
|
parameter integer PL_N_FTS_GEN2 = 255;
|
|
parameter integer PL_N_FTS_GEN3 = 255;
|
|
parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE";
|
|
parameter PL_SIM_FAST_LINK_TRAINING = "FALSE";
|
|
parameter PL_UPSTREAM_FACING = "TRUE";
|
|
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC;
|
|
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000;
|
|
parameter PM_ENABLE_L23_ENTRY = "FALSE";
|
|
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
|
|
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000;
|
|
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0;
|
|
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064;
|
|
parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000;
|
|
parameter SIM_VERSION = "1.0";
|
|
parameter integer SPARE_BIT0 = 0;
|
|
parameter integer SPARE_BIT1 = 0;
|
|
parameter integer SPARE_BIT2 = 0;
|
|
parameter integer SPARE_BIT3 = 0;
|
|
parameter integer SPARE_BIT4 = 0;
|
|
parameter integer SPARE_BIT5 = 0;
|
|
parameter integer SPARE_BIT6 = 0;
|
|
parameter integer SPARE_BIT7 = 0;
|
|
parameter integer SPARE_BIT8 = 0;
|
|
parameter [7:0] SPARE_BYTE0 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE1 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE2 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE3 = 8'h00;
|
|
parameter [31:0] SPARE_WORD0 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD1 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD2 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD3 = 32'h00000000;
|
|
parameter SRIOV_CAP_ENABLE = "FALSE";
|
|
parameter TL_COMPLETION_RAM_SIZE_16K = "TRUE";
|
|
parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
|
|
parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2FAF080;
|
|
parameter [11:0] TL_CREDITS_CD = 12'h3E0;
|
|
parameter [7:0] TL_CREDITS_CH = 8'h20;
|
|
parameter [11:0] TL_CREDITS_NPD = 12'h028;
|
|
parameter [7:0] TL_CREDITS_NPH = 8'h20;
|
|
parameter [11:0] TL_CREDITS_PD = 12'h198;
|
|
parameter [7:0] TL_CREDITS_PH = 8'h20;
|
|
parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE";
|
|
parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
|
|
parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
|
|
parameter TL_LEGACY_MODE_ENABLE = "FALSE";
|
|
parameter [1:0] TL_PF_ENABLE_REG = 2'h0;
|
|
parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE";
|
|
parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE";
|
|
parameter TWO_LAYER_MODE_ENABLE = "FALSE";
|
|
parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE";
|
|
parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50;
|
|
parameter integer VF0_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF0_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF0_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF0_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF0_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF1_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF1_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF1_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF1_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF1_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF2_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF2_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF2_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF2_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF2_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF3_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF3_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF3_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF3_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF3_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF4_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF4_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF4_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF4_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF4_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF5_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF5_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF5_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF5_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF5_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF6_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF6_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF6_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF6_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF6_TPHR_CAP_VER = 4'h1;
|
|
parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter integer VF7_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VF7_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] VF7_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3;
|
|
parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter VF7_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] VF7_TPHR_CAP_VER = 4'h1;
|
|
output [2:0] CFGCURRENTSPEED;
|
|
output [3:0] CFGDPASUBSTATECHANGE;
|
|
output CFGERRCOROUT;
|
|
output CFGERRFATALOUT;
|
|
output CFGERRNONFATALOUT;
|
|
output [7:0] CFGEXTFUNCTIONNUMBER;
|
|
output CFGEXTREADRECEIVED;
|
|
output [9:0] CFGEXTREGISTERNUMBER;
|
|
output [3:0] CFGEXTWRITEBYTEENABLE;
|
|
output [31:0] CFGEXTWRITEDATA;
|
|
output CFGEXTWRITERECEIVED;
|
|
output [11:0] CFGFCCPLD;
|
|
output [7:0] CFGFCCPLH;
|
|
output [11:0] CFGFCNPD;
|
|
output [7:0] CFGFCNPH;
|
|
output [11:0] CFGFCPD;
|
|
output [7:0] CFGFCPH;
|
|
output [3:0] CFGFLRINPROCESS;
|
|
output [11:0] CFGFUNCTIONPOWERSTATE;
|
|
output [15:0] CFGFUNCTIONSTATUS;
|
|
output CFGHOTRESETOUT;
|
|
output [31:0] CFGINTERRUPTMSIDATA;
|
|
output [3:0] CFGINTERRUPTMSIENABLE;
|
|
output CFGINTERRUPTMSIFAIL;
|
|
output CFGINTERRUPTMSIMASKUPDATE;
|
|
output [11:0] CFGINTERRUPTMSIMMENABLE;
|
|
output CFGINTERRUPTMSISENT;
|
|
output [7:0] CFGINTERRUPTMSIVFENABLE;
|
|
output [3:0] CFGINTERRUPTMSIXENABLE;
|
|
output CFGINTERRUPTMSIXFAIL;
|
|
output [3:0] CFGINTERRUPTMSIXMASK;
|
|
output CFGINTERRUPTMSIXSENT;
|
|
output [7:0] CFGINTERRUPTMSIXVFENABLE;
|
|
output [7:0] CFGINTERRUPTMSIXVFMASK;
|
|
output CFGINTERRUPTSENT;
|
|
output [1:0] CFGLINKPOWERSTATE;
|
|
output CFGLOCALERROR;
|
|
output CFGLTRENABLE;
|
|
output [5:0] CFGLTSSMSTATE;
|
|
output [2:0] CFGMAXPAYLOAD;
|
|
output [2:0] CFGMAXREADREQ;
|
|
output [31:0] CFGMGMTREADDATA;
|
|
output CFGMGMTREADWRITEDONE;
|
|
output CFGMSGRECEIVED;
|
|
output [7:0] CFGMSGRECEIVEDDATA;
|
|
output [4:0] CFGMSGRECEIVEDTYPE;
|
|
output CFGMSGTRANSMITDONE;
|
|
output [3:0] CFGNEGOTIATEDWIDTH;
|
|
output [1:0] CFGOBFFENABLE;
|
|
output [15:0] CFGPERFUNCSTATUSDATA;
|
|
output CFGPERFUNCTIONUPDATEDONE;
|
|
output CFGPHYLINKDOWN;
|
|
output [1:0] CFGPHYLINKSTATUS;
|
|
output CFGPLSTATUSCHANGE;
|
|
output CFGPOWERSTATECHANGEINTERRUPT;
|
|
output [3:0] CFGRCBSTATUS;
|
|
output [3:0] CFGTPHFUNCTIONNUM;
|
|
output [3:0] CFGTPHREQUESTERENABLE;
|
|
output [11:0] CFGTPHSTMODE;
|
|
output [4:0] CFGTPHSTTADDRESS;
|
|
output CFGTPHSTTREADENABLE;
|
|
output [3:0] CFGTPHSTTWRITEBYTEVALID;
|
|
output [31:0] CFGTPHSTTWRITEDATA;
|
|
output CFGTPHSTTWRITEENABLE;
|
|
output [7:0] CFGVFFLRINPROCESS;
|
|
output [23:0] CFGVFPOWERSTATE;
|
|
output [15:0] CFGVFSTATUS;
|
|
output [7:0] CFGVFTPHREQUESTERENABLE;
|
|
output [23:0] CFGVFTPHSTMODE;
|
|
output CONFMCAPDESIGNSWITCH;
|
|
output CONFMCAPEOS;
|
|
output CONFMCAPINUSEBYPCIE;
|
|
output CONFREQREADY;
|
|
output [31:0] CONFRESPRDATA;
|
|
output CONFRESPVALID;
|
|
output [15:0] DBGDATAOUT;
|
|
output DBGMCAPCSB;
|
|
output [31:0] DBGMCAPDATA;
|
|
output DBGMCAPEOS;
|
|
output DBGMCAPERROR;
|
|
output DBGMCAPMODE;
|
|
output DBGMCAPRDATAVALID;
|
|
output DBGMCAPRDWRB;
|
|
output DBGMCAPRESET;
|
|
output DBGPLDATABLOCKRECEIVEDAFTEREDS;
|
|
output DBGPLGEN3FRAMINGERRORDETECTED;
|
|
output DBGPLGEN3SYNCHEADERERRORDETECTED;
|
|
output [7:0] DBGPLINFERREDRXELECTRICALIDLE;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output LL2LMMASTERTLPSENT0;
|
|
output LL2LMMASTERTLPSENT1;
|
|
output [3:0] LL2LMMASTERTLPSENTTLPID0;
|
|
output [3:0] LL2LMMASTERTLPSENTTLPID1;
|
|
output [255:0] LL2LMMAXISRXTDATA;
|
|
output [17:0] LL2LMMAXISRXTUSER;
|
|
output [7:0] LL2LMMAXISRXTVALID;
|
|
output [7:0] LL2LMSAXISTXTREADY;
|
|
output [255:0] MAXISCQTDATA;
|
|
output [7:0] MAXISCQTKEEP;
|
|
output MAXISCQTLAST;
|
|
output [84:0] MAXISCQTUSER;
|
|
output MAXISCQTVALID;
|
|
output [255:0] MAXISRCTDATA;
|
|
output [7:0] MAXISRCTKEEP;
|
|
output MAXISRCTLAST;
|
|
output [74:0] MAXISRCTUSER;
|
|
output MAXISRCTVALID;
|
|
output [9:0] MICOMPLETIONRAMREADADDRESSAL;
|
|
output [9:0] MICOMPLETIONRAMREADADDRESSAU;
|
|
output [9:0] MICOMPLETIONRAMREADADDRESSBL;
|
|
output [9:0] MICOMPLETIONRAMREADADDRESSBU;
|
|
output [3:0] MICOMPLETIONRAMREADENABLEL;
|
|
output [3:0] MICOMPLETIONRAMREADENABLEU;
|
|
output [9:0] MICOMPLETIONRAMWRITEADDRESSAL;
|
|
output [9:0] MICOMPLETIONRAMWRITEADDRESSAU;
|
|
output [9:0] MICOMPLETIONRAMWRITEADDRESSBL;
|
|
output [9:0] MICOMPLETIONRAMWRITEADDRESSBU;
|
|
output [71:0] MICOMPLETIONRAMWRITEDATAL;
|
|
output [71:0] MICOMPLETIONRAMWRITEDATAU;
|
|
output [3:0] MICOMPLETIONRAMWRITEENABLEL;
|
|
output [3:0] MICOMPLETIONRAMWRITEENABLEU;
|
|
output [8:0] MIREPLAYRAMADDRESS;
|
|
output [1:0] MIREPLAYRAMREADENABLE;
|
|
output [143:0] MIREPLAYRAMWRITEDATA;
|
|
output [1:0] MIREPLAYRAMWRITEENABLE;
|
|
output [8:0] MIREQUESTRAMREADADDRESSA;
|
|
output [8:0] MIREQUESTRAMREADADDRESSB;
|
|
output [3:0] MIREQUESTRAMREADENABLE;
|
|
output [8:0] MIREQUESTRAMWRITEADDRESSA;
|
|
output [8:0] MIREQUESTRAMWRITEADDRESSB;
|
|
output [143:0] MIREQUESTRAMWRITEDATA;
|
|
output [3:0] MIREQUESTRAMWRITEENABLE;
|
|
output [5:0] PCIECQNPREQCOUNT;
|
|
output PCIEPERST0B;
|
|
output PCIEPERST1B;
|
|
output [3:0] PCIERQSEQNUM;
|
|
output PCIERQSEQNUMVLD;
|
|
output [5:0] PCIERQTAG;
|
|
output [1:0] PCIERQTAGAV;
|
|
output PCIERQTAGVLD;
|
|
output [1:0] PCIETFCNPDAV;
|
|
output [1:0] PCIETFCNPHAV;
|
|
output [1:0] PIPERX0EQCONTROL;
|
|
output [5:0] PIPERX0EQLPLFFS;
|
|
output [3:0] PIPERX0EQLPTXPRESET;
|
|
output [2:0] PIPERX0EQPRESET;
|
|
output PIPERX0POLARITY;
|
|
output [1:0] PIPERX1EQCONTROL;
|
|
output [5:0] PIPERX1EQLPLFFS;
|
|
output [3:0] PIPERX1EQLPTXPRESET;
|
|
output [2:0] PIPERX1EQPRESET;
|
|
output PIPERX1POLARITY;
|
|
output [1:0] PIPERX2EQCONTROL;
|
|
output [5:0] PIPERX2EQLPLFFS;
|
|
output [3:0] PIPERX2EQLPTXPRESET;
|
|
output [2:0] PIPERX2EQPRESET;
|
|
output PIPERX2POLARITY;
|
|
output [1:0] PIPERX3EQCONTROL;
|
|
output [5:0] PIPERX3EQLPLFFS;
|
|
output [3:0] PIPERX3EQLPTXPRESET;
|
|
output [2:0] PIPERX3EQPRESET;
|
|
output PIPERX3POLARITY;
|
|
output [1:0] PIPERX4EQCONTROL;
|
|
output [5:0] PIPERX4EQLPLFFS;
|
|
output [3:0] PIPERX4EQLPTXPRESET;
|
|
output [2:0] PIPERX4EQPRESET;
|
|
output PIPERX4POLARITY;
|
|
output [1:0] PIPERX5EQCONTROL;
|
|
output [5:0] PIPERX5EQLPLFFS;
|
|
output [3:0] PIPERX5EQLPTXPRESET;
|
|
output [2:0] PIPERX5EQPRESET;
|
|
output PIPERX5POLARITY;
|
|
output [1:0] PIPERX6EQCONTROL;
|
|
output [5:0] PIPERX6EQLPLFFS;
|
|
output [3:0] PIPERX6EQLPTXPRESET;
|
|
output [2:0] PIPERX6EQPRESET;
|
|
output PIPERX6POLARITY;
|
|
output [1:0] PIPERX7EQCONTROL;
|
|
output [5:0] PIPERX7EQLPLFFS;
|
|
output [3:0] PIPERX7EQLPTXPRESET;
|
|
output [2:0] PIPERX7EQPRESET;
|
|
output PIPERX7POLARITY;
|
|
output [1:0] PIPETX0CHARISK;
|
|
output PIPETX0COMPLIANCE;
|
|
output [31:0] PIPETX0DATA;
|
|
output PIPETX0DATAVALID;
|
|
output PIPETX0DEEMPH;
|
|
output PIPETX0ELECIDLE;
|
|
output [1:0] PIPETX0EQCONTROL;
|
|
output [5:0] PIPETX0EQDEEMPH;
|
|
output [3:0] PIPETX0EQPRESET;
|
|
output [2:0] PIPETX0MARGIN;
|
|
output [1:0] PIPETX0POWERDOWN;
|
|
output [1:0] PIPETX0RATE;
|
|
output PIPETX0RCVRDET;
|
|
output PIPETX0RESET;
|
|
output PIPETX0STARTBLOCK;
|
|
output PIPETX0SWING;
|
|
output [1:0] PIPETX0SYNCHEADER;
|
|
output [1:0] PIPETX1CHARISK;
|
|
output PIPETX1COMPLIANCE;
|
|
output [31:0] PIPETX1DATA;
|
|
output PIPETX1DATAVALID;
|
|
output PIPETX1DEEMPH;
|
|
output PIPETX1ELECIDLE;
|
|
output [1:0] PIPETX1EQCONTROL;
|
|
output [5:0] PIPETX1EQDEEMPH;
|
|
output [3:0] PIPETX1EQPRESET;
|
|
output [2:0] PIPETX1MARGIN;
|
|
output [1:0] PIPETX1POWERDOWN;
|
|
output [1:0] PIPETX1RATE;
|
|
output PIPETX1RCVRDET;
|
|
output PIPETX1RESET;
|
|
output PIPETX1STARTBLOCK;
|
|
output PIPETX1SWING;
|
|
output [1:0] PIPETX1SYNCHEADER;
|
|
output [1:0] PIPETX2CHARISK;
|
|
output PIPETX2COMPLIANCE;
|
|
output [31:0] PIPETX2DATA;
|
|
output PIPETX2DATAVALID;
|
|
output PIPETX2DEEMPH;
|
|
output PIPETX2ELECIDLE;
|
|
output [1:0] PIPETX2EQCONTROL;
|
|
output [5:0] PIPETX2EQDEEMPH;
|
|
output [3:0] PIPETX2EQPRESET;
|
|
output [2:0] PIPETX2MARGIN;
|
|
output [1:0] PIPETX2POWERDOWN;
|
|
output [1:0] PIPETX2RATE;
|
|
output PIPETX2RCVRDET;
|
|
output PIPETX2RESET;
|
|
output PIPETX2STARTBLOCK;
|
|
output PIPETX2SWING;
|
|
output [1:0] PIPETX2SYNCHEADER;
|
|
output [1:0] PIPETX3CHARISK;
|
|
output PIPETX3COMPLIANCE;
|
|
output [31:0] PIPETX3DATA;
|
|
output PIPETX3DATAVALID;
|
|
output PIPETX3DEEMPH;
|
|
output PIPETX3ELECIDLE;
|
|
output [1:0] PIPETX3EQCONTROL;
|
|
output [5:0] PIPETX3EQDEEMPH;
|
|
output [3:0] PIPETX3EQPRESET;
|
|
output [2:0] PIPETX3MARGIN;
|
|
output [1:0] PIPETX3POWERDOWN;
|
|
output [1:0] PIPETX3RATE;
|
|
output PIPETX3RCVRDET;
|
|
output PIPETX3RESET;
|
|
output PIPETX3STARTBLOCK;
|
|
output PIPETX3SWING;
|
|
output [1:0] PIPETX3SYNCHEADER;
|
|
output [1:0] PIPETX4CHARISK;
|
|
output PIPETX4COMPLIANCE;
|
|
output [31:0] PIPETX4DATA;
|
|
output PIPETX4DATAVALID;
|
|
output PIPETX4DEEMPH;
|
|
output PIPETX4ELECIDLE;
|
|
output [1:0] PIPETX4EQCONTROL;
|
|
output [5:0] PIPETX4EQDEEMPH;
|
|
output [3:0] PIPETX4EQPRESET;
|
|
output [2:0] PIPETX4MARGIN;
|
|
output [1:0] PIPETX4POWERDOWN;
|
|
output [1:0] PIPETX4RATE;
|
|
output PIPETX4RCVRDET;
|
|
output PIPETX4RESET;
|
|
output PIPETX4STARTBLOCK;
|
|
output PIPETX4SWING;
|
|
output [1:0] PIPETX4SYNCHEADER;
|
|
output [1:0] PIPETX5CHARISK;
|
|
output PIPETX5COMPLIANCE;
|
|
output [31:0] PIPETX5DATA;
|
|
output PIPETX5DATAVALID;
|
|
output PIPETX5DEEMPH;
|
|
output PIPETX5ELECIDLE;
|
|
output [1:0] PIPETX5EQCONTROL;
|
|
output [5:0] PIPETX5EQDEEMPH;
|
|
output [3:0] PIPETX5EQPRESET;
|
|
output [2:0] PIPETX5MARGIN;
|
|
output [1:0] PIPETX5POWERDOWN;
|
|
output [1:0] PIPETX5RATE;
|
|
output PIPETX5RCVRDET;
|
|
output PIPETX5RESET;
|
|
output PIPETX5STARTBLOCK;
|
|
output PIPETX5SWING;
|
|
output [1:0] PIPETX5SYNCHEADER;
|
|
output [1:0] PIPETX6CHARISK;
|
|
output PIPETX6COMPLIANCE;
|
|
output [31:0] PIPETX6DATA;
|
|
output PIPETX6DATAVALID;
|
|
output PIPETX6DEEMPH;
|
|
output PIPETX6ELECIDLE;
|
|
output [1:0] PIPETX6EQCONTROL;
|
|
output [5:0] PIPETX6EQDEEMPH;
|
|
output [3:0] PIPETX6EQPRESET;
|
|
output [2:0] PIPETX6MARGIN;
|
|
output [1:0] PIPETX6POWERDOWN;
|
|
output [1:0] PIPETX6RATE;
|
|
output PIPETX6RCVRDET;
|
|
output PIPETX6RESET;
|
|
output PIPETX6STARTBLOCK;
|
|
output PIPETX6SWING;
|
|
output [1:0] PIPETX6SYNCHEADER;
|
|
output [1:0] PIPETX7CHARISK;
|
|
output PIPETX7COMPLIANCE;
|
|
output [31:0] PIPETX7DATA;
|
|
output PIPETX7DATAVALID;
|
|
output PIPETX7DEEMPH;
|
|
output PIPETX7ELECIDLE;
|
|
output [1:0] PIPETX7EQCONTROL;
|
|
output [5:0] PIPETX7EQDEEMPH;
|
|
output [3:0] PIPETX7EQPRESET;
|
|
output [2:0] PIPETX7MARGIN;
|
|
output [1:0] PIPETX7POWERDOWN;
|
|
output [1:0] PIPETX7RATE;
|
|
output PIPETX7RCVRDET;
|
|
output PIPETX7RESET;
|
|
output PIPETX7STARTBLOCK;
|
|
output PIPETX7SWING;
|
|
output [1:0] PIPETX7SYNCHEADER;
|
|
output PLEQINPROGRESS;
|
|
output [1:0] PLEQPHASE;
|
|
output [3:0] SAXISCCTREADY;
|
|
output [3:0] SAXISRQTREADY;
|
|
output [31:0] SPAREOUT;
|
|
input CFGCONFIGSPACEENABLE;
|
|
input [15:0] CFGDEVID;
|
|
input [7:0] CFGDSBUSNUMBER;
|
|
input [4:0] CFGDSDEVICENUMBER;
|
|
input [2:0] CFGDSFUNCTIONNUMBER;
|
|
input [63:0] CFGDSN;
|
|
input [7:0] CFGDSPORTNUMBER;
|
|
input CFGERRCORIN;
|
|
input CFGERRUNCORIN;
|
|
input [31:0] CFGEXTREADDATA;
|
|
input CFGEXTREADDATAVALID;
|
|
input [2:0] CFGFCSEL;
|
|
input [3:0] CFGFLRDONE;
|
|
input CFGHOTRESETIN;
|
|
input [3:0] CFGINTERRUPTINT;
|
|
input [2:0] CFGINTERRUPTMSIATTR;
|
|
input [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
|
|
input [31:0] CFGINTERRUPTMSIINT;
|
|
input [31:0] CFGINTERRUPTMSIPENDINGSTATUS;
|
|
input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE;
|
|
input [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM;
|
|
input [3:0] CFGINTERRUPTMSISELECT;
|
|
input CFGINTERRUPTMSITPHPRESENT;
|
|
input [8:0] CFGINTERRUPTMSITPHSTTAG;
|
|
input [1:0] CFGINTERRUPTMSITPHTYPE;
|
|
input [63:0] CFGINTERRUPTMSIXADDRESS;
|
|
input [31:0] CFGINTERRUPTMSIXDATA;
|
|
input CFGINTERRUPTMSIXINT;
|
|
input [3:0] CFGINTERRUPTPENDING;
|
|
input CFGLINKTRAININGENABLE;
|
|
input [18:0] CFGMGMTADDR;
|
|
input [3:0] CFGMGMTBYTEENABLE;
|
|
input CFGMGMTREAD;
|
|
input CFGMGMTTYPE1CFGREGACCESS;
|
|
input CFGMGMTWRITE;
|
|
input [31:0] CFGMGMTWRITEDATA;
|
|
input CFGMSGTRANSMIT;
|
|
input [31:0] CFGMSGTRANSMITDATA;
|
|
input [2:0] CFGMSGTRANSMITTYPE;
|
|
input [2:0] CFGPERFUNCSTATUSCONTROL;
|
|
input [3:0] CFGPERFUNCTIONNUMBER;
|
|
input CFGPERFUNCTIONOUTPUTREQUEST;
|
|
input CFGPOWERSTATECHANGEACK;
|
|
input CFGREQPMTRANSITIONL23READY;
|
|
input [7:0] CFGREVID;
|
|
input [15:0] CFGSUBSYSID;
|
|
input [15:0] CFGSUBSYSVENDID;
|
|
input [31:0] CFGTPHSTTREADDATA;
|
|
input CFGTPHSTTREADDATAVALID;
|
|
input [15:0] CFGVENDID;
|
|
input [7:0] CFGVFFLRDONE;
|
|
input CONFMCAPREQUESTBYCONF;
|
|
input [31:0] CONFREQDATA;
|
|
input [3:0] CONFREQREGNUM;
|
|
input [1:0] CONFREQTYPE;
|
|
input CONFREQVALID;
|
|
input CORECLK;
|
|
input CORECLKMICOMPLETIONRAML;
|
|
input CORECLKMICOMPLETIONRAMU;
|
|
input CORECLKMIREPLAYRAM;
|
|
input CORECLKMIREQUESTRAM;
|
|
input DBGCFGLOCALMGMTREGOVERRIDE;
|
|
input [3:0] DBGDATASEL;
|
|
input [9:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input [13:0] LL2LMSAXISTXTUSER;
|
|
input LL2LMSAXISTXTVALID;
|
|
input [3:0] LL2LMTXTLPID0;
|
|
input [3:0] LL2LMTXTLPID1;
|
|
input [21:0] MAXISCQTREADY;
|
|
input [21:0] MAXISRCTREADY;
|
|
input MCAPCLK;
|
|
input MCAPPERST0B;
|
|
input MCAPPERST1B;
|
|
input MGMTRESETN;
|
|
input MGMTSTICKYRESETN;
|
|
input [143:0] MICOMPLETIONRAMREADDATA;
|
|
input [143:0] MIREPLAYRAMREADDATA;
|
|
input [143:0] MIREQUESTRAMREADDATA;
|
|
input PCIECQNPREQ;
|
|
input PIPECLK;
|
|
input [5:0] PIPEEQFS;
|
|
input [5:0] PIPEEQLF;
|
|
input PIPERESETN;
|
|
input [1:0] PIPERX0CHARISK;
|
|
input [31:0] PIPERX0DATA;
|
|
input PIPERX0DATAVALID;
|
|
input PIPERX0ELECIDLE;
|
|
input PIPERX0EQDONE;
|
|
input PIPERX0EQLPADAPTDONE;
|
|
input PIPERX0EQLPLFFSSEL;
|
|
input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX0PHYSTATUS;
|
|
input PIPERX0STARTBLOCK;
|
|
input [2:0] PIPERX0STATUS;
|
|
input [1:0] PIPERX0SYNCHEADER;
|
|
input PIPERX0VALID;
|
|
input [1:0] PIPERX1CHARISK;
|
|
input [31:0] PIPERX1DATA;
|
|
input PIPERX1DATAVALID;
|
|
input PIPERX1ELECIDLE;
|
|
input PIPERX1EQDONE;
|
|
input PIPERX1EQLPADAPTDONE;
|
|
input PIPERX1EQLPLFFSSEL;
|
|
input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX1PHYSTATUS;
|
|
input PIPERX1STARTBLOCK;
|
|
input [2:0] PIPERX1STATUS;
|
|
input [1:0] PIPERX1SYNCHEADER;
|
|
input PIPERX1VALID;
|
|
input [1:0] PIPERX2CHARISK;
|
|
input [31:0] PIPERX2DATA;
|
|
input PIPERX2DATAVALID;
|
|
input PIPERX2ELECIDLE;
|
|
input PIPERX2EQDONE;
|
|
input PIPERX2EQLPADAPTDONE;
|
|
input PIPERX2EQLPLFFSSEL;
|
|
input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX2PHYSTATUS;
|
|
input PIPERX2STARTBLOCK;
|
|
input [2:0] PIPERX2STATUS;
|
|
input [1:0] PIPERX2SYNCHEADER;
|
|
input PIPERX2VALID;
|
|
input [1:0] PIPERX3CHARISK;
|
|
input [31:0] PIPERX3DATA;
|
|
input PIPERX3DATAVALID;
|
|
input PIPERX3ELECIDLE;
|
|
input PIPERX3EQDONE;
|
|
input PIPERX3EQLPADAPTDONE;
|
|
input PIPERX3EQLPLFFSSEL;
|
|
input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX3PHYSTATUS;
|
|
input PIPERX3STARTBLOCK;
|
|
input [2:0] PIPERX3STATUS;
|
|
input [1:0] PIPERX3SYNCHEADER;
|
|
input PIPERX3VALID;
|
|
input [1:0] PIPERX4CHARISK;
|
|
input [31:0] PIPERX4DATA;
|
|
input PIPERX4DATAVALID;
|
|
input PIPERX4ELECIDLE;
|
|
input PIPERX4EQDONE;
|
|
input PIPERX4EQLPADAPTDONE;
|
|
input PIPERX4EQLPLFFSSEL;
|
|
input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX4PHYSTATUS;
|
|
input PIPERX4STARTBLOCK;
|
|
input [2:0] PIPERX4STATUS;
|
|
input [1:0] PIPERX4SYNCHEADER;
|
|
input PIPERX4VALID;
|
|
input [1:0] PIPERX5CHARISK;
|
|
input [31:0] PIPERX5DATA;
|
|
input PIPERX5DATAVALID;
|
|
input PIPERX5ELECIDLE;
|
|
input PIPERX5EQDONE;
|
|
input PIPERX5EQLPADAPTDONE;
|
|
input PIPERX5EQLPLFFSSEL;
|
|
input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX5PHYSTATUS;
|
|
input PIPERX5STARTBLOCK;
|
|
input [2:0] PIPERX5STATUS;
|
|
input [1:0] PIPERX5SYNCHEADER;
|
|
input PIPERX5VALID;
|
|
input [1:0] PIPERX6CHARISK;
|
|
input [31:0] PIPERX6DATA;
|
|
input PIPERX6DATAVALID;
|
|
input PIPERX6ELECIDLE;
|
|
input PIPERX6EQDONE;
|
|
input PIPERX6EQLPADAPTDONE;
|
|
input PIPERX6EQLPLFFSSEL;
|
|
input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX6PHYSTATUS;
|
|
input PIPERX6STARTBLOCK;
|
|
input [2:0] PIPERX6STATUS;
|
|
input [1:0] PIPERX6SYNCHEADER;
|
|
input PIPERX6VALID;
|
|
input [1:0] PIPERX7CHARISK;
|
|
input [31:0] PIPERX7DATA;
|
|
input PIPERX7DATAVALID;
|
|
input PIPERX7ELECIDLE;
|
|
input PIPERX7EQDONE;
|
|
input PIPERX7EQLPADAPTDONE;
|
|
input PIPERX7EQLPLFFSSEL;
|
|
input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX7PHYSTATUS;
|
|
input PIPERX7STARTBLOCK;
|
|
input [2:0] PIPERX7STATUS;
|
|
input [1:0] PIPERX7SYNCHEADER;
|
|
input PIPERX7VALID;
|
|
input [17:0] PIPETX0EQCOEFF;
|
|
input PIPETX0EQDONE;
|
|
input [17:0] PIPETX1EQCOEFF;
|
|
input PIPETX1EQDONE;
|
|
input [17:0] PIPETX2EQCOEFF;
|
|
input PIPETX2EQDONE;
|
|
input [17:0] PIPETX3EQCOEFF;
|
|
input PIPETX3EQDONE;
|
|
input [17:0] PIPETX4EQCOEFF;
|
|
input PIPETX4EQDONE;
|
|
input [17:0] PIPETX5EQCOEFF;
|
|
input PIPETX5EQDONE;
|
|
input [17:0] PIPETX6EQCOEFF;
|
|
input PIPETX6EQDONE;
|
|
input [17:0] PIPETX7EQCOEFF;
|
|
input PIPETX7EQDONE;
|
|
input PLEQRESETEIEOSCOUNT;
|
|
input PLGEN2UPSTREAMPREFERDEEMPH;
|
|
input RESETN;
|
|
input [255:0] SAXISCCTDATA;
|
|
input [7:0] SAXISCCTKEEP;
|
|
input SAXISCCTLAST;
|
|
input [32:0] SAXISCCTUSER;
|
|
input SAXISCCTVALID;
|
|
input [255:0] SAXISRQTDATA;
|
|
input [7:0] SAXISRQTKEEP;
|
|
input SAXISRQTLAST;
|
|
input [59:0] SAXISRQTUSER;
|
|
input SAXISRQTVALID;
|
|
input [31:0] SPAREIN;
|
|
input USERCLK;
|
|
endmodule
|
|
|
|
module PCIE40E4(AXIUSEROUT, CFGBUSNUMBER, CFGCURRENTSPEED, CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTFUNCTIONNUMBER, CFGEXTREADRECEIVED, CFGEXTREGISTERNUMBER, CFGEXTWRITEBYTEENABLE, CFGEXTWRITEDATA, CFGEXTWRITERECEIVED, CFGFCCPLD, CFGFCCPLH, CFGFCNPD, CFGFCNPH, CFGFCPD, CFGFCPH, CFGFLRINPROCESS, CFGFUNCTIONPOWERSTATE, CFGFUNCTIONSTATUS
|
|
, CFGHOTRESETOUT, CFGINTERRUPTMSIDATA, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXMASK, CFGINTERRUPTMSIXVECPENDINGSTATUS, CFGINTERRUPTSENT, CFGLINKPOWERSTATE, CFGLOCALERROROUT, CFGLOCALERRORVALID, CFGLTRENABLE, CFGLTSSMSTATE, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGMGMTREADDATA, CFGMGMTREADWRITEDONE, CFGMSGRECEIVED
|
|
, CFGMSGRECEIVEDDATA, CFGMSGRECEIVEDTYPE, CFGMSGTRANSMITDONE, CFGMSIXRAMADDRESS, CFGMSIXRAMREADENABLE, CFGMSIXRAMWRITEBYTEENABLE, CFGMSIXRAMWRITEDATA, CFGNEGOTIATEDWIDTH, CFGOBFFENABLE, CFGPHYLINKDOWN, CFGPHYLINKSTATUS, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGRCBSTATUS, CFGRXPMSTATE, CFGTPHRAMADDRESS, CFGTPHRAMREADENABLE, CFGTPHRAMWRITEBYTEENABLE, CFGTPHRAMWRITEDATA, CFGTPHREQUESTERENABLE, CFGTPHSTMODE
|
|
, CFGTXPMSTATE, CONFMCAPDESIGNSWITCH, CONFMCAPEOS, CONFMCAPINUSEBYPCIE, CONFREQREADY, CONFRESPRDATA, CONFRESPVALID, DBGCTRL0OUT, DBGCTRL1OUT, DBGDATA0OUT, DBGDATA1OUT, DRPDO, DRPRDY, MAXISCQTDATA, MAXISCQTKEEP, MAXISCQTLAST, MAXISCQTUSER, MAXISCQTVALID, MAXISRCTDATA, MAXISRCTKEEP, MAXISRCTLAST
|
|
, MAXISRCTUSER, MAXISRCTVALID, MIREPLAYRAMADDRESS0, MIREPLAYRAMADDRESS1, MIREPLAYRAMREADENABLE0, MIREPLAYRAMREADENABLE1, MIREPLAYRAMWRITEDATA0, MIREPLAYRAMWRITEDATA1, MIREPLAYRAMWRITEENABLE0, MIREPLAYRAMWRITEENABLE1, MIRXCOMPLETIONRAMREADADDRESS0, MIRXCOMPLETIONRAMREADADDRESS1, MIRXCOMPLETIONRAMREADENABLE0, MIRXCOMPLETIONRAMREADENABLE1, MIRXCOMPLETIONRAMWRITEADDRESS0, MIRXCOMPLETIONRAMWRITEADDRESS1, MIRXCOMPLETIONRAMWRITEDATA0, MIRXCOMPLETIONRAMWRITEDATA1, MIRXCOMPLETIONRAMWRITEENABLE0, MIRXCOMPLETIONRAMWRITEENABLE1, MIRXPOSTEDREQUESTRAMREADADDRESS0
|
|
, MIRXPOSTEDREQUESTRAMREADADDRESS1, MIRXPOSTEDREQUESTRAMREADENABLE0, MIRXPOSTEDREQUESTRAMREADENABLE1, MIRXPOSTEDREQUESTRAMWRITEADDRESS0, MIRXPOSTEDREQUESTRAMWRITEADDRESS1, MIRXPOSTEDREQUESTRAMWRITEDATA0, MIRXPOSTEDREQUESTRAMWRITEDATA1, MIRXPOSTEDREQUESTRAMWRITEENABLE0, MIRXPOSTEDREQUESTRAMWRITEENABLE1, PCIECQNPREQCOUNT, PCIEPERST0B, PCIEPERST1B, PCIERQSEQNUM0, PCIERQSEQNUM1, PCIERQSEQNUMVLD0, PCIERQSEQNUMVLD1, PCIERQTAG0, PCIERQTAG1, PCIERQTAGAV, PCIERQTAGVLD0, PCIERQTAGVLD1
|
|
, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX00EQCONTROL, PIPERX00POLARITY, PIPERX01EQCONTROL, PIPERX01POLARITY, PIPERX02EQCONTROL, PIPERX02POLARITY, PIPERX03EQCONTROL, PIPERX03POLARITY, PIPERX04EQCONTROL, PIPERX04POLARITY, PIPERX05EQCONTROL, PIPERX05POLARITY, PIPERX06EQCONTROL, PIPERX06POLARITY, PIPERX07EQCONTROL, PIPERX07POLARITY, PIPERX08EQCONTROL, PIPERX08POLARITY, PIPERX09EQCONTROL
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|
, PIPERX09POLARITY, PIPERX10EQCONTROL, PIPERX10POLARITY, PIPERX11EQCONTROL, PIPERX11POLARITY, PIPERX12EQCONTROL, PIPERX12POLARITY, PIPERX13EQCONTROL, PIPERX13POLARITY, PIPERX14EQCONTROL, PIPERX14POLARITY, PIPERX15EQCONTROL, PIPERX15POLARITY, PIPERXEQLPLFFS, PIPERXEQLPTXPRESET, PIPETX00CHARISK, PIPETX00COMPLIANCE, PIPETX00DATA, PIPETX00DATAVALID, PIPETX00ELECIDLE, PIPETX00EQCONTROL
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, PIPETX00EQDEEMPH, PIPETX00POWERDOWN, PIPETX00STARTBLOCK, PIPETX00SYNCHEADER, PIPETX01CHARISK, PIPETX01COMPLIANCE, PIPETX01DATA, PIPETX01DATAVALID, PIPETX01ELECIDLE, PIPETX01EQCONTROL, PIPETX01EQDEEMPH, PIPETX01POWERDOWN, PIPETX01STARTBLOCK, PIPETX01SYNCHEADER, PIPETX02CHARISK, PIPETX02COMPLIANCE, PIPETX02DATA, PIPETX02DATAVALID, PIPETX02ELECIDLE, PIPETX02EQCONTROL, PIPETX02EQDEEMPH
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|
, PIPETX02POWERDOWN, PIPETX02STARTBLOCK, PIPETX02SYNCHEADER, PIPETX03CHARISK, PIPETX03COMPLIANCE, PIPETX03DATA, PIPETX03DATAVALID, PIPETX03ELECIDLE, PIPETX03EQCONTROL, PIPETX03EQDEEMPH, PIPETX03POWERDOWN, PIPETX03STARTBLOCK, PIPETX03SYNCHEADER, PIPETX04CHARISK, PIPETX04COMPLIANCE, PIPETX04DATA, PIPETX04DATAVALID, PIPETX04ELECIDLE, PIPETX04EQCONTROL, PIPETX04EQDEEMPH, PIPETX04POWERDOWN
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|
, PIPETX04STARTBLOCK, PIPETX04SYNCHEADER, PIPETX05CHARISK, PIPETX05COMPLIANCE, PIPETX05DATA, PIPETX05DATAVALID, PIPETX05ELECIDLE, PIPETX05EQCONTROL, PIPETX05EQDEEMPH, PIPETX05POWERDOWN, PIPETX05STARTBLOCK, PIPETX05SYNCHEADER, PIPETX06CHARISK, PIPETX06COMPLIANCE, PIPETX06DATA, PIPETX06DATAVALID, PIPETX06ELECIDLE, PIPETX06EQCONTROL, PIPETX06EQDEEMPH, PIPETX06POWERDOWN, PIPETX06STARTBLOCK
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|
, PIPETX06SYNCHEADER, PIPETX07CHARISK, PIPETX07COMPLIANCE, PIPETX07DATA, PIPETX07DATAVALID, PIPETX07ELECIDLE, PIPETX07EQCONTROL, PIPETX07EQDEEMPH, PIPETX07POWERDOWN, PIPETX07STARTBLOCK, PIPETX07SYNCHEADER, PIPETX08CHARISK, PIPETX08COMPLIANCE, PIPETX08DATA, PIPETX08DATAVALID, PIPETX08ELECIDLE, PIPETX08EQCONTROL, PIPETX08EQDEEMPH, PIPETX08POWERDOWN, PIPETX08STARTBLOCK, PIPETX08SYNCHEADER
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|
, PIPETX09CHARISK, PIPETX09COMPLIANCE, PIPETX09DATA, PIPETX09DATAVALID, PIPETX09ELECIDLE, PIPETX09EQCONTROL, PIPETX09EQDEEMPH, PIPETX09POWERDOWN, PIPETX09STARTBLOCK, PIPETX09SYNCHEADER, PIPETX10CHARISK, PIPETX10COMPLIANCE, PIPETX10DATA, PIPETX10DATAVALID, PIPETX10ELECIDLE, PIPETX10EQCONTROL, PIPETX10EQDEEMPH, PIPETX10POWERDOWN, PIPETX10STARTBLOCK, PIPETX10SYNCHEADER, PIPETX11CHARISK
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|
, PIPETX11COMPLIANCE, PIPETX11DATA, PIPETX11DATAVALID, PIPETX11ELECIDLE, PIPETX11EQCONTROL, PIPETX11EQDEEMPH, PIPETX11POWERDOWN, PIPETX11STARTBLOCK, PIPETX11SYNCHEADER, PIPETX12CHARISK, PIPETX12COMPLIANCE, PIPETX12DATA, PIPETX12DATAVALID, PIPETX12ELECIDLE, PIPETX12EQCONTROL, PIPETX12EQDEEMPH, PIPETX12POWERDOWN, PIPETX12STARTBLOCK, PIPETX12SYNCHEADER, PIPETX13CHARISK, PIPETX13COMPLIANCE
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|
, PIPETX13DATA, PIPETX13DATAVALID, PIPETX13ELECIDLE, PIPETX13EQCONTROL, PIPETX13EQDEEMPH, PIPETX13POWERDOWN, PIPETX13STARTBLOCK, PIPETX13SYNCHEADER, PIPETX14CHARISK, PIPETX14COMPLIANCE, PIPETX14DATA, PIPETX14DATAVALID, PIPETX14ELECIDLE, PIPETX14EQCONTROL, PIPETX14EQDEEMPH, PIPETX14POWERDOWN, PIPETX14STARTBLOCK, PIPETX14SYNCHEADER, PIPETX15CHARISK, PIPETX15COMPLIANCE, PIPETX15DATA
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|
, PIPETX15DATAVALID, PIPETX15ELECIDLE, PIPETX15EQCONTROL, PIPETX15EQDEEMPH, PIPETX15POWERDOWN, PIPETX15STARTBLOCK, PIPETX15SYNCHEADER, PIPETXDEEMPH, PIPETXMARGIN, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PIPETXSWING, PLEQINPROGRESS, PLEQPHASE, PLGEN34EQMISMATCH, SAXISCCTREADY, SAXISRQTREADY, USERSPAREOUT, AXIUSERIN, CFGCONFIGSPACEENABLE
|
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, CFGDEVIDPF0, CFGDEVIDPF1, CFGDEVIDPF2, CFGDEVIDPF3, CFGDSBUSNUMBER, CFGDSDEVICENUMBER, CFGDSFUNCTIONNUMBER, CFGDSN, CFGDSPORTNUMBER, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATA, CFGEXTREADDATAVALID, CFGFCSEL, CFGFLRDONE, CFGHOTRESETIN, CFGINTERRUPTINT, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIPENDINGSTATUS
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, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, CFGINTERRUPTMSISELECT, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSITPHSTTAG, CFGINTERRUPTMSITPHTYPE, CFGINTERRUPTMSIXADDRESS, CFGINTERRUPTMSIXDATA, CFGINTERRUPTMSIXINT, CFGINTERRUPTMSIXVECPENDING, CFGINTERRUPTPENDING, CFGLINKTRAININGENABLE, CFGMGMTADDR, CFGMGMTBYTEENABLE, CFGMGMTDEBUGACCESS, CFGMGMTFUNCTIONNUMBER, CFGMGMTREAD, CFGMGMTWRITE, CFGMGMTWRITEDATA, CFGMSGTRANSMIT, CFGMSGTRANSMITDATA
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, CFGMSGTRANSMITTYPE, CFGMSIXRAMREADDATA, CFGPMASPML1ENTRYREJECT, CFGPMASPMTXL0SENTRYDISABLE, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY, CFGREVIDPF0, CFGREVIDPF1, CFGREVIDPF2, CFGREVIDPF3, CFGSUBSYSIDPF0, CFGSUBSYSIDPF1, CFGSUBSYSIDPF2, CFGSUBSYSIDPF3, CFGSUBSYSVENDID, CFGTPHRAMREADDATA, CFGVENDID, CFGVFFLRDONE, CFGVFFLRFUNCNUM, CONFMCAPREQUESTBYCONF, CONFREQDATA
|
|
, CONFREQREGNUM, CONFREQTYPE, CONFREQVALID, CORECLK, CORECLKMIREPLAYRAM0, CORECLKMIREPLAYRAM1, CORECLKMIRXCOMPLETIONRAM0, CORECLKMIRXCOMPLETIONRAM1, CORECLKMIRXPOSTEDREQUESTRAM0, CORECLKMIRXPOSTEDREQUESTRAM1, DBGSEL0, DBGSEL1, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, MAXISCQTREADY, MAXISRCTREADY, MCAPCLK, MCAPPERST0B
|
|
, MCAPPERST1B, MGMTRESETN, MGMTSTICKYRESETN, MIREPLAYRAMERRCOR, MIREPLAYRAMERRUNCOR, MIREPLAYRAMREADDATA0, MIREPLAYRAMREADDATA1, MIRXCOMPLETIONRAMERRCOR, MIRXCOMPLETIONRAMERRUNCOR, MIRXCOMPLETIONRAMREADDATA0, MIRXCOMPLETIONRAMREADDATA1, MIRXPOSTEDREQUESTRAMERRCOR, MIRXPOSTEDREQUESTRAMERRUNCOR, MIRXPOSTEDREQUESTRAMREADDATA0, MIRXPOSTEDREQUESTRAMREADDATA1, PCIECOMPLDELIVERED, PCIECOMPLDELIVEREDTAG0, PCIECOMPLDELIVEREDTAG1, PCIECQNPREQ, PCIECQNPUSERCREDITRCVD, PCIECQPIPELINEEMPTY
|
|
, PCIEPOSTEDREQDELIVERED, PIPECLK, PIPECLKEN, PIPEEQFS, PIPEEQLF, PIPERESETN, PIPERX00CHARISK, PIPERX00DATA, PIPERX00DATAVALID, PIPERX00ELECIDLE, PIPERX00EQDONE, PIPERX00EQLPADAPTDONE, PIPERX00EQLPLFFSSEL, PIPERX00EQLPNEWTXCOEFFORPRESET, PIPERX00PHYSTATUS, PIPERX00STARTBLOCK, PIPERX00STATUS, PIPERX00SYNCHEADER, PIPERX00VALID, PIPERX01CHARISK, PIPERX01DATA
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|
, PIPERX01DATAVALID, PIPERX01ELECIDLE, PIPERX01EQDONE, PIPERX01EQLPADAPTDONE, PIPERX01EQLPLFFSSEL, PIPERX01EQLPNEWTXCOEFFORPRESET, PIPERX01PHYSTATUS, PIPERX01STARTBLOCK, PIPERX01STATUS, PIPERX01SYNCHEADER, PIPERX01VALID, PIPERX02CHARISK, PIPERX02DATA, PIPERX02DATAVALID, PIPERX02ELECIDLE, PIPERX02EQDONE, PIPERX02EQLPADAPTDONE, PIPERX02EQLPLFFSSEL, PIPERX02EQLPNEWTXCOEFFORPRESET, PIPERX02PHYSTATUS, PIPERX02STARTBLOCK
|
|
, PIPERX02STATUS, PIPERX02SYNCHEADER, PIPERX02VALID, PIPERX03CHARISK, PIPERX03DATA, PIPERX03DATAVALID, PIPERX03ELECIDLE, PIPERX03EQDONE, PIPERX03EQLPADAPTDONE, PIPERX03EQLPLFFSSEL, PIPERX03EQLPNEWTXCOEFFORPRESET, PIPERX03PHYSTATUS, PIPERX03STARTBLOCK, PIPERX03STATUS, PIPERX03SYNCHEADER, PIPERX03VALID, PIPERX04CHARISK, PIPERX04DATA, PIPERX04DATAVALID, PIPERX04ELECIDLE, PIPERX04EQDONE
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|
, PIPERX04EQLPADAPTDONE, PIPERX04EQLPLFFSSEL, PIPERX04EQLPNEWTXCOEFFORPRESET, PIPERX04PHYSTATUS, PIPERX04STARTBLOCK, PIPERX04STATUS, PIPERX04SYNCHEADER, PIPERX04VALID, PIPERX05CHARISK, PIPERX05DATA, PIPERX05DATAVALID, PIPERX05ELECIDLE, PIPERX05EQDONE, PIPERX05EQLPADAPTDONE, PIPERX05EQLPLFFSSEL, PIPERX05EQLPNEWTXCOEFFORPRESET, PIPERX05PHYSTATUS, PIPERX05STARTBLOCK, PIPERX05STATUS, PIPERX05SYNCHEADER, PIPERX05VALID
|
|
, PIPERX06CHARISK, PIPERX06DATA, PIPERX06DATAVALID, PIPERX06ELECIDLE, PIPERX06EQDONE, PIPERX06EQLPADAPTDONE, PIPERX06EQLPLFFSSEL, PIPERX06EQLPNEWTXCOEFFORPRESET, PIPERX06PHYSTATUS, PIPERX06STARTBLOCK, PIPERX06STATUS, PIPERX06SYNCHEADER, PIPERX06VALID, PIPERX07CHARISK, PIPERX07DATA, PIPERX07DATAVALID, PIPERX07ELECIDLE, PIPERX07EQDONE, PIPERX07EQLPADAPTDONE, PIPERX07EQLPLFFSSEL, PIPERX07EQLPNEWTXCOEFFORPRESET
|
|
, PIPERX07PHYSTATUS, PIPERX07STARTBLOCK, PIPERX07STATUS, PIPERX07SYNCHEADER, PIPERX07VALID, PIPERX08CHARISK, PIPERX08DATA, PIPERX08DATAVALID, PIPERX08ELECIDLE, PIPERX08EQDONE, PIPERX08EQLPADAPTDONE, PIPERX08EQLPLFFSSEL, PIPERX08EQLPNEWTXCOEFFORPRESET, PIPERX08PHYSTATUS, PIPERX08STARTBLOCK, PIPERX08STATUS, PIPERX08SYNCHEADER, PIPERX08VALID, PIPERX09CHARISK, PIPERX09DATA, PIPERX09DATAVALID
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|
, PIPERX09ELECIDLE, PIPERX09EQDONE, PIPERX09EQLPADAPTDONE, PIPERX09EQLPLFFSSEL, PIPERX09EQLPNEWTXCOEFFORPRESET, PIPERX09PHYSTATUS, PIPERX09STARTBLOCK, PIPERX09STATUS, PIPERX09SYNCHEADER, PIPERX09VALID, PIPERX10CHARISK, PIPERX10DATA, PIPERX10DATAVALID, PIPERX10ELECIDLE, PIPERX10EQDONE, PIPERX10EQLPADAPTDONE, PIPERX10EQLPLFFSSEL, PIPERX10EQLPNEWTXCOEFFORPRESET, PIPERX10PHYSTATUS, PIPERX10STARTBLOCK, PIPERX10STATUS
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|
, PIPERX10SYNCHEADER, PIPERX10VALID, PIPERX11CHARISK, PIPERX11DATA, PIPERX11DATAVALID, PIPERX11ELECIDLE, PIPERX11EQDONE, PIPERX11EQLPADAPTDONE, PIPERX11EQLPLFFSSEL, PIPERX11EQLPNEWTXCOEFFORPRESET, PIPERX11PHYSTATUS, PIPERX11STARTBLOCK, PIPERX11STATUS, PIPERX11SYNCHEADER, PIPERX11VALID, PIPERX12CHARISK, PIPERX12DATA, PIPERX12DATAVALID, PIPERX12ELECIDLE, PIPERX12EQDONE, PIPERX12EQLPADAPTDONE
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|
, PIPERX12EQLPLFFSSEL, PIPERX12EQLPNEWTXCOEFFORPRESET, PIPERX12PHYSTATUS, PIPERX12STARTBLOCK, PIPERX12STATUS, PIPERX12SYNCHEADER, PIPERX12VALID, PIPERX13CHARISK, PIPERX13DATA, PIPERX13DATAVALID, PIPERX13ELECIDLE, PIPERX13EQDONE, PIPERX13EQLPADAPTDONE, PIPERX13EQLPLFFSSEL, PIPERX13EQLPNEWTXCOEFFORPRESET, PIPERX13PHYSTATUS, PIPERX13STARTBLOCK, PIPERX13STATUS, PIPERX13SYNCHEADER, PIPERX13VALID, PIPERX14CHARISK
|
|
, PIPERX14DATA, PIPERX14DATAVALID, PIPERX14ELECIDLE, PIPERX14EQDONE, PIPERX14EQLPADAPTDONE, PIPERX14EQLPLFFSSEL, PIPERX14EQLPNEWTXCOEFFORPRESET, PIPERX14PHYSTATUS, PIPERX14STARTBLOCK, PIPERX14STATUS, PIPERX14SYNCHEADER, PIPERX14VALID, PIPERX15CHARISK, PIPERX15DATA, PIPERX15DATAVALID, PIPERX15ELECIDLE, PIPERX15EQDONE, PIPERX15EQLPADAPTDONE, PIPERX15EQLPLFFSSEL, PIPERX15EQLPNEWTXCOEFFORPRESET, PIPERX15PHYSTATUS
|
|
, PIPERX15STARTBLOCK, PIPERX15STATUS, PIPERX15SYNCHEADER, PIPERX15VALID, PIPETX00EQCOEFF, PIPETX00EQDONE, PIPETX01EQCOEFF, PIPETX01EQDONE, PIPETX02EQCOEFF, PIPETX02EQDONE, PIPETX03EQCOEFF, PIPETX03EQDONE, PIPETX04EQCOEFF, PIPETX04EQDONE, PIPETX05EQCOEFF, PIPETX05EQDONE, PIPETX06EQCOEFF, PIPETX06EQDONE, PIPETX07EQCOEFF, PIPETX07EQDONE, PIPETX08EQCOEFF
|
|
, PIPETX08EQDONE, PIPETX09EQCOEFF, PIPETX09EQDONE, PIPETX10EQCOEFF, PIPETX10EQDONE, PIPETX11EQCOEFF, PIPETX11EQDONE, PIPETX12EQCOEFF, PIPETX12EQDONE, PIPETX13EQCOEFF, PIPETX13EQDONE, PIPETX14EQCOEFF, PIPETX14EQDONE, PIPETX15EQCOEFF, PIPETX15EQDONE, PLEQRESETEIEOSCOUNT, PLGEN2UPSTREAMPREFERDEEMPH, PLGEN34REDOEQSPEED, PLGEN34REDOEQUALIZATION, RESETN, SAXISCCTDATA
|
|
, SAXISCCTKEEP, SAXISCCTLAST, SAXISCCTUSER, SAXISCCTVALID, SAXISRQTDATA, SAXISRQTKEEP, SAXISRQTLAST, SAXISRQTUSER, SAXISRQTVALID, USERCLK, USERCLK2, USERCLKEN, USERSPAREIN);
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parameter ARI_CAP_ENABLE = "FALSE";
|
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parameter AUTO_FLR_RESPONSE = "FALSE";
|
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parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0;
|
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parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
|
|
parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080;
|
|
parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0;
|
|
parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE";
|
|
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
|
|
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512 = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE";
|
|
parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE";
|
|
parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE";
|
|
parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE";
|
|
parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0;
|
|
parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
|
|
parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0;
|
|
parameter AXISTEN_IF_RX_PARITY_EN = "TRUE";
|
|
parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE";
|
|
parameter AXISTEN_IF_TX_PARITY_EN = "TRUE";
|
|
parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
|
|
parameter CFG_BYPASS_MODE_ENABLE = "FALSE";
|
|
parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
|
|
parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
|
|
parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000;
|
|
parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00;
|
|
parameter [3:0] DEBUG_CAR_SPARE = 4'h0;
|
|
parameter [15:0] DEBUG_CFG_SPARE = 16'h0000;
|
|
parameter [15:0] DEBUG_LL_SPARE = 16'h0000;
|
|
parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE";
|
|
parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE";
|
|
parameter [15:0] DEBUG_PL_SPARE = 16'h0000;
|
|
parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE";
|
|
parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE";
|
|
parameter [15:0] DEBUG_TL_SPARE = 16'h0000;
|
|
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
|
|
parameter DSN_CAP_ENABLE = "FALSE";
|
|
parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
|
|
parameter HEADER_TYPE_OVERRIDE = "FALSE";
|
|
parameter IS_SWITCH_PORT = "FALSE";
|
|
parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
|
|
parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
|
|
parameter LL_ACK_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
|
|
parameter LL_DISABLE_SCHED_TX_NAK = "FALSE";
|
|
parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE";
|
|
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
|
|
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
|
|
parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE";
|
|
parameter LL_RX_TLP_PARITY_GEN = "TRUE";
|
|
parameter LL_TX_TLP_PARITY_CHK = "TRUE";
|
|
parameter [15:0] LL_USER_SPARE = 16'h0000;
|
|
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250;
|
|
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
|
|
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
|
|
parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000;
|
|
parameter MCAP_CONFIGURE_OVERRIDE = "FALSE";
|
|
parameter MCAP_ENABLE = "FALSE";
|
|
parameter MCAP_EOS_DESIGN_SWITCH = "FALSE";
|
|
parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000;
|
|
parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE";
|
|
parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE";
|
|
parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE";
|
|
parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE";
|
|
parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE";
|
|
parameter [15:0] MCAP_VSEC_ID = 16'h0000;
|
|
parameter [11:0] MCAP_VSEC_LEN = 12'h02C;
|
|
parameter [3:0] MCAP_VSEC_REV = 4'h0;
|
|
parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE";
|
|
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
|
|
parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80;
|
|
parameter [23:0] PF0_CLASS_CODE = 24'h000000;
|
|
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE";
|
|
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
|
|
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
|
|
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
|
|
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
|
|
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
|
|
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
|
|
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
|
|
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
|
|
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
|
|
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7;
|
|
parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0;
|
|
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
|
|
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
|
|
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
|
|
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
|
|
parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
|
|
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04;
|
|
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [7:0] PF0_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
|
|
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
|
|
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
|
|
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
|
|
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
|
|
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
|
|
parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000;
|
|
parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
|
|
parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter PF0_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
|
|
parameter PF0_VC_CAP_ENABLE = "FALSE";
|
|
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
|
|
parameter [3:0] PF0_VC_CAP_VER = 4'h1;
|
|
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80;
|
|
parameter [23:0] PF1_CLASS_CODE = 24'h000000;
|
|
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
|
|
parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF2_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80;
|
|
parameter [23:0] PF2_CLASS_CODE = 24'h000000;
|
|
parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF2_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [2:0] PF2_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF2_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF2_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
|
|
parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF3_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80;
|
|
parameter [23:0] PF3_CLASS_CODE = 24'h000000;
|
|
parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF3_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [2:0] PF3_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF3_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF3_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
|
|
parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE";
|
|
parameter PL_DEEMPH_SOURCE_SELECT = "TRUE";
|
|
parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE";
|
|
parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE";
|
|
parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE";
|
|
parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE";
|
|
parameter PL_DISABLE_DC_BALANCE = "FALSE";
|
|
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
|
|
parameter PL_DISABLE_LANE_REVERSAL = "FALSE";
|
|
parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0;
|
|
parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE";
|
|
parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE";
|
|
parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000;
|
|
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
|
|
parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0;
|
|
parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0;
|
|
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
|
|
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
|
|
parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0;
|
|
parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33;
|
|
parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44;
|
|
parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE";
|
|
parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0;
|
|
parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0;
|
|
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
|
|
parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE";
|
|
parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE";
|
|
parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE";
|
|
parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE";
|
|
parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE";
|
|
parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00;
|
|
parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4;
|
|
parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08;
|
|
parameter integer PL_N_FTS = 255;
|
|
parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE";
|
|
parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE";
|
|
parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00;
|
|
parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0;
|
|
parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0;
|
|
parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0;
|
|
parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0;
|
|
parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0;
|
|
parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0;
|
|
parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0;
|
|
parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0;
|
|
parameter PL_SRIS_ENABLE = "FALSE";
|
|
parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00;
|
|
parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00;
|
|
parameter PL_UPSTREAM_FACING = "TRUE";
|
|
parameter [15:0] PL_USER_SPARE = 16'h0000;
|
|
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500;
|
|
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8;
|
|
parameter PM_ENABLE_L23_ENTRY = "FALSE";
|
|
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
|
|
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100;
|
|
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000;
|
|
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000;
|
|
parameter SIM_VERSION = "1.0";
|
|
parameter SPARE_BIT0 = "FALSE";
|
|
parameter integer SPARE_BIT1 = 0;
|
|
parameter integer SPARE_BIT2 = 0;
|
|
parameter SPARE_BIT3 = "FALSE";
|
|
parameter integer SPARE_BIT4 = 0;
|
|
parameter integer SPARE_BIT5 = 0;
|
|
parameter integer SPARE_BIT6 = 0;
|
|
parameter integer SPARE_BIT7 = 0;
|
|
parameter integer SPARE_BIT8 = 0;
|
|
parameter [7:0] SPARE_BYTE0 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE1 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE2 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE3 = 8'h00;
|
|
parameter [31:0] SPARE_WORD0 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD1 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD2 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD3 = 32'h00000000;
|
|
parameter [3:0] SRIOV_CAP_ENABLE = 4'h0;
|
|
parameter TL2CFG_IF_PARITY_CHK = "TRUE";
|
|
parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0;
|
|
parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1;
|
|
parameter [11:0] TL_CREDITS_CD = 12'h000;
|
|
parameter [7:0] TL_CREDITS_CH = 8'h00;
|
|
parameter [11:0] TL_CREDITS_NPD = 12'h004;
|
|
parameter [7:0] TL_CREDITS_NPH = 8'h20;
|
|
parameter [11:0] TL_CREDITS_PD = 12'h0E0;
|
|
parameter [7:0] TL_CREDITS_PH = 8'h20;
|
|
parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02;
|
|
parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08;
|
|
parameter [1:0] TL_PF_ENABLE_REG = 2'h0;
|
|
parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0;
|
|
parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE";
|
|
parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE";
|
|
parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE";
|
|
parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE";
|
|
parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE";
|
|
parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE";
|
|
parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE";
|
|
parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE";
|
|
parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE";
|
|
parameter [15:0] TL_USER_SPARE = 16'h0000;
|
|
parameter TPH_FROM_RAM_PIPELINE = "FALSE";
|
|
parameter TPH_TO_RAM_PIPELINE = "FALSE";
|
|
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80;
|
|
parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer VFG0_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer VFG1_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer VFG2_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer VFG3_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
output [7:0] AXIUSEROUT;
|
|
output [7:0] CFGBUSNUMBER;
|
|
output [1:0] CFGCURRENTSPEED;
|
|
output CFGERRCOROUT;
|
|
output CFGERRFATALOUT;
|
|
output CFGERRNONFATALOUT;
|
|
output [7:0] CFGEXTFUNCTIONNUMBER;
|
|
output CFGEXTREADRECEIVED;
|
|
output [9:0] CFGEXTREGISTERNUMBER;
|
|
output [3:0] CFGEXTWRITEBYTEENABLE;
|
|
output [31:0] CFGEXTWRITEDATA;
|
|
output CFGEXTWRITERECEIVED;
|
|
output [11:0] CFGFCCPLD;
|
|
output [7:0] CFGFCCPLH;
|
|
output [11:0] CFGFCNPD;
|
|
output [7:0] CFGFCNPH;
|
|
output [11:0] CFGFCPD;
|
|
output [7:0] CFGFCPH;
|
|
output [3:0] CFGFLRINPROCESS;
|
|
output [11:0] CFGFUNCTIONPOWERSTATE;
|
|
output [15:0] CFGFUNCTIONSTATUS;
|
|
output CFGHOTRESETOUT;
|
|
output [31:0] CFGINTERRUPTMSIDATA;
|
|
output [3:0] CFGINTERRUPTMSIENABLE;
|
|
output CFGINTERRUPTMSIFAIL;
|
|
output CFGINTERRUPTMSIMASKUPDATE;
|
|
output [11:0] CFGINTERRUPTMSIMMENABLE;
|
|
output CFGINTERRUPTMSISENT;
|
|
output [3:0] CFGINTERRUPTMSIXENABLE;
|
|
output [3:0] CFGINTERRUPTMSIXMASK;
|
|
output CFGINTERRUPTMSIXVECPENDINGSTATUS;
|
|
output CFGINTERRUPTSENT;
|
|
output [1:0] CFGLINKPOWERSTATE;
|
|
output [4:0] CFGLOCALERROROUT;
|
|
output CFGLOCALERRORVALID;
|
|
output CFGLTRENABLE;
|
|
output [5:0] CFGLTSSMSTATE;
|
|
output [1:0] CFGMAXPAYLOAD;
|
|
output [2:0] CFGMAXREADREQ;
|
|
output [31:0] CFGMGMTREADDATA;
|
|
output CFGMGMTREADWRITEDONE;
|
|
output CFGMSGRECEIVED;
|
|
output [7:0] CFGMSGRECEIVEDDATA;
|
|
output [4:0] CFGMSGRECEIVEDTYPE;
|
|
output CFGMSGTRANSMITDONE;
|
|
output [12:0] CFGMSIXRAMADDRESS;
|
|
output CFGMSIXRAMREADENABLE;
|
|
output [3:0] CFGMSIXRAMWRITEBYTEENABLE;
|
|
output [35:0] CFGMSIXRAMWRITEDATA;
|
|
output [2:0] CFGNEGOTIATEDWIDTH;
|
|
output [1:0] CFGOBFFENABLE;
|
|
output CFGPHYLINKDOWN;
|
|
output [1:0] CFGPHYLINKSTATUS;
|
|
output CFGPLSTATUSCHANGE;
|
|
output CFGPOWERSTATECHANGEINTERRUPT;
|
|
output [3:0] CFGRCBSTATUS;
|
|
output [1:0] CFGRXPMSTATE;
|
|
output [11:0] CFGTPHRAMADDRESS;
|
|
output CFGTPHRAMREADENABLE;
|
|
output [3:0] CFGTPHRAMWRITEBYTEENABLE;
|
|
output [35:0] CFGTPHRAMWRITEDATA;
|
|
output [3:0] CFGTPHREQUESTERENABLE;
|
|
output [11:0] CFGTPHSTMODE;
|
|
output [1:0] CFGTXPMSTATE;
|
|
output CONFMCAPDESIGNSWITCH;
|
|
output CONFMCAPEOS;
|
|
output CONFMCAPINUSEBYPCIE;
|
|
output CONFREQREADY;
|
|
output [31:0] CONFRESPRDATA;
|
|
output CONFRESPVALID;
|
|
output [31:0] DBGCTRL0OUT;
|
|
output [31:0] DBGCTRL1OUT;
|
|
output [255:0] DBGDATA0OUT;
|
|
output [255:0] DBGDATA1OUT;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output [255:0] MAXISCQTDATA;
|
|
output [7:0] MAXISCQTKEEP;
|
|
output MAXISCQTLAST;
|
|
output [87:0] MAXISCQTUSER;
|
|
output MAXISCQTVALID;
|
|
output [255:0] MAXISRCTDATA;
|
|
output [7:0] MAXISRCTKEEP;
|
|
output MAXISRCTLAST;
|
|
output [74:0] MAXISRCTUSER;
|
|
output MAXISRCTVALID;
|
|
output [8:0] MIREPLAYRAMADDRESS0;
|
|
output [8:0] MIREPLAYRAMADDRESS1;
|
|
output MIREPLAYRAMREADENABLE0;
|
|
output MIREPLAYRAMREADENABLE1;
|
|
output [127:0] MIREPLAYRAMWRITEDATA0;
|
|
output [127:0] MIREPLAYRAMWRITEDATA1;
|
|
output MIREPLAYRAMWRITEENABLE0;
|
|
output MIREPLAYRAMWRITEENABLE1;
|
|
output [8:0] MIRXCOMPLETIONRAMREADADDRESS0;
|
|
output [8:0] MIRXCOMPLETIONRAMREADADDRESS1;
|
|
output [1:0] MIRXCOMPLETIONRAMREADENABLE0;
|
|
output [1:0] MIRXCOMPLETIONRAMREADENABLE1;
|
|
output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0;
|
|
output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1;
|
|
output [143:0] MIRXCOMPLETIONRAMWRITEDATA0;
|
|
output [143:0] MIRXCOMPLETIONRAMWRITEDATA1;
|
|
output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0;
|
|
output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1;
|
|
output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0;
|
|
output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1;
|
|
output MIRXPOSTEDREQUESTRAMREADENABLE0;
|
|
output MIRXPOSTEDREQUESTRAMREADENABLE1;
|
|
output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0;
|
|
output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1;
|
|
output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0;
|
|
output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1;
|
|
output MIRXPOSTEDREQUESTRAMWRITEENABLE0;
|
|
output MIRXPOSTEDREQUESTRAMWRITEENABLE1;
|
|
output [5:0] PCIECQNPREQCOUNT;
|
|
output PCIEPERST0B;
|
|
output PCIEPERST1B;
|
|
output [5:0] PCIERQSEQNUM0;
|
|
output [5:0] PCIERQSEQNUM1;
|
|
output PCIERQSEQNUMVLD0;
|
|
output PCIERQSEQNUMVLD1;
|
|
output [7:0] PCIERQTAG0;
|
|
output [7:0] PCIERQTAG1;
|
|
output [3:0] PCIERQTAGAV;
|
|
output PCIERQTAGVLD0;
|
|
output PCIERQTAGVLD1;
|
|
output [3:0] PCIETFCNPDAV;
|
|
output [3:0] PCIETFCNPHAV;
|
|
output [1:0] PIPERX00EQCONTROL;
|
|
output PIPERX00POLARITY;
|
|
output [1:0] PIPERX01EQCONTROL;
|
|
output PIPERX01POLARITY;
|
|
output [1:0] PIPERX02EQCONTROL;
|
|
output PIPERX02POLARITY;
|
|
output [1:0] PIPERX03EQCONTROL;
|
|
output PIPERX03POLARITY;
|
|
output [1:0] PIPERX04EQCONTROL;
|
|
output PIPERX04POLARITY;
|
|
output [1:0] PIPERX05EQCONTROL;
|
|
output PIPERX05POLARITY;
|
|
output [1:0] PIPERX06EQCONTROL;
|
|
output PIPERX06POLARITY;
|
|
output [1:0] PIPERX07EQCONTROL;
|
|
output PIPERX07POLARITY;
|
|
output [1:0] PIPERX08EQCONTROL;
|
|
output PIPERX08POLARITY;
|
|
output [1:0] PIPERX09EQCONTROL;
|
|
output PIPERX09POLARITY;
|
|
output [1:0] PIPERX10EQCONTROL;
|
|
output PIPERX10POLARITY;
|
|
output [1:0] PIPERX11EQCONTROL;
|
|
output PIPERX11POLARITY;
|
|
output [1:0] PIPERX12EQCONTROL;
|
|
output PIPERX12POLARITY;
|
|
output [1:0] PIPERX13EQCONTROL;
|
|
output PIPERX13POLARITY;
|
|
output [1:0] PIPERX14EQCONTROL;
|
|
output PIPERX14POLARITY;
|
|
output [1:0] PIPERX15EQCONTROL;
|
|
output PIPERX15POLARITY;
|
|
output [5:0] PIPERXEQLPLFFS;
|
|
output [3:0] PIPERXEQLPTXPRESET;
|
|
output [1:0] PIPETX00CHARISK;
|
|
output PIPETX00COMPLIANCE;
|
|
output [31:0] PIPETX00DATA;
|
|
output PIPETX00DATAVALID;
|
|
output PIPETX00ELECIDLE;
|
|
output [1:0] PIPETX00EQCONTROL;
|
|
output [5:0] PIPETX00EQDEEMPH;
|
|
output [1:0] PIPETX00POWERDOWN;
|
|
output PIPETX00STARTBLOCK;
|
|
output [1:0] PIPETX00SYNCHEADER;
|
|
output [1:0] PIPETX01CHARISK;
|
|
output PIPETX01COMPLIANCE;
|
|
output [31:0] PIPETX01DATA;
|
|
output PIPETX01DATAVALID;
|
|
output PIPETX01ELECIDLE;
|
|
output [1:0] PIPETX01EQCONTROL;
|
|
output [5:0] PIPETX01EQDEEMPH;
|
|
output [1:0] PIPETX01POWERDOWN;
|
|
output PIPETX01STARTBLOCK;
|
|
output [1:0] PIPETX01SYNCHEADER;
|
|
output [1:0] PIPETX02CHARISK;
|
|
output PIPETX02COMPLIANCE;
|
|
output [31:0] PIPETX02DATA;
|
|
output PIPETX02DATAVALID;
|
|
output PIPETX02ELECIDLE;
|
|
output [1:0] PIPETX02EQCONTROL;
|
|
output [5:0] PIPETX02EQDEEMPH;
|
|
output [1:0] PIPETX02POWERDOWN;
|
|
output PIPETX02STARTBLOCK;
|
|
output [1:0] PIPETX02SYNCHEADER;
|
|
output [1:0] PIPETX03CHARISK;
|
|
output PIPETX03COMPLIANCE;
|
|
output [31:0] PIPETX03DATA;
|
|
output PIPETX03DATAVALID;
|
|
output PIPETX03ELECIDLE;
|
|
output [1:0] PIPETX03EQCONTROL;
|
|
output [5:0] PIPETX03EQDEEMPH;
|
|
output [1:0] PIPETX03POWERDOWN;
|
|
output PIPETX03STARTBLOCK;
|
|
output [1:0] PIPETX03SYNCHEADER;
|
|
output [1:0] PIPETX04CHARISK;
|
|
output PIPETX04COMPLIANCE;
|
|
output [31:0] PIPETX04DATA;
|
|
output PIPETX04DATAVALID;
|
|
output PIPETX04ELECIDLE;
|
|
output [1:0] PIPETX04EQCONTROL;
|
|
output [5:0] PIPETX04EQDEEMPH;
|
|
output [1:0] PIPETX04POWERDOWN;
|
|
output PIPETX04STARTBLOCK;
|
|
output [1:0] PIPETX04SYNCHEADER;
|
|
output [1:0] PIPETX05CHARISK;
|
|
output PIPETX05COMPLIANCE;
|
|
output [31:0] PIPETX05DATA;
|
|
output PIPETX05DATAVALID;
|
|
output PIPETX05ELECIDLE;
|
|
output [1:0] PIPETX05EQCONTROL;
|
|
output [5:0] PIPETX05EQDEEMPH;
|
|
output [1:0] PIPETX05POWERDOWN;
|
|
output PIPETX05STARTBLOCK;
|
|
output [1:0] PIPETX05SYNCHEADER;
|
|
output [1:0] PIPETX06CHARISK;
|
|
output PIPETX06COMPLIANCE;
|
|
output [31:0] PIPETX06DATA;
|
|
output PIPETX06DATAVALID;
|
|
output PIPETX06ELECIDLE;
|
|
output [1:0] PIPETX06EQCONTROL;
|
|
output [5:0] PIPETX06EQDEEMPH;
|
|
output [1:0] PIPETX06POWERDOWN;
|
|
output PIPETX06STARTBLOCK;
|
|
output [1:0] PIPETX06SYNCHEADER;
|
|
output [1:0] PIPETX07CHARISK;
|
|
output PIPETX07COMPLIANCE;
|
|
output [31:0] PIPETX07DATA;
|
|
output PIPETX07DATAVALID;
|
|
output PIPETX07ELECIDLE;
|
|
output [1:0] PIPETX07EQCONTROL;
|
|
output [5:0] PIPETX07EQDEEMPH;
|
|
output [1:0] PIPETX07POWERDOWN;
|
|
output PIPETX07STARTBLOCK;
|
|
output [1:0] PIPETX07SYNCHEADER;
|
|
output [1:0] PIPETX08CHARISK;
|
|
output PIPETX08COMPLIANCE;
|
|
output [31:0] PIPETX08DATA;
|
|
output PIPETX08DATAVALID;
|
|
output PIPETX08ELECIDLE;
|
|
output [1:0] PIPETX08EQCONTROL;
|
|
output [5:0] PIPETX08EQDEEMPH;
|
|
output [1:0] PIPETX08POWERDOWN;
|
|
output PIPETX08STARTBLOCK;
|
|
output [1:0] PIPETX08SYNCHEADER;
|
|
output [1:0] PIPETX09CHARISK;
|
|
output PIPETX09COMPLIANCE;
|
|
output [31:0] PIPETX09DATA;
|
|
output PIPETX09DATAVALID;
|
|
output PIPETX09ELECIDLE;
|
|
output [1:0] PIPETX09EQCONTROL;
|
|
output [5:0] PIPETX09EQDEEMPH;
|
|
output [1:0] PIPETX09POWERDOWN;
|
|
output PIPETX09STARTBLOCK;
|
|
output [1:0] PIPETX09SYNCHEADER;
|
|
output [1:0] PIPETX10CHARISK;
|
|
output PIPETX10COMPLIANCE;
|
|
output [31:0] PIPETX10DATA;
|
|
output PIPETX10DATAVALID;
|
|
output PIPETX10ELECIDLE;
|
|
output [1:0] PIPETX10EQCONTROL;
|
|
output [5:0] PIPETX10EQDEEMPH;
|
|
output [1:0] PIPETX10POWERDOWN;
|
|
output PIPETX10STARTBLOCK;
|
|
output [1:0] PIPETX10SYNCHEADER;
|
|
output [1:0] PIPETX11CHARISK;
|
|
output PIPETX11COMPLIANCE;
|
|
output [31:0] PIPETX11DATA;
|
|
output PIPETX11DATAVALID;
|
|
output PIPETX11ELECIDLE;
|
|
output [1:0] PIPETX11EQCONTROL;
|
|
output [5:0] PIPETX11EQDEEMPH;
|
|
output [1:0] PIPETX11POWERDOWN;
|
|
output PIPETX11STARTBLOCK;
|
|
output [1:0] PIPETX11SYNCHEADER;
|
|
output [1:0] PIPETX12CHARISK;
|
|
output PIPETX12COMPLIANCE;
|
|
output [31:0] PIPETX12DATA;
|
|
output PIPETX12DATAVALID;
|
|
output PIPETX12ELECIDLE;
|
|
output [1:0] PIPETX12EQCONTROL;
|
|
output [5:0] PIPETX12EQDEEMPH;
|
|
output [1:0] PIPETX12POWERDOWN;
|
|
output PIPETX12STARTBLOCK;
|
|
output [1:0] PIPETX12SYNCHEADER;
|
|
output [1:0] PIPETX13CHARISK;
|
|
output PIPETX13COMPLIANCE;
|
|
output [31:0] PIPETX13DATA;
|
|
output PIPETX13DATAVALID;
|
|
output PIPETX13ELECIDLE;
|
|
output [1:0] PIPETX13EQCONTROL;
|
|
output [5:0] PIPETX13EQDEEMPH;
|
|
output [1:0] PIPETX13POWERDOWN;
|
|
output PIPETX13STARTBLOCK;
|
|
output [1:0] PIPETX13SYNCHEADER;
|
|
output [1:0] PIPETX14CHARISK;
|
|
output PIPETX14COMPLIANCE;
|
|
output [31:0] PIPETX14DATA;
|
|
output PIPETX14DATAVALID;
|
|
output PIPETX14ELECIDLE;
|
|
output [1:0] PIPETX14EQCONTROL;
|
|
output [5:0] PIPETX14EQDEEMPH;
|
|
output [1:0] PIPETX14POWERDOWN;
|
|
output PIPETX14STARTBLOCK;
|
|
output [1:0] PIPETX14SYNCHEADER;
|
|
output [1:0] PIPETX15CHARISK;
|
|
output PIPETX15COMPLIANCE;
|
|
output [31:0] PIPETX15DATA;
|
|
output PIPETX15DATAVALID;
|
|
output PIPETX15ELECIDLE;
|
|
output [1:0] PIPETX15EQCONTROL;
|
|
output [5:0] PIPETX15EQDEEMPH;
|
|
output [1:0] PIPETX15POWERDOWN;
|
|
output PIPETX15STARTBLOCK;
|
|
output [1:0] PIPETX15SYNCHEADER;
|
|
output PIPETXDEEMPH;
|
|
output [2:0] PIPETXMARGIN;
|
|
output [1:0] PIPETXRATE;
|
|
output PIPETXRCVRDET;
|
|
output PIPETXRESET;
|
|
output PIPETXSWING;
|
|
output PLEQINPROGRESS;
|
|
output [1:0] PLEQPHASE;
|
|
output PLGEN34EQMISMATCH;
|
|
output [3:0] SAXISCCTREADY;
|
|
output [3:0] SAXISRQTREADY;
|
|
output [31:0] USERSPAREOUT;
|
|
input [7:0] AXIUSERIN;
|
|
input CFGCONFIGSPACEENABLE;
|
|
input [15:0] CFGDEVIDPF0;
|
|
input [15:0] CFGDEVIDPF1;
|
|
input [15:0] CFGDEVIDPF2;
|
|
input [15:0] CFGDEVIDPF3;
|
|
input [7:0] CFGDSBUSNUMBER;
|
|
input [4:0] CFGDSDEVICENUMBER;
|
|
input [2:0] CFGDSFUNCTIONNUMBER;
|
|
input [63:0] CFGDSN;
|
|
input [7:0] CFGDSPORTNUMBER;
|
|
input CFGERRCORIN;
|
|
input CFGERRUNCORIN;
|
|
input [31:0] CFGEXTREADDATA;
|
|
input CFGEXTREADDATAVALID;
|
|
input [2:0] CFGFCSEL;
|
|
input [3:0] CFGFLRDONE;
|
|
input CFGHOTRESETIN;
|
|
input [3:0] CFGINTERRUPTINT;
|
|
input [2:0] CFGINTERRUPTMSIATTR;
|
|
input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
|
|
input [31:0] CFGINTERRUPTMSIINT;
|
|
input [31:0] CFGINTERRUPTMSIPENDINGSTATUS;
|
|
input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE;
|
|
input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM;
|
|
input [1:0] CFGINTERRUPTMSISELECT;
|
|
input CFGINTERRUPTMSITPHPRESENT;
|
|
input [7:0] CFGINTERRUPTMSITPHSTTAG;
|
|
input [1:0] CFGINTERRUPTMSITPHTYPE;
|
|
input [63:0] CFGINTERRUPTMSIXADDRESS;
|
|
input [31:0] CFGINTERRUPTMSIXDATA;
|
|
input CFGINTERRUPTMSIXINT;
|
|
input [1:0] CFGINTERRUPTMSIXVECPENDING;
|
|
input [3:0] CFGINTERRUPTPENDING;
|
|
input CFGLINKTRAININGENABLE;
|
|
input [9:0] CFGMGMTADDR;
|
|
input [3:0] CFGMGMTBYTEENABLE;
|
|
input CFGMGMTDEBUGACCESS;
|
|
input [7:0] CFGMGMTFUNCTIONNUMBER;
|
|
input CFGMGMTREAD;
|
|
input CFGMGMTWRITE;
|
|
input [31:0] CFGMGMTWRITEDATA;
|
|
input CFGMSGTRANSMIT;
|
|
input [31:0] CFGMSGTRANSMITDATA;
|
|
input [2:0] CFGMSGTRANSMITTYPE;
|
|
input [35:0] CFGMSIXRAMREADDATA;
|
|
input CFGPMASPML1ENTRYREJECT;
|
|
input CFGPMASPMTXL0SENTRYDISABLE;
|
|
input CFGPOWERSTATECHANGEACK;
|
|
input CFGREQPMTRANSITIONL23READY;
|
|
input [7:0] CFGREVIDPF0;
|
|
input [7:0] CFGREVIDPF1;
|
|
input [7:0] CFGREVIDPF2;
|
|
input [7:0] CFGREVIDPF3;
|
|
input [15:0] CFGSUBSYSIDPF0;
|
|
input [15:0] CFGSUBSYSIDPF1;
|
|
input [15:0] CFGSUBSYSIDPF2;
|
|
input [15:0] CFGSUBSYSIDPF3;
|
|
input [15:0] CFGSUBSYSVENDID;
|
|
input [35:0] CFGTPHRAMREADDATA;
|
|
input [15:0] CFGVENDID;
|
|
input CFGVFFLRDONE;
|
|
input [7:0] CFGVFFLRFUNCNUM;
|
|
input CONFMCAPREQUESTBYCONF;
|
|
input [31:0] CONFREQDATA;
|
|
input [3:0] CONFREQREGNUM;
|
|
input [1:0] CONFREQTYPE;
|
|
input CONFREQVALID;
|
|
input CORECLK;
|
|
input CORECLKMIREPLAYRAM0;
|
|
input CORECLKMIREPLAYRAM1;
|
|
input CORECLKMIRXCOMPLETIONRAM0;
|
|
input CORECLKMIRXCOMPLETIONRAM1;
|
|
input CORECLKMIRXPOSTEDREQUESTRAM0;
|
|
input CORECLKMIRXPOSTEDREQUESTRAM1;
|
|
input [5:0] DBGSEL0;
|
|
input [5:0] DBGSEL1;
|
|
input [9:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input [21:0] MAXISCQTREADY;
|
|
input [21:0] MAXISRCTREADY;
|
|
input MCAPCLK;
|
|
input MCAPPERST0B;
|
|
input MCAPPERST1B;
|
|
input MGMTRESETN;
|
|
input MGMTSTICKYRESETN;
|
|
input [5:0] MIREPLAYRAMERRCOR;
|
|
input [5:0] MIREPLAYRAMERRUNCOR;
|
|
input [127:0] MIREPLAYRAMREADDATA0;
|
|
input [127:0] MIREPLAYRAMREADDATA1;
|
|
input [11:0] MIRXCOMPLETIONRAMERRCOR;
|
|
input [11:0] MIRXCOMPLETIONRAMERRUNCOR;
|
|
input [143:0] MIRXCOMPLETIONRAMREADDATA0;
|
|
input [143:0] MIRXCOMPLETIONRAMREADDATA1;
|
|
input [5:0] MIRXPOSTEDREQUESTRAMERRCOR;
|
|
input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR;
|
|
input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0;
|
|
input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1;
|
|
input [1:0] PCIECOMPLDELIVERED;
|
|
input [7:0] PCIECOMPLDELIVEREDTAG0;
|
|
input [7:0] PCIECOMPLDELIVEREDTAG1;
|
|
input [1:0] PCIECQNPREQ;
|
|
input PCIECQNPUSERCREDITRCVD;
|
|
input PCIECQPIPELINEEMPTY;
|
|
input PCIEPOSTEDREQDELIVERED;
|
|
input PIPECLK;
|
|
input PIPECLKEN;
|
|
input [5:0] PIPEEQFS;
|
|
input [5:0] PIPEEQLF;
|
|
input PIPERESETN;
|
|
input [1:0] PIPERX00CHARISK;
|
|
input [31:0] PIPERX00DATA;
|
|
input PIPERX00DATAVALID;
|
|
input PIPERX00ELECIDLE;
|
|
input PIPERX00EQDONE;
|
|
input PIPERX00EQLPADAPTDONE;
|
|
input PIPERX00EQLPLFFSSEL;
|
|
input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX00PHYSTATUS;
|
|
input [1:0] PIPERX00STARTBLOCK;
|
|
input [2:0] PIPERX00STATUS;
|
|
input [1:0] PIPERX00SYNCHEADER;
|
|
input PIPERX00VALID;
|
|
input [1:0] PIPERX01CHARISK;
|
|
input [31:0] PIPERX01DATA;
|
|
input PIPERX01DATAVALID;
|
|
input PIPERX01ELECIDLE;
|
|
input PIPERX01EQDONE;
|
|
input PIPERX01EQLPADAPTDONE;
|
|
input PIPERX01EQLPLFFSSEL;
|
|
input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX01PHYSTATUS;
|
|
input [1:0] PIPERX01STARTBLOCK;
|
|
input [2:0] PIPERX01STATUS;
|
|
input [1:0] PIPERX01SYNCHEADER;
|
|
input PIPERX01VALID;
|
|
input [1:0] PIPERX02CHARISK;
|
|
input [31:0] PIPERX02DATA;
|
|
input PIPERX02DATAVALID;
|
|
input PIPERX02ELECIDLE;
|
|
input PIPERX02EQDONE;
|
|
input PIPERX02EQLPADAPTDONE;
|
|
input PIPERX02EQLPLFFSSEL;
|
|
input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX02PHYSTATUS;
|
|
input [1:0] PIPERX02STARTBLOCK;
|
|
input [2:0] PIPERX02STATUS;
|
|
input [1:0] PIPERX02SYNCHEADER;
|
|
input PIPERX02VALID;
|
|
input [1:0] PIPERX03CHARISK;
|
|
input [31:0] PIPERX03DATA;
|
|
input PIPERX03DATAVALID;
|
|
input PIPERX03ELECIDLE;
|
|
input PIPERX03EQDONE;
|
|
input PIPERX03EQLPADAPTDONE;
|
|
input PIPERX03EQLPLFFSSEL;
|
|
input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX03PHYSTATUS;
|
|
input [1:0] PIPERX03STARTBLOCK;
|
|
input [2:0] PIPERX03STATUS;
|
|
input [1:0] PIPERX03SYNCHEADER;
|
|
input PIPERX03VALID;
|
|
input [1:0] PIPERX04CHARISK;
|
|
input [31:0] PIPERX04DATA;
|
|
input PIPERX04DATAVALID;
|
|
input PIPERX04ELECIDLE;
|
|
input PIPERX04EQDONE;
|
|
input PIPERX04EQLPADAPTDONE;
|
|
input PIPERX04EQLPLFFSSEL;
|
|
input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX04PHYSTATUS;
|
|
input [1:0] PIPERX04STARTBLOCK;
|
|
input [2:0] PIPERX04STATUS;
|
|
input [1:0] PIPERX04SYNCHEADER;
|
|
input PIPERX04VALID;
|
|
input [1:0] PIPERX05CHARISK;
|
|
input [31:0] PIPERX05DATA;
|
|
input PIPERX05DATAVALID;
|
|
input PIPERX05ELECIDLE;
|
|
input PIPERX05EQDONE;
|
|
input PIPERX05EQLPADAPTDONE;
|
|
input PIPERX05EQLPLFFSSEL;
|
|
input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX05PHYSTATUS;
|
|
input [1:0] PIPERX05STARTBLOCK;
|
|
input [2:0] PIPERX05STATUS;
|
|
input [1:0] PIPERX05SYNCHEADER;
|
|
input PIPERX05VALID;
|
|
input [1:0] PIPERX06CHARISK;
|
|
input [31:0] PIPERX06DATA;
|
|
input PIPERX06DATAVALID;
|
|
input PIPERX06ELECIDLE;
|
|
input PIPERX06EQDONE;
|
|
input PIPERX06EQLPADAPTDONE;
|
|
input PIPERX06EQLPLFFSSEL;
|
|
input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX06PHYSTATUS;
|
|
input [1:0] PIPERX06STARTBLOCK;
|
|
input [2:0] PIPERX06STATUS;
|
|
input [1:0] PIPERX06SYNCHEADER;
|
|
input PIPERX06VALID;
|
|
input [1:0] PIPERX07CHARISK;
|
|
input [31:0] PIPERX07DATA;
|
|
input PIPERX07DATAVALID;
|
|
input PIPERX07ELECIDLE;
|
|
input PIPERX07EQDONE;
|
|
input PIPERX07EQLPADAPTDONE;
|
|
input PIPERX07EQLPLFFSSEL;
|
|
input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX07PHYSTATUS;
|
|
input [1:0] PIPERX07STARTBLOCK;
|
|
input [2:0] PIPERX07STATUS;
|
|
input [1:0] PIPERX07SYNCHEADER;
|
|
input PIPERX07VALID;
|
|
input [1:0] PIPERX08CHARISK;
|
|
input [31:0] PIPERX08DATA;
|
|
input PIPERX08DATAVALID;
|
|
input PIPERX08ELECIDLE;
|
|
input PIPERX08EQDONE;
|
|
input PIPERX08EQLPADAPTDONE;
|
|
input PIPERX08EQLPLFFSSEL;
|
|
input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX08PHYSTATUS;
|
|
input [1:0] PIPERX08STARTBLOCK;
|
|
input [2:0] PIPERX08STATUS;
|
|
input [1:0] PIPERX08SYNCHEADER;
|
|
input PIPERX08VALID;
|
|
input [1:0] PIPERX09CHARISK;
|
|
input [31:0] PIPERX09DATA;
|
|
input PIPERX09DATAVALID;
|
|
input PIPERX09ELECIDLE;
|
|
input PIPERX09EQDONE;
|
|
input PIPERX09EQLPADAPTDONE;
|
|
input PIPERX09EQLPLFFSSEL;
|
|
input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX09PHYSTATUS;
|
|
input [1:0] PIPERX09STARTBLOCK;
|
|
input [2:0] PIPERX09STATUS;
|
|
input [1:0] PIPERX09SYNCHEADER;
|
|
input PIPERX09VALID;
|
|
input [1:0] PIPERX10CHARISK;
|
|
input [31:0] PIPERX10DATA;
|
|
input PIPERX10DATAVALID;
|
|
input PIPERX10ELECIDLE;
|
|
input PIPERX10EQDONE;
|
|
input PIPERX10EQLPADAPTDONE;
|
|
input PIPERX10EQLPLFFSSEL;
|
|
input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX10PHYSTATUS;
|
|
input [1:0] PIPERX10STARTBLOCK;
|
|
input [2:0] PIPERX10STATUS;
|
|
input [1:0] PIPERX10SYNCHEADER;
|
|
input PIPERX10VALID;
|
|
input [1:0] PIPERX11CHARISK;
|
|
input [31:0] PIPERX11DATA;
|
|
input PIPERX11DATAVALID;
|
|
input PIPERX11ELECIDLE;
|
|
input PIPERX11EQDONE;
|
|
input PIPERX11EQLPADAPTDONE;
|
|
input PIPERX11EQLPLFFSSEL;
|
|
input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX11PHYSTATUS;
|
|
input [1:0] PIPERX11STARTBLOCK;
|
|
input [2:0] PIPERX11STATUS;
|
|
input [1:0] PIPERX11SYNCHEADER;
|
|
input PIPERX11VALID;
|
|
input [1:0] PIPERX12CHARISK;
|
|
input [31:0] PIPERX12DATA;
|
|
input PIPERX12DATAVALID;
|
|
input PIPERX12ELECIDLE;
|
|
input PIPERX12EQDONE;
|
|
input PIPERX12EQLPADAPTDONE;
|
|
input PIPERX12EQLPLFFSSEL;
|
|
input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX12PHYSTATUS;
|
|
input [1:0] PIPERX12STARTBLOCK;
|
|
input [2:0] PIPERX12STATUS;
|
|
input [1:0] PIPERX12SYNCHEADER;
|
|
input PIPERX12VALID;
|
|
input [1:0] PIPERX13CHARISK;
|
|
input [31:0] PIPERX13DATA;
|
|
input PIPERX13DATAVALID;
|
|
input PIPERX13ELECIDLE;
|
|
input PIPERX13EQDONE;
|
|
input PIPERX13EQLPADAPTDONE;
|
|
input PIPERX13EQLPLFFSSEL;
|
|
input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX13PHYSTATUS;
|
|
input [1:0] PIPERX13STARTBLOCK;
|
|
input [2:0] PIPERX13STATUS;
|
|
input [1:0] PIPERX13SYNCHEADER;
|
|
input PIPERX13VALID;
|
|
input [1:0] PIPERX14CHARISK;
|
|
input [31:0] PIPERX14DATA;
|
|
input PIPERX14DATAVALID;
|
|
input PIPERX14ELECIDLE;
|
|
input PIPERX14EQDONE;
|
|
input PIPERX14EQLPADAPTDONE;
|
|
input PIPERX14EQLPLFFSSEL;
|
|
input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX14PHYSTATUS;
|
|
input [1:0] PIPERX14STARTBLOCK;
|
|
input [2:0] PIPERX14STATUS;
|
|
input [1:0] PIPERX14SYNCHEADER;
|
|
input PIPERX14VALID;
|
|
input [1:0] PIPERX15CHARISK;
|
|
input [31:0] PIPERX15DATA;
|
|
input PIPERX15DATAVALID;
|
|
input PIPERX15ELECIDLE;
|
|
input PIPERX15EQDONE;
|
|
input PIPERX15EQLPADAPTDONE;
|
|
input PIPERX15EQLPLFFSSEL;
|
|
input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX15PHYSTATUS;
|
|
input [1:0] PIPERX15STARTBLOCK;
|
|
input [2:0] PIPERX15STATUS;
|
|
input [1:0] PIPERX15SYNCHEADER;
|
|
input PIPERX15VALID;
|
|
input [17:0] PIPETX00EQCOEFF;
|
|
input PIPETX00EQDONE;
|
|
input [17:0] PIPETX01EQCOEFF;
|
|
input PIPETX01EQDONE;
|
|
input [17:0] PIPETX02EQCOEFF;
|
|
input PIPETX02EQDONE;
|
|
input [17:0] PIPETX03EQCOEFF;
|
|
input PIPETX03EQDONE;
|
|
input [17:0] PIPETX04EQCOEFF;
|
|
input PIPETX04EQDONE;
|
|
input [17:0] PIPETX05EQCOEFF;
|
|
input PIPETX05EQDONE;
|
|
input [17:0] PIPETX06EQCOEFF;
|
|
input PIPETX06EQDONE;
|
|
input [17:0] PIPETX07EQCOEFF;
|
|
input PIPETX07EQDONE;
|
|
input [17:0] PIPETX08EQCOEFF;
|
|
input PIPETX08EQDONE;
|
|
input [17:0] PIPETX09EQCOEFF;
|
|
input PIPETX09EQDONE;
|
|
input [17:0] PIPETX10EQCOEFF;
|
|
input PIPETX10EQDONE;
|
|
input [17:0] PIPETX11EQCOEFF;
|
|
input PIPETX11EQDONE;
|
|
input [17:0] PIPETX12EQCOEFF;
|
|
input PIPETX12EQDONE;
|
|
input [17:0] PIPETX13EQCOEFF;
|
|
input PIPETX13EQDONE;
|
|
input [17:0] PIPETX14EQCOEFF;
|
|
input PIPETX14EQDONE;
|
|
input [17:0] PIPETX15EQCOEFF;
|
|
input PIPETX15EQDONE;
|
|
input PLEQRESETEIEOSCOUNT;
|
|
input PLGEN2UPSTREAMPREFERDEEMPH;
|
|
input PLGEN34REDOEQSPEED;
|
|
input PLGEN34REDOEQUALIZATION;
|
|
input RESETN;
|
|
input [255:0] SAXISCCTDATA;
|
|
input [7:0] SAXISCCTKEEP;
|
|
input SAXISCCTLAST;
|
|
input [32:0] SAXISCCTUSER;
|
|
input SAXISCCTVALID;
|
|
input [255:0] SAXISRQTDATA;
|
|
input [7:0] SAXISRQTKEEP;
|
|
input SAXISRQTLAST;
|
|
input [61:0] SAXISRQTUSER;
|
|
input SAXISRQTVALID;
|
|
input USERCLK;
|
|
input USERCLK2;
|
|
input USERCLKEN;
|
|
input [31:0] USERSPAREIN;
|
|
endmodule
|
|
|
|
module PCIE4CE4(AXIUSEROUT, CCIXTXCREDIT, CFGBUSNUMBER, CFGCURRENTSPEED, CFGERRCOROUT, CFGERRFATALOUT, CFGERRNONFATALOUT, CFGEXTFUNCTIONNUMBER, CFGEXTREADRECEIVED, CFGEXTREGISTERNUMBER, CFGEXTWRITEBYTEENABLE, CFGEXTWRITEDATA, CFGEXTWRITERECEIVED, CFGFCCPLD, CFGFCCPLH, CFGFCNPD, CFGFCNPH, CFGFCPD, CFGFCPH, CFGFLRINPROCESS, CFGFUNCTIONPOWERSTATE
|
|
, CFGFUNCTIONSTATUS, CFGHOTRESETOUT, CFGINTERRUPTMSIDATA, CFGINTERRUPTMSIENABLE, CFGINTERRUPTMSIFAIL, CFGINTERRUPTMSIMASKUPDATE, CFGINTERRUPTMSIMMENABLE, CFGINTERRUPTMSISENT, CFGINTERRUPTMSIXENABLE, CFGINTERRUPTMSIXMASK, CFGINTERRUPTMSIXVECPENDINGSTATUS, CFGINTERRUPTSENT, CFGLINKPOWERSTATE, CFGLOCALERROROUT, CFGLOCALERRORVALID, CFGLTRENABLE, CFGLTSSMSTATE, CFGMAXPAYLOAD, CFGMAXREADREQ, CFGMGMTREADDATA, CFGMGMTREADWRITEDONE
|
|
, CFGMSGRECEIVED, CFGMSGRECEIVEDDATA, CFGMSGRECEIVEDTYPE, CFGMSGTRANSMITDONE, CFGMSIXRAMADDRESS, CFGMSIXRAMREADENABLE, CFGMSIXRAMWRITEBYTEENABLE, CFGMSIXRAMWRITEDATA, CFGNEGOTIATEDWIDTH, CFGOBFFENABLE, CFGPHYLINKDOWN, CFGPHYLINKSTATUS, CFGPLSTATUSCHANGE, CFGPOWERSTATECHANGEINTERRUPT, CFGRCBSTATUS, CFGRXPMSTATE, CFGTPHRAMADDRESS, CFGTPHRAMREADENABLE, CFGTPHRAMWRITEBYTEENABLE, CFGTPHRAMWRITEDATA, CFGTPHREQUESTERENABLE
|
|
, CFGTPHSTMODE, CFGTXPMSTATE, CFGVC1ENABLE, CFGVC1NEGOTIATIONPENDING, CONFMCAPDESIGNSWITCH, CONFMCAPEOS, CONFMCAPINUSEBYPCIE, CONFREQREADY, CONFRESPRDATA, CONFRESPVALID, DBGCCIXOUT, DBGCTRL0OUT, DBGCTRL1OUT, DBGDATA0OUT, DBGDATA1OUT, DRPDO, DRPRDY, MAXISCCIXRXTUSER, MAXISCCIXRXTVALID, MAXISCQTDATA, MAXISCQTKEEP
|
|
, MAXISCQTLAST, MAXISCQTUSER, MAXISCQTVALID, MAXISRCTDATA, MAXISRCTKEEP, MAXISRCTLAST, MAXISRCTUSER, MAXISRCTVALID, MIREPLAYRAMADDRESS0, MIREPLAYRAMADDRESS1, MIREPLAYRAMREADENABLE0, MIREPLAYRAMREADENABLE1, MIREPLAYRAMWRITEDATA0, MIREPLAYRAMWRITEDATA1, MIREPLAYRAMWRITEENABLE0, MIREPLAYRAMWRITEENABLE1, MIRXCOMPLETIONRAMREADADDRESS0, MIRXCOMPLETIONRAMREADADDRESS1, MIRXCOMPLETIONRAMREADENABLE0, MIRXCOMPLETIONRAMREADENABLE1, MIRXCOMPLETIONRAMWRITEADDRESS0
|
|
, MIRXCOMPLETIONRAMWRITEADDRESS1, MIRXCOMPLETIONRAMWRITEDATA0, MIRXCOMPLETIONRAMWRITEDATA1, MIRXCOMPLETIONRAMWRITEENABLE0, MIRXCOMPLETIONRAMWRITEENABLE1, MIRXPOSTEDREQUESTRAMREADADDRESS0, MIRXPOSTEDREQUESTRAMREADADDRESS1, MIRXPOSTEDREQUESTRAMREADENABLE0, MIRXPOSTEDREQUESTRAMREADENABLE1, MIRXPOSTEDREQUESTRAMWRITEADDRESS0, MIRXPOSTEDREQUESTRAMWRITEADDRESS1, MIRXPOSTEDREQUESTRAMWRITEDATA0, MIRXPOSTEDREQUESTRAMWRITEDATA1, MIRXPOSTEDREQUESTRAMWRITEENABLE0, MIRXPOSTEDREQUESTRAMWRITEENABLE1, PCIECQNPREQCOUNT, PCIEPERST0B, PCIEPERST1B, PCIERQSEQNUM0, PCIERQSEQNUM1, PCIERQSEQNUMVLD0
|
|
, PCIERQSEQNUMVLD1, PCIERQTAG0, PCIERQTAG1, PCIERQTAGAV, PCIERQTAGVLD0, PCIERQTAGVLD1, PCIETFCNPDAV, PCIETFCNPHAV, PIPERX00EQCONTROL, PIPERX00POLARITY, PIPERX01EQCONTROL, PIPERX01POLARITY, PIPERX02EQCONTROL, PIPERX02POLARITY, PIPERX03EQCONTROL, PIPERX03POLARITY, PIPERX04EQCONTROL, PIPERX04POLARITY, PIPERX05EQCONTROL, PIPERX05POLARITY, PIPERX06EQCONTROL
|
|
, PIPERX06POLARITY, PIPERX07EQCONTROL, PIPERX07POLARITY, PIPERX08EQCONTROL, PIPERX08POLARITY, PIPERX09EQCONTROL, PIPERX09POLARITY, PIPERX10EQCONTROL, PIPERX10POLARITY, PIPERX11EQCONTROL, PIPERX11POLARITY, PIPERX12EQCONTROL, PIPERX12POLARITY, PIPERX13EQCONTROL, PIPERX13POLARITY, PIPERX14EQCONTROL, PIPERX14POLARITY, PIPERX15EQCONTROL, PIPERX15POLARITY, PIPERXEQLPLFFS, PIPERXEQLPTXPRESET
|
|
, PIPETX00CHARISK, PIPETX00COMPLIANCE, PIPETX00DATA, PIPETX00DATAVALID, PIPETX00ELECIDLE, PIPETX00EQCONTROL, PIPETX00EQDEEMPH, PIPETX00POWERDOWN, PIPETX00STARTBLOCK, PIPETX00SYNCHEADER, PIPETX01CHARISK, PIPETX01COMPLIANCE, PIPETX01DATA, PIPETX01DATAVALID, PIPETX01ELECIDLE, PIPETX01EQCONTROL, PIPETX01EQDEEMPH, PIPETX01POWERDOWN, PIPETX01STARTBLOCK, PIPETX01SYNCHEADER, PIPETX02CHARISK
|
|
, PIPETX02COMPLIANCE, PIPETX02DATA, PIPETX02DATAVALID, PIPETX02ELECIDLE, PIPETX02EQCONTROL, PIPETX02EQDEEMPH, PIPETX02POWERDOWN, PIPETX02STARTBLOCK, PIPETX02SYNCHEADER, PIPETX03CHARISK, PIPETX03COMPLIANCE, PIPETX03DATA, PIPETX03DATAVALID, PIPETX03ELECIDLE, PIPETX03EQCONTROL, PIPETX03EQDEEMPH, PIPETX03POWERDOWN, PIPETX03STARTBLOCK, PIPETX03SYNCHEADER, PIPETX04CHARISK, PIPETX04COMPLIANCE
|
|
, PIPETX04DATA, PIPETX04DATAVALID, PIPETX04ELECIDLE, PIPETX04EQCONTROL, PIPETX04EQDEEMPH, PIPETX04POWERDOWN, PIPETX04STARTBLOCK, PIPETX04SYNCHEADER, PIPETX05CHARISK, PIPETX05COMPLIANCE, PIPETX05DATA, PIPETX05DATAVALID, PIPETX05ELECIDLE, PIPETX05EQCONTROL, PIPETX05EQDEEMPH, PIPETX05POWERDOWN, PIPETX05STARTBLOCK, PIPETX05SYNCHEADER, PIPETX06CHARISK, PIPETX06COMPLIANCE, PIPETX06DATA
|
|
, PIPETX06DATAVALID, PIPETX06ELECIDLE, PIPETX06EQCONTROL, PIPETX06EQDEEMPH, PIPETX06POWERDOWN, PIPETX06STARTBLOCK, PIPETX06SYNCHEADER, PIPETX07CHARISK, PIPETX07COMPLIANCE, PIPETX07DATA, PIPETX07DATAVALID, PIPETX07ELECIDLE, PIPETX07EQCONTROL, PIPETX07EQDEEMPH, PIPETX07POWERDOWN, PIPETX07STARTBLOCK, PIPETX07SYNCHEADER, PIPETX08CHARISK, PIPETX08COMPLIANCE, PIPETX08DATA, PIPETX08DATAVALID
|
|
, PIPETX08ELECIDLE, PIPETX08EQCONTROL, PIPETX08EQDEEMPH, PIPETX08POWERDOWN, PIPETX08STARTBLOCK, PIPETX08SYNCHEADER, PIPETX09CHARISK, PIPETX09COMPLIANCE, PIPETX09DATA, PIPETX09DATAVALID, PIPETX09ELECIDLE, PIPETX09EQCONTROL, PIPETX09EQDEEMPH, PIPETX09POWERDOWN, PIPETX09STARTBLOCK, PIPETX09SYNCHEADER, PIPETX10CHARISK, PIPETX10COMPLIANCE, PIPETX10DATA, PIPETX10DATAVALID, PIPETX10ELECIDLE
|
|
, PIPETX10EQCONTROL, PIPETX10EQDEEMPH, PIPETX10POWERDOWN, PIPETX10STARTBLOCK, PIPETX10SYNCHEADER, PIPETX11CHARISK, PIPETX11COMPLIANCE, PIPETX11DATA, PIPETX11DATAVALID, PIPETX11ELECIDLE, PIPETX11EQCONTROL, PIPETX11EQDEEMPH, PIPETX11POWERDOWN, PIPETX11STARTBLOCK, PIPETX11SYNCHEADER, PIPETX12CHARISK, PIPETX12COMPLIANCE, PIPETX12DATA, PIPETX12DATAVALID, PIPETX12ELECIDLE, PIPETX12EQCONTROL
|
|
, PIPETX12EQDEEMPH, PIPETX12POWERDOWN, PIPETX12STARTBLOCK, PIPETX12SYNCHEADER, PIPETX13CHARISK, PIPETX13COMPLIANCE, PIPETX13DATA, PIPETX13DATAVALID, PIPETX13ELECIDLE, PIPETX13EQCONTROL, PIPETX13EQDEEMPH, PIPETX13POWERDOWN, PIPETX13STARTBLOCK, PIPETX13SYNCHEADER, PIPETX14CHARISK, PIPETX14COMPLIANCE, PIPETX14DATA, PIPETX14DATAVALID, PIPETX14ELECIDLE, PIPETX14EQCONTROL, PIPETX14EQDEEMPH
|
|
, PIPETX14POWERDOWN, PIPETX14STARTBLOCK, PIPETX14SYNCHEADER, PIPETX15CHARISK, PIPETX15COMPLIANCE, PIPETX15DATA, PIPETX15DATAVALID, PIPETX15ELECIDLE, PIPETX15EQCONTROL, PIPETX15EQDEEMPH, PIPETX15POWERDOWN, PIPETX15STARTBLOCK, PIPETX15SYNCHEADER, PIPETXDEEMPH, PIPETXMARGIN, PIPETXRATE, PIPETXRCVRDET, PIPETXRESET, PIPETXSWING, PLEQINPROGRESS, PLEQPHASE
|
|
, PLGEN34EQMISMATCH, SAXISCCTREADY, SAXISRQTREADY, USERSPAREOUT, AXIUSERIN, CCIXOPTIMIZEDTLPTXANDRXENABLE, CCIXRXCORRECTABLEERRORDETECTED, CCIXRXFIFOOVERFLOW, CCIXRXTLPFORWARDED0, CCIXRXTLPFORWARDED1, CCIXRXTLPFORWARDEDLENGTH0, CCIXRXTLPFORWARDEDLENGTH1, CCIXRXUNCORRECTABLEERRORDETECTED, CFGCONFIGSPACEENABLE, CFGDEVIDPF0, CFGDEVIDPF1, CFGDEVIDPF2, CFGDEVIDPF3, CFGDSBUSNUMBER, CFGDSDEVICENUMBER, CFGDSFUNCTIONNUMBER
|
|
, CFGDSN, CFGDSPORTNUMBER, CFGERRCORIN, CFGERRUNCORIN, CFGEXTREADDATA, CFGEXTREADDATAVALID, CFGFCSEL, CFGFCVCSEL, CFGFLRDONE, CFGHOTRESETIN, CFGINTERRUPTINT, CFGINTERRUPTMSIATTR, CFGINTERRUPTMSIFUNCTIONNUMBER, CFGINTERRUPTMSIINT, CFGINTERRUPTMSIPENDINGSTATUS, CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE, CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM, CFGINTERRUPTMSISELECT, CFGINTERRUPTMSITPHPRESENT, CFGINTERRUPTMSITPHSTTAG, CFGINTERRUPTMSITPHTYPE
|
|
, CFGINTERRUPTMSIXADDRESS, CFGINTERRUPTMSIXDATA, CFGINTERRUPTMSIXINT, CFGINTERRUPTMSIXVECPENDING, CFGINTERRUPTPENDING, CFGLINKTRAININGENABLE, CFGMGMTADDR, CFGMGMTBYTEENABLE, CFGMGMTDEBUGACCESS, CFGMGMTFUNCTIONNUMBER, CFGMGMTREAD, CFGMGMTWRITE, CFGMGMTWRITEDATA, CFGMSGTRANSMIT, CFGMSGTRANSMITDATA, CFGMSGTRANSMITTYPE, CFGMSIXRAMREADDATA, CFGPMASPML1ENTRYREJECT, CFGPMASPMTXL0SENTRYDISABLE, CFGPOWERSTATECHANGEACK, CFGREQPMTRANSITIONL23READY
|
|
, CFGREVIDPF0, CFGREVIDPF1, CFGREVIDPF2, CFGREVIDPF3, CFGSUBSYSIDPF0, CFGSUBSYSIDPF1, CFGSUBSYSIDPF2, CFGSUBSYSIDPF3, CFGSUBSYSVENDID, CFGTPHRAMREADDATA, CFGVENDID, CFGVFFLRDONE, CFGVFFLRFUNCNUM, CONFMCAPREQUESTBYCONF, CONFREQDATA, CONFREQREGNUM, CONFREQTYPE, CONFREQVALID, CORECLK, CORECLKCCIX, CORECLKMIREPLAYRAM0
|
|
, CORECLKMIREPLAYRAM1, CORECLKMIRXCOMPLETIONRAM0, CORECLKMIRXCOMPLETIONRAM1, CORECLKMIRXPOSTEDREQUESTRAM0, CORECLKMIRXPOSTEDREQUESTRAM1, DBGSEL0, DBGSEL1, DRPADDR, DRPCLK, DRPDI, DRPEN, DRPWE, MAXISCQTREADY, MAXISRCTREADY, MCAPCLK, MCAPPERST0B, MCAPPERST1B, MGMTRESETN, MGMTSTICKYRESETN, MIREPLAYRAMERRCOR, MIREPLAYRAMERRUNCOR
|
|
, MIREPLAYRAMREADDATA0, MIREPLAYRAMREADDATA1, MIRXCOMPLETIONRAMERRCOR, MIRXCOMPLETIONRAMERRUNCOR, MIRXCOMPLETIONRAMREADDATA0, MIRXCOMPLETIONRAMREADDATA1, MIRXPOSTEDREQUESTRAMERRCOR, MIRXPOSTEDREQUESTRAMERRUNCOR, MIRXPOSTEDREQUESTRAMREADDATA0, MIRXPOSTEDREQUESTRAMREADDATA1, PCIECOMPLDELIVERED, PCIECOMPLDELIVEREDTAG0, PCIECOMPLDELIVEREDTAG1, PCIECQNPREQ, PCIECQNPUSERCREDITRCVD, PCIECQPIPELINEEMPTY, PCIEPOSTEDREQDELIVERED, PIPECLK, PIPECLKEN, PIPEEQFS, PIPEEQLF
|
|
, PIPERESETN, PIPERX00CHARISK, PIPERX00DATA, PIPERX00DATAVALID, PIPERX00ELECIDLE, PIPERX00EQDONE, PIPERX00EQLPADAPTDONE, PIPERX00EQLPLFFSSEL, PIPERX00EQLPNEWTXCOEFFORPRESET, PIPERX00PHYSTATUS, PIPERX00STARTBLOCK, PIPERX00STATUS, PIPERX00SYNCHEADER, PIPERX00VALID, PIPERX01CHARISK, PIPERX01DATA, PIPERX01DATAVALID, PIPERX01ELECIDLE, PIPERX01EQDONE, PIPERX01EQLPADAPTDONE, PIPERX01EQLPLFFSSEL
|
|
, PIPERX01EQLPNEWTXCOEFFORPRESET, PIPERX01PHYSTATUS, PIPERX01STARTBLOCK, PIPERX01STATUS, PIPERX01SYNCHEADER, PIPERX01VALID, PIPERX02CHARISK, PIPERX02DATA, PIPERX02DATAVALID, PIPERX02ELECIDLE, PIPERX02EQDONE, PIPERX02EQLPADAPTDONE, PIPERX02EQLPLFFSSEL, PIPERX02EQLPNEWTXCOEFFORPRESET, PIPERX02PHYSTATUS, PIPERX02STARTBLOCK, PIPERX02STATUS, PIPERX02SYNCHEADER, PIPERX02VALID, PIPERX03CHARISK, PIPERX03DATA
|
|
, PIPERX03DATAVALID, PIPERX03ELECIDLE, PIPERX03EQDONE, PIPERX03EQLPADAPTDONE, PIPERX03EQLPLFFSSEL, PIPERX03EQLPNEWTXCOEFFORPRESET, PIPERX03PHYSTATUS, PIPERX03STARTBLOCK, PIPERX03STATUS, PIPERX03SYNCHEADER, PIPERX03VALID, PIPERX04CHARISK, PIPERX04DATA, PIPERX04DATAVALID, PIPERX04ELECIDLE, PIPERX04EQDONE, PIPERX04EQLPADAPTDONE, PIPERX04EQLPLFFSSEL, PIPERX04EQLPNEWTXCOEFFORPRESET, PIPERX04PHYSTATUS, PIPERX04STARTBLOCK
|
|
, PIPERX04STATUS, PIPERX04SYNCHEADER, PIPERX04VALID, PIPERX05CHARISK, PIPERX05DATA, PIPERX05DATAVALID, PIPERX05ELECIDLE, PIPERX05EQDONE, PIPERX05EQLPADAPTDONE, PIPERX05EQLPLFFSSEL, PIPERX05EQLPNEWTXCOEFFORPRESET, PIPERX05PHYSTATUS, PIPERX05STARTBLOCK, PIPERX05STATUS, PIPERX05SYNCHEADER, PIPERX05VALID, PIPERX06CHARISK, PIPERX06DATA, PIPERX06DATAVALID, PIPERX06ELECIDLE, PIPERX06EQDONE
|
|
, PIPERX06EQLPADAPTDONE, PIPERX06EQLPLFFSSEL, PIPERX06EQLPNEWTXCOEFFORPRESET, PIPERX06PHYSTATUS, PIPERX06STARTBLOCK, PIPERX06STATUS, PIPERX06SYNCHEADER, PIPERX06VALID, PIPERX07CHARISK, PIPERX07DATA, PIPERX07DATAVALID, PIPERX07ELECIDLE, PIPERX07EQDONE, PIPERX07EQLPADAPTDONE, PIPERX07EQLPLFFSSEL, PIPERX07EQLPNEWTXCOEFFORPRESET, PIPERX07PHYSTATUS, PIPERX07STARTBLOCK, PIPERX07STATUS, PIPERX07SYNCHEADER, PIPERX07VALID
|
|
, PIPERX08CHARISK, PIPERX08DATA, PIPERX08DATAVALID, PIPERX08ELECIDLE, PIPERX08EQDONE, PIPERX08EQLPADAPTDONE, PIPERX08EQLPLFFSSEL, PIPERX08EQLPNEWTXCOEFFORPRESET, PIPERX08PHYSTATUS, PIPERX08STARTBLOCK, PIPERX08STATUS, PIPERX08SYNCHEADER, PIPERX08VALID, PIPERX09CHARISK, PIPERX09DATA, PIPERX09DATAVALID, PIPERX09ELECIDLE, PIPERX09EQDONE, PIPERX09EQLPADAPTDONE, PIPERX09EQLPLFFSSEL, PIPERX09EQLPNEWTXCOEFFORPRESET
|
|
, PIPERX09PHYSTATUS, PIPERX09STARTBLOCK, PIPERX09STATUS, PIPERX09SYNCHEADER, PIPERX09VALID, PIPERX10CHARISK, PIPERX10DATA, PIPERX10DATAVALID, PIPERX10ELECIDLE, PIPERX10EQDONE, PIPERX10EQLPADAPTDONE, PIPERX10EQLPLFFSSEL, PIPERX10EQLPNEWTXCOEFFORPRESET, PIPERX10PHYSTATUS, PIPERX10STARTBLOCK, PIPERX10STATUS, PIPERX10SYNCHEADER, PIPERX10VALID, PIPERX11CHARISK, PIPERX11DATA, PIPERX11DATAVALID
|
|
, PIPERX11ELECIDLE, PIPERX11EQDONE, PIPERX11EQLPADAPTDONE, PIPERX11EQLPLFFSSEL, PIPERX11EQLPNEWTXCOEFFORPRESET, PIPERX11PHYSTATUS, PIPERX11STARTBLOCK, PIPERX11STATUS, PIPERX11SYNCHEADER, PIPERX11VALID, PIPERX12CHARISK, PIPERX12DATA, PIPERX12DATAVALID, PIPERX12ELECIDLE, PIPERX12EQDONE, PIPERX12EQLPADAPTDONE, PIPERX12EQLPLFFSSEL, PIPERX12EQLPNEWTXCOEFFORPRESET, PIPERX12PHYSTATUS, PIPERX12STARTBLOCK, PIPERX12STATUS
|
|
, PIPERX12SYNCHEADER, PIPERX12VALID, PIPERX13CHARISK, PIPERX13DATA, PIPERX13DATAVALID, PIPERX13ELECIDLE, PIPERX13EQDONE, PIPERX13EQLPADAPTDONE, PIPERX13EQLPLFFSSEL, PIPERX13EQLPNEWTXCOEFFORPRESET, PIPERX13PHYSTATUS, PIPERX13STARTBLOCK, PIPERX13STATUS, PIPERX13SYNCHEADER, PIPERX13VALID, PIPERX14CHARISK, PIPERX14DATA, PIPERX14DATAVALID, PIPERX14ELECIDLE, PIPERX14EQDONE, PIPERX14EQLPADAPTDONE
|
|
, PIPERX14EQLPLFFSSEL, PIPERX14EQLPNEWTXCOEFFORPRESET, PIPERX14PHYSTATUS, PIPERX14STARTBLOCK, PIPERX14STATUS, PIPERX14SYNCHEADER, PIPERX14VALID, PIPERX15CHARISK, PIPERX15DATA, PIPERX15DATAVALID, PIPERX15ELECIDLE, PIPERX15EQDONE, PIPERX15EQLPADAPTDONE, PIPERX15EQLPLFFSSEL, PIPERX15EQLPNEWTXCOEFFORPRESET, PIPERX15PHYSTATUS, PIPERX15STARTBLOCK, PIPERX15STATUS, PIPERX15SYNCHEADER, PIPERX15VALID, PIPETX00EQCOEFF
|
|
, PIPETX00EQDONE, PIPETX01EQCOEFF, PIPETX01EQDONE, PIPETX02EQCOEFF, PIPETX02EQDONE, PIPETX03EQCOEFF, PIPETX03EQDONE, PIPETX04EQCOEFF, PIPETX04EQDONE, PIPETX05EQCOEFF, PIPETX05EQDONE, PIPETX06EQCOEFF, PIPETX06EQDONE, PIPETX07EQCOEFF, PIPETX07EQDONE, PIPETX08EQCOEFF, PIPETX08EQDONE, PIPETX09EQCOEFF, PIPETX09EQDONE, PIPETX10EQCOEFF, PIPETX10EQDONE
|
|
, PIPETX11EQCOEFF, PIPETX11EQDONE, PIPETX12EQCOEFF, PIPETX12EQDONE, PIPETX13EQCOEFF, PIPETX13EQDONE, PIPETX14EQCOEFF, PIPETX14EQDONE, PIPETX15EQCOEFF, PIPETX15EQDONE, PLEQRESETEIEOSCOUNT, PLGEN2UPSTREAMPREFERDEEMPH, PLGEN34REDOEQSPEED, PLGEN34REDOEQUALIZATION, RESETN, SAXISCCIXTXTDATA, SAXISCCIXTXTUSER, SAXISCCIXTXTVALID, SAXISCCTDATA, SAXISCCTKEEP, SAXISCCTLAST
|
|
, SAXISCCTUSER, SAXISCCTVALID, SAXISRQTDATA, SAXISRQTKEEP, SAXISRQTLAST, SAXISRQTUSER, SAXISRQTVALID, USERCLK, USERCLK2, USERCLKEN, USERSPAREIN);
|
|
parameter ARI_CAP_ENABLE = "FALSE";
|
|
parameter AUTO_FLR_RESPONSE = "FALSE";
|
|
parameter [7:0] AXISTEN_IF_CCIX_RX_CREDIT_LIMIT = 8'h08;
|
|
parameter [7:0] AXISTEN_IF_CCIX_TX_CREDIT_LIMIT = 8'h08;
|
|
parameter AXISTEN_IF_CCIX_TX_REGISTERED_TREADY = "FALSE";
|
|
parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0;
|
|
parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
|
|
parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080;
|
|
parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0;
|
|
parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE";
|
|
parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE";
|
|
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
|
|
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512 = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE";
|
|
parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE";
|
|
parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE";
|
|
parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE";
|
|
parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE";
|
|
parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0;
|
|
parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
|
|
parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0;
|
|
parameter AXISTEN_IF_RX_PARITY_EN = "TRUE";
|
|
parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE";
|
|
parameter AXISTEN_IF_TX_PARITY_EN = "TRUE";
|
|
parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
|
|
parameter CCIX_DIRECT_ATTACH_MODE = "FALSE";
|
|
parameter CCIX_ENABLE = "FALSE";
|
|
parameter [15:0] CCIX_VENDOR_ID = 16'h0000;
|
|
parameter CFG_BYPASS_MODE_ENABLE = "FALSE";
|
|
parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
|
|
parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
|
|
parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000;
|
|
parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00;
|
|
parameter [3:0] DEBUG_CAR_SPARE = 4'h0;
|
|
parameter [15:0] DEBUG_CFG_SPARE = 16'h0000;
|
|
parameter [15:0] DEBUG_LL_SPARE = 16'h0000;
|
|
parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE";
|
|
parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE";
|
|
parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE";
|
|
parameter [15:0] DEBUG_PL_SPARE = 16'h0000;
|
|
parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE";
|
|
parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE";
|
|
parameter [15:0] DEBUG_TL_SPARE = 16'h0000;
|
|
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
|
|
parameter DSN_CAP_ENABLE = "FALSE";
|
|
parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
|
|
parameter HEADER_TYPE_OVERRIDE = "FALSE";
|
|
parameter IS_SWITCH_PORT = "FALSE";
|
|
parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
|
|
parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
|
|
parameter LL_ACK_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
|
|
parameter LL_DISABLE_SCHED_TX_NAK = "FALSE";
|
|
parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE";
|
|
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
|
|
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
|
|
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
|
|
parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE";
|
|
parameter LL_RX_TLP_PARITY_GEN = "TRUE";
|
|
parameter LL_TX_TLP_PARITY_CHK = "TRUE";
|
|
parameter [15:0] LL_USER_SPARE = 16'h0000;
|
|
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250;
|
|
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
|
|
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
|
|
parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000;
|
|
parameter MCAP_CONFIGURE_OVERRIDE = "FALSE";
|
|
parameter MCAP_ENABLE = "FALSE";
|
|
parameter MCAP_EOS_DESIGN_SWITCH = "FALSE";
|
|
parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000;
|
|
parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE";
|
|
parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE";
|
|
parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE";
|
|
parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE";
|
|
parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE";
|
|
parameter [15:0] MCAP_VSEC_ID = 16'h0000;
|
|
parameter [11:0] MCAP_VSEC_LEN = 12'h02C;
|
|
parameter [3:0] MCAP_VSEC_REV = 4'h0;
|
|
parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE";
|
|
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
|
|
parameter [4:0] PF0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
|
|
parameter [11:0] PF0_ATS_CAP_NEXTPTR = 12'h000;
|
|
parameter PF0_ATS_CAP_ON = "FALSE";
|
|
parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80;
|
|
parameter [23:0] PF0_CLASS_CODE = 24'h000000;
|
|
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
|
|
parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE";
|
|
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
|
|
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
|
|
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
|
|
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
|
|
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
|
|
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
|
|
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
|
|
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
|
|
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
|
|
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
|
|
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7;
|
|
parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0;
|
|
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
|
|
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
|
|
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
|
|
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
|
|
parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
|
|
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04;
|
|
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [7:0] PF0_PM_CAP_ID = 8'h01;
|
|
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
|
|
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
|
|
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
|
|
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
|
|
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
|
|
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
|
|
parameter [11:0] PF0_PRI_CAP_NEXTPTR = 12'h000;
|
|
parameter PF0_PRI_CAP_ON = "FALSE";
|
|
parameter [31:0] PF0_PRI_OST_PR_CAPACITY = 32'h00000000;
|
|
parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000;
|
|
parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
|
|
parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
|
|
parameter PF0_TPHR_CAP_ENABLE = "FALSE";
|
|
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
|
|
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
|
|
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
|
|
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
|
|
parameter [3:0] PF0_VC_ARB_CAPABILITY = 4'h0;
|
|
parameter [7:0] PF0_VC_ARB_TBL_OFFSET = 8'h00;
|
|
parameter PF0_VC_CAP_ENABLE = "FALSE";
|
|
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
|
|
parameter [3:0] PF0_VC_CAP_VER = 4'h1;
|
|
parameter PF0_VC_EXTENDED_COUNT = "FALSE";
|
|
parameter PF0_VC_LOW_PRIORITY_EXTENDED_COUNT = "FALSE";
|
|
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [4:0] PF1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
|
|
parameter [11:0] PF1_ATS_CAP_NEXTPTR = 12'h000;
|
|
parameter PF1_ATS_CAP_ON = "FALSE";
|
|
parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80;
|
|
parameter [23:0] PF1_CLASS_CODE = 24'h000000;
|
|
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] PF1_PRI_CAP_NEXTPTR = 12'h000;
|
|
parameter PF1_PRI_CAP_ON = "FALSE";
|
|
parameter [31:0] PF1_PRI_OST_PR_CAPACITY = 32'h00000000;
|
|
parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
|
|
parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [4:0] PF2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
|
|
parameter [11:0] PF2_ATS_CAP_NEXTPTR = 12'h000;
|
|
parameter PF2_ATS_CAP_ON = "FALSE";
|
|
parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF2_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80;
|
|
parameter [23:0] PF2_CLASS_CODE = 24'h000000;
|
|
parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF2_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [2:0] PF2_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF2_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF2_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] PF2_PRI_CAP_NEXTPTR = 12'h000;
|
|
parameter PF2_PRI_CAP_ON = "FALSE";
|
|
parameter [31:0] PF2_PRI_OST_PR_CAPACITY = 32'h00000000;
|
|
parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
|
|
parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000;
|
|
parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00;
|
|
parameter [4:0] PF3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
|
|
parameter [11:0] PF3_ATS_CAP_NEXTPTR = 12'h000;
|
|
parameter PF3_ATS_CAP_ON = "FALSE";
|
|
parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF3_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_BAR5_CONTROL = 3'h0;
|
|
parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80;
|
|
parameter [23:0] PF3_CLASS_CODE = 24'h000000;
|
|
parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
|
|
parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C;
|
|
parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
|
|
parameter PF3_EXPANSION_ROM_ENABLE = "FALSE";
|
|
parameter [2:0] PF3_INTERRUPT_PIN = 3'h1;
|
|
parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer PF3_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer PF3_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0;
|
|
parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00;
|
|
parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE";
|
|
parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] PF3_PRI_CAP_NEXTPTR = 12'h000;
|
|
parameter PF3_PRI_CAP_ON = "FALSE";
|
|
parameter [31:0] PF3_PRI_OST_PR_CAPACITY = 32'h00000000;
|
|
parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE";
|
|
parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
|
|
parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0;
|
|
parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0;
|
|
parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4;
|
|
parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
|
|
parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0;
|
|
parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000;
|
|
parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000;
|
|
parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000;
|
|
parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1;
|
|
parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000;
|
|
parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000;
|
|
parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
|
|
parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000;
|
|
parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE";
|
|
parameter PL_CTRL_SKP_GEN_ENABLE = "FALSE";
|
|
parameter PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE = "TRUE";
|
|
parameter PL_DEEMPH_SOURCE_SELECT = "TRUE";
|
|
parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE";
|
|
parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE";
|
|
parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE";
|
|
parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE";
|
|
parameter PL_DISABLE_DC_BALANCE = "FALSE";
|
|
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
|
|
parameter PL_DISABLE_LANE_REVERSAL = "FALSE";
|
|
parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0;
|
|
parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE";
|
|
parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE";
|
|
parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000;
|
|
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
|
|
parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0;
|
|
parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0;
|
|
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
|
|
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
|
|
parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0;
|
|
parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33;
|
|
parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44;
|
|
parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE";
|
|
parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0;
|
|
parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0;
|
|
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
|
|
parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE";
|
|
parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE";
|
|
parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE";
|
|
parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE";
|
|
parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE";
|
|
parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00;
|
|
parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00;
|
|
parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4;
|
|
parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08;
|
|
parameter integer PL_N_FTS = 255;
|
|
parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE";
|
|
parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE";
|
|
parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00;
|
|
parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0;
|
|
parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0;
|
|
parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0;
|
|
parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0;
|
|
parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0;
|
|
parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0;
|
|
parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0;
|
|
parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0;
|
|
parameter PL_SRIS_ENABLE = "FALSE";
|
|
parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00;
|
|
parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00;
|
|
parameter PL_UPSTREAM_FACING = "TRUE";
|
|
parameter [15:0] PL_USER_SPARE = 16'h0000;
|
|
parameter [15:0] PL_USER_SPARE2 = 16'h0000;
|
|
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500;
|
|
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8;
|
|
parameter PM_ENABLE_L23_ENTRY = "FALSE";
|
|
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
|
|
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100;
|
|
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000;
|
|
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000;
|
|
parameter SIM_VERSION = "1.0";
|
|
parameter SPARE_BIT0 = "FALSE";
|
|
parameter integer SPARE_BIT1 = 0;
|
|
parameter integer SPARE_BIT2 = 0;
|
|
parameter SPARE_BIT3 = "FALSE";
|
|
parameter integer SPARE_BIT4 = 0;
|
|
parameter integer SPARE_BIT5 = 0;
|
|
parameter integer SPARE_BIT6 = 0;
|
|
parameter integer SPARE_BIT7 = 0;
|
|
parameter integer SPARE_BIT8 = 0;
|
|
parameter [7:0] SPARE_BYTE0 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE1 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE2 = 8'h00;
|
|
parameter [7:0] SPARE_BYTE3 = 8'h00;
|
|
parameter [31:0] SPARE_WORD0 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD1 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD2 = 32'h00000000;
|
|
parameter [31:0] SPARE_WORD3 = 32'h00000000;
|
|
parameter [3:0] SRIOV_CAP_ENABLE = 4'h0;
|
|
parameter TL2CFG_IF_PARITY_CHK = "TRUE";
|
|
parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0;
|
|
parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1;
|
|
parameter [11:0] TL_CREDITS_CD = 12'h000;
|
|
parameter [11:0] TL_CREDITS_CD_VC1 = 12'h000;
|
|
parameter [7:0] TL_CREDITS_CH = 8'h00;
|
|
parameter [7:0] TL_CREDITS_CH_VC1 = 8'h00;
|
|
parameter [11:0] TL_CREDITS_NPD = 12'h004;
|
|
parameter [11:0] TL_CREDITS_NPD_VC1 = 12'h000;
|
|
parameter [7:0] TL_CREDITS_NPH = 8'h20;
|
|
parameter [7:0] TL_CREDITS_NPH_VC1 = 8'h01;
|
|
parameter [11:0] TL_CREDITS_PD = 12'h0E0;
|
|
parameter [11:0] TL_CREDITS_PD_VC1 = 12'h3E0;
|
|
parameter [7:0] TL_CREDITS_PH = 8'h20;
|
|
parameter [7:0] TL_CREDITS_PH_VC1 = 8'h20;
|
|
parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02;
|
|
parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1 = 5'h02;
|
|
parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08;
|
|
parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1 = 5'h08;
|
|
parameter TL_FEATURE_ENABLE_FC_SCALING = "FALSE";
|
|
parameter [1:0] TL_PF_ENABLE_REG = 2'h0;
|
|
parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0;
|
|
parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE";
|
|
parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE";
|
|
parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE";
|
|
parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE";
|
|
parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE";
|
|
parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE";
|
|
parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE";
|
|
parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE";
|
|
parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE";
|
|
parameter [15:0] TL_USER_SPARE = 16'h0000;
|
|
parameter TPH_FROM_RAM_PIPELINE = "FALSE";
|
|
parameter TPH_TO_RAM_PIPELINE = "FALSE";
|
|
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80;
|
|
parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] VFG0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
|
|
parameter [11:0] VFG0_ATS_CAP_NEXTPTR = 12'h000;
|
|
parameter VFG0_ATS_CAP_ON = "FALSE";
|
|
parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer VFG0_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] VFG1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
|
|
parameter [11:0] VFG1_ATS_CAP_NEXTPTR = 12'h000;
|
|
parameter VFG1_ATS_CAP_ON = "FALSE";
|
|
parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer VFG1_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] VFG2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
|
|
parameter [11:0] VFG2_ATS_CAP_NEXTPTR = 12'h000;
|
|
parameter VFG2_ATS_CAP_ON = "FALSE";
|
|
parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer VFG2_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000;
|
|
parameter [4:0] VFG3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00;
|
|
parameter [11:0] VFG3_ATS_CAP_NEXTPTR = 12'h000;
|
|
parameter VFG3_ATS_CAP_ON = "FALSE";
|
|
parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00;
|
|
parameter integer VFG3_MSIX_CAP_PBA_BIR = 0;
|
|
parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
|
|
parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0;
|
|
parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
|
|
parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000;
|
|
parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00;
|
|
parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000;
|
|
parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0;
|
|
output [7:0] AXIUSEROUT;
|
|
output CCIXTXCREDIT;
|
|
output [7:0] CFGBUSNUMBER;
|
|
output [1:0] CFGCURRENTSPEED;
|
|
output CFGERRCOROUT;
|
|
output CFGERRFATALOUT;
|
|
output CFGERRNONFATALOUT;
|
|
output [7:0] CFGEXTFUNCTIONNUMBER;
|
|
output CFGEXTREADRECEIVED;
|
|
output [9:0] CFGEXTREGISTERNUMBER;
|
|
output [3:0] CFGEXTWRITEBYTEENABLE;
|
|
output [31:0] CFGEXTWRITEDATA;
|
|
output CFGEXTWRITERECEIVED;
|
|
output [11:0] CFGFCCPLD;
|
|
output [7:0] CFGFCCPLH;
|
|
output [11:0] CFGFCNPD;
|
|
output [7:0] CFGFCNPH;
|
|
output [11:0] CFGFCPD;
|
|
output [7:0] CFGFCPH;
|
|
output [3:0] CFGFLRINPROCESS;
|
|
output [11:0] CFGFUNCTIONPOWERSTATE;
|
|
output [15:0] CFGFUNCTIONSTATUS;
|
|
output CFGHOTRESETOUT;
|
|
output [31:0] CFGINTERRUPTMSIDATA;
|
|
output [3:0] CFGINTERRUPTMSIENABLE;
|
|
output CFGINTERRUPTMSIFAIL;
|
|
output CFGINTERRUPTMSIMASKUPDATE;
|
|
output [11:0] CFGINTERRUPTMSIMMENABLE;
|
|
output CFGINTERRUPTMSISENT;
|
|
output [3:0] CFGINTERRUPTMSIXENABLE;
|
|
output [3:0] CFGINTERRUPTMSIXMASK;
|
|
output CFGINTERRUPTMSIXVECPENDINGSTATUS;
|
|
output CFGINTERRUPTSENT;
|
|
output [1:0] CFGLINKPOWERSTATE;
|
|
output [4:0] CFGLOCALERROROUT;
|
|
output CFGLOCALERRORVALID;
|
|
output CFGLTRENABLE;
|
|
output [5:0] CFGLTSSMSTATE;
|
|
output [1:0] CFGMAXPAYLOAD;
|
|
output [2:0] CFGMAXREADREQ;
|
|
output [31:0] CFGMGMTREADDATA;
|
|
output CFGMGMTREADWRITEDONE;
|
|
output CFGMSGRECEIVED;
|
|
output [7:0] CFGMSGRECEIVEDDATA;
|
|
output [4:0] CFGMSGRECEIVEDTYPE;
|
|
output CFGMSGTRANSMITDONE;
|
|
output [12:0] CFGMSIXRAMADDRESS;
|
|
output CFGMSIXRAMREADENABLE;
|
|
output [3:0] CFGMSIXRAMWRITEBYTEENABLE;
|
|
output [35:0] CFGMSIXRAMWRITEDATA;
|
|
output [2:0] CFGNEGOTIATEDWIDTH;
|
|
output [1:0] CFGOBFFENABLE;
|
|
output CFGPHYLINKDOWN;
|
|
output [1:0] CFGPHYLINKSTATUS;
|
|
output CFGPLSTATUSCHANGE;
|
|
output CFGPOWERSTATECHANGEINTERRUPT;
|
|
output [3:0] CFGRCBSTATUS;
|
|
output [1:0] CFGRXPMSTATE;
|
|
output [11:0] CFGTPHRAMADDRESS;
|
|
output CFGTPHRAMREADENABLE;
|
|
output [3:0] CFGTPHRAMWRITEBYTEENABLE;
|
|
output [35:0] CFGTPHRAMWRITEDATA;
|
|
output [3:0] CFGTPHREQUESTERENABLE;
|
|
output [11:0] CFGTPHSTMODE;
|
|
output [1:0] CFGTXPMSTATE;
|
|
output CFGVC1ENABLE;
|
|
output CFGVC1NEGOTIATIONPENDING;
|
|
output CONFMCAPDESIGNSWITCH;
|
|
output CONFMCAPEOS;
|
|
output CONFMCAPINUSEBYPCIE;
|
|
output CONFREQREADY;
|
|
output [31:0] CONFRESPRDATA;
|
|
output CONFRESPVALID;
|
|
output [129:0] DBGCCIXOUT;
|
|
output [31:0] DBGCTRL0OUT;
|
|
output [31:0] DBGCTRL1OUT;
|
|
output [255:0] DBGDATA0OUT;
|
|
output [255:0] DBGDATA1OUT;
|
|
output [15:0] DRPDO;
|
|
output DRPRDY;
|
|
output [45:0] MAXISCCIXRXTUSER;
|
|
output MAXISCCIXRXTVALID;
|
|
output [255:0] MAXISCQTDATA;
|
|
output [7:0] MAXISCQTKEEP;
|
|
output MAXISCQTLAST;
|
|
output [87:0] MAXISCQTUSER;
|
|
output MAXISCQTVALID;
|
|
output [255:0] MAXISRCTDATA;
|
|
output [7:0] MAXISRCTKEEP;
|
|
output MAXISRCTLAST;
|
|
output [74:0] MAXISRCTUSER;
|
|
output MAXISRCTVALID;
|
|
output [8:0] MIREPLAYRAMADDRESS0;
|
|
output [8:0] MIREPLAYRAMADDRESS1;
|
|
output MIREPLAYRAMREADENABLE0;
|
|
output MIREPLAYRAMREADENABLE1;
|
|
output [127:0] MIREPLAYRAMWRITEDATA0;
|
|
output [127:0] MIREPLAYRAMWRITEDATA1;
|
|
output MIREPLAYRAMWRITEENABLE0;
|
|
output MIREPLAYRAMWRITEENABLE1;
|
|
output [8:0] MIRXCOMPLETIONRAMREADADDRESS0;
|
|
output [8:0] MIRXCOMPLETIONRAMREADADDRESS1;
|
|
output [1:0] MIRXCOMPLETIONRAMREADENABLE0;
|
|
output [1:0] MIRXCOMPLETIONRAMREADENABLE1;
|
|
output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0;
|
|
output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1;
|
|
output [143:0] MIRXCOMPLETIONRAMWRITEDATA0;
|
|
output [143:0] MIRXCOMPLETIONRAMWRITEDATA1;
|
|
output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0;
|
|
output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1;
|
|
output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0;
|
|
output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1;
|
|
output MIRXPOSTEDREQUESTRAMREADENABLE0;
|
|
output MIRXPOSTEDREQUESTRAMREADENABLE1;
|
|
output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0;
|
|
output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1;
|
|
output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0;
|
|
output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1;
|
|
output MIRXPOSTEDREQUESTRAMWRITEENABLE0;
|
|
output MIRXPOSTEDREQUESTRAMWRITEENABLE1;
|
|
output [5:0] PCIECQNPREQCOUNT;
|
|
output PCIEPERST0B;
|
|
output PCIEPERST1B;
|
|
output [5:0] PCIERQSEQNUM0;
|
|
output [5:0] PCIERQSEQNUM1;
|
|
output PCIERQSEQNUMVLD0;
|
|
output PCIERQSEQNUMVLD1;
|
|
output [7:0] PCIERQTAG0;
|
|
output [7:0] PCIERQTAG1;
|
|
output [3:0] PCIERQTAGAV;
|
|
output PCIERQTAGVLD0;
|
|
output PCIERQTAGVLD1;
|
|
output [3:0] PCIETFCNPDAV;
|
|
output [3:0] PCIETFCNPHAV;
|
|
output [1:0] PIPERX00EQCONTROL;
|
|
output PIPERX00POLARITY;
|
|
output [1:0] PIPERX01EQCONTROL;
|
|
output PIPERX01POLARITY;
|
|
output [1:0] PIPERX02EQCONTROL;
|
|
output PIPERX02POLARITY;
|
|
output [1:0] PIPERX03EQCONTROL;
|
|
output PIPERX03POLARITY;
|
|
output [1:0] PIPERX04EQCONTROL;
|
|
output PIPERX04POLARITY;
|
|
output [1:0] PIPERX05EQCONTROL;
|
|
output PIPERX05POLARITY;
|
|
output [1:0] PIPERX06EQCONTROL;
|
|
output PIPERX06POLARITY;
|
|
output [1:0] PIPERX07EQCONTROL;
|
|
output PIPERX07POLARITY;
|
|
output [1:0] PIPERX08EQCONTROL;
|
|
output PIPERX08POLARITY;
|
|
output [1:0] PIPERX09EQCONTROL;
|
|
output PIPERX09POLARITY;
|
|
output [1:0] PIPERX10EQCONTROL;
|
|
output PIPERX10POLARITY;
|
|
output [1:0] PIPERX11EQCONTROL;
|
|
output PIPERX11POLARITY;
|
|
output [1:0] PIPERX12EQCONTROL;
|
|
output PIPERX12POLARITY;
|
|
output [1:0] PIPERX13EQCONTROL;
|
|
output PIPERX13POLARITY;
|
|
output [1:0] PIPERX14EQCONTROL;
|
|
output PIPERX14POLARITY;
|
|
output [1:0] PIPERX15EQCONTROL;
|
|
output PIPERX15POLARITY;
|
|
output [5:0] PIPERXEQLPLFFS;
|
|
output [3:0] PIPERXEQLPTXPRESET;
|
|
output [1:0] PIPETX00CHARISK;
|
|
output PIPETX00COMPLIANCE;
|
|
output [31:0] PIPETX00DATA;
|
|
output PIPETX00DATAVALID;
|
|
output PIPETX00ELECIDLE;
|
|
output [1:0] PIPETX00EQCONTROL;
|
|
output [5:0] PIPETX00EQDEEMPH;
|
|
output [1:0] PIPETX00POWERDOWN;
|
|
output PIPETX00STARTBLOCK;
|
|
output [1:0] PIPETX00SYNCHEADER;
|
|
output [1:0] PIPETX01CHARISK;
|
|
output PIPETX01COMPLIANCE;
|
|
output [31:0] PIPETX01DATA;
|
|
output PIPETX01DATAVALID;
|
|
output PIPETX01ELECIDLE;
|
|
output [1:0] PIPETX01EQCONTROL;
|
|
output [5:0] PIPETX01EQDEEMPH;
|
|
output [1:0] PIPETX01POWERDOWN;
|
|
output PIPETX01STARTBLOCK;
|
|
output [1:0] PIPETX01SYNCHEADER;
|
|
output [1:0] PIPETX02CHARISK;
|
|
output PIPETX02COMPLIANCE;
|
|
output [31:0] PIPETX02DATA;
|
|
output PIPETX02DATAVALID;
|
|
output PIPETX02ELECIDLE;
|
|
output [1:0] PIPETX02EQCONTROL;
|
|
output [5:0] PIPETX02EQDEEMPH;
|
|
output [1:0] PIPETX02POWERDOWN;
|
|
output PIPETX02STARTBLOCK;
|
|
output [1:0] PIPETX02SYNCHEADER;
|
|
output [1:0] PIPETX03CHARISK;
|
|
output PIPETX03COMPLIANCE;
|
|
output [31:0] PIPETX03DATA;
|
|
output PIPETX03DATAVALID;
|
|
output PIPETX03ELECIDLE;
|
|
output [1:0] PIPETX03EQCONTROL;
|
|
output [5:0] PIPETX03EQDEEMPH;
|
|
output [1:0] PIPETX03POWERDOWN;
|
|
output PIPETX03STARTBLOCK;
|
|
output [1:0] PIPETX03SYNCHEADER;
|
|
output [1:0] PIPETX04CHARISK;
|
|
output PIPETX04COMPLIANCE;
|
|
output [31:0] PIPETX04DATA;
|
|
output PIPETX04DATAVALID;
|
|
output PIPETX04ELECIDLE;
|
|
output [1:0] PIPETX04EQCONTROL;
|
|
output [5:0] PIPETX04EQDEEMPH;
|
|
output [1:0] PIPETX04POWERDOWN;
|
|
output PIPETX04STARTBLOCK;
|
|
output [1:0] PIPETX04SYNCHEADER;
|
|
output [1:0] PIPETX05CHARISK;
|
|
output PIPETX05COMPLIANCE;
|
|
output [31:0] PIPETX05DATA;
|
|
output PIPETX05DATAVALID;
|
|
output PIPETX05ELECIDLE;
|
|
output [1:0] PIPETX05EQCONTROL;
|
|
output [5:0] PIPETX05EQDEEMPH;
|
|
output [1:0] PIPETX05POWERDOWN;
|
|
output PIPETX05STARTBLOCK;
|
|
output [1:0] PIPETX05SYNCHEADER;
|
|
output [1:0] PIPETX06CHARISK;
|
|
output PIPETX06COMPLIANCE;
|
|
output [31:0] PIPETX06DATA;
|
|
output PIPETX06DATAVALID;
|
|
output PIPETX06ELECIDLE;
|
|
output [1:0] PIPETX06EQCONTROL;
|
|
output [5:0] PIPETX06EQDEEMPH;
|
|
output [1:0] PIPETX06POWERDOWN;
|
|
output PIPETX06STARTBLOCK;
|
|
output [1:0] PIPETX06SYNCHEADER;
|
|
output [1:0] PIPETX07CHARISK;
|
|
output PIPETX07COMPLIANCE;
|
|
output [31:0] PIPETX07DATA;
|
|
output PIPETX07DATAVALID;
|
|
output PIPETX07ELECIDLE;
|
|
output [1:0] PIPETX07EQCONTROL;
|
|
output [5:0] PIPETX07EQDEEMPH;
|
|
output [1:0] PIPETX07POWERDOWN;
|
|
output PIPETX07STARTBLOCK;
|
|
output [1:0] PIPETX07SYNCHEADER;
|
|
output [1:0] PIPETX08CHARISK;
|
|
output PIPETX08COMPLIANCE;
|
|
output [31:0] PIPETX08DATA;
|
|
output PIPETX08DATAVALID;
|
|
output PIPETX08ELECIDLE;
|
|
output [1:0] PIPETX08EQCONTROL;
|
|
output [5:0] PIPETX08EQDEEMPH;
|
|
output [1:0] PIPETX08POWERDOWN;
|
|
output PIPETX08STARTBLOCK;
|
|
output [1:0] PIPETX08SYNCHEADER;
|
|
output [1:0] PIPETX09CHARISK;
|
|
output PIPETX09COMPLIANCE;
|
|
output [31:0] PIPETX09DATA;
|
|
output PIPETX09DATAVALID;
|
|
output PIPETX09ELECIDLE;
|
|
output [1:0] PIPETX09EQCONTROL;
|
|
output [5:0] PIPETX09EQDEEMPH;
|
|
output [1:0] PIPETX09POWERDOWN;
|
|
output PIPETX09STARTBLOCK;
|
|
output [1:0] PIPETX09SYNCHEADER;
|
|
output [1:0] PIPETX10CHARISK;
|
|
output PIPETX10COMPLIANCE;
|
|
output [31:0] PIPETX10DATA;
|
|
output PIPETX10DATAVALID;
|
|
output PIPETX10ELECIDLE;
|
|
output [1:0] PIPETX10EQCONTROL;
|
|
output [5:0] PIPETX10EQDEEMPH;
|
|
output [1:0] PIPETX10POWERDOWN;
|
|
output PIPETX10STARTBLOCK;
|
|
output [1:0] PIPETX10SYNCHEADER;
|
|
output [1:0] PIPETX11CHARISK;
|
|
output PIPETX11COMPLIANCE;
|
|
output [31:0] PIPETX11DATA;
|
|
output PIPETX11DATAVALID;
|
|
output PIPETX11ELECIDLE;
|
|
output [1:0] PIPETX11EQCONTROL;
|
|
output [5:0] PIPETX11EQDEEMPH;
|
|
output [1:0] PIPETX11POWERDOWN;
|
|
output PIPETX11STARTBLOCK;
|
|
output [1:0] PIPETX11SYNCHEADER;
|
|
output [1:0] PIPETX12CHARISK;
|
|
output PIPETX12COMPLIANCE;
|
|
output [31:0] PIPETX12DATA;
|
|
output PIPETX12DATAVALID;
|
|
output PIPETX12ELECIDLE;
|
|
output [1:0] PIPETX12EQCONTROL;
|
|
output [5:0] PIPETX12EQDEEMPH;
|
|
output [1:0] PIPETX12POWERDOWN;
|
|
output PIPETX12STARTBLOCK;
|
|
output [1:0] PIPETX12SYNCHEADER;
|
|
output [1:0] PIPETX13CHARISK;
|
|
output PIPETX13COMPLIANCE;
|
|
output [31:0] PIPETX13DATA;
|
|
output PIPETX13DATAVALID;
|
|
output PIPETX13ELECIDLE;
|
|
output [1:0] PIPETX13EQCONTROL;
|
|
output [5:0] PIPETX13EQDEEMPH;
|
|
output [1:0] PIPETX13POWERDOWN;
|
|
output PIPETX13STARTBLOCK;
|
|
output [1:0] PIPETX13SYNCHEADER;
|
|
output [1:0] PIPETX14CHARISK;
|
|
output PIPETX14COMPLIANCE;
|
|
output [31:0] PIPETX14DATA;
|
|
output PIPETX14DATAVALID;
|
|
output PIPETX14ELECIDLE;
|
|
output [1:0] PIPETX14EQCONTROL;
|
|
output [5:0] PIPETX14EQDEEMPH;
|
|
output [1:0] PIPETX14POWERDOWN;
|
|
output PIPETX14STARTBLOCK;
|
|
output [1:0] PIPETX14SYNCHEADER;
|
|
output [1:0] PIPETX15CHARISK;
|
|
output PIPETX15COMPLIANCE;
|
|
output [31:0] PIPETX15DATA;
|
|
output PIPETX15DATAVALID;
|
|
output PIPETX15ELECIDLE;
|
|
output [1:0] PIPETX15EQCONTROL;
|
|
output [5:0] PIPETX15EQDEEMPH;
|
|
output [1:0] PIPETX15POWERDOWN;
|
|
output PIPETX15STARTBLOCK;
|
|
output [1:0] PIPETX15SYNCHEADER;
|
|
output PIPETXDEEMPH;
|
|
output [2:0] PIPETXMARGIN;
|
|
output [1:0] PIPETXRATE;
|
|
output PIPETXRCVRDET;
|
|
output PIPETXRESET;
|
|
output PIPETXSWING;
|
|
output PLEQINPROGRESS;
|
|
output [1:0] PLEQPHASE;
|
|
output PLGEN34EQMISMATCH;
|
|
output [3:0] SAXISCCTREADY;
|
|
output [3:0] SAXISRQTREADY;
|
|
output [23:0] USERSPAREOUT;
|
|
input [7:0] AXIUSERIN;
|
|
input CCIXOPTIMIZEDTLPTXANDRXENABLE;
|
|
input CCIXRXCORRECTABLEERRORDETECTED;
|
|
input CCIXRXFIFOOVERFLOW;
|
|
input CCIXRXTLPFORWARDED0;
|
|
input CCIXRXTLPFORWARDED1;
|
|
input [5:0] CCIXRXTLPFORWARDEDLENGTH0;
|
|
input [5:0] CCIXRXTLPFORWARDEDLENGTH1;
|
|
input CCIXRXUNCORRECTABLEERRORDETECTED;
|
|
input CFGCONFIGSPACEENABLE;
|
|
input [15:0] CFGDEVIDPF0;
|
|
input [15:0] CFGDEVIDPF1;
|
|
input [15:0] CFGDEVIDPF2;
|
|
input [15:0] CFGDEVIDPF3;
|
|
input [7:0] CFGDSBUSNUMBER;
|
|
input [4:0] CFGDSDEVICENUMBER;
|
|
input [2:0] CFGDSFUNCTIONNUMBER;
|
|
input [63:0] CFGDSN;
|
|
input [7:0] CFGDSPORTNUMBER;
|
|
input CFGERRCORIN;
|
|
input CFGERRUNCORIN;
|
|
input [31:0] CFGEXTREADDATA;
|
|
input CFGEXTREADDATAVALID;
|
|
input [2:0] CFGFCSEL;
|
|
input CFGFCVCSEL;
|
|
input [3:0] CFGFLRDONE;
|
|
input CFGHOTRESETIN;
|
|
input [3:0] CFGINTERRUPTINT;
|
|
input [2:0] CFGINTERRUPTMSIATTR;
|
|
input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
|
|
input [31:0] CFGINTERRUPTMSIINT;
|
|
input [31:0] CFGINTERRUPTMSIPENDINGSTATUS;
|
|
input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE;
|
|
input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM;
|
|
input [1:0] CFGINTERRUPTMSISELECT;
|
|
input CFGINTERRUPTMSITPHPRESENT;
|
|
input [7:0] CFGINTERRUPTMSITPHSTTAG;
|
|
input [1:0] CFGINTERRUPTMSITPHTYPE;
|
|
input [63:0] CFGINTERRUPTMSIXADDRESS;
|
|
input [31:0] CFGINTERRUPTMSIXDATA;
|
|
input CFGINTERRUPTMSIXINT;
|
|
input [1:0] CFGINTERRUPTMSIXVECPENDING;
|
|
input [3:0] CFGINTERRUPTPENDING;
|
|
input CFGLINKTRAININGENABLE;
|
|
input [9:0] CFGMGMTADDR;
|
|
input [3:0] CFGMGMTBYTEENABLE;
|
|
input CFGMGMTDEBUGACCESS;
|
|
input [7:0] CFGMGMTFUNCTIONNUMBER;
|
|
input CFGMGMTREAD;
|
|
input CFGMGMTWRITE;
|
|
input [31:0] CFGMGMTWRITEDATA;
|
|
input CFGMSGTRANSMIT;
|
|
input [31:0] CFGMSGTRANSMITDATA;
|
|
input [2:0] CFGMSGTRANSMITTYPE;
|
|
input [35:0] CFGMSIXRAMREADDATA;
|
|
input CFGPMASPML1ENTRYREJECT;
|
|
input CFGPMASPMTXL0SENTRYDISABLE;
|
|
input CFGPOWERSTATECHANGEACK;
|
|
input CFGREQPMTRANSITIONL23READY;
|
|
input [7:0] CFGREVIDPF0;
|
|
input [7:0] CFGREVIDPF1;
|
|
input [7:0] CFGREVIDPF2;
|
|
input [7:0] CFGREVIDPF3;
|
|
input [15:0] CFGSUBSYSIDPF0;
|
|
input [15:0] CFGSUBSYSIDPF1;
|
|
input [15:0] CFGSUBSYSIDPF2;
|
|
input [15:0] CFGSUBSYSIDPF3;
|
|
input [15:0] CFGSUBSYSVENDID;
|
|
input [35:0] CFGTPHRAMREADDATA;
|
|
input [15:0] CFGVENDID;
|
|
input CFGVFFLRDONE;
|
|
input [7:0] CFGVFFLRFUNCNUM;
|
|
input CONFMCAPREQUESTBYCONF;
|
|
input [31:0] CONFREQDATA;
|
|
input [3:0] CONFREQREGNUM;
|
|
input [1:0] CONFREQTYPE;
|
|
input CONFREQVALID;
|
|
input CORECLK;
|
|
input CORECLKCCIX;
|
|
input CORECLKMIREPLAYRAM0;
|
|
input CORECLKMIREPLAYRAM1;
|
|
input CORECLKMIRXCOMPLETIONRAM0;
|
|
input CORECLKMIRXCOMPLETIONRAM1;
|
|
input CORECLKMIRXPOSTEDREQUESTRAM0;
|
|
input CORECLKMIRXPOSTEDREQUESTRAM1;
|
|
input [5:0] DBGSEL0;
|
|
input [5:0] DBGSEL1;
|
|
input [9:0] DRPADDR;
|
|
input DRPCLK;
|
|
input [15:0] DRPDI;
|
|
input DRPEN;
|
|
input DRPWE;
|
|
input [21:0] MAXISCQTREADY;
|
|
input [21:0] MAXISRCTREADY;
|
|
input MCAPCLK;
|
|
input MCAPPERST0B;
|
|
input MCAPPERST1B;
|
|
input MGMTRESETN;
|
|
input MGMTSTICKYRESETN;
|
|
input [5:0] MIREPLAYRAMERRCOR;
|
|
input [5:0] MIREPLAYRAMERRUNCOR;
|
|
input [127:0] MIREPLAYRAMREADDATA0;
|
|
input [127:0] MIREPLAYRAMREADDATA1;
|
|
input [11:0] MIRXCOMPLETIONRAMERRCOR;
|
|
input [11:0] MIRXCOMPLETIONRAMERRUNCOR;
|
|
input [143:0] MIRXCOMPLETIONRAMREADDATA0;
|
|
input [143:0] MIRXCOMPLETIONRAMREADDATA1;
|
|
input [5:0] MIRXPOSTEDREQUESTRAMERRCOR;
|
|
input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR;
|
|
input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0;
|
|
input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1;
|
|
input [1:0] PCIECOMPLDELIVERED;
|
|
input [7:0] PCIECOMPLDELIVEREDTAG0;
|
|
input [7:0] PCIECOMPLDELIVEREDTAG1;
|
|
input [1:0] PCIECQNPREQ;
|
|
input PCIECQNPUSERCREDITRCVD;
|
|
input PCIECQPIPELINEEMPTY;
|
|
input PCIEPOSTEDREQDELIVERED;
|
|
input PIPECLK;
|
|
input PIPECLKEN;
|
|
input [5:0] PIPEEQFS;
|
|
input [5:0] PIPEEQLF;
|
|
input PIPERESETN;
|
|
input [1:0] PIPERX00CHARISK;
|
|
input [31:0] PIPERX00DATA;
|
|
input PIPERX00DATAVALID;
|
|
input PIPERX00ELECIDLE;
|
|
input PIPERX00EQDONE;
|
|
input PIPERX00EQLPADAPTDONE;
|
|
input PIPERX00EQLPLFFSSEL;
|
|
input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX00PHYSTATUS;
|
|
input [1:0] PIPERX00STARTBLOCK;
|
|
input [2:0] PIPERX00STATUS;
|
|
input [1:0] PIPERX00SYNCHEADER;
|
|
input PIPERX00VALID;
|
|
input [1:0] PIPERX01CHARISK;
|
|
input [31:0] PIPERX01DATA;
|
|
input PIPERX01DATAVALID;
|
|
input PIPERX01ELECIDLE;
|
|
input PIPERX01EQDONE;
|
|
input PIPERX01EQLPADAPTDONE;
|
|
input PIPERX01EQLPLFFSSEL;
|
|
input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX01PHYSTATUS;
|
|
input [1:0] PIPERX01STARTBLOCK;
|
|
input [2:0] PIPERX01STATUS;
|
|
input [1:0] PIPERX01SYNCHEADER;
|
|
input PIPERX01VALID;
|
|
input [1:0] PIPERX02CHARISK;
|
|
input [31:0] PIPERX02DATA;
|
|
input PIPERX02DATAVALID;
|
|
input PIPERX02ELECIDLE;
|
|
input PIPERX02EQDONE;
|
|
input PIPERX02EQLPADAPTDONE;
|
|
input PIPERX02EQLPLFFSSEL;
|
|
input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX02PHYSTATUS;
|
|
input [1:0] PIPERX02STARTBLOCK;
|
|
input [2:0] PIPERX02STATUS;
|
|
input [1:0] PIPERX02SYNCHEADER;
|
|
input PIPERX02VALID;
|
|
input [1:0] PIPERX03CHARISK;
|
|
input [31:0] PIPERX03DATA;
|
|
input PIPERX03DATAVALID;
|
|
input PIPERX03ELECIDLE;
|
|
input PIPERX03EQDONE;
|
|
input PIPERX03EQLPADAPTDONE;
|
|
input PIPERX03EQLPLFFSSEL;
|
|
input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX03PHYSTATUS;
|
|
input [1:0] PIPERX03STARTBLOCK;
|
|
input [2:0] PIPERX03STATUS;
|
|
input [1:0] PIPERX03SYNCHEADER;
|
|
input PIPERX03VALID;
|
|
input [1:0] PIPERX04CHARISK;
|
|
input [31:0] PIPERX04DATA;
|
|
input PIPERX04DATAVALID;
|
|
input PIPERX04ELECIDLE;
|
|
input PIPERX04EQDONE;
|
|
input PIPERX04EQLPADAPTDONE;
|
|
input PIPERX04EQLPLFFSSEL;
|
|
input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX04PHYSTATUS;
|
|
input [1:0] PIPERX04STARTBLOCK;
|
|
input [2:0] PIPERX04STATUS;
|
|
input [1:0] PIPERX04SYNCHEADER;
|
|
input PIPERX04VALID;
|
|
input [1:0] PIPERX05CHARISK;
|
|
input [31:0] PIPERX05DATA;
|
|
input PIPERX05DATAVALID;
|
|
input PIPERX05ELECIDLE;
|
|
input PIPERX05EQDONE;
|
|
input PIPERX05EQLPADAPTDONE;
|
|
input PIPERX05EQLPLFFSSEL;
|
|
input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX05PHYSTATUS;
|
|
input [1:0] PIPERX05STARTBLOCK;
|
|
input [2:0] PIPERX05STATUS;
|
|
input [1:0] PIPERX05SYNCHEADER;
|
|
input PIPERX05VALID;
|
|
input [1:0] PIPERX06CHARISK;
|
|
input [31:0] PIPERX06DATA;
|
|
input PIPERX06DATAVALID;
|
|
input PIPERX06ELECIDLE;
|
|
input PIPERX06EQDONE;
|
|
input PIPERX06EQLPADAPTDONE;
|
|
input PIPERX06EQLPLFFSSEL;
|
|
input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX06PHYSTATUS;
|
|
input [1:0] PIPERX06STARTBLOCK;
|
|
input [2:0] PIPERX06STATUS;
|
|
input [1:0] PIPERX06SYNCHEADER;
|
|
input PIPERX06VALID;
|
|
input [1:0] PIPERX07CHARISK;
|
|
input [31:0] PIPERX07DATA;
|
|
input PIPERX07DATAVALID;
|
|
input PIPERX07ELECIDLE;
|
|
input PIPERX07EQDONE;
|
|
input PIPERX07EQLPADAPTDONE;
|
|
input PIPERX07EQLPLFFSSEL;
|
|
input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX07PHYSTATUS;
|
|
input [1:0] PIPERX07STARTBLOCK;
|
|
input [2:0] PIPERX07STATUS;
|
|
input [1:0] PIPERX07SYNCHEADER;
|
|
input PIPERX07VALID;
|
|
input [1:0] PIPERX08CHARISK;
|
|
input [31:0] PIPERX08DATA;
|
|
input PIPERX08DATAVALID;
|
|
input PIPERX08ELECIDLE;
|
|
input PIPERX08EQDONE;
|
|
input PIPERX08EQLPADAPTDONE;
|
|
input PIPERX08EQLPLFFSSEL;
|
|
input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX08PHYSTATUS;
|
|
input [1:0] PIPERX08STARTBLOCK;
|
|
input [2:0] PIPERX08STATUS;
|
|
input [1:0] PIPERX08SYNCHEADER;
|
|
input PIPERX08VALID;
|
|
input [1:0] PIPERX09CHARISK;
|
|
input [31:0] PIPERX09DATA;
|
|
input PIPERX09DATAVALID;
|
|
input PIPERX09ELECIDLE;
|
|
input PIPERX09EQDONE;
|
|
input PIPERX09EQLPADAPTDONE;
|
|
input PIPERX09EQLPLFFSSEL;
|
|
input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX09PHYSTATUS;
|
|
input [1:0] PIPERX09STARTBLOCK;
|
|
input [2:0] PIPERX09STATUS;
|
|
input [1:0] PIPERX09SYNCHEADER;
|
|
input PIPERX09VALID;
|
|
input [1:0] PIPERX10CHARISK;
|
|
input [31:0] PIPERX10DATA;
|
|
input PIPERX10DATAVALID;
|
|
input PIPERX10ELECIDLE;
|
|
input PIPERX10EQDONE;
|
|
input PIPERX10EQLPADAPTDONE;
|
|
input PIPERX10EQLPLFFSSEL;
|
|
input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX10PHYSTATUS;
|
|
input [1:0] PIPERX10STARTBLOCK;
|
|
input [2:0] PIPERX10STATUS;
|
|
input [1:0] PIPERX10SYNCHEADER;
|
|
input PIPERX10VALID;
|
|
input [1:0] PIPERX11CHARISK;
|
|
input [31:0] PIPERX11DATA;
|
|
input PIPERX11DATAVALID;
|
|
input PIPERX11ELECIDLE;
|
|
input PIPERX11EQDONE;
|
|
input PIPERX11EQLPADAPTDONE;
|
|
input PIPERX11EQLPLFFSSEL;
|
|
input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX11PHYSTATUS;
|
|
input [1:0] PIPERX11STARTBLOCK;
|
|
input [2:0] PIPERX11STATUS;
|
|
input [1:0] PIPERX11SYNCHEADER;
|
|
input PIPERX11VALID;
|
|
input [1:0] PIPERX12CHARISK;
|
|
input [31:0] PIPERX12DATA;
|
|
input PIPERX12DATAVALID;
|
|
input PIPERX12ELECIDLE;
|
|
input PIPERX12EQDONE;
|
|
input PIPERX12EQLPADAPTDONE;
|
|
input PIPERX12EQLPLFFSSEL;
|
|
input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX12PHYSTATUS;
|
|
input [1:0] PIPERX12STARTBLOCK;
|
|
input [2:0] PIPERX12STATUS;
|
|
input [1:0] PIPERX12SYNCHEADER;
|
|
input PIPERX12VALID;
|
|
input [1:0] PIPERX13CHARISK;
|
|
input [31:0] PIPERX13DATA;
|
|
input PIPERX13DATAVALID;
|
|
input PIPERX13ELECIDLE;
|
|
input PIPERX13EQDONE;
|
|
input PIPERX13EQLPADAPTDONE;
|
|
input PIPERX13EQLPLFFSSEL;
|
|
input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX13PHYSTATUS;
|
|
input [1:0] PIPERX13STARTBLOCK;
|
|
input [2:0] PIPERX13STATUS;
|
|
input [1:0] PIPERX13SYNCHEADER;
|
|
input PIPERX13VALID;
|
|
input [1:0] PIPERX14CHARISK;
|
|
input [31:0] PIPERX14DATA;
|
|
input PIPERX14DATAVALID;
|
|
input PIPERX14ELECIDLE;
|
|
input PIPERX14EQDONE;
|
|
input PIPERX14EQLPADAPTDONE;
|
|
input PIPERX14EQLPLFFSSEL;
|
|
input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX14PHYSTATUS;
|
|
input [1:0] PIPERX14STARTBLOCK;
|
|
input [2:0] PIPERX14STATUS;
|
|
input [1:0] PIPERX14SYNCHEADER;
|
|
input PIPERX14VALID;
|
|
input [1:0] PIPERX15CHARISK;
|
|
input [31:0] PIPERX15DATA;
|
|
input PIPERX15DATAVALID;
|
|
input PIPERX15ELECIDLE;
|
|
input PIPERX15EQDONE;
|
|
input PIPERX15EQLPADAPTDONE;
|
|
input PIPERX15EQLPLFFSSEL;
|
|
input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET;
|
|
input PIPERX15PHYSTATUS;
|
|
input [1:0] PIPERX15STARTBLOCK;
|
|
input [2:0] PIPERX15STATUS;
|
|
input [1:0] PIPERX15SYNCHEADER;
|
|
input PIPERX15VALID;
|
|
input [17:0] PIPETX00EQCOEFF;
|
|
input PIPETX00EQDONE;
|
|
input [17:0] PIPETX01EQCOEFF;
|
|
input PIPETX01EQDONE;
|
|
input [17:0] PIPETX02EQCOEFF;
|
|
input PIPETX02EQDONE;
|
|
input [17:0] PIPETX03EQCOEFF;
|
|
input PIPETX03EQDONE;
|
|
input [17:0] PIPETX04EQCOEFF;
|
|
input PIPETX04EQDONE;
|
|
input [17:0] PIPETX05EQCOEFF;
|
|
input PIPETX05EQDONE;
|
|
input [17:0] PIPETX06EQCOEFF;
|
|
input PIPETX06EQDONE;
|
|
input [17:0] PIPETX07EQCOEFF;
|
|
input PIPETX07EQDONE;
|
|
input [17:0] PIPETX08EQCOEFF;
|
|
input PIPETX08EQDONE;
|
|
input [17:0] PIPETX09EQCOEFF;
|
|
input PIPETX09EQDONE;
|
|
input [17:0] PIPETX10EQCOEFF;
|
|
input PIPETX10EQDONE;
|
|
input [17:0] PIPETX11EQCOEFF;
|
|
input PIPETX11EQDONE;
|
|
input [17:0] PIPETX12EQCOEFF;
|
|
input PIPETX12EQDONE;
|
|
input [17:0] PIPETX13EQCOEFF;
|
|
input PIPETX13EQDONE;
|
|
input [17:0] PIPETX14EQCOEFF;
|
|
input PIPETX14EQDONE;
|
|
input [17:0] PIPETX15EQCOEFF;
|
|
input PIPETX15EQDONE;
|
|
input PLEQRESETEIEOSCOUNT;
|
|
input PLGEN2UPSTREAMPREFERDEEMPH;
|
|
input PLGEN34REDOEQSPEED;
|
|
input PLGEN34REDOEQUALIZATION;
|
|
input RESETN;
|
|
input [255:0] SAXISCCIXTXTDATA;
|
|
input [45:0] SAXISCCIXTXTUSER;
|
|
input SAXISCCIXTXTVALID;
|
|
input [255:0] SAXISCCTDATA;
|
|
input [7:0] SAXISCCTKEEP;
|
|
input SAXISCCTLAST;
|
|
input [32:0] SAXISCCTUSER;
|
|
input SAXISCCTVALID;
|
|
input [255:0] SAXISRQTDATA;
|
|
input [7:0] SAXISRQTKEEP;
|
|
input SAXISRQTLAST;
|
|
input [61:0] SAXISRQTUSER;
|
|
input SAXISRQTVALID;
|
|
input USERCLK;
|
|
input USERCLK2;
|
|
input USERCLKEN;
|
|
input [31:0] USERSPAREIN;
|
|
endmodule
|
|
|
|
module EMAC(DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXDVREG6, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXGMIIMIICLKOUT, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB
|
|
, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXDVREG6, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME
|
|
, EMAC1CLIENTRXSTATSBYTEVLD, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXGMIIMIICLKOUT, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL
|
|
, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK, EMAC1PHYTXEN, EMAC1PHYTXER, EMACDCRACK, HOSTMIIMRDY, EMACDCRDBUS, EMAC0CLIENTRXD, EMAC1CLIENTRXD, HOSTRDDATA, EMAC0CLIENTRXSTATS, EMAC1CLIENTRXSTATS, EMAC0PHYTXD, EMAC1PHYTXD, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE
|
|
, CLIENTEMAC0TXGMIIMIICLKIN, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXGMIIMIICLKIN, CLIENTEMAC1TXUNDERRUN, DCREMACCLK, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTREQ, PHYEMAC0COL, PHYEMAC0CRS
|
|
, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0RXBUFERR, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCOMMADET, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN
|
|
, PHYEMAC1MDIN, PHYEMAC1MIITXCLK, PHYEMAC1RXBUFERR, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCOMMADET, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, RESET, DCREMACDBUS, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0TXD, CLIENTEMAC1PAUSEVAL, CLIENTEMAC1TXD
|
|
, HOSTOPCODE, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXLOSSOFSYNC, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXLOSSOFSYNC, PHYEMAC0RXCLKCORCNT, PHYEMAC1RXCLKCORCNT, HOSTWRDATA, TIEEMAC0UNICASTADDR, TIEEMAC1UNICASTADDR, PHYEMAC0PHYAD, PHYEMAC1PHYAD, TIEEMAC0CONFIGVEC, TIEEMAC1CONFIGVEC, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC1TXIFGDELAY, PHYEMAC0RXD, PHYEMAC1RXD, DCREMACABUS, HOSTADDR);
|
|
parameter EMAC0_MODE = "RGMII";
|
|
parameter EMAC1_MODE = "RGMII";
|
|
output DCRHOSTDONEIR;
|
|
output EMAC0CLIENTANINTERRUPT;
|
|
output EMAC0CLIENTRXBADFRAME;
|
|
output EMAC0CLIENTRXCLIENTCLKOUT;
|
|
output EMAC0CLIENTRXDVLD;
|
|
output EMAC0CLIENTRXDVLDMSW;
|
|
output EMAC0CLIENTRXDVREG6;
|
|
output EMAC0CLIENTRXFRAMEDROP;
|
|
output EMAC0CLIENTRXGOODFRAME;
|
|
output EMAC0CLIENTRXSTATSBYTEVLD;
|
|
output EMAC0CLIENTRXSTATSVLD;
|
|
output EMAC0CLIENTTXACK;
|
|
output EMAC0CLIENTTXCLIENTCLKOUT;
|
|
output EMAC0CLIENTTXCOLLISION;
|
|
output EMAC0CLIENTTXGMIIMIICLKOUT;
|
|
output EMAC0CLIENTTXRETRANSMIT;
|
|
output EMAC0CLIENTTXSTATS;
|
|
output EMAC0CLIENTTXSTATSBYTEVLD;
|
|
output EMAC0CLIENTTXSTATSVLD;
|
|
output EMAC0PHYENCOMMAALIGN;
|
|
output EMAC0PHYLOOPBACKMSB;
|
|
output EMAC0PHYMCLKOUT;
|
|
output EMAC0PHYMDOUT;
|
|
output EMAC0PHYMDTRI;
|
|
output EMAC0PHYMGTRXRESET;
|
|
output EMAC0PHYMGTTXRESET;
|
|
output EMAC0PHYPOWERDOWN;
|
|
output EMAC0PHYSYNCACQSTATUS;
|
|
output EMAC0PHYTXCHARDISPMODE;
|
|
output EMAC0PHYTXCHARDISPVAL;
|
|
output EMAC0PHYTXCHARISK;
|
|
output EMAC0PHYTXCLK;
|
|
output EMAC0PHYTXEN;
|
|
output EMAC0PHYTXER;
|
|
output EMAC1CLIENTANINTERRUPT;
|
|
output EMAC1CLIENTRXBADFRAME;
|
|
output EMAC1CLIENTRXCLIENTCLKOUT;
|
|
output EMAC1CLIENTRXDVLD;
|
|
output EMAC1CLIENTRXDVLDMSW;
|
|
output EMAC1CLIENTRXDVREG6;
|
|
output EMAC1CLIENTRXFRAMEDROP;
|
|
output EMAC1CLIENTRXGOODFRAME;
|
|
output EMAC1CLIENTRXSTATSBYTEVLD;
|
|
output EMAC1CLIENTRXSTATSVLD;
|
|
output EMAC1CLIENTTXACK;
|
|
output EMAC1CLIENTTXCLIENTCLKOUT;
|
|
output EMAC1CLIENTTXCOLLISION;
|
|
output EMAC1CLIENTTXGMIIMIICLKOUT;
|
|
output EMAC1CLIENTTXRETRANSMIT;
|
|
output EMAC1CLIENTTXSTATS;
|
|
output EMAC1CLIENTTXSTATSBYTEVLD;
|
|
output EMAC1CLIENTTXSTATSVLD;
|
|
output EMAC1PHYENCOMMAALIGN;
|
|
output EMAC1PHYLOOPBACKMSB;
|
|
output EMAC1PHYMCLKOUT;
|
|
output EMAC1PHYMDOUT;
|
|
output EMAC1PHYMDTRI;
|
|
output EMAC1PHYMGTRXRESET;
|
|
output EMAC1PHYMGTTXRESET;
|
|
output EMAC1PHYPOWERDOWN;
|
|
output EMAC1PHYSYNCACQSTATUS;
|
|
output EMAC1PHYTXCHARDISPMODE;
|
|
output EMAC1PHYTXCHARDISPVAL;
|
|
output EMAC1PHYTXCHARISK;
|
|
output EMAC1PHYTXCLK;
|
|
output EMAC1PHYTXEN;
|
|
output EMAC1PHYTXER;
|
|
output EMACDCRACK;
|
|
output HOSTMIIMRDY;
|
|
output [0:31] EMACDCRDBUS;
|
|
output [15:0] EMAC0CLIENTRXD;
|
|
output [15:0] EMAC1CLIENTRXD;
|
|
output [31:0] HOSTRDDATA;
|
|
output [6:0] EMAC0CLIENTRXSTATS;
|
|
output [6:0] EMAC1CLIENTRXSTATS;
|
|
output [7:0] EMAC0PHYTXD;
|
|
output [7:0] EMAC1PHYTXD;
|
|
input CLIENTEMAC0DCMLOCKED;
|
|
input CLIENTEMAC0PAUSEREQ;
|
|
input CLIENTEMAC0RXCLIENTCLKIN;
|
|
input CLIENTEMAC0TXCLIENTCLKIN;
|
|
input CLIENTEMAC0TXDVLD;
|
|
input CLIENTEMAC0TXDVLDMSW;
|
|
input CLIENTEMAC0TXFIRSTBYTE;
|
|
input CLIENTEMAC0TXGMIIMIICLKIN;
|
|
input CLIENTEMAC0TXUNDERRUN;
|
|
input CLIENTEMAC1DCMLOCKED;
|
|
input CLIENTEMAC1PAUSEREQ;
|
|
input CLIENTEMAC1RXCLIENTCLKIN;
|
|
input CLIENTEMAC1TXCLIENTCLKIN;
|
|
input CLIENTEMAC1TXDVLD;
|
|
input CLIENTEMAC1TXDVLDMSW;
|
|
input CLIENTEMAC1TXFIRSTBYTE;
|
|
input CLIENTEMAC1TXGMIIMIICLKIN;
|
|
input CLIENTEMAC1TXUNDERRUN;
|
|
input DCREMACCLK;
|
|
input DCREMACENABLE;
|
|
input DCREMACREAD;
|
|
input DCREMACWRITE;
|
|
input HOSTCLK;
|
|
input HOSTEMAC1SEL;
|
|
input HOSTMIIMSEL;
|
|
input HOSTREQ;
|
|
input PHYEMAC0COL;
|
|
input PHYEMAC0CRS;
|
|
input PHYEMAC0GTXCLK;
|
|
input PHYEMAC0MCLKIN;
|
|
input PHYEMAC0MDIN;
|
|
input PHYEMAC0MIITXCLK;
|
|
input PHYEMAC0RXBUFERR;
|
|
input PHYEMAC0RXCHARISCOMMA;
|
|
input PHYEMAC0RXCHARISK;
|
|
input PHYEMAC0RXCHECKINGCRC;
|
|
input PHYEMAC0RXCLK;
|
|
input PHYEMAC0RXCOMMADET;
|
|
input PHYEMAC0RXDISPERR;
|
|
input PHYEMAC0RXDV;
|
|
input PHYEMAC0RXER;
|
|
input PHYEMAC0RXNOTINTABLE;
|
|
input PHYEMAC0RXRUNDISP;
|
|
input PHYEMAC0SIGNALDET;
|
|
input PHYEMAC0TXBUFERR;
|
|
input PHYEMAC1COL;
|
|
input PHYEMAC1CRS;
|
|
input PHYEMAC1GTXCLK;
|
|
input PHYEMAC1MCLKIN;
|
|
input PHYEMAC1MDIN;
|
|
input PHYEMAC1MIITXCLK;
|
|
input PHYEMAC1RXBUFERR;
|
|
input PHYEMAC1RXCHARISCOMMA;
|
|
input PHYEMAC1RXCHARISK;
|
|
input PHYEMAC1RXCHECKINGCRC;
|
|
input PHYEMAC1RXCLK;
|
|
input PHYEMAC1RXCOMMADET;
|
|
input PHYEMAC1RXDISPERR;
|
|
input PHYEMAC1RXDV;
|
|
input PHYEMAC1RXER;
|
|
input PHYEMAC1RXNOTINTABLE;
|
|
input PHYEMAC1RXRUNDISP;
|
|
input PHYEMAC1SIGNALDET;
|
|
input PHYEMAC1TXBUFERR;
|
|
input RESET;
|
|
input [0:31] DCREMACDBUS;
|
|
input [15:0] CLIENTEMAC0PAUSEVAL;
|
|
input [15:0] CLIENTEMAC0TXD;
|
|
input [15:0] CLIENTEMAC1PAUSEVAL;
|
|
input [15:0] CLIENTEMAC1TXD;
|
|
input [1:0] HOSTOPCODE;
|
|
input [1:0] PHYEMAC0RXBUFSTATUS;
|
|
input [1:0] PHYEMAC0RXLOSSOFSYNC;
|
|
input [1:0] PHYEMAC1RXBUFSTATUS;
|
|
input [1:0] PHYEMAC1RXLOSSOFSYNC;
|
|
input [2:0] PHYEMAC0RXCLKCORCNT;
|
|
input [2:0] PHYEMAC1RXCLKCORCNT;
|
|
input [31:0] HOSTWRDATA;
|
|
input [47:0] TIEEMAC0UNICASTADDR;
|
|
input [47:0] TIEEMAC1UNICASTADDR;
|
|
input [4:0] PHYEMAC0PHYAD;
|
|
input [4:0] PHYEMAC1PHYAD;
|
|
input [79:0] TIEEMAC0CONFIGVEC;
|
|
input [79:0] TIEEMAC1CONFIGVEC;
|
|
input [7:0] CLIENTEMAC0TXIFGDELAY;
|
|
input [7:0] CLIENTEMAC1TXIFGDELAY;
|
|
input [7:0] PHYEMAC0RXD;
|
|
input [7:0] PHYEMAC1RXD;
|
|
input [8:9] DCREMACABUS;
|
|
input [9:0] HOSTADDR;
|
|
endmodule
|
|
|
|
module TEMAC(DCRHOSTDONEIR, EMAC0CLIENTANINTERRUPT, EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXCLIENTCLKOUT, EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTTXACK, EMAC0CLIENTTXCLIENTCLKOUT, EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXRETRANSMIT, EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, EMAC0PHYENCOMMAALIGN, EMAC0PHYLOOPBACKMSB, EMAC0PHYMCLKOUT, EMAC0PHYMDOUT
|
|
, EMAC0PHYMDTRI, EMAC0PHYMGTRXRESET, EMAC0PHYMGTTXRESET, EMAC0PHYPOWERDOWN, EMAC0PHYSYNCACQSTATUS, EMAC0PHYTXCHARDISPMODE, EMAC0PHYTXCHARDISPVAL, EMAC0PHYTXCHARISK, EMAC0PHYTXCLK, EMAC0PHYTXEN, EMAC0PHYTXER, EMAC0PHYTXGMIIMIICLKOUT, EMAC0SPEEDIS10100, EMAC1CLIENTANINTERRUPT, EMAC1CLIENTRXBADFRAME, EMAC1CLIENTRXCLIENTCLKOUT, EMAC1CLIENTRXDVLD, EMAC1CLIENTRXDVLDMSW, EMAC1CLIENTRXFRAMEDROP, EMAC1CLIENTRXGOODFRAME, EMAC1CLIENTRXSTATSBYTEVLD
|
|
, EMAC1CLIENTRXSTATSVLD, EMAC1CLIENTTXACK, EMAC1CLIENTTXCLIENTCLKOUT, EMAC1CLIENTTXCOLLISION, EMAC1CLIENTTXRETRANSMIT, EMAC1CLIENTTXSTATS, EMAC1CLIENTTXSTATSBYTEVLD, EMAC1CLIENTTXSTATSVLD, EMAC1PHYENCOMMAALIGN, EMAC1PHYLOOPBACKMSB, EMAC1PHYMCLKOUT, EMAC1PHYMDOUT, EMAC1PHYMDTRI, EMAC1PHYMGTRXRESET, EMAC1PHYMGTTXRESET, EMAC1PHYPOWERDOWN, EMAC1PHYSYNCACQSTATUS, EMAC1PHYTXCHARDISPMODE, EMAC1PHYTXCHARDISPVAL, EMAC1PHYTXCHARISK, EMAC1PHYTXCLK
|
|
, EMAC1PHYTXEN, EMAC1PHYTXER, EMAC1PHYTXGMIIMIICLKOUT, EMAC1SPEEDIS10100, EMACDCRACK, HOSTMIIMRDY, EMACDCRDBUS, EMAC0CLIENTRXD, EMAC1CLIENTRXD, HOSTRDDATA, EMAC0CLIENTRXSTATS, EMAC1CLIENTRXSTATS, EMAC0PHYTXD, EMAC1PHYTXD, CLIENTEMAC0DCMLOCKED, CLIENTEMAC0PAUSEREQ, CLIENTEMAC0RXCLIENTCLKIN, CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXDVLD, CLIENTEMAC0TXDVLDMSW, CLIENTEMAC0TXFIRSTBYTE
|
|
, CLIENTEMAC0TXUNDERRUN, CLIENTEMAC1DCMLOCKED, CLIENTEMAC1PAUSEREQ, CLIENTEMAC1RXCLIENTCLKIN, CLIENTEMAC1TXCLIENTCLKIN, CLIENTEMAC1TXDVLD, CLIENTEMAC1TXDVLDMSW, CLIENTEMAC1TXFIRSTBYTE, CLIENTEMAC1TXUNDERRUN, DCREMACCLK, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTCLK, HOSTEMAC1SEL, HOSTMIIMSEL, HOSTREQ, PHYEMAC0COL, PHYEMAC0CRS, PHYEMAC0GTXCLK, PHYEMAC0MCLKIN
|
|
, PHYEMAC0MDIN, PHYEMAC0MIITXCLK, PHYEMAC0RXBUFERR, PHYEMAC0RXCHARISCOMMA, PHYEMAC0RXCHARISK, PHYEMAC0RXCHECKINGCRC, PHYEMAC0RXCLK, PHYEMAC0RXCOMMADET, PHYEMAC0RXDISPERR, PHYEMAC0RXDV, PHYEMAC0RXER, PHYEMAC0RXNOTINTABLE, PHYEMAC0RXRUNDISP, PHYEMAC0SIGNALDET, PHYEMAC0TXBUFERR, PHYEMAC0TXGMIIMIICLKIN, PHYEMAC1COL, PHYEMAC1CRS, PHYEMAC1GTXCLK, PHYEMAC1MCLKIN, PHYEMAC1MDIN
|
|
, PHYEMAC1MIITXCLK, PHYEMAC1RXBUFERR, PHYEMAC1RXCHARISCOMMA, PHYEMAC1RXCHARISK, PHYEMAC1RXCHECKINGCRC, PHYEMAC1RXCLK, PHYEMAC1RXCOMMADET, PHYEMAC1RXDISPERR, PHYEMAC1RXDV, PHYEMAC1RXER, PHYEMAC1RXNOTINTABLE, PHYEMAC1RXRUNDISP, PHYEMAC1SIGNALDET, PHYEMAC1TXBUFERR, PHYEMAC1TXGMIIMIICLKIN, RESET, DCREMACDBUS, DCREMACABUS, CLIENTEMAC0PAUSEVAL, CLIENTEMAC0TXD, CLIENTEMAC1PAUSEVAL
|
|
, CLIENTEMAC1TXD, HOSTOPCODE, PHYEMAC0RXBUFSTATUS, PHYEMAC0RXLOSSOFSYNC, PHYEMAC1RXBUFSTATUS, PHYEMAC1RXLOSSOFSYNC, PHYEMAC0RXCLKCORCNT, PHYEMAC1RXCLKCORCNT, HOSTWRDATA, PHYEMAC0PHYAD, PHYEMAC1PHYAD, CLIENTEMAC0TXIFGDELAY, CLIENTEMAC1TXIFGDELAY, PHYEMAC0RXD, PHYEMAC1RXD, HOSTADDR);
|
|
parameter EMAC0_1000BASEX_ENABLE = "FALSE";
|
|
parameter EMAC0_ADDRFILTER_ENABLE = "FALSE";
|
|
parameter EMAC0_BYTEPHY = "FALSE";
|
|
parameter EMAC0_CONFIGVEC_79 = "FALSE";
|
|
parameter EMAC0_GTLOOPBACK = "FALSE";
|
|
parameter EMAC0_HOST_ENABLE = "FALSE";
|
|
parameter EMAC0_LTCHECK_DISABLE = "FALSE";
|
|
parameter EMAC0_MDIO_ENABLE = "FALSE";
|
|
parameter EMAC0_PHYINITAUTONEG_ENABLE = "FALSE";
|
|
parameter EMAC0_PHYISOLATE = "FALSE";
|
|
parameter EMAC0_PHYLOOPBACKMSB = "FALSE";
|
|
parameter EMAC0_PHYPOWERDOWN = "FALSE";
|
|
parameter EMAC0_PHYRESET = "FALSE";
|
|
parameter EMAC0_RGMII_ENABLE = "FALSE";
|
|
parameter EMAC0_RX16BITCLIENT_ENABLE = "FALSE";
|
|
parameter EMAC0_RXFLOWCTRL_ENABLE = "FALSE";
|
|
parameter EMAC0_RXHALFDUPLEX = "FALSE";
|
|
parameter EMAC0_RXINBANDFCS_ENABLE = "FALSE";
|
|
parameter EMAC0_RXJUMBOFRAME_ENABLE = "FALSE";
|
|
parameter EMAC0_RXRESET = "FALSE";
|
|
parameter EMAC0_RXVLAN_ENABLE = "FALSE";
|
|
parameter EMAC0_RX_ENABLE = "FALSE";
|
|
parameter EMAC0_SGMII_ENABLE = "FALSE";
|
|
parameter EMAC0_SPEED_LSB = "FALSE";
|
|
parameter EMAC0_SPEED_MSB = "FALSE";
|
|
parameter EMAC0_TX16BITCLIENT_ENABLE = "FALSE";
|
|
parameter EMAC0_TXFLOWCTRL_ENABLE = "FALSE";
|
|
parameter EMAC0_TXHALFDUPLEX = "FALSE";
|
|
parameter EMAC0_TXIFGADJUST_ENABLE = "FALSE";
|
|
parameter EMAC0_TXINBANDFCS_ENABLE = "FALSE";
|
|
parameter EMAC0_TXJUMBOFRAME_ENABLE = "FALSE";
|
|
parameter EMAC0_TXRESET = "FALSE";
|
|
parameter EMAC0_TXVLAN_ENABLE = "FALSE";
|
|
parameter EMAC0_TX_ENABLE = "FALSE";
|
|
parameter EMAC0_UNIDIRECTION_ENABLE = "FALSE";
|
|
parameter EMAC0_USECLKEN = "FALSE";
|
|
parameter EMAC1_1000BASEX_ENABLE = "FALSE";
|
|
parameter EMAC1_ADDRFILTER_ENABLE = "FALSE";
|
|
parameter EMAC1_BYTEPHY = "FALSE";
|
|
parameter EMAC1_CONFIGVEC_79 = "FALSE";
|
|
parameter EMAC1_GTLOOPBACK = "FALSE";
|
|
parameter EMAC1_HOST_ENABLE = "FALSE";
|
|
parameter EMAC1_LTCHECK_DISABLE = "FALSE";
|
|
parameter EMAC1_MDIO_ENABLE = "FALSE";
|
|
parameter EMAC1_PHYINITAUTONEG_ENABLE = "FALSE";
|
|
parameter EMAC1_PHYISOLATE = "FALSE";
|
|
parameter EMAC1_PHYLOOPBACKMSB = "FALSE";
|
|
parameter EMAC1_PHYPOWERDOWN = "FALSE";
|
|
parameter EMAC1_PHYRESET = "FALSE";
|
|
parameter EMAC1_RGMII_ENABLE = "FALSE";
|
|
parameter EMAC1_RX16BITCLIENT_ENABLE = "FALSE";
|
|
parameter EMAC1_RXFLOWCTRL_ENABLE = "FALSE";
|
|
parameter EMAC1_RXHALFDUPLEX = "FALSE";
|
|
parameter EMAC1_RXINBANDFCS_ENABLE = "FALSE";
|
|
parameter EMAC1_RXJUMBOFRAME_ENABLE = "FALSE";
|
|
parameter EMAC1_RXRESET = "FALSE";
|
|
parameter EMAC1_RXVLAN_ENABLE = "FALSE";
|
|
parameter EMAC1_RX_ENABLE = "FALSE";
|
|
parameter EMAC1_SGMII_ENABLE = "FALSE";
|
|
parameter EMAC1_SPEED_LSB = "FALSE";
|
|
parameter EMAC1_SPEED_MSB = "FALSE";
|
|
parameter EMAC1_TX16BITCLIENT_ENABLE = "FALSE";
|
|
parameter EMAC1_TXFLOWCTRL_ENABLE = "FALSE";
|
|
parameter EMAC1_TXHALFDUPLEX = "FALSE";
|
|
parameter EMAC1_TXIFGADJUST_ENABLE = "FALSE";
|
|
parameter EMAC1_TXINBANDFCS_ENABLE = "FALSE";
|
|
parameter EMAC1_TXJUMBOFRAME_ENABLE = "FALSE";
|
|
parameter EMAC1_TXRESET = "FALSE";
|
|
parameter EMAC1_TXVLAN_ENABLE = "FALSE";
|
|
parameter EMAC1_TX_ENABLE = "FALSE";
|
|
parameter EMAC1_UNIDIRECTION_ENABLE = "FALSE";
|
|
parameter EMAC1_USECLKEN = "FALSE";
|
|
parameter [0:7] EMAC0_DCRBASEADDR = 8'h00;
|
|
parameter [0:7] EMAC1_DCRBASEADDR = 8'h00;
|
|
parameter [47:0] EMAC0_PAUSEADDR = 48'h000000000000;
|
|
parameter [47:0] EMAC0_UNICASTADDR = 48'h000000000000;
|
|
parameter [47:0] EMAC1_PAUSEADDR = 48'h000000000000;
|
|
parameter [47:0] EMAC1_UNICASTADDR = 48'h000000000000;
|
|
parameter [8:0] EMAC0_LINKTIMERVAL = 9'h000;
|
|
parameter [8:0] EMAC1_LINKTIMERVAL = 9'h000;
|
|
output DCRHOSTDONEIR;
|
|
output EMAC0CLIENTANINTERRUPT;
|
|
output EMAC0CLIENTRXBADFRAME;
|
|
output EMAC0CLIENTRXCLIENTCLKOUT;
|
|
output EMAC0CLIENTRXDVLD;
|
|
output EMAC0CLIENTRXDVLDMSW;
|
|
output EMAC0CLIENTRXFRAMEDROP;
|
|
output EMAC0CLIENTRXGOODFRAME;
|
|
output EMAC0CLIENTRXSTATSBYTEVLD;
|
|
output EMAC0CLIENTRXSTATSVLD;
|
|
output EMAC0CLIENTTXACK;
|
|
output EMAC0CLIENTTXCLIENTCLKOUT;
|
|
output EMAC0CLIENTTXCOLLISION;
|
|
output EMAC0CLIENTTXRETRANSMIT;
|
|
output EMAC0CLIENTTXSTATS;
|
|
output EMAC0CLIENTTXSTATSBYTEVLD;
|
|
output EMAC0CLIENTTXSTATSVLD;
|
|
output EMAC0PHYENCOMMAALIGN;
|
|
output EMAC0PHYLOOPBACKMSB;
|
|
output EMAC0PHYMCLKOUT;
|
|
output EMAC0PHYMDOUT;
|
|
output EMAC0PHYMDTRI;
|
|
output EMAC0PHYMGTRXRESET;
|
|
output EMAC0PHYMGTTXRESET;
|
|
output EMAC0PHYPOWERDOWN;
|
|
output EMAC0PHYSYNCACQSTATUS;
|
|
output EMAC0PHYTXCHARDISPMODE;
|
|
output EMAC0PHYTXCHARDISPVAL;
|
|
output EMAC0PHYTXCHARISK;
|
|
output EMAC0PHYTXCLK;
|
|
output EMAC0PHYTXEN;
|
|
output EMAC0PHYTXER;
|
|
output EMAC0PHYTXGMIIMIICLKOUT;
|
|
output EMAC0SPEEDIS10100;
|
|
output EMAC1CLIENTANINTERRUPT;
|
|
output EMAC1CLIENTRXBADFRAME;
|
|
output EMAC1CLIENTRXCLIENTCLKOUT;
|
|
output EMAC1CLIENTRXDVLD;
|
|
output EMAC1CLIENTRXDVLDMSW;
|
|
output EMAC1CLIENTRXFRAMEDROP;
|
|
output EMAC1CLIENTRXGOODFRAME;
|
|
output EMAC1CLIENTRXSTATSBYTEVLD;
|
|
output EMAC1CLIENTRXSTATSVLD;
|
|
output EMAC1CLIENTTXACK;
|
|
output EMAC1CLIENTTXCLIENTCLKOUT;
|
|
output EMAC1CLIENTTXCOLLISION;
|
|
output EMAC1CLIENTTXRETRANSMIT;
|
|
output EMAC1CLIENTTXSTATS;
|
|
output EMAC1CLIENTTXSTATSBYTEVLD;
|
|
output EMAC1CLIENTTXSTATSVLD;
|
|
output EMAC1PHYENCOMMAALIGN;
|
|
output EMAC1PHYLOOPBACKMSB;
|
|
output EMAC1PHYMCLKOUT;
|
|
output EMAC1PHYMDOUT;
|
|
output EMAC1PHYMDTRI;
|
|
output EMAC1PHYMGTRXRESET;
|
|
output EMAC1PHYMGTTXRESET;
|
|
output EMAC1PHYPOWERDOWN;
|
|
output EMAC1PHYSYNCACQSTATUS;
|
|
output EMAC1PHYTXCHARDISPMODE;
|
|
output EMAC1PHYTXCHARDISPVAL;
|
|
output EMAC1PHYTXCHARISK;
|
|
output EMAC1PHYTXCLK;
|
|
output EMAC1PHYTXEN;
|
|
output EMAC1PHYTXER;
|
|
output EMAC1PHYTXGMIIMIICLKOUT;
|
|
output EMAC1SPEEDIS10100;
|
|
output EMACDCRACK;
|
|
output HOSTMIIMRDY;
|
|
output [0:31] EMACDCRDBUS;
|
|
output [15:0] EMAC0CLIENTRXD;
|
|
output [15:0] EMAC1CLIENTRXD;
|
|
output [31:0] HOSTRDDATA;
|
|
output [6:0] EMAC0CLIENTRXSTATS;
|
|
output [6:0] EMAC1CLIENTRXSTATS;
|
|
output [7:0] EMAC0PHYTXD;
|
|
output [7:0] EMAC1PHYTXD;
|
|
input CLIENTEMAC0DCMLOCKED;
|
|
input CLIENTEMAC0PAUSEREQ;
|
|
input CLIENTEMAC0RXCLIENTCLKIN;
|
|
input CLIENTEMAC0TXCLIENTCLKIN;
|
|
input CLIENTEMAC0TXDVLD;
|
|
input CLIENTEMAC0TXDVLDMSW;
|
|
input CLIENTEMAC0TXFIRSTBYTE;
|
|
input CLIENTEMAC0TXUNDERRUN;
|
|
input CLIENTEMAC1DCMLOCKED;
|
|
input CLIENTEMAC1PAUSEREQ;
|
|
input CLIENTEMAC1RXCLIENTCLKIN;
|
|
input CLIENTEMAC1TXCLIENTCLKIN;
|
|
input CLIENTEMAC1TXDVLD;
|
|
input CLIENTEMAC1TXDVLDMSW;
|
|
input CLIENTEMAC1TXFIRSTBYTE;
|
|
input CLIENTEMAC1TXUNDERRUN;
|
|
input DCREMACCLK;
|
|
input DCREMACENABLE;
|
|
input DCREMACREAD;
|
|
input DCREMACWRITE;
|
|
input HOSTCLK;
|
|
input HOSTEMAC1SEL;
|
|
input HOSTMIIMSEL;
|
|
input HOSTREQ;
|
|
input PHYEMAC0COL;
|
|
input PHYEMAC0CRS;
|
|
input PHYEMAC0GTXCLK;
|
|
input PHYEMAC0MCLKIN;
|
|
input PHYEMAC0MDIN;
|
|
input PHYEMAC0MIITXCLK;
|
|
input PHYEMAC0RXBUFERR;
|
|
input PHYEMAC0RXCHARISCOMMA;
|
|
input PHYEMAC0RXCHARISK;
|
|
input PHYEMAC0RXCHECKINGCRC;
|
|
input PHYEMAC0RXCLK;
|
|
input PHYEMAC0RXCOMMADET;
|
|
input PHYEMAC0RXDISPERR;
|
|
input PHYEMAC0RXDV;
|
|
input PHYEMAC0RXER;
|
|
input PHYEMAC0RXNOTINTABLE;
|
|
input PHYEMAC0RXRUNDISP;
|
|
input PHYEMAC0SIGNALDET;
|
|
input PHYEMAC0TXBUFERR;
|
|
input PHYEMAC0TXGMIIMIICLKIN;
|
|
input PHYEMAC1COL;
|
|
input PHYEMAC1CRS;
|
|
input PHYEMAC1GTXCLK;
|
|
input PHYEMAC1MCLKIN;
|
|
input PHYEMAC1MDIN;
|
|
input PHYEMAC1MIITXCLK;
|
|
input PHYEMAC1RXBUFERR;
|
|
input PHYEMAC1RXCHARISCOMMA;
|
|
input PHYEMAC1RXCHARISK;
|
|
input PHYEMAC1RXCHECKINGCRC;
|
|
input PHYEMAC1RXCLK;
|
|
input PHYEMAC1RXCOMMADET;
|
|
input PHYEMAC1RXDISPERR;
|
|
input PHYEMAC1RXDV;
|
|
input PHYEMAC1RXER;
|
|
input PHYEMAC1RXNOTINTABLE;
|
|
input PHYEMAC1RXRUNDISP;
|
|
input PHYEMAC1SIGNALDET;
|
|
input PHYEMAC1TXBUFERR;
|
|
input PHYEMAC1TXGMIIMIICLKIN;
|
|
input RESET;
|
|
input [0:31] DCREMACDBUS;
|
|
input [0:9] DCREMACABUS;
|
|
input [15:0] CLIENTEMAC0PAUSEVAL;
|
|
input [15:0] CLIENTEMAC0TXD;
|
|
input [15:0] CLIENTEMAC1PAUSEVAL;
|
|
input [15:0] CLIENTEMAC1TXD;
|
|
input [1:0] HOSTOPCODE;
|
|
input [1:0] PHYEMAC0RXBUFSTATUS;
|
|
input [1:0] PHYEMAC0RXLOSSOFSYNC;
|
|
input [1:0] PHYEMAC1RXBUFSTATUS;
|
|
input [1:0] PHYEMAC1RXLOSSOFSYNC;
|
|
input [2:0] PHYEMAC0RXCLKCORCNT;
|
|
input [2:0] PHYEMAC1RXCLKCORCNT;
|
|
input [31:0] HOSTWRDATA;
|
|
input [4:0] PHYEMAC0PHYAD;
|
|
input [4:0] PHYEMAC1PHYAD;
|
|
input [7:0] CLIENTEMAC0TXIFGDELAY;
|
|
input [7:0] CLIENTEMAC1TXIFGDELAY;
|
|
input [7:0] PHYEMAC0RXD;
|
|
input [7:0] PHYEMAC1RXD;
|
|
input [9:0] HOSTADDR;
|
|
endmodule
|
|
|
|
module TEMAC_SINGLE(DCRHOSTDONEIR, EMACCLIENTANINTERRUPT, EMACCLIENTRXBADFRAME, EMACCLIENTRXCLIENTCLKOUT, EMACCLIENTRXDVLD, EMACCLIENTRXDVLDMSW, EMACCLIENTRXFRAMEDROP, EMACCLIENTRXGOODFRAME, EMACCLIENTRXSTATSBYTEVLD, EMACCLIENTRXSTATSVLD, EMACCLIENTTXACK, EMACCLIENTTXCLIENTCLKOUT, EMACCLIENTTXCOLLISION, EMACCLIENTTXRETRANSMIT, EMACCLIENTTXSTATS, EMACCLIENTTXSTATSBYTEVLD, EMACCLIENTTXSTATSVLD, EMACDCRACK, EMACPHYENCOMMAALIGN, EMACPHYLOOPBACKMSB, EMACPHYMCLKOUT
|
|
, EMACPHYMDOUT, EMACPHYMDTRI, EMACPHYMGTRXRESET, EMACPHYMGTTXRESET, EMACPHYPOWERDOWN, EMACPHYSYNCACQSTATUS, EMACPHYTXCHARDISPMODE, EMACPHYTXCHARDISPVAL, EMACPHYTXCHARISK, EMACPHYTXCLK, EMACPHYTXEN, EMACPHYTXER, EMACPHYTXGMIIMIICLKOUT, EMACSPEEDIS10100, HOSTMIIMRDY, EMACDCRDBUS, EMACCLIENTRXD, HOSTRDDATA, EMACCLIENTRXSTATS, EMACPHYTXD, CLIENTEMACDCMLOCKED
|
|
, CLIENTEMACPAUSEREQ, CLIENTEMACRXCLIENTCLKIN, CLIENTEMACTXCLIENTCLKIN, CLIENTEMACTXDVLD, CLIENTEMACTXDVLDMSW, CLIENTEMACTXFIRSTBYTE, CLIENTEMACTXUNDERRUN, DCREMACCLK, DCREMACENABLE, DCREMACREAD, DCREMACWRITE, HOSTCLK, HOSTMIIMSEL, HOSTREQ, PHYEMACCOL, PHYEMACCRS, PHYEMACGTXCLK, PHYEMACMCLKIN, PHYEMACMDIN, PHYEMACMIITXCLK, PHYEMACRXCHARISCOMMA
|
|
, PHYEMACRXCHARISK, PHYEMACRXCLK, PHYEMACRXDISPERR, PHYEMACRXDV, PHYEMACRXER, PHYEMACRXNOTINTABLE, PHYEMACRXRUNDISP, PHYEMACSIGNALDET, PHYEMACTXBUFERR, PHYEMACTXGMIIMIICLKIN, RESET, DCREMACDBUS, DCREMACABUS, CLIENTEMACPAUSEVAL, CLIENTEMACTXD, HOSTOPCODE, PHYEMACRXBUFSTATUS, PHYEMACRXCLKCORCNT, HOSTWRDATA, PHYEMACPHYAD, CLIENTEMACTXIFGDELAY
|
|
, PHYEMACRXD, HOSTADDR);
|
|
parameter EMAC_1000BASEX_ENABLE = "FALSE";
|
|
parameter EMAC_ADDRFILTER_ENABLE = "FALSE";
|
|
parameter EMAC_BYTEPHY = "FALSE";
|
|
parameter EMAC_CTRLLENCHECK_DISABLE = "FALSE";
|
|
parameter [0:7] EMAC_DCRBASEADDR = 8'h00;
|
|
parameter EMAC_GTLOOPBACK = "FALSE";
|
|
parameter EMAC_HOST_ENABLE = "FALSE";
|
|
parameter [8:0] EMAC_LINKTIMERVAL = 9'h000;
|
|
parameter EMAC_LTCHECK_DISABLE = "FALSE";
|
|
parameter EMAC_MDIO_ENABLE = "FALSE";
|
|
parameter EMAC_MDIO_IGNORE_PHYADZERO = "FALSE";
|
|
parameter [47:0] EMAC_PAUSEADDR = 48'h000000000000;
|
|
parameter EMAC_PHYINITAUTONEG_ENABLE = "FALSE";
|
|
parameter EMAC_PHYISOLATE = "FALSE";
|
|
parameter EMAC_PHYLOOPBACKMSB = "FALSE";
|
|
parameter EMAC_PHYPOWERDOWN = "FALSE";
|
|
parameter EMAC_PHYRESET = "FALSE";
|
|
parameter EMAC_RGMII_ENABLE = "FALSE";
|
|
parameter EMAC_RX16BITCLIENT_ENABLE = "FALSE";
|
|
parameter EMAC_RXFLOWCTRL_ENABLE = "FALSE";
|
|
parameter EMAC_RXHALFDUPLEX = "FALSE";
|
|
parameter EMAC_RXINBANDFCS_ENABLE = "FALSE";
|
|
parameter EMAC_RXJUMBOFRAME_ENABLE = "FALSE";
|
|
parameter EMAC_RXRESET = "FALSE";
|
|
parameter EMAC_RXVLAN_ENABLE = "FALSE";
|
|
parameter EMAC_RX_ENABLE = "TRUE";
|
|
parameter EMAC_SGMII_ENABLE = "FALSE";
|
|
parameter EMAC_SPEED_LSB = "FALSE";
|
|
parameter EMAC_SPEED_MSB = "FALSE";
|
|
parameter EMAC_TX16BITCLIENT_ENABLE = "FALSE";
|
|
parameter EMAC_TXFLOWCTRL_ENABLE = "FALSE";
|
|
parameter EMAC_TXHALFDUPLEX = "FALSE";
|
|
parameter EMAC_TXIFGADJUST_ENABLE = "FALSE";
|
|
parameter EMAC_TXINBANDFCS_ENABLE = "FALSE";
|
|
parameter EMAC_TXJUMBOFRAME_ENABLE = "FALSE";
|
|
parameter EMAC_TXRESET = "FALSE";
|
|
parameter EMAC_TXVLAN_ENABLE = "FALSE";
|
|
parameter EMAC_TX_ENABLE = "TRUE";
|
|
parameter [47:0] EMAC_UNICASTADDR = 48'h000000000000;
|
|
parameter EMAC_UNIDIRECTION_ENABLE = "FALSE";
|
|
parameter EMAC_USECLKEN = "FALSE";
|
|
parameter SIM_VERSION = "1.0";
|
|
output DCRHOSTDONEIR;
|
|
output EMACCLIENTANINTERRUPT;
|
|
output EMACCLIENTRXBADFRAME;
|
|
output EMACCLIENTRXCLIENTCLKOUT;
|
|
output EMACCLIENTRXDVLD;
|
|
output EMACCLIENTRXDVLDMSW;
|
|
output EMACCLIENTRXFRAMEDROP;
|
|
output EMACCLIENTRXGOODFRAME;
|
|
output EMACCLIENTRXSTATSBYTEVLD;
|
|
output EMACCLIENTRXSTATSVLD;
|
|
output EMACCLIENTTXACK;
|
|
output EMACCLIENTTXCLIENTCLKOUT;
|
|
output EMACCLIENTTXCOLLISION;
|
|
output EMACCLIENTTXRETRANSMIT;
|
|
output EMACCLIENTTXSTATS;
|
|
output EMACCLIENTTXSTATSBYTEVLD;
|
|
output EMACCLIENTTXSTATSVLD;
|
|
output EMACDCRACK;
|
|
output EMACPHYENCOMMAALIGN;
|
|
output EMACPHYLOOPBACKMSB;
|
|
output EMACPHYMCLKOUT;
|
|
output EMACPHYMDOUT;
|
|
output EMACPHYMDTRI;
|
|
output EMACPHYMGTRXRESET;
|
|
output EMACPHYMGTTXRESET;
|
|
output EMACPHYPOWERDOWN;
|
|
output EMACPHYSYNCACQSTATUS;
|
|
output EMACPHYTXCHARDISPMODE;
|
|
output EMACPHYTXCHARDISPVAL;
|
|
output EMACPHYTXCHARISK;
|
|
output EMACPHYTXCLK;
|
|
output EMACPHYTXEN;
|
|
output EMACPHYTXER;
|
|
output EMACPHYTXGMIIMIICLKOUT;
|
|
output EMACSPEEDIS10100;
|
|
output HOSTMIIMRDY;
|
|
output [0:31] EMACDCRDBUS;
|
|
output [15:0] EMACCLIENTRXD;
|
|
output [31:0] HOSTRDDATA;
|
|
output [6:0] EMACCLIENTRXSTATS;
|
|
output [7:0] EMACPHYTXD;
|
|
input CLIENTEMACDCMLOCKED;
|
|
input CLIENTEMACPAUSEREQ;
|
|
input CLIENTEMACRXCLIENTCLKIN;
|
|
input CLIENTEMACTXCLIENTCLKIN;
|
|
input CLIENTEMACTXDVLD;
|
|
input CLIENTEMACTXDVLDMSW;
|
|
input CLIENTEMACTXFIRSTBYTE;
|
|
input CLIENTEMACTXUNDERRUN;
|
|
input DCREMACCLK;
|
|
input DCREMACENABLE;
|
|
input DCREMACREAD;
|
|
input DCREMACWRITE;
|
|
input HOSTCLK;
|
|
input HOSTMIIMSEL;
|
|
input HOSTREQ;
|
|
input PHYEMACCOL;
|
|
input PHYEMACCRS;
|
|
input PHYEMACGTXCLK;
|
|
input PHYEMACMCLKIN;
|
|
input PHYEMACMDIN;
|
|
input PHYEMACMIITXCLK;
|
|
input PHYEMACRXCHARISCOMMA;
|
|
input PHYEMACRXCHARISK;
|
|
input PHYEMACRXCLK;
|
|
input PHYEMACRXDISPERR;
|
|
input PHYEMACRXDV;
|
|
input PHYEMACRXER;
|
|
input PHYEMACRXNOTINTABLE;
|
|
input PHYEMACRXRUNDISP;
|
|
input PHYEMACSIGNALDET;
|
|
input PHYEMACTXBUFERR;
|
|
input PHYEMACTXGMIIMIICLKIN;
|
|
input RESET;
|
|
input [0:31] DCREMACDBUS;
|
|
input [0:9] DCREMACABUS;
|
|
input [15:0] CLIENTEMACPAUSEVAL;
|
|
input [15:0] CLIENTEMACTXD;
|
|
input [1:0] HOSTOPCODE;
|
|
input [1:0] PHYEMACRXBUFSTATUS;
|
|
input [2:0] PHYEMACRXCLKCORCNT;
|
|
input [31:0] HOSTWRDATA;
|
|
input [4:0] PHYEMACPHYAD;
|
|
input [7:0] CLIENTEMACTXIFGDELAY;
|
|
input [7:0] PHYEMACRXD;
|
|
input [9:0] HOSTADDR;
|
|
endmodule
|
|
|
|
module CMAC(DRP_DO, DRP_RDY, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_LANE_ALIGNER_FILL_0, RX_LANE_ALIGNER_FILL_1, RX_LANE_ALIGNER_FILL_10
|
|
, RX_LANE_ALIGNER_FILL_11, RX_LANE_ALIGNER_FILL_12, RX_LANE_ALIGNER_FILL_13, RX_LANE_ALIGNER_FILL_14, RX_LANE_ALIGNER_FILL_15, RX_LANE_ALIGNER_FILL_16, RX_LANE_ALIGNER_FILL_17, RX_LANE_ALIGNER_FILL_18, RX_LANE_ALIGNER_FILL_19, RX_LANE_ALIGNER_FILL_2, RX_LANE_ALIGNER_FILL_3, RX_LANE_ALIGNER_FILL_4, RX_LANE_ALIGNER_FILL_5, RX_LANE_ALIGNER_FILL_6, RX_LANE_ALIGNER_FILL_7, RX_LANE_ALIGNER_FILL_8, RX_LANE_ALIGNER_FILL_9, RX_MTYOUT0, RX_MTYOUT1, RX_MTYOUT2, RX_MTYOUT3
|
|
, RX_PTP_PCSLANE_OUT, RX_PTP_TSTAMP_OUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_CODE, STAT_RX_BAD_FCS, STAT_RX_BAD_PREAMBLE, STAT_RX_BAD_SFD, STAT_RX_BIP_ERR_0, STAT_RX_BIP_ERR_1, STAT_RX_BIP_ERR_10, STAT_RX_BIP_ERR_11, STAT_RX_BIP_ERR_12, STAT_RX_BIP_ERR_13, STAT_RX_BIP_ERR_14, STAT_RX_BIP_ERR_15, STAT_RX_BIP_ERR_16
|
|
, STAT_RX_BIP_ERR_17, STAT_RX_BIP_ERR_18, STAT_RX_BIP_ERR_19, STAT_RX_BIP_ERR_2, STAT_RX_BIP_ERR_3, STAT_RX_BIP_ERR_4, STAT_RX_BIP_ERR_5, STAT_RX_BIP_ERR_6, STAT_RX_BIP_ERR_7, STAT_RX_BIP_ERR_8, STAT_RX_BIP_ERR_9, STAT_RX_BLOCK_LOCK, STAT_RX_BROADCAST, STAT_RX_FRAGMENT, STAT_RX_FRAMING_ERR_0, STAT_RX_FRAMING_ERR_1, STAT_RX_FRAMING_ERR_10, STAT_RX_FRAMING_ERR_11, STAT_RX_FRAMING_ERR_12, STAT_RX_FRAMING_ERR_13, STAT_RX_FRAMING_ERR_14
|
|
, STAT_RX_FRAMING_ERR_15, STAT_RX_FRAMING_ERR_16, STAT_RX_FRAMING_ERR_17, STAT_RX_FRAMING_ERR_18, STAT_RX_FRAMING_ERR_19, STAT_RX_FRAMING_ERR_2, STAT_RX_FRAMING_ERR_3, STAT_RX_FRAMING_ERR_4, STAT_RX_FRAMING_ERR_5, STAT_RX_FRAMING_ERR_6, STAT_RX_FRAMING_ERR_7, STAT_RX_FRAMING_ERR_8, STAT_RX_FRAMING_ERR_9, STAT_RX_FRAMING_ERR_VALID_0, STAT_RX_FRAMING_ERR_VALID_1, STAT_RX_FRAMING_ERR_VALID_10, STAT_RX_FRAMING_ERR_VALID_11, STAT_RX_FRAMING_ERR_VALID_12, STAT_RX_FRAMING_ERR_VALID_13, STAT_RX_FRAMING_ERR_VALID_14, STAT_RX_FRAMING_ERR_VALID_15
|
|
, STAT_RX_FRAMING_ERR_VALID_16, STAT_RX_FRAMING_ERR_VALID_17, STAT_RX_FRAMING_ERR_VALID_18, STAT_RX_FRAMING_ERR_VALID_19, STAT_RX_FRAMING_ERR_VALID_2, STAT_RX_FRAMING_ERR_VALID_3, STAT_RX_FRAMING_ERR_VALID_4, STAT_RX_FRAMING_ERR_VALID_5, STAT_RX_FRAMING_ERR_VALID_6, STAT_RX_FRAMING_ERR_VALID_7, STAT_RX_FRAMING_ERR_VALID_8, STAT_RX_FRAMING_ERR_VALID_9, STAT_RX_GOT_SIGNAL_OS, STAT_RX_HI_BER, STAT_RX_INRANGEERR, STAT_RX_INTERNAL_LOCAL_FAULT, STAT_RX_JABBER, STAT_RX_LANE0_VLM_BIP7, STAT_RX_LANE0_VLM_BIP7_VALID, STAT_RX_LOCAL_FAULT, STAT_RX_MF_ERR
|
|
, STAT_RX_MF_LEN_ERR, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MULTICAST, STAT_RX_OVERSIZE, STAT_RX_PACKET_1024_1518_BYTES, STAT_RX_PACKET_128_255_BYTES, STAT_RX_PACKET_1519_1522_BYTES, STAT_RX_PACKET_1523_1548_BYTES, STAT_RX_PACKET_1549_2047_BYTES, STAT_RX_PACKET_2048_4095_BYTES, STAT_RX_PACKET_256_511_BYTES, STAT_RX_PACKET_4096_8191_BYTES, STAT_RX_PACKET_512_1023_BYTES, STAT_RX_PACKET_64_BYTES, STAT_RX_PACKET_65_127_BYTES, STAT_RX_PACKET_8192_9215_BYTES, STAT_RX_PACKET_BAD_FCS, STAT_RX_PACKET_LARGE, STAT_RX_PACKET_SMALL, STAT_RX_PAUSE
|
|
, STAT_RX_PAUSE_QUANTA0, STAT_RX_PAUSE_QUANTA1, STAT_RX_PAUSE_QUANTA2, STAT_RX_PAUSE_QUANTA3, STAT_RX_PAUSE_QUANTA4, STAT_RX_PAUSE_QUANTA5, STAT_RX_PAUSE_QUANTA6, STAT_RX_PAUSE_QUANTA7, STAT_RX_PAUSE_QUANTA8, STAT_RX_PAUSE_REQ, STAT_RX_PAUSE_VALID, STAT_RX_RECEIVED_LOCAL_FAULT, STAT_RX_REMOTE_FAULT, STAT_RX_STATUS, STAT_RX_STOMPED_FCS, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR, STAT_RX_TEST_PATTERN_MISMATCH, STAT_RX_TOOLONG, STAT_RX_TOTAL_BYTES, STAT_RX_TOTAL_GOOD_BYTES
|
|
, STAT_RX_TOTAL_GOOD_PACKETS, STAT_RX_TOTAL_PACKETS, STAT_RX_TRUNCATED, STAT_RX_UNDERSIZE, STAT_RX_UNICAST, STAT_RX_USER_PAUSE, STAT_RX_VLAN, STAT_RX_VL_DEMUXED, STAT_RX_VL_NUMBER_0, STAT_RX_VL_NUMBER_1, STAT_RX_VL_NUMBER_10, STAT_RX_VL_NUMBER_11, STAT_RX_VL_NUMBER_12, STAT_RX_VL_NUMBER_13, STAT_RX_VL_NUMBER_14, STAT_RX_VL_NUMBER_15, STAT_RX_VL_NUMBER_16, STAT_RX_VL_NUMBER_17, STAT_RX_VL_NUMBER_18, STAT_RX_VL_NUMBER_19, STAT_RX_VL_NUMBER_2
|
|
, STAT_RX_VL_NUMBER_3, STAT_RX_VL_NUMBER_4, STAT_RX_VL_NUMBER_5, STAT_RX_VL_NUMBER_6, STAT_RX_VL_NUMBER_7, STAT_RX_VL_NUMBER_8, STAT_RX_VL_NUMBER_9, STAT_TX_BAD_FCS, STAT_TX_BROADCAST, STAT_TX_FRAME_ERROR, STAT_TX_LOCAL_FAULT, STAT_TX_MULTICAST, STAT_TX_PACKET_1024_1518_BYTES, STAT_TX_PACKET_128_255_BYTES, STAT_TX_PACKET_1519_1522_BYTES, STAT_TX_PACKET_1523_1548_BYTES, STAT_TX_PACKET_1549_2047_BYTES, STAT_TX_PACKET_2048_4095_BYTES, STAT_TX_PACKET_256_511_BYTES, STAT_TX_PACKET_4096_8191_BYTES, STAT_TX_PACKET_512_1023_BYTES
|
|
, STAT_TX_PACKET_64_BYTES, STAT_TX_PACKET_65_127_BYTES, STAT_TX_PACKET_8192_9215_BYTES, STAT_TX_PACKET_LARGE, STAT_TX_PACKET_SMALL, STAT_TX_PAUSE, STAT_TX_PAUSE_VALID, STAT_TX_PTP_FIFO_READ_ERROR, STAT_TX_PTP_FIFO_WRITE_ERROR, STAT_TX_TOTAL_BYTES, STAT_TX_TOTAL_GOOD_BYTES, STAT_TX_TOTAL_GOOD_PACKETS, STAT_TX_TOTAL_PACKETS, STAT_TX_UNICAST, STAT_TX_USER_PAUSE, STAT_TX_VLAN, TX_OVFOUT, TX_PTP_PCSLANE_OUT, TX_PTP_TSTAMP_OUT, TX_PTP_TSTAMP_TAG_OUT, TX_PTP_TSTAMP_VALID_OUT
|
|
, TX_RDYOUT, TX_SERDES_ALT_DATA0, TX_SERDES_ALT_DATA1, TX_SERDES_ALT_DATA2, TX_SERDES_ALT_DATA3, TX_SERDES_DATA0, TX_SERDES_DATA1, TX_SERDES_DATA2, TX_SERDES_DATA3, TX_SERDES_DATA4, TX_SERDES_DATA5, TX_SERDES_DATA6, TX_SERDES_DATA7, TX_SERDES_DATA8, TX_SERDES_DATA9, TX_UNFOUT, CTL_CAUI4_MODE, CTL_RX_CHECK_ETYPE_GCP, CTL_RX_CHECK_ETYPE_GPP, CTL_RX_CHECK_ETYPE_PCP, CTL_RX_CHECK_ETYPE_PPP
|
|
, CTL_RX_CHECK_MCAST_GCP, CTL_RX_CHECK_MCAST_GPP, CTL_RX_CHECK_MCAST_PCP, CTL_RX_CHECK_MCAST_PPP, CTL_RX_CHECK_OPCODE_GCP, CTL_RX_CHECK_OPCODE_GPP, CTL_RX_CHECK_OPCODE_PCP, CTL_RX_CHECK_OPCODE_PPP, CTL_RX_CHECK_SA_GCP, CTL_RX_CHECK_SA_GPP, CTL_RX_CHECK_SA_PCP, CTL_RX_CHECK_SA_PPP, CTL_RX_CHECK_UCAST_GCP, CTL_RX_CHECK_UCAST_GPP, CTL_RX_CHECK_UCAST_PCP, CTL_RX_CHECK_UCAST_PPP, CTL_RX_ENABLE, CTL_RX_ENABLE_GCP, CTL_RX_ENABLE_GPP, CTL_RX_ENABLE_PCP, CTL_RX_ENABLE_PPP
|
|
, CTL_RX_FORCE_RESYNC, CTL_RX_PAUSE_ACK, CTL_RX_PAUSE_ENABLE, CTL_RX_SYSTEMTIMERIN, CTL_RX_TEST_PATTERN, CTL_TX_ENABLE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE, CTL_TX_PAUSE_ENABLE, CTL_TX_PAUSE_QUANTA0, CTL_TX_PAUSE_QUANTA1, CTL_TX_PAUSE_QUANTA2, CTL_TX_PAUSE_QUANTA3, CTL_TX_PAUSE_QUANTA4, CTL_TX_PAUSE_QUANTA5, CTL_TX_PAUSE_QUANTA6, CTL_TX_PAUSE_QUANTA7, CTL_TX_PAUSE_QUANTA8, CTL_TX_PAUSE_REFRESH_TIMER0, CTL_TX_PAUSE_REFRESH_TIMER1, CTL_TX_PAUSE_REFRESH_TIMER2
|
|
, CTL_TX_PAUSE_REFRESH_TIMER3, CTL_TX_PAUSE_REFRESH_TIMER4, CTL_TX_PAUSE_REFRESH_TIMER5, CTL_TX_PAUSE_REFRESH_TIMER6, CTL_TX_PAUSE_REFRESH_TIMER7, CTL_TX_PAUSE_REFRESH_TIMER8, CTL_TX_PAUSE_REQ, CTL_TX_PTP_VLANE_ADJUST_MODE, CTL_TX_RESEND_PAUSE, CTL_TX_SEND_IDLE, CTL_TX_SEND_RFI, CTL_TX_SYSTEMTIMERIN, CTL_TX_TEST_PATTERN, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN, DRP_WE, RX_CLK, RX_RESET, RX_SERDES_ALT_DATA0
|
|
, RX_SERDES_ALT_DATA1, RX_SERDES_ALT_DATA2, RX_SERDES_ALT_DATA3, RX_SERDES_CLK, RX_SERDES_DATA0, RX_SERDES_DATA1, RX_SERDES_DATA2, RX_SERDES_DATA3, RX_SERDES_DATA4, RX_SERDES_DATA5, RX_SERDES_DATA6, RX_SERDES_DATA7, RX_SERDES_DATA8, RX_SERDES_DATA9, RX_SERDES_RESET, TX_CLK, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0
|
|
, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1, TX_MTYIN2, TX_MTYIN3, TX_PTP_1588OP_IN, TX_PTP_CHKSUM_OFFSET_IN, TX_PTP_RXTSTAMP_IN, TX_PTP_TAG_FIELD_IN, TX_PTP_TSTAMP_OFFSET_IN, TX_PTP_UPD_CHKSUM_IN
|
|
, TX_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3);
|
|
parameter CTL_PTP_TRANSPCLK_MODE = "FALSE";
|
|
parameter CTL_RX_CHECK_ACK = "TRUE";
|
|
parameter CTL_RX_CHECK_PREAMBLE = "FALSE";
|
|
parameter CTL_RX_CHECK_SFD = "FALSE";
|
|
parameter CTL_RX_DELETE_FCS = "TRUE";
|
|
parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808;
|
|
parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808;
|
|
parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808;
|
|
parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808;
|
|
parameter CTL_RX_FORWARD_CONTROL = "FALSE";
|
|
parameter CTL_RX_IGNORE_FCS = "FALSE";
|
|
parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580;
|
|
parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40;
|
|
parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001;
|
|
parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF;
|
|
parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF;
|
|
parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000;
|
|
parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000;
|
|
parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001;
|
|
parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001;
|
|
parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000;
|
|
parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000;
|
|
parameter CTL_RX_PROCESS_LFI = "FALSE";
|
|
parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
|
|
parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
|
|
parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
|
|
parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001;
|
|
parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001;
|
|
parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808;
|
|
parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808;
|
|
parameter CTL_TX_FCS_INS_ENABLE = "TRUE";
|
|
parameter CTL_TX_IGNORE_FCS = "FALSE";
|
|
parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001;
|
|
parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001;
|
|
parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE";
|
|
parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1;
|
|
parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000;
|
|
parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000;
|
|
parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
|
|
parameter SIM_VERSION = "2.0";
|
|
parameter TEST_MODE_PIN_CHAR = "FALSE";
|
|
output [15:0] DRP_DO;
|
|
output DRP_RDY;
|
|
output [127:0] RX_DATAOUT0;
|
|
output [127:0] RX_DATAOUT1;
|
|
output [127:0] RX_DATAOUT2;
|
|
output [127:0] RX_DATAOUT3;
|
|
output RX_ENAOUT0;
|
|
output RX_ENAOUT1;
|
|
output RX_ENAOUT2;
|
|
output RX_ENAOUT3;
|
|
output RX_EOPOUT0;
|
|
output RX_EOPOUT1;
|
|
output RX_EOPOUT2;
|
|
output RX_EOPOUT3;
|
|
output RX_ERROUT0;
|
|
output RX_ERROUT1;
|
|
output RX_ERROUT2;
|
|
output RX_ERROUT3;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_0;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_1;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_10;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_11;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_12;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_13;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_14;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_15;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_16;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_17;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_18;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_19;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_2;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_3;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_4;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_5;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_6;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_7;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_8;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_9;
|
|
output [3:0] RX_MTYOUT0;
|
|
output [3:0] RX_MTYOUT1;
|
|
output [3:0] RX_MTYOUT2;
|
|
output [3:0] RX_MTYOUT3;
|
|
output [4:0] RX_PTP_PCSLANE_OUT;
|
|
output [79:0] RX_PTP_TSTAMP_OUT;
|
|
output RX_SOPOUT0;
|
|
output RX_SOPOUT1;
|
|
output RX_SOPOUT2;
|
|
output RX_SOPOUT3;
|
|
output STAT_RX_ALIGNED;
|
|
output STAT_RX_ALIGNED_ERR;
|
|
output [6:0] STAT_RX_BAD_CODE;
|
|
output [3:0] STAT_RX_BAD_FCS;
|
|
output STAT_RX_BAD_PREAMBLE;
|
|
output STAT_RX_BAD_SFD;
|
|
output STAT_RX_BIP_ERR_0;
|
|
output STAT_RX_BIP_ERR_1;
|
|
output STAT_RX_BIP_ERR_10;
|
|
output STAT_RX_BIP_ERR_11;
|
|
output STAT_RX_BIP_ERR_12;
|
|
output STAT_RX_BIP_ERR_13;
|
|
output STAT_RX_BIP_ERR_14;
|
|
output STAT_RX_BIP_ERR_15;
|
|
output STAT_RX_BIP_ERR_16;
|
|
output STAT_RX_BIP_ERR_17;
|
|
output STAT_RX_BIP_ERR_18;
|
|
output STAT_RX_BIP_ERR_19;
|
|
output STAT_RX_BIP_ERR_2;
|
|
output STAT_RX_BIP_ERR_3;
|
|
output STAT_RX_BIP_ERR_4;
|
|
output STAT_RX_BIP_ERR_5;
|
|
output STAT_RX_BIP_ERR_6;
|
|
output STAT_RX_BIP_ERR_7;
|
|
output STAT_RX_BIP_ERR_8;
|
|
output STAT_RX_BIP_ERR_9;
|
|
output [19:0] STAT_RX_BLOCK_LOCK;
|
|
output STAT_RX_BROADCAST;
|
|
output [3:0] STAT_RX_FRAGMENT;
|
|
output [3:0] STAT_RX_FRAMING_ERR_0;
|
|
output [3:0] STAT_RX_FRAMING_ERR_1;
|
|
output [3:0] STAT_RX_FRAMING_ERR_10;
|
|
output [3:0] STAT_RX_FRAMING_ERR_11;
|
|
output [3:0] STAT_RX_FRAMING_ERR_12;
|
|
output [3:0] STAT_RX_FRAMING_ERR_13;
|
|
output [3:0] STAT_RX_FRAMING_ERR_14;
|
|
output [3:0] STAT_RX_FRAMING_ERR_15;
|
|
output [3:0] STAT_RX_FRAMING_ERR_16;
|
|
output [3:0] STAT_RX_FRAMING_ERR_17;
|
|
output [3:0] STAT_RX_FRAMING_ERR_18;
|
|
output [3:0] STAT_RX_FRAMING_ERR_19;
|
|
output [3:0] STAT_RX_FRAMING_ERR_2;
|
|
output [3:0] STAT_RX_FRAMING_ERR_3;
|
|
output [3:0] STAT_RX_FRAMING_ERR_4;
|
|
output [3:0] STAT_RX_FRAMING_ERR_5;
|
|
output [3:0] STAT_RX_FRAMING_ERR_6;
|
|
output [3:0] STAT_RX_FRAMING_ERR_7;
|
|
output [3:0] STAT_RX_FRAMING_ERR_8;
|
|
output [3:0] STAT_RX_FRAMING_ERR_9;
|
|
output STAT_RX_FRAMING_ERR_VALID_0;
|
|
output STAT_RX_FRAMING_ERR_VALID_1;
|
|
output STAT_RX_FRAMING_ERR_VALID_10;
|
|
output STAT_RX_FRAMING_ERR_VALID_11;
|
|
output STAT_RX_FRAMING_ERR_VALID_12;
|
|
output STAT_RX_FRAMING_ERR_VALID_13;
|
|
output STAT_RX_FRAMING_ERR_VALID_14;
|
|
output STAT_RX_FRAMING_ERR_VALID_15;
|
|
output STAT_RX_FRAMING_ERR_VALID_16;
|
|
output STAT_RX_FRAMING_ERR_VALID_17;
|
|
output STAT_RX_FRAMING_ERR_VALID_18;
|
|
output STAT_RX_FRAMING_ERR_VALID_19;
|
|
output STAT_RX_FRAMING_ERR_VALID_2;
|
|
output STAT_RX_FRAMING_ERR_VALID_3;
|
|
output STAT_RX_FRAMING_ERR_VALID_4;
|
|
output STAT_RX_FRAMING_ERR_VALID_5;
|
|
output STAT_RX_FRAMING_ERR_VALID_6;
|
|
output STAT_RX_FRAMING_ERR_VALID_7;
|
|
output STAT_RX_FRAMING_ERR_VALID_8;
|
|
output STAT_RX_FRAMING_ERR_VALID_9;
|
|
output STAT_RX_GOT_SIGNAL_OS;
|
|
output STAT_RX_HI_BER;
|
|
output STAT_RX_INRANGEERR;
|
|
output STAT_RX_INTERNAL_LOCAL_FAULT;
|
|
output STAT_RX_JABBER;
|
|
output [7:0] STAT_RX_LANE0_VLM_BIP7;
|
|
output STAT_RX_LANE0_VLM_BIP7_VALID;
|
|
output STAT_RX_LOCAL_FAULT;
|
|
output [19:0] STAT_RX_MF_ERR;
|
|
output [19:0] STAT_RX_MF_LEN_ERR;
|
|
output [19:0] STAT_RX_MF_REPEAT_ERR;
|
|
output STAT_RX_MISALIGNED;
|
|
output STAT_RX_MULTICAST;
|
|
output STAT_RX_OVERSIZE;
|
|
output STAT_RX_PACKET_1024_1518_BYTES;
|
|
output STAT_RX_PACKET_128_255_BYTES;
|
|
output STAT_RX_PACKET_1519_1522_BYTES;
|
|
output STAT_RX_PACKET_1523_1548_BYTES;
|
|
output STAT_RX_PACKET_1549_2047_BYTES;
|
|
output STAT_RX_PACKET_2048_4095_BYTES;
|
|
output STAT_RX_PACKET_256_511_BYTES;
|
|
output STAT_RX_PACKET_4096_8191_BYTES;
|
|
output STAT_RX_PACKET_512_1023_BYTES;
|
|
output STAT_RX_PACKET_64_BYTES;
|
|
output STAT_RX_PACKET_65_127_BYTES;
|
|
output STAT_RX_PACKET_8192_9215_BYTES;
|
|
output STAT_RX_PACKET_BAD_FCS;
|
|
output STAT_RX_PACKET_LARGE;
|
|
output [3:0] STAT_RX_PACKET_SMALL;
|
|
output STAT_RX_PAUSE;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA0;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA1;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA2;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA3;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA4;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA5;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA6;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA7;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA8;
|
|
output [8:0] STAT_RX_PAUSE_REQ;
|
|
output [8:0] STAT_RX_PAUSE_VALID;
|
|
output STAT_RX_RECEIVED_LOCAL_FAULT;
|
|
output STAT_RX_REMOTE_FAULT;
|
|
output STAT_RX_STATUS;
|
|
output [3:0] STAT_RX_STOMPED_FCS;
|
|
output [19:0] STAT_RX_SYNCED;
|
|
output [19:0] STAT_RX_SYNCED_ERR;
|
|
output [2:0] STAT_RX_TEST_PATTERN_MISMATCH;
|
|
output STAT_RX_TOOLONG;
|
|
output [7:0] STAT_RX_TOTAL_BYTES;
|
|
output [13:0] STAT_RX_TOTAL_GOOD_BYTES;
|
|
output STAT_RX_TOTAL_GOOD_PACKETS;
|
|
output [3:0] STAT_RX_TOTAL_PACKETS;
|
|
output STAT_RX_TRUNCATED;
|
|
output [3:0] STAT_RX_UNDERSIZE;
|
|
output STAT_RX_UNICAST;
|
|
output STAT_RX_USER_PAUSE;
|
|
output STAT_RX_VLAN;
|
|
output [19:0] STAT_RX_VL_DEMUXED;
|
|
output [4:0] STAT_RX_VL_NUMBER_0;
|
|
output [4:0] STAT_RX_VL_NUMBER_1;
|
|
output [4:0] STAT_RX_VL_NUMBER_10;
|
|
output [4:0] STAT_RX_VL_NUMBER_11;
|
|
output [4:0] STAT_RX_VL_NUMBER_12;
|
|
output [4:0] STAT_RX_VL_NUMBER_13;
|
|
output [4:0] STAT_RX_VL_NUMBER_14;
|
|
output [4:0] STAT_RX_VL_NUMBER_15;
|
|
output [4:0] STAT_RX_VL_NUMBER_16;
|
|
output [4:0] STAT_RX_VL_NUMBER_17;
|
|
output [4:0] STAT_RX_VL_NUMBER_18;
|
|
output [4:0] STAT_RX_VL_NUMBER_19;
|
|
output [4:0] STAT_RX_VL_NUMBER_2;
|
|
output [4:0] STAT_RX_VL_NUMBER_3;
|
|
output [4:0] STAT_RX_VL_NUMBER_4;
|
|
output [4:0] STAT_RX_VL_NUMBER_5;
|
|
output [4:0] STAT_RX_VL_NUMBER_6;
|
|
output [4:0] STAT_RX_VL_NUMBER_7;
|
|
output [4:0] STAT_RX_VL_NUMBER_8;
|
|
output [4:0] STAT_RX_VL_NUMBER_9;
|
|
output STAT_TX_BAD_FCS;
|
|
output STAT_TX_BROADCAST;
|
|
output STAT_TX_FRAME_ERROR;
|
|
output STAT_TX_LOCAL_FAULT;
|
|
output STAT_TX_MULTICAST;
|
|
output STAT_TX_PACKET_1024_1518_BYTES;
|
|
output STAT_TX_PACKET_128_255_BYTES;
|
|
output STAT_TX_PACKET_1519_1522_BYTES;
|
|
output STAT_TX_PACKET_1523_1548_BYTES;
|
|
output STAT_TX_PACKET_1549_2047_BYTES;
|
|
output STAT_TX_PACKET_2048_4095_BYTES;
|
|
output STAT_TX_PACKET_256_511_BYTES;
|
|
output STAT_TX_PACKET_4096_8191_BYTES;
|
|
output STAT_TX_PACKET_512_1023_BYTES;
|
|
output STAT_TX_PACKET_64_BYTES;
|
|
output STAT_TX_PACKET_65_127_BYTES;
|
|
output STAT_TX_PACKET_8192_9215_BYTES;
|
|
output STAT_TX_PACKET_LARGE;
|
|
output STAT_TX_PACKET_SMALL;
|
|
output STAT_TX_PAUSE;
|
|
output [8:0] STAT_TX_PAUSE_VALID;
|
|
output STAT_TX_PTP_FIFO_READ_ERROR;
|
|
output STAT_TX_PTP_FIFO_WRITE_ERROR;
|
|
output [6:0] STAT_TX_TOTAL_BYTES;
|
|
output [13:0] STAT_TX_TOTAL_GOOD_BYTES;
|
|
output STAT_TX_TOTAL_GOOD_PACKETS;
|
|
output STAT_TX_TOTAL_PACKETS;
|
|
output STAT_TX_UNICAST;
|
|
output STAT_TX_USER_PAUSE;
|
|
output STAT_TX_VLAN;
|
|
output TX_OVFOUT;
|
|
output [4:0] TX_PTP_PCSLANE_OUT;
|
|
output [79:0] TX_PTP_TSTAMP_OUT;
|
|
output [15:0] TX_PTP_TSTAMP_TAG_OUT;
|
|
output TX_PTP_TSTAMP_VALID_OUT;
|
|
output TX_RDYOUT;
|
|
output [15:0] TX_SERDES_ALT_DATA0;
|
|
output [15:0] TX_SERDES_ALT_DATA1;
|
|
output [15:0] TX_SERDES_ALT_DATA2;
|
|
output [15:0] TX_SERDES_ALT_DATA3;
|
|
output [63:0] TX_SERDES_DATA0;
|
|
output [63:0] TX_SERDES_DATA1;
|
|
output [63:0] TX_SERDES_DATA2;
|
|
output [63:0] TX_SERDES_DATA3;
|
|
output [31:0] TX_SERDES_DATA4;
|
|
output [31:0] TX_SERDES_DATA5;
|
|
output [31:0] TX_SERDES_DATA6;
|
|
output [31:0] TX_SERDES_DATA7;
|
|
output [31:0] TX_SERDES_DATA8;
|
|
output [31:0] TX_SERDES_DATA9;
|
|
output TX_UNFOUT;
|
|
input CTL_CAUI4_MODE;
|
|
input CTL_RX_CHECK_ETYPE_GCP;
|
|
input CTL_RX_CHECK_ETYPE_GPP;
|
|
input CTL_RX_CHECK_ETYPE_PCP;
|
|
input CTL_RX_CHECK_ETYPE_PPP;
|
|
input CTL_RX_CHECK_MCAST_GCP;
|
|
input CTL_RX_CHECK_MCAST_GPP;
|
|
input CTL_RX_CHECK_MCAST_PCP;
|
|
input CTL_RX_CHECK_MCAST_PPP;
|
|
input CTL_RX_CHECK_OPCODE_GCP;
|
|
input CTL_RX_CHECK_OPCODE_GPP;
|
|
input CTL_RX_CHECK_OPCODE_PCP;
|
|
input CTL_RX_CHECK_OPCODE_PPP;
|
|
input CTL_RX_CHECK_SA_GCP;
|
|
input CTL_RX_CHECK_SA_GPP;
|
|
input CTL_RX_CHECK_SA_PCP;
|
|
input CTL_RX_CHECK_SA_PPP;
|
|
input CTL_RX_CHECK_UCAST_GCP;
|
|
input CTL_RX_CHECK_UCAST_GPP;
|
|
input CTL_RX_CHECK_UCAST_PCP;
|
|
input CTL_RX_CHECK_UCAST_PPP;
|
|
input CTL_RX_ENABLE;
|
|
input CTL_RX_ENABLE_GCP;
|
|
input CTL_RX_ENABLE_GPP;
|
|
input CTL_RX_ENABLE_PCP;
|
|
input CTL_RX_ENABLE_PPP;
|
|
input CTL_RX_FORCE_RESYNC;
|
|
input [8:0] CTL_RX_PAUSE_ACK;
|
|
input [8:0] CTL_RX_PAUSE_ENABLE;
|
|
input [79:0] CTL_RX_SYSTEMTIMERIN;
|
|
input CTL_RX_TEST_PATTERN;
|
|
input CTL_TX_ENABLE;
|
|
input CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
|
|
input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
|
|
input [8:0] CTL_TX_PAUSE_ENABLE;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA0;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA1;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA2;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA3;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA4;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA5;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA6;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA7;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA8;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8;
|
|
input [8:0] CTL_TX_PAUSE_REQ;
|
|
input CTL_TX_PTP_VLANE_ADJUST_MODE;
|
|
input CTL_TX_RESEND_PAUSE;
|
|
input CTL_TX_SEND_IDLE;
|
|
input CTL_TX_SEND_RFI;
|
|
input [79:0] CTL_TX_SYSTEMTIMERIN;
|
|
input CTL_TX_TEST_PATTERN;
|
|
input [9:0] DRP_ADDR;
|
|
input DRP_CLK;
|
|
input [15:0] DRP_DI;
|
|
input DRP_EN;
|
|
input DRP_WE;
|
|
input RX_CLK;
|
|
input RX_RESET;
|
|
input [15:0] RX_SERDES_ALT_DATA0;
|
|
input [15:0] RX_SERDES_ALT_DATA1;
|
|
input [15:0] RX_SERDES_ALT_DATA2;
|
|
input [15:0] RX_SERDES_ALT_DATA3;
|
|
input [9:0] RX_SERDES_CLK;
|
|
input [63:0] RX_SERDES_DATA0;
|
|
input [63:0] RX_SERDES_DATA1;
|
|
input [63:0] RX_SERDES_DATA2;
|
|
input [63:0] RX_SERDES_DATA3;
|
|
input [31:0] RX_SERDES_DATA4;
|
|
input [31:0] RX_SERDES_DATA5;
|
|
input [31:0] RX_SERDES_DATA6;
|
|
input [31:0] RX_SERDES_DATA7;
|
|
input [31:0] RX_SERDES_DATA8;
|
|
input [31:0] RX_SERDES_DATA9;
|
|
input [9:0] RX_SERDES_RESET;
|
|
input TX_CLK;
|
|
input [127:0] TX_DATAIN0;
|
|
input [127:0] TX_DATAIN1;
|
|
input [127:0] TX_DATAIN2;
|
|
input [127:0] TX_DATAIN3;
|
|
input TX_ENAIN0;
|
|
input TX_ENAIN1;
|
|
input TX_ENAIN2;
|
|
input TX_ENAIN3;
|
|
input TX_EOPIN0;
|
|
input TX_EOPIN1;
|
|
input TX_EOPIN2;
|
|
input TX_EOPIN3;
|
|
input TX_ERRIN0;
|
|
input TX_ERRIN1;
|
|
input TX_ERRIN2;
|
|
input TX_ERRIN3;
|
|
input [3:0] TX_MTYIN0;
|
|
input [3:0] TX_MTYIN1;
|
|
input [3:0] TX_MTYIN2;
|
|
input [3:0] TX_MTYIN3;
|
|
input [1:0] TX_PTP_1588OP_IN;
|
|
input [15:0] TX_PTP_CHKSUM_OFFSET_IN;
|
|
input [63:0] TX_PTP_RXTSTAMP_IN;
|
|
input [15:0] TX_PTP_TAG_FIELD_IN;
|
|
input [15:0] TX_PTP_TSTAMP_OFFSET_IN;
|
|
input TX_PTP_UPD_CHKSUM_IN;
|
|
input TX_RESET;
|
|
input TX_SOPIN0;
|
|
input TX_SOPIN1;
|
|
input TX_SOPIN2;
|
|
input TX_SOPIN3;
|
|
endmodule
|
|
|
|
module CMACE4(DRP_DO, DRP_RDY, RSFEC_BYPASS_RX_DOUT, RSFEC_BYPASS_RX_DOUT_CW_START, RSFEC_BYPASS_RX_DOUT_VALID, RSFEC_BYPASS_TX_DOUT, RSFEC_BYPASS_TX_DOUT_CW_START, RSFEC_BYPASS_TX_DOUT_VALID, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0
|
|
, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_LANE_ALIGNER_FILL_0, RX_LANE_ALIGNER_FILL_1, RX_LANE_ALIGNER_FILL_10, RX_LANE_ALIGNER_FILL_11, RX_LANE_ALIGNER_FILL_12, RX_LANE_ALIGNER_FILL_13, RX_LANE_ALIGNER_FILL_14, RX_LANE_ALIGNER_FILL_15, RX_LANE_ALIGNER_FILL_16, RX_LANE_ALIGNER_FILL_17, RX_LANE_ALIGNER_FILL_18, RX_LANE_ALIGNER_FILL_19, RX_LANE_ALIGNER_FILL_2, RX_LANE_ALIGNER_FILL_3, RX_LANE_ALIGNER_FILL_4, RX_LANE_ALIGNER_FILL_5, RX_LANE_ALIGNER_FILL_6, RX_LANE_ALIGNER_FILL_7
|
|
, RX_LANE_ALIGNER_FILL_8, RX_LANE_ALIGNER_FILL_9, RX_MTYOUT0, RX_MTYOUT1, RX_MTYOUT2, RX_MTYOUT3, RX_OTN_BIP8_0, RX_OTN_BIP8_1, RX_OTN_BIP8_2, RX_OTN_BIP8_3, RX_OTN_BIP8_4, RX_OTN_DATA_0, RX_OTN_DATA_1, RX_OTN_DATA_2, RX_OTN_DATA_3, RX_OTN_DATA_4, RX_OTN_ENA, RX_OTN_LANE0, RX_OTN_VLMARKER, RX_PREOUT, RX_PTP_PCSLANE_OUT
|
|
, RX_PTP_TSTAMP_OUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_CODE, STAT_RX_BAD_FCS, STAT_RX_BAD_PREAMBLE, STAT_RX_BAD_SFD, STAT_RX_BIP_ERR_0, STAT_RX_BIP_ERR_1, STAT_RX_BIP_ERR_10, STAT_RX_BIP_ERR_11, STAT_RX_BIP_ERR_12, STAT_RX_BIP_ERR_13, STAT_RX_BIP_ERR_14, STAT_RX_BIP_ERR_15, STAT_RX_BIP_ERR_16, STAT_RX_BIP_ERR_17
|
|
, STAT_RX_BIP_ERR_18, STAT_RX_BIP_ERR_19, STAT_RX_BIP_ERR_2, STAT_RX_BIP_ERR_3, STAT_RX_BIP_ERR_4, STAT_RX_BIP_ERR_5, STAT_RX_BIP_ERR_6, STAT_RX_BIP_ERR_7, STAT_RX_BIP_ERR_8, STAT_RX_BIP_ERR_9, STAT_RX_BLOCK_LOCK, STAT_RX_BROADCAST, STAT_RX_FRAGMENT, STAT_RX_FRAMING_ERR_0, STAT_RX_FRAMING_ERR_1, STAT_RX_FRAMING_ERR_10, STAT_RX_FRAMING_ERR_11, STAT_RX_FRAMING_ERR_12, STAT_RX_FRAMING_ERR_13, STAT_RX_FRAMING_ERR_14, STAT_RX_FRAMING_ERR_15
|
|
, STAT_RX_FRAMING_ERR_16, STAT_RX_FRAMING_ERR_17, STAT_RX_FRAMING_ERR_18, STAT_RX_FRAMING_ERR_19, STAT_RX_FRAMING_ERR_2, STAT_RX_FRAMING_ERR_3, STAT_RX_FRAMING_ERR_4, STAT_RX_FRAMING_ERR_5, STAT_RX_FRAMING_ERR_6, STAT_RX_FRAMING_ERR_7, STAT_RX_FRAMING_ERR_8, STAT_RX_FRAMING_ERR_9, STAT_RX_FRAMING_ERR_VALID_0, STAT_RX_FRAMING_ERR_VALID_1, STAT_RX_FRAMING_ERR_VALID_10, STAT_RX_FRAMING_ERR_VALID_11, STAT_RX_FRAMING_ERR_VALID_12, STAT_RX_FRAMING_ERR_VALID_13, STAT_RX_FRAMING_ERR_VALID_14, STAT_RX_FRAMING_ERR_VALID_15, STAT_RX_FRAMING_ERR_VALID_16
|
|
, STAT_RX_FRAMING_ERR_VALID_17, STAT_RX_FRAMING_ERR_VALID_18, STAT_RX_FRAMING_ERR_VALID_19, STAT_RX_FRAMING_ERR_VALID_2, STAT_RX_FRAMING_ERR_VALID_3, STAT_RX_FRAMING_ERR_VALID_4, STAT_RX_FRAMING_ERR_VALID_5, STAT_RX_FRAMING_ERR_VALID_6, STAT_RX_FRAMING_ERR_VALID_7, STAT_RX_FRAMING_ERR_VALID_8, STAT_RX_FRAMING_ERR_VALID_9, STAT_RX_GOT_SIGNAL_OS, STAT_RX_HI_BER, STAT_RX_INRANGEERR, STAT_RX_INTERNAL_LOCAL_FAULT, STAT_RX_JABBER, STAT_RX_LANE0_VLM_BIP7, STAT_RX_LANE0_VLM_BIP7_VALID, STAT_RX_LOCAL_FAULT, STAT_RX_MF_ERR, STAT_RX_MF_LEN_ERR
|
|
, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MULTICAST, STAT_RX_OVERSIZE, STAT_RX_PACKET_1024_1518_BYTES, STAT_RX_PACKET_128_255_BYTES, STAT_RX_PACKET_1519_1522_BYTES, STAT_RX_PACKET_1523_1548_BYTES, STAT_RX_PACKET_1549_2047_BYTES, STAT_RX_PACKET_2048_4095_BYTES, STAT_RX_PACKET_256_511_BYTES, STAT_RX_PACKET_4096_8191_BYTES, STAT_RX_PACKET_512_1023_BYTES, STAT_RX_PACKET_64_BYTES, STAT_RX_PACKET_65_127_BYTES, STAT_RX_PACKET_8192_9215_BYTES, STAT_RX_PACKET_BAD_FCS, STAT_RX_PACKET_LARGE, STAT_RX_PACKET_SMALL, STAT_RX_PAUSE, STAT_RX_PAUSE_QUANTA0
|
|
, STAT_RX_PAUSE_QUANTA1, STAT_RX_PAUSE_QUANTA2, STAT_RX_PAUSE_QUANTA3, STAT_RX_PAUSE_QUANTA4, STAT_RX_PAUSE_QUANTA5, STAT_RX_PAUSE_QUANTA6, STAT_RX_PAUSE_QUANTA7, STAT_RX_PAUSE_QUANTA8, STAT_RX_PAUSE_REQ, STAT_RX_PAUSE_VALID, STAT_RX_RECEIVED_LOCAL_FAULT, STAT_RX_REMOTE_FAULT, STAT_RX_RSFEC_AM_LOCK0, STAT_RX_RSFEC_AM_LOCK1, STAT_RX_RSFEC_AM_LOCK2, STAT_RX_RSFEC_AM_LOCK3, STAT_RX_RSFEC_CORRECTED_CW_INC, STAT_RX_RSFEC_CW_INC, STAT_RX_RSFEC_ERR_COUNT0_INC, STAT_RX_RSFEC_ERR_COUNT1_INC, STAT_RX_RSFEC_ERR_COUNT2_INC
|
|
, STAT_RX_RSFEC_ERR_COUNT3_INC, STAT_RX_RSFEC_HI_SER, STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS, STAT_RX_RSFEC_LANE_FILL_0, STAT_RX_RSFEC_LANE_FILL_1, STAT_RX_RSFEC_LANE_FILL_2, STAT_RX_RSFEC_LANE_FILL_3, STAT_RX_RSFEC_LANE_MAPPING, STAT_RX_RSFEC_RSVD, STAT_RX_RSFEC_UNCORRECTED_CW_INC, STAT_RX_STATUS, STAT_RX_STOMPED_FCS, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR, STAT_RX_TEST_PATTERN_MISMATCH, STAT_RX_TOOLONG, STAT_RX_TOTAL_BYTES, STAT_RX_TOTAL_GOOD_BYTES, STAT_RX_TOTAL_GOOD_PACKETS, STAT_RX_TOTAL_PACKETS, STAT_RX_TRUNCATED
|
|
, STAT_RX_UNDERSIZE, STAT_RX_UNICAST, STAT_RX_USER_PAUSE, STAT_RX_VLAN, STAT_RX_VL_DEMUXED, STAT_RX_VL_NUMBER_0, STAT_RX_VL_NUMBER_1, STAT_RX_VL_NUMBER_10, STAT_RX_VL_NUMBER_11, STAT_RX_VL_NUMBER_12, STAT_RX_VL_NUMBER_13, STAT_RX_VL_NUMBER_14, STAT_RX_VL_NUMBER_15, STAT_RX_VL_NUMBER_16, STAT_RX_VL_NUMBER_17, STAT_RX_VL_NUMBER_18, STAT_RX_VL_NUMBER_19, STAT_RX_VL_NUMBER_2, STAT_RX_VL_NUMBER_3, STAT_RX_VL_NUMBER_4, STAT_RX_VL_NUMBER_5
|
|
, STAT_RX_VL_NUMBER_6, STAT_RX_VL_NUMBER_7, STAT_RX_VL_NUMBER_8, STAT_RX_VL_NUMBER_9, STAT_TX_BAD_FCS, STAT_TX_BROADCAST, STAT_TX_FRAME_ERROR, STAT_TX_LOCAL_FAULT, STAT_TX_MULTICAST, STAT_TX_PACKET_1024_1518_BYTES, STAT_TX_PACKET_128_255_BYTES, STAT_TX_PACKET_1519_1522_BYTES, STAT_TX_PACKET_1523_1548_BYTES, STAT_TX_PACKET_1549_2047_BYTES, STAT_TX_PACKET_2048_4095_BYTES, STAT_TX_PACKET_256_511_BYTES, STAT_TX_PACKET_4096_8191_BYTES, STAT_TX_PACKET_512_1023_BYTES, STAT_TX_PACKET_64_BYTES, STAT_TX_PACKET_65_127_BYTES, STAT_TX_PACKET_8192_9215_BYTES
|
|
, STAT_TX_PACKET_LARGE, STAT_TX_PACKET_SMALL, STAT_TX_PAUSE, STAT_TX_PAUSE_VALID, STAT_TX_PTP_FIFO_READ_ERROR, STAT_TX_PTP_FIFO_WRITE_ERROR, STAT_TX_TOTAL_BYTES, STAT_TX_TOTAL_GOOD_BYTES, STAT_TX_TOTAL_GOOD_PACKETS, STAT_TX_TOTAL_PACKETS, STAT_TX_UNICAST, STAT_TX_USER_PAUSE, STAT_TX_VLAN, TX_OVFOUT, TX_PTP_PCSLANE_OUT, TX_PTP_TSTAMP_OUT, TX_PTP_TSTAMP_TAG_OUT, TX_PTP_TSTAMP_VALID_OUT, TX_RDYOUT, TX_SERDES_ALT_DATA0, TX_SERDES_ALT_DATA1
|
|
, TX_SERDES_ALT_DATA2, TX_SERDES_ALT_DATA3, TX_SERDES_DATA0, TX_SERDES_DATA1, TX_SERDES_DATA2, TX_SERDES_DATA3, TX_SERDES_DATA4, TX_SERDES_DATA5, TX_SERDES_DATA6, TX_SERDES_DATA7, TX_SERDES_DATA8, TX_SERDES_DATA9, TX_UNFOUT, CTL_CAUI4_MODE, CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE, CTL_RSFEC_IEEE_ERROR_INDICATION_MODE, CTL_RX_CHECK_ETYPE_GCP, CTL_RX_CHECK_ETYPE_GPP, CTL_RX_CHECK_ETYPE_PCP, CTL_RX_CHECK_ETYPE_PPP, CTL_RX_CHECK_MCAST_GCP
|
|
, CTL_RX_CHECK_MCAST_GPP, CTL_RX_CHECK_MCAST_PCP, CTL_RX_CHECK_MCAST_PPP, CTL_RX_CHECK_OPCODE_GCP, CTL_RX_CHECK_OPCODE_GPP, CTL_RX_CHECK_OPCODE_PCP, CTL_RX_CHECK_OPCODE_PPP, CTL_RX_CHECK_SA_GCP, CTL_RX_CHECK_SA_GPP, CTL_RX_CHECK_SA_PCP, CTL_RX_CHECK_SA_PPP, CTL_RX_CHECK_UCAST_GCP, CTL_RX_CHECK_UCAST_GPP, CTL_RX_CHECK_UCAST_PCP, CTL_RX_CHECK_UCAST_PPP, CTL_RX_ENABLE, CTL_RX_ENABLE_GCP, CTL_RX_ENABLE_GPP, CTL_RX_ENABLE_PCP, CTL_RX_ENABLE_PPP, CTL_RX_FORCE_RESYNC
|
|
, CTL_RX_PAUSE_ACK, CTL_RX_PAUSE_ENABLE, CTL_RX_RSFEC_ENABLE, CTL_RX_RSFEC_ENABLE_CORRECTION, CTL_RX_RSFEC_ENABLE_INDICATION, CTL_RX_SYSTEMTIMERIN, CTL_RX_TEST_PATTERN, CTL_TX_ENABLE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE, CTL_TX_PAUSE_ENABLE, CTL_TX_PAUSE_QUANTA0, CTL_TX_PAUSE_QUANTA1, CTL_TX_PAUSE_QUANTA2, CTL_TX_PAUSE_QUANTA3, CTL_TX_PAUSE_QUANTA4, CTL_TX_PAUSE_QUANTA5, CTL_TX_PAUSE_QUANTA6, CTL_TX_PAUSE_QUANTA7, CTL_TX_PAUSE_QUANTA8, CTL_TX_PAUSE_REFRESH_TIMER0
|
|
, CTL_TX_PAUSE_REFRESH_TIMER1, CTL_TX_PAUSE_REFRESH_TIMER2, CTL_TX_PAUSE_REFRESH_TIMER3, CTL_TX_PAUSE_REFRESH_TIMER4, CTL_TX_PAUSE_REFRESH_TIMER5, CTL_TX_PAUSE_REFRESH_TIMER6, CTL_TX_PAUSE_REFRESH_TIMER7, CTL_TX_PAUSE_REFRESH_TIMER8, CTL_TX_PAUSE_REQ, CTL_TX_PTP_VLANE_ADJUST_MODE, CTL_TX_RESEND_PAUSE, CTL_TX_RSFEC_ENABLE, CTL_TX_SEND_IDLE, CTL_TX_SEND_LFI, CTL_TX_SEND_RFI, CTL_TX_SYSTEMTIMERIN, CTL_TX_TEST_PATTERN, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN
|
|
, DRP_WE, RSFEC_BYPASS_RX_DIN, RSFEC_BYPASS_RX_DIN_CW_START, RSFEC_BYPASS_TX_DIN, RSFEC_BYPASS_TX_DIN_CW_START, RX_CLK, RX_RESET, RX_SERDES_ALT_DATA0, RX_SERDES_ALT_DATA1, RX_SERDES_ALT_DATA2, RX_SERDES_ALT_DATA3, RX_SERDES_CLK, RX_SERDES_DATA0, RX_SERDES_DATA1, RX_SERDES_DATA2, RX_SERDES_DATA3, RX_SERDES_DATA4, RX_SERDES_DATA5, RX_SERDES_DATA6, RX_SERDES_DATA7, RX_SERDES_DATA8
|
|
, RX_SERDES_DATA9, RX_SERDES_RESET, TX_CLK, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1
|
|
, TX_MTYIN2, TX_MTYIN3, TX_PREIN, TX_PTP_1588OP_IN, TX_PTP_CHKSUM_OFFSET_IN, TX_PTP_RXTSTAMP_IN, TX_PTP_TAG_FIELD_IN, TX_PTP_TSTAMP_OFFSET_IN, TX_PTP_UPD_CHKSUM_IN, TX_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3);
|
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parameter CTL_PTP_TRANSPCLK_MODE = "FALSE";
|
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parameter CTL_RX_CHECK_ACK = "TRUE";
|
|
parameter CTL_RX_CHECK_PREAMBLE = "FALSE";
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|
parameter CTL_RX_CHECK_SFD = "FALSE";
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|
parameter CTL_RX_DELETE_FCS = "TRUE";
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|
parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808;
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|
parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808;
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parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808;
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parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808;
|
|
parameter CTL_RX_FORWARD_CONTROL = "FALSE";
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|
parameter CTL_RX_IGNORE_FCS = "FALSE";
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parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580;
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parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40;
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parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001;
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parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF;
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parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF;
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parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000;
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parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000;
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parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001;
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parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001;
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parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000;
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parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000;
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parameter CTL_RX_PROCESS_LFI = "FALSE";
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parameter [8:0] CTL_RX_RSFEC_AM_THRESHOLD = 9'h046;
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parameter [1:0] CTL_RX_RSFEC_FILL_ADJUST = 2'h0;
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parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF;
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parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
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parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
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parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600;
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parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
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parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
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parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
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parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
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parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
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parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
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parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800;
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parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
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parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
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parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
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parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
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parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
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parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
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parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
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parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
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parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
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parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
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parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
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parameter CTL_TX_CUSTOM_PREAMBLE_ENABLE = "FALSE";
|
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parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001;
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|
parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001;
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parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808;
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|
parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808;
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|
parameter CTL_TX_FCS_INS_ENABLE = "TRUE";
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|
parameter CTL_TX_IGNORE_FCS = "FALSE";
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|
parameter [3:0] CTL_TX_IPG_VALUE = 4'hC;
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|
parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001;
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parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001;
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parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE";
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parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1;
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|
parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000;
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|
parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000;
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parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00;
|
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parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100;
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|
parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00;
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|
parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900;
|
|
parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter TEST_MODE_PIN_CHAR = "FALSE";
|
|
output [15:0] DRP_DO;
|
|
output DRP_RDY;
|
|
output [329:0] RSFEC_BYPASS_RX_DOUT;
|
|
output RSFEC_BYPASS_RX_DOUT_CW_START;
|
|
output RSFEC_BYPASS_RX_DOUT_VALID;
|
|
output [329:0] RSFEC_BYPASS_TX_DOUT;
|
|
output RSFEC_BYPASS_TX_DOUT_CW_START;
|
|
output RSFEC_BYPASS_TX_DOUT_VALID;
|
|
output [127:0] RX_DATAOUT0;
|
|
output [127:0] RX_DATAOUT1;
|
|
output [127:0] RX_DATAOUT2;
|
|
output [127:0] RX_DATAOUT3;
|
|
output RX_ENAOUT0;
|
|
output RX_ENAOUT1;
|
|
output RX_ENAOUT2;
|
|
output RX_ENAOUT3;
|
|
output RX_EOPOUT0;
|
|
output RX_EOPOUT1;
|
|
output RX_EOPOUT2;
|
|
output RX_EOPOUT3;
|
|
output RX_ERROUT0;
|
|
output RX_ERROUT1;
|
|
output RX_ERROUT2;
|
|
output RX_ERROUT3;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_0;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_1;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_10;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_11;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_12;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_13;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_14;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_15;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_16;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_17;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_18;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_19;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_2;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_3;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_4;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_5;
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|
output [6:0] RX_LANE_ALIGNER_FILL_6;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_7;
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|
output [6:0] RX_LANE_ALIGNER_FILL_8;
|
|
output [6:0] RX_LANE_ALIGNER_FILL_9;
|
|
output [3:0] RX_MTYOUT0;
|
|
output [3:0] RX_MTYOUT1;
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|
output [3:0] RX_MTYOUT2;
|
|
output [3:0] RX_MTYOUT3;
|
|
output [7:0] RX_OTN_BIP8_0;
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|
output [7:0] RX_OTN_BIP8_1;
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|
output [7:0] RX_OTN_BIP8_2;
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|
output [7:0] RX_OTN_BIP8_3;
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|
output [7:0] RX_OTN_BIP8_4;
|
|
output [65:0] RX_OTN_DATA_0;
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|
output [65:0] RX_OTN_DATA_1;
|
|
output [65:0] RX_OTN_DATA_2;
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|
output [65:0] RX_OTN_DATA_3;
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|
output [65:0] RX_OTN_DATA_4;
|
|
output RX_OTN_ENA;
|
|
output RX_OTN_LANE0;
|
|
output RX_OTN_VLMARKER;
|
|
output [55:0] RX_PREOUT;
|
|
output [4:0] RX_PTP_PCSLANE_OUT;
|
|
output [79:0] RX_PTP_TSTAMP_OUT;
|
|
output RX_SOPOUT0;
|
|
output RX_SOPOUT1;
|
|
output RX_SOPOUT2;
|
|
output RX_SOPOUT3;
|
|
output STAT_RX_ALIGNED;
|
|
output STAT_RX_ALIGNED_ERR;
|
|
output [2:0] STAT_RX_BAD_CODE;
|
|
output [2:0] STAT_RX_BAD_FCS;
|
|
output STAT_RX_BAD_PREAMBLE;
|
|
output STAT_RX_BAD_SFD;
|
|
output STAT_RX_BIP_ERR_0;
|
|
output STAT_RX_BIP_ERR_1;
|
|
output STAT_RX_BIP_ERR_10;
|
|
output STAT_RX_BIP_ERR_11;
|
|
output STAT_RX_BIP_ERR_12;
|
|
output STAT_RX_BIP_ERR_13;
|
|
output STAT_RX_BIP_ERR_14;
|
|
output STAT_RX_BIP_ERR_15;
|
|
output STAT_RX_BIP_ERR_16;
|
|
output STAT_RX_BIP_ERR_17;
|
|
output STAT_RX_BIP_ERR_18;
|
|
output STAT_RX_BIP_ERR_19;
|
|
output STAT_RX_BIP_ERR_2;
|
|
output STAT_RX_BIP_ERR_3;
|
|
output STAT_RX_BIP_ERR_4;
|
|
output STAT_RX_BIP_ERR_5;
|
|
output STAT_RX_BIP_ERR_6;
|
|
output STAT_RX_BIP_ERR_7;
|
|
output STAT_RX_BIP_ERR_8;
|
|
output STAT_RX_BIP_ERR_9;
|
|
output [19:0] STAT_RX_BLOCK_LOCK;
|
|
output STAT_RX_BROADCAST;
|
|
output [2:0] STAT_RX_FRAGMENT;
|
|
output [1:0] STAT_RX_FRAMING_ERR_0;
|
|
output [1:0] STAT_RX_FRAMING_ERR_1;
|
|
output [1:0] STAT_RX_FRAMING_ERR_10;
|
|
output [1:0] STAT_RX_FRAMING_ERR_11;
|
|
output [1:0] STAT_RX_FRAMING_ERR_12;
|
|
output [1:0] STAT_RX_FRAMING_ERR_13;
|
|
output [1:0] STAT_RX_FRAMING_ERR_14;
|
|
output [1:0] STAT_RX_FRAMING_ERR_15;
|
|
output [1:0] STAT_RX_FRAMING_ERR_16;
|
|
output [1:0] STAT_RX_FRAMING_ERR_17;
|
|
output [1:0] STAT_RX_FRAMING_ERR_18;
|
|
output [1:0] STAT_RX_FRAMING_ERR_19;
|
|
output [1:0] STAT_RX_FRAMING_ERR_2;
|
|
output [1:0] STAT_RX_FRAMING_ERR_3;
|
|
output [1:0] STAT_RX_FRAMING_ERR_4;
|
|
output [1:0] STAT_RX_FRAMING_ERR_5;
|
|
output [1:0] STAT_RX_FRAMING_ERR_6;
|
|
output [1:0] STAT_RX_FRAMING_ERR_7;
|
|
output [1:0] STAT_RX_FRAMING_ERR_8;
|
|
output [1:0] STAT_RX_FRAMING_ERR_9;
|
|
output STAT_RX_FRAMING_ERR_VALID_0;
|
|
output STAT_RX_FRAMING_ERR_VALID_1;
|
|
output STAT_RX_FRAMING_ERR_VALID_10;
|
|
output STAT_RX_FRAMING_ERR_VALID_11;
|
|
output STAT_RX_FRAMING_ERR_VALID_12;
|
|
output STAT_RX_FRAMING_ERR_VALID_13;
|
|
output STAT_RX_FRAMING_ERR_VALID_14;
|
|
output STAT_RX_FRAMING_ERR_VALID_15;
|
|
output STAT_RX_FRAMING_ERR_VALID_16;
|
|
output STAT_RX_FRAMING_ERR_VALID_17;
|
|
output STAT_RX_FRAMING_ERR_VALID_18;
|
|
output STAT_RX_FRAMING_ERR_VALID_19;
|
|
output STAT_RX_FRAMING_ERR_VALID_2;
|
|
output STAT_RX_FRAMING_ERR_VALID_3;
|
|
output STAT_RX_FRAMING_ERR_VALID_4;
|
|
output STAT_RX_FRAMING_ERR_VALID_5;
|
|
output STAT_RX_FRAMING_ERR_VALID_6;
|
|
output STAT_RX_FRAMING_ERR_VALID_7;
|
|
output STAT_RX_FRAMING_ERR_VALID_8;
|
|
output STAT_RX_FRAMING_ERR_VALID_9;
|
|
output STAT_RX_GOT_SIGNAL_OS;
|
|
output STAT_RX_HI_BER;
|
|
output STAT_RX_INRANGEERR;
|
|
output STAT_RX_INTERNAL_LOCAL_FAULT;
|
|
output STAT_RX_JABBER;
|
|
output [7:0] STAT_RX_LANE0_VLM_BIP7;
|
|
output STAT_RX_LANE0_VLM_BIP7_VALID;
|
|
output STAT_RX_LOCAL_FAULT;
|
|
output [19:0] STAT_RX_MF_ERR;
|
|
output [19:0] STAT_RX_MF_LEN_ERR;
|
|
output [19:0] STAT_RX_MF_REPEAT_ERR;
|
|
output STAT_RX_MISALIGNED;
|
|
output STAT_RX_MULTICAST;
|
|
output STAT_RX_OVERSIZE;
|
|
output STAT_RX_PACKET_1024_1518_BYTES;
|
|
output STAT_RX_PACKET_128_255_BYTES;
|
|
output STAT_RX_PACKET_1519_1522_BYTES;
|
|
output STAT_RX_PACKET_1523_1548_BYTES;
|
|
output STAT_RX_PACKET_1549_2047_BYTES;
|
|
output STAT_RX_PACKET_2048_4095_BYTES;
|
|
output STAT_RX_PACKET_256_511_BYTES;
|
|
output STAT_RX_PACKET_4096_8191_BYTES;
|
|
output STAT_RX_PACKET_512_1023_BYTES;
|
|
output STAT_RX_PACKET_64_BYTES;
|
|
output STAT_RX_PACKET_65_127_BYTES;
|
|
output STAT_RX_PACKET_8192_9215_BYTES;
|
|
output STAT_RX_PACKET_BAD_FCS;
|
|
output STAT_RX_PACKET_LARGE;
|
|
output [2:0] STAT_RX_PACKET_SMALL;
|
|
output STAT_RX_PAUSE;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA0;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA1;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA2;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA3;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA4;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA5;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA6;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA7;
|
|
output [15:0] STAT_RX_PAUSE_QUANTA8;
|
|
output [8:0] STAT_RX_PAUSE_REQ;
|
|
output [8:0] STAT_RX_PAUSE_VALID;
|
|
output STAT_RX_RECEIVED_LOCAL_FAULT;
|
|
output STAT_RX_REMOTE_FAULT;
|
|
output STAT_RX_RSFEC_AM_LOCK0;
|
|
output STAT_RX_RSFEC_AM_LOCK1;
|
|
output STAT_RX_RSFEC_AM_LOCK2;
|
|
output STAT_RX_RSFEC_AM_LOCK3;
|
|
output STAT_RX_RSFEC_CORRECTED_CW_INC;
|
|
output STAT_RX_RSFEC_CW_INC;
|
|
output [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC;
|
|
output [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC;
|
|
output [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC;
|
|
output [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC;
|
|
output STAT_RX_RSFEC_HI_SER;
|
|
output STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS;
|
|
output [13:0] STAT_RX_RSFEC_LANE_FILL_0;
|
|
output [13:0] STAT_RX_RSFEC_LANE_FILL_1;
|
|
output [13:0] STAT_RX_RSFEC_LANE_FILL_2;
|
|
output [13:0] STAT_RX_RSFEC_LANE_FILL_3;
|
|
output [7:0] STAT_RX_RSFEC_LANE_MAPPING;
|
|
output [31:0] STAT_RX_RSFEC_RSVD;
|
|
output STAT_RX_RSFEC_UNCORRECTED_CW_INC;
|
|
output STAT_RX_STATUS;
|
|
output [2:0] STAT_RX_STOMPED_FCS;
|
|
output [19:0] STAT_RX_SYNCED;
|
|
output [19:0] STAT_RX_SYNCED_ERR;
|
|
output [2:0] STAT_RX_TEST_PATTERN_MISMATCH;
|
|
output STAT_RX_TOOLONG;
|
|
output [6:0] STAT_RX_TOTAL_BYTES;
|
|
output [13:0] STAT_RX_TOTAL_GOOD_BYTES;
|
|
output STAT_RX_TOTAL_GOOD_PACKETS;
|
|
output [2:0] STAT_RX_TOTAL_PACKETS;
|
|
output STAT_RX_TRUNCATED;
|
|
output [2:0] STAT_RX_UNDERSIZE;
|
|
output STAT_RX_UNICAST;
|
|
output STAT_RX_USER_PAUSE;
|
|
output STAT_RX_VLAN;
|
|
output [19:0] STAT_RX_VL_DEMUXED;
|
|
output [4:0] STAT_RX_VL_NUMBER_0;
|
|
output [4:0] STAT_RX_VL_NUMBER_1;
|
|
output [4:0] STAT_RX_VL_NUMBER_10;
|
|
output [4:0] STAT_RX_VL_NUMBER_11;
|
|
output [4:0] STAT_RX_VL_NUMBER_12;
|
|
output [4:0] STAT_RX_VL_NUMBER_13;
|
|
output [4:0] STAT_RX_VL_NUMBER_14;
|
|
output [4:0] STAT_RX_VL_NUMBER_15;
|
|
output [4:0] STAT_RX_VL_NUMBER_16;
|
|
output [4:0] STAT_RX_VL_NUMBER_17;
|
|
output [4:0] STAT_RX_VL_NUMBER_18;
|
|
output [4:0] STAT_RX_VL_NUMBER_19;
|
|
output [4:0] STAT_RX_VL_NUMBER_2;
|
|
output [4:0] STAT_RX_VL_NUMBER_3;
|
|
output [4:0] STAT_RX_VL_NUMBER_4;
|
|
output [4:0] STAT_RX_VL_NUMBER_5;
|
|
output [4:0] STAT_RX_VL_NUMBER_6;
|
|
output [4:0] STAT_RX_VL_NUMBER_7;
|
|
output [4:0] STAT_RX_VL_NUMBER_8;
|
|
output [4:0] STAT_RX_VL_NUMBER_9;
|
|
output STAT_TX_BAD_FCS;
|
|
output STAT_TX_BROADCAST;
|
|
output STAT_TX_FRAME_ERROR;
|
|
output STAT_TX_LOCAL_FAULT;
|
|
output STAT_TX_MULTICAST;
|
|
output STAT_TX_PACKET_1024_1518_BYTES;
|
|
output STAT_TX_PACKET_128_255_BYTES;
|
|
output STAT_TX_PACKET_1519_1522_BYTES;
|
|
output STAT_TX_PACKET_1523_1548_BYTES;
|
|
output STAT_TX_PACKET_1549_2047_BYTES;
|
|
output STAT_TX_PACKET_2048_4095_BYTES;
|
|
output STAT_TX_PACKET_256_511_BYTES;
|
|
output STAT_TX_PACKET_4096_8191_BYTES;
|
|
output STAT_TX_PACKET_512_1023_BYTES;
|
|
output STAT_TX_PACKET_64_BYTES;
|
|
output STAT_TX_PACKET_65_127_BYTES;
|
|
output STAT_TX_PACKET_8192_9215_BYTES;
|
|
output STAT_TX_PACKET_LARGE;
|
|
output STAT_TX_PACKET_SMALL;
|
|
output STAT_TX_PAUSE;
|
|
output [8:0] STAT_TX_PAUSE_VALID;
|
|
output STAT_TX_PTP_FIFO_READ_ERROR;
|
|
output STAT_TX_PTP_FIFO_WRITE_ERROR;
|
|
output [5:0] STAT_TX_TOTAL_BYTES;
|
|
output [13:0] STAT_TX_TOTAL_GOOD_BYTES;
|
|
output STAT_TX_TOTAL_GOOD_PACKETS;
|
|
output STAT_TX_TOTAL_PACKETS;
|
|
output STAT_TX_UNICAST;
|
|
output STAT_TX_USER_PAUSE;
|
|
output STAT_TX_VLAN;
|
|
output TX_OVFOUT;
|
|
output [4:0] TX_PTP_PCSLANE_OUT;
|
|
output [79:0] TX_PTP_TSTAMP_OUT;
|
|
output [15:0] TX_PTP_TSTAMP_TAG_OUT;
|
|
output TX_PTP_TSTAMP_VALID_OUT;
|
|
output TX_RDYOUT;
|
|
output [15:0] TX_SERDES_ALT_DATA0;
|
|
output [15:0] TX_SERDES_ALT_DATA1;
|
|
output [15:0] TX_SERDES_ALT_DATA2;
|
|
output [15:0] TX_SERDES_ALT_DATA3;
|
|
output [63:0] TX_SERDES_DATA0;
|
|
output [63:0] TX_SERDES_DATA1;
|
|
output [63:0] TX_SERDES_DATA2;
|
|
output [63:0] TX_SERDES_DATA3;
|
|
output [31:0] TX_SERDES_DATA4;
|
|
output [31:0] TX_SERDES_DATA5;
|
|
output [31:0] TX_SERDES_DATA6;
|
|
output [31:0] TX_SERDES_DATA7;
|
|
output [31:0] TX_SERDES_DATA8;
|
|
output [31:0] TX_SERDES_DATA9;
|
|
output TX_UNFOUT;
|
|
input CTL_CAUI4_MODE;
|
|
input CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE;
|
|
input CTL_RSFEC_IEEE_ERROR_INDICATION_MODE;
|
|
input CTL_RX_CHECK_ETYPE_GCP;
|
|
input CTL_RX_CHECK_ETYPE_GPP;
|
|
input CTL_RX_CHECK_ETYPE_PCP;
|
|
input CTL_RX_CHECK_ETYPE_PPP;
|
|
input CTL_RX_CHECK_MCAST_GCP;
|
|
input CTL_RX_CHECK_MCAST_GPP;
|
|
input CTL_RX_CHECK_MCAST_PCP;
|
|
input CTL_RX_CHECK_MCAST_PPP;
|
|
input CTL_RX_CHECK_OPCODE_GCP;
|
|
input CTL_RX_CHECK_OPCODE_GPP;
|
|
input CTL_RX_CHECK_OPCODE_PCP;
|
|
input CTL_RX_CHECK_OPCODE_PPP;
|
|
input CTL_RX_CHECK_SA_GCP;
|
|
input CTL_RX_CHECK_SA_GPP;
|
|
input CTL_RX_CHECK_SA_PCP;
|
|
input CTL_RX_CHECK_SA_PPP;
|
|
input CTL_RX_CHECK_UCAST_GCP;
|
|
input CTL_RX_CHECK_UCAST_GPP;
|
|
input CTL_RX_CHECK_UCAST_PCP;
|
|
input CTL_RX_CHECK_UCAST_PPP;
|
|
input CTL_RX_ENABLE;
|
|
input CTL_RX_ENABLE_GCP;
|
|
input CTL_RX_ENABLE_GPP;
|
|
input CTL_RX_ENABLE_PCP;
|
|
input CTL_RX_ENABLE_PPP;
|
|
input CTL_RX_FORCE_RESYNC;
|
|
input [8:0] CTL_RX_PAUSE_ACK;
|
|
input [8:0] CTL_RX_PAUSE_ENABLE;
|
|
input CTL_RX_RSFEC_ENABLE;
|
|
input CTL_RX_RSFEC_ENABLE_CORRECTION;
|
|
input CTL_RX_RSFEC_ENABLE_INDICATION;
|
|
input [79:0] CTL_RX_SYSTEMTIMERIN;
|
|
input CTL_RX_TEST_PATTERN;
|
|
input CTL_TX_ENABLE;
|
|
input CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
|
|
input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
|
|
input [8:0] CTL_TX_PAUSE_ENABLE;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA0;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA1;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA2;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA3;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA4;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA5;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA6;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA7;
|
|
input [15:0] CTL_TX_PAUSE_QUANTA8;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7;
|
|
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8;
|
|
input [8:0] CTL_TX_PAUSE_REQ;
|
|
input CTL_TX_PTP_VLANE_ADJUST_MODE;
|
|
input CTL_TX_RESEND_PAUSE;
|
|
input CTL_TX_RSFEC_ENABLE;
|
|
input CTL_TX_SEND_IDLE;
|
|
input CTL_TX_SEND_LFI;
|
|
input CTL_TX_SEND_RFI;
|
|
input [79:0] CTL_TX_SYSTEMTIMERIN;
|
|
input CTL_TX_TEST_PATTERN;
|
|
input [9:0] DRP_ADDR;
|
|
input DRP_CLK;
|
|
input [15:0] DRP_DI;
|
|
input DRP_EN;
|
|
input DRP_WE;
|
|
input [329:0] RSFEC_BYPASS_RX_DIN;
|
|
input RSFEC_BYPASS_RX_DIN_CW_START;
|
|
input [329:0] RSFEC_BYPASS_TX_DIN;
|
|
input RSFEC_BYPASS_TX_DIN_CW_START;
|
|
input RX_CLK;
|
|
input RX_RESET;
|
|
input [15:0] RX_SERDES_ALT_DATA0;
|
|
input [15:0] RX_SERDES_ALT_DATA1;
|
|
input [15:0] RX_SERDES_ALT_DATA2;
|
|
input [15:0] RX_SERDES_ALT_DATA3;
|
|
input [9:0] RX_SERDES_CLK;
|
|
input [63:0] RX_SERDES_DATA0;
|
|
input [63:0] RX_SERDES_DATA1;
|
|
input [63:0] RX_SERDES_DATA2;
|
|
input [63:0] RX_SERDES_DATA3;
|
|
input [31:0] RX_SERDES_DATA4;
|
|
input [31:0] RX_SERDES_DATA5;
|
|
input [31:0] RX_SERDES_DATA6;
|
|
input [31:0] RX_SERDES_DATA7;
|
|
input [31:0] RX_SERDES_DATA8;
|
|
input [31:0] RX_SERDES_DATA9;
|
|
input [9:0] RX_SERDES_RESET;
|
|
input TX_CLK;
|
|
input [127:0] TX_DATAIN0;
|
|
input [127:0] TX_DATAIN1;
|
|
input [127:0] TX_DATAIN2;
|
|
input [127:0] TX_DATAIN3;
|
|
input TX_ENAIN0;
|
|
input TX_ENAIN1;
|
|
input TX_ENAIN2;
|
|
input TX_ENAIN3;
|
|
input TX_EOPIN0;
|
|
input TX_EOPIN1;
|
|
input TX_EOPIN2;
|
|
input TX_EOPIN3;
|
|
input TX_ERRIN0;
|
|
input TX_ERRIN1;
|
|
input TX_ERRIN2;
|
|
input TX_ERRIN3;
|
|
input [3:0] TX_MTYIN0;
|
|
input [3:0] TX_MTYIN1;
|
|
input [3:0] TX_MTYIN2;
|
|
input [3:0] TX_MTYIN3;
|
|
input [55:0] TX_PREIN;
|
|
input [1:0] TX_PTP_1588OP_IN;
|
|
input [15:0] TX_PTP_CHKSUM_OFFSET_IN;
|
|
input [63:0] TX_PTP_RXTSTAMP_IN;
|
|
input [15:0] TX_PTP_TAG_FIELD_IN;
|
|
input [15:0] TX_PTP_TSTAMP_OFFSET_IN;
|
|
input TX_PTP_UPD_CHKSUM_IN;
|
|
input TX_RESET;
|
|
input TX_SOPIN0;
|
|
input TX_SOPIN1;
|
|
input TX_SOPIN2;
|
|
input TX_SOPIN3;
|
|
endmodule
|
|
|
|
module MCB(CAS, CKE, DQIOWEN0, DQSIOWEN90N, DQSIOWEN90P, IOIDRPADD, IOIDRPBROADCAST, IOIDRPCLK, IOIDRPCS, IOIDRPSDO, IOIDRPTRAIN, IOIDRPUPDATE, LDMN, LDMP, ODT, P0CMDEMPTY, P0CMDFULL, P0RDEMPTY, P0RDERROR, P0RDFULL, P0RDOVERFLOW
|
|
, P0WREMPTY, P0WRERROR, P0WRFULL, P0WRUNDERRUN, P1CMDEMPTY, P1CMDFULL, P1RDEMPTY, P1RDERROR, P1RDFULL, P1RDOVERFLOW, P1WREMPTY, P1WRERROR, P1WRFULL, P1WRUNDERRUN, P2CMDEMPTY, P2CMDFULL, P2EMPTY, P2ERROR, P2FULL, P2RDOVERFLOW, P2WRUNDERRUN
|
|
, P3CMDEMPTY, P3CMDFULL, P3EMPTY, P3ERROR, P3FULL, P3RDOVERFLOW, P3WRUNDERRUN, P4CMDEMPTY, P4CMDFULL, P4EMPTY, P4ERROR, P4FULL, P4RDOVERFLOW, P4WRUNDERRUN, P5CMDEMPTY, P5CMDFULL, P5EMPTY, P5ERROR, P5FULL, P5RDOVERFLOW, P5WRUNDERRUN
|
|
, RAS, RST, SELFREFRESHMODE, UDMN, UDMP, UOCALSTART, UOCMDREADYIN, UODATAVALID, UODONECAL, UOREFRSHFLAG, UOSDO, WE, ADDR, DQON, DQOP, BA, P0RDDATA, P1RDDATA, P2RDDATA, P3RDDATA, P4RDDATA
|
|
, P5RDDATA, STATUS, IOIDRPADDR, P0RDCOUNT, P0WRCOUNT, P1RDCOUNT, P1WRCOUNT, P2COUNT, P3COUNT, P4COUNT, P5COUNT, UODATA, DQSIOIN, DQSIOIP, IOIDRPSDI, P0ARBEN, P0CMDCLK, P0CMDEN, P0RDCLK, P0RDEN, P0WRCLK
|
|
, P0WREN, P1ARBEN, P1CMDCLK, P1CMDEN, P1RDCLK, P1RDEN, P1WRCLK, P1WREN, P2ARBEN, P2CLK, P2CMDCLK, P2CMDEN, P2EN, P3ARBEN, P3CLK, P3CMDCLK, P3CMDEN, P3EN, P4ARBEN, P4CLK, P4CMDCLK
|
|
, P4CMDEN, P4EN, P5ARBEN, P5CLK, P5CMDCLK, P5CMDEN, P5EN, PLLLOCK, RECAL, SELFREFRESHENTER, SYSRST, UDQSIOIN, UDQSIOIP, UIADD, UIBROADCAST, UICLK, UICMD, UICMDEN, UICMDIN, UICS, UIDONECAL
|
|
, UIDQLOWERDEC, UIDQLOWERINC, UIDQUPPERDEC, UIDQUPPERINC, UIDRPUPDATE, UILDQSDEC, UILDQSINC, UIREAD, UISDI, UIUDQSDEC, UIUDQSINC, P0CMDCA, P1CMDCA, P2CMDCA, P3CMDCA, P4CMDCA, P5CMDCA, P0CMDRA, P1CMDRA, P2CMDRA, P3CMDRA
|
|
, P4CMDRA, P5CMDRA, DQI, PLLCE, PLLCLK, P0CMDBA, P0CMDINSTR, P1CMDBA, P1CMDINSTR, P2CMDBA, P2CMDINSTR, P3CMDBA, P3CMDINSTR, P4CMDBA, P4CMDINSTR, P5CMDBA, P5CMDINSTR, P0WRDATA, P1WRDATA, P2WRDATA, P3WRDATA
|
|
, P4WRDATA, P5WRDATA, P0RWRMASK, P1RWRMASK, P2WRMASK, P3WRMASK, P4WRMASK, P5WRMASK, UIDQCOUNT, UIADDR, P0CMDBL, P1CMDBL, P2CMDBL, P3CMDBL, P4CMDBL, P5CMDBL);
|
|
parameter integer ARB_NUM_TIME_SLOTS = 12;
|
|
parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_10 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_11 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_2 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_3 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_4 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_5 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_6 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_7 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_8 = 18'b111111111111111111;
|
|
parameter [17:0] ARB_TIME_SLOT_9 = 18'b111111111111111111;
|
|
parameter [2:0] CAL_BA = 3'h0;
|
|
parameter CAL_BYPASS = "YES";
|
|
parameter [11:0] CAL_CA = 12'h000;
|
|
parameter CAL_CALIBRATION_MODE = "NOCALIBRATION";
|
|
parameter integer CAL_CLK_DIV = 1;
|
|
parameter CAL_DELAY = "QUARTER";
|
|
parameter [14:0] CAL_RA = 15'h0000;
|
|
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN";
|
|
parameter integer MEM_BA_SIZE = 3;
|
|
parameter integer MEM_BURST_LEN = 8;
|
|
parameter integer MEM_CAS_LATENCY = 4;
|
|
parameter integer MEM_CA_SIZE = 11;
|
|
parameter MEM_DDR1_2_ODS = "FULL";
|
|
parameter MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL";
|
|
parameter MEM_DDR2_3_PA_SR = "FULL";
|
|
parameter integer MEM_DDR2_ADD_LATENCY = 0;
|
|
parameter MEM_DDR2_DIFF_DQS_EN = "YES";
|
|
parameter MEM_DDR2_RTT = "50OHMS";
|
|
parameter integer MEM_DDR2_WRT_RECOVERY = 4;
|
|
parameter MEM_DDR3_ADD_LATENCY = "OFF";
|
|
parameter MEM_DDR3_AUTO_SR = "ENABLED";
|
|
parameter integer MEM_DDR3_CAS_LATENCY = 7;
|
|
parameter integer MEM_DDR3_CAS_WR_LATENCY = 5;
|
|
parameter MEM_DDR3_DYN_WRT_ODT = "OFF";
|
|
parameter MEM_DDR3_ODS = "DIV7";
|
|
parameter MEM_DDR3_RTT = "DIV2";
|
|
parameter integer MEM_DDR3_WRT_RECOVERY = 7;
|
|
parameter MEM_MDDR_ODS = "FULL";
|
|
parameter MEM_MOBILE_PA_SR = "FULL";
|
|
parameter integer MEM_MOBILE_TC_SR = 0;
|
|
parameter integer MEM_RAS_VAL = 0;
|
|
parameter integer MEM_RA_SIZE = 13;
|
|
parameter integer MEM_RCD_VAL = 1;
|
|
parameter integer MEM_REFI_VAL = 0;
|
|
parameter integer MEM_RFC_VAL = 0;
|
|
parameter integer MEM_RP_VAL = 0;
|
|
parameter integer MEM_RTP_VAL = 0;
|
|
parameter MEM_TYPE = "DDR3";
|
|
parameter integer MEM_WIDTH = 4;
|
|
parameter integer MEM_WR_VAL = 0;
|
|
parameter integer MEM_WTR_VAL = 3;
|
|
parameter PORT_CONFIG = "B32_B32_B32_B32";
|
|
output CAS;
|
|
output CKE;
|
|
output DQIOWEN0;
|
|
output DQSIOWEN90N;
|
|
output DQSIOWEN90P;
|
|
output IOIDRPADD;
|
|
output IOIDRPBROADCAST;
|
|
output IOIDRPCLK;
|
|
output IOIDRPCS;
|
|
output IOIDRPSDO;
|
|
output IOIDRPTRAIN;
|
|
output IOIDRPUPDATE;
|
|
output LDMN;
|
|
output LDMP;
|
|
output ODT;
|
|
output P0CMDEMPTY;
|
|
output P0CMDFULL;
|
|
output P0RDEMPTY;
|
|
output P0RDERROR;
|
|
output P0RDFULL;
|
|
output P0RDOVERFLOW;
|
|
output P0WREMPTY;
|
|
output P0WRERROR;
|
|
output P0WRFULL;
|
|
output P0WRUNDERRUN;
|
|
output P1CMDEMPTY;
|
|
output P1CMDFULL;
|
|
output P1RDEMPTY;
|
|
output P1RDERROR;
|
|
output P1RDFULL;
|
|
output P1RDOVERFLOW;
|
|
output P1WREMPTY;
|
|
output P1WRERROR;
|
|
output P1WRFULL;
|
|
output P1WRUNDERRUN;
|
|
output P2CMDEMPTY;
|
|
output P2CMDFULL;
|
|
output P2EMPTY;
|
|
output P2ERROR;
|
|
output P2FULL;
|
|
output P2RDOVERFLOW;
|
|
output P2WRUNDERRUN;
|
|
output P3CMDEMPTY;
|
|
output P3CMDFULL;
|
|
output P3EMPTY;
|
|
output P3ERROR;
|
|
output P3FULL;
|
|
output P3RDOVERFLOW;
|
|
output P3WRUNDERRUN;
|
|
output P4CMDEMPTY;
|
|
output P4CMDFULL;
|
|
output P4EMPTY;
|
|
output P4ERROR;
|
|
output P4FULL;
|
|
output P4RDOVERFLOW;
|
|
output P4WRUNDERRUN;
|
|
output P5CMDEMPTY;
|
|
output P5CMDFULL;
|
|
output P5EMPTY;
|
|
output P5ERROR;
|
|
output P5FULL;
|
|
output P5RDOVERFLOW;
|
|
output P5WRUNDERRUN;
|
|
output RAS;
|
|
output RST;
|
|
output SELFREFRESHMODE;
|
|
output UDMN;
|
|
output UDMP;
|
|
output UOCALSTART;
|
|
output UOCMDREADYIN;
|
|
output UODATAVALID;
|
|
output UODONECAL;
|
|
output UOREFRSHFLAG;
|
|
output UOSDO;
|
|
output WE;
|
|
output [14:0] ADDR;
|
|
output [15:0] DQON;
|
|
output [15:0] DQOP;
|
|
output [2:0] BA;
|
|
output [31:0] P0RDDATA;
|
|
output [31:0] P1RDDATA;
|
|
output [31:0] P2RDDATA;
|
|
output [31:0] P3RDDATA;
|
|
output [31:0] P4RDDATA;
|
|
output [31:0] P5RDDATA;
|
|
output [31:0] STATUS;
|
|
output [4:0] IOIDRPADDR;
|
|
output [6:0] P0RDCOUNT;
|
|
output [6:0] P0WRCOUNT;
|
|
output [6:0] P1RDCOUNT;
|
|
output [6:0] P1WRCOUNT;
|
|
output [6:0] P2COUNT;
|
|
output [6:0] P3COUNT;
|
|
output [6:0] P4COUNT;
|
|
output [6:0] P5COUNT;
|
|
output [7:0] UODATA;
|
|
input DQSIOIN;
|
|
input DQSIOIP;
|
|
input IOIDRPSDI;
|
|
input P0ARBEN;
|
|
input P0CMDCLK;
|
|
input P0CMDEN;
|
|
input P0RDCLK;
|
|
input P0RDEN;
|
|
input P0WRCLK;
|
|
input P0WREN;
|
|
input P1ARBEN;
|
|
input P1CMDCLK;
|
|
input P1CMDEN;
|
|
input P1RDCLK;
|
|
input P1RDEN;
|
|
input P1WRCLK;
|
|
input P1WREN;
|
|
input P2ARBEN;
|
|
input P2CLK;
|
|
input P2CMDCLK;
|
|
input P2CMDEN;
|
|
input P2EN;
|
|
input P3ARBEN;
|
|
input P3CLK;
|
|
input P3CMDCLK;
|
|
input P3CMDEN;
|
|
input P3EN;
|
|
input P4ARBEN;
|
|
input P4CLK;
|
|
input P4CMDCLK;
|
|
input P4CMDEN;
|
|
input P4EN;
|
|
input P5ARBEN;
|
|
input P5CLK;
|
|
input P5CMDCLK;
|
|
input P5CMDEN;
|
|
input P5EN;
|
|
input PLLLOCK;
|
|
input RECAL;
|
|
input SELFREFRESHENTER;
|
|
input SYSRST;
|
|
input UDQSIOIN;
|
|
input UDQSIOIP;
|
|
input UIADD;
|
|
input UIBROADCAST;
|
|
input UICLK;
|
|
input UICMD;
|
|
input UICMDEN;
|
|
input UICMDIN;
|
|
input UICS;
|
|
input UIDONECAL;
|
|
input UIDQLOWERDEC;
|
|
input UIDQLOWERINC;
|
|
input UIDQUPPERDEC;
|
|
input UIDQUPPERINC;
|
|
input UIDRPUPDATE;
|
|
input UILDQSDEC;
|
|
input UILDQSINC;
|
|
input UIREAD;
|
|
input UISDI;
|
|
input UIUDQSDEC;
|
|
input UIUDQSINC;
|
|
input [11:0] P0CMDCA;
|
|
input [11:0] P1CMDCA;
|
|
input [11:0] P2CMDCA;
|
|
input [11:0] P3CMDCA;
|
|
input [11:0] P4CMDCA;
|
|
input [11:0] P5CMDCA;
|
|
input [14:0] P0CMDRA;
|
|
input [14:0] P1CMDRA;
|
|
input [14:0] P2CMDRA;
|
|
input [14:0] P3CMDRA;
|
|
input [14:0] P4CMDRA;
|
|
input [14:0] P5CMDRA;
|
|
input [15:0] DQI;
|
|
input [1:0] PLLCE;
|
|
input [1:0] PLLCLK;
|
|
input [2:0] P0CMDBA;
|
|
input [2:0] P0CMDINSTR;
|
|
input [2:0] P1CMDBA;
|
|
input [2:0] P1CMDINSTR;
|
|
input [2:0] P2CMDBA;
|
|
input [2:0] P2CMDINSTR;
|
|
input [2:0] P3CMDBA;
|
|
input [2:0] P3CMDINSTR;
|
|
input [2:0] P4CMDBA;
|
|
input [2:0] P4CMDINSTR;
|
|
input [2:0] P5CMDBA;
|
|
input [2:0] P5CMDINSTR;
|
|
input [31:0] P0WRDATA;
|
|
input [31:0] P1WRDATA;
|
|
input [31:0] P2WRDATA;
|
|
input [31:0] P3WRDATA;
|
|
input [31:0] P4WRDATA;
|
|
input [31:0] P5WRDATA;
|
|
input [3:0] P0RWRMASK;
|
|
input [3:0] P1RWRMASK;
|
|
input [3:0] P2WRMASK;
|
|
input [3:0] P3WRMASK;
|
|
input [3:0] P4WRMASK;
|
|
input [3:0] P5WRMASK;
|
|
input [3:0] UIDQCOUNT;
|
|
input [4:0] UIADDR;
|
|
input [5:0] P0CMDBL;
|
|
input [5:0] P1CMDBL;
|
|
input [5:0] P2CMDBL;
|
|
input [5:0] P3CMDBL;
|
|
input [5:0] P4CMDBL;
|
|
input [5:0] P5CMDBL;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module HBM_REF_CLK(REF_CLK);
|
|
input REF_CLK;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module HBM_SNGLBLI_INTF_APB(CATTRIP_PIPE, PRDATA_PIPE, PREADY_PIPE, PSLVERR_PIPE, TEMP_PIPE, PADDR, PCLK, PENABLE, PRESET_N, PSEL, PWDATA, PWRITE);
|
|
parameter CLK_SEL = "FALSE";
|
|
parameter [0:0] IS_PCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_PRESET_N_INVERTED = 1'b0;
|
|
parameter MC_ENABLE = "FALSE";
|
|
parameter PHY_ENABLE = "FALSE";
|
|
parameter PHY_PCLK_INVERT = "FALSE";
|
|
parameter SWITCH_ENABLE = "FALSE";
|
|
output CATTRIP_PIPE;
|
|
output [31:0] PRDATA_PIPE;
|
|
output PREADY_PIPE;
|
|
output PSLVERR_PIPE;
|
|
output [2:0] TEMP_PIPE;
|
|
input [21:0] PADDR;
|
|
(* invertible_pin = "IS_PCLK_INVERTED" *)
|
|
input PCLK;
|
|
input PENABLE;
|
|
(* invertible_pin = "IS_PRESET_N_INVERTED" *)
|
|
input PRESET_N;
|
|
input PSEL;
|
|
input [31:0] PWDATA;
|
|
input PWRITE;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module HBM_SNGLBLI_INTF_AXI(ARREADY_PIPE, AWREADY_PIPE, BID_PIPE, BRESP_PIPE, BVALID_PIPE, DFI_AW_AERR_N_PIPE, DFI_CLK_BUF, DFI_CTRLUPD_ACK_PIPE, DFI_DBI_BYTE_DISABLE_PIPE, DFI_DW_RDDATA_DBI_PIPE, DFI_DW_RDDATA_DERR_PIPE, DFI_DW_RDDATA_PAR_VALID_PIPE, DFI_DW_RDDATA_VALID_PIPE, DFI_INIT_COMPLETE_PIPE, DFI_PHYUPD_REQ_PIPE, DFI_PHYUPD_TYPE_PIPE, DFI_PHY_LP_STATE_PIPE, DFI_RST_N_BUF, MC_STATUS, PHY_STATUS, RDATA_PARITY_PIPE
|
|
, RDATA_PIPE, RID_PIPE, RLAST_PIPE, RRESP_PIPE, RVALID_PIPE, STATUS, WREADY_PIPE, ACLK, ARADDR, ARBURST, ARESET_N, ARID, ARLEN, ARSIZE, ARVALID, AWADDR, AWBURST, AWID, AWLEN, AWSIZE, AWVALID
|
|
, BREADY, BSCAN_CK, DFI_LP_PWR_X_REQ, MBIST_EN, RREADY, WDATA, WDATA_PARITY, WLAST, WSTRB, WVALID);
|
|
parameter CLK_SEL = "FALSE";
|
|
parameter integer DATARATE = 1800;
|
|
parameter [0:0] IS_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_ARESET_N_INVERTED = 1'b0;
|
|
parameter MC_ENABLE = "FALSE";
|
|
parameter integer PAGEHIT_PERCENT = 75;
|
|
parameter PHY_ENABLE = "FALSE";
|
|
parameter integer READ_PERCENT = 50;
|
|
parameter SWITCH_ENABLE = "FALSE";
|
|
parameter integer WRITE_PERCENT = 50;
|
|
output ARREADY_PIPE;
|
|
output AWREADY_PIPE;
|
|
output [5:0] BID_PIPE;
|
|
output [1:0] BRESP_PIPE;
|
|
output BVALID_PIPE;
|
|
output [1:0] DFI_AW_AERR_N_PIPE;
|
|
output DFI_CLK_BUF;
|
|
output DFI_CTRLUPD_ACK_PIPE;
|
|
output [7:0] DFI_DBI_BYTE_DISABLE_PIPE;
|
|
output [20:0] DFI_DW_RDDATA_DBI_PIPE;
|
|
output [7:0] DFI_DW_RDDATA_DERR_PIPE;
|
|
output [1:0] DFI_DW_RDDATA_PAR_VALID_PIPE;
|
|
output [1:0] DFI_DW_RDDATA_VALID_PIPE;
|
|
output DFI_INIT_COMPLETE_PIPE;
|
|
output DFI_PHYUPD_REQ_PIPE;
|
|
output DFI_PHYUPD_TYPE_PIPE;
|
|
output DFI_PHY_LP_STATE_PIPE;
|
|
output DFI_RST_N_BUF;
|
|
output [5:0] MC_STATUS;
|
|
output [7:0] PHY_STATUS;
|
|
output [31:0] RDATA_PARITY_PIPE;
|
|
output [255:0] RDATA_PIPE;
|
|
output [5:0] RID_PIPE;
|
|
output RLAST_PIPE;
|
|
output [1:0] RRESP_PIPE;
|
|
output RVALID_PIPE;
|
|
output [5:0] STATUS;
|
|
output WREADY_PIPE;
|
|
(* invertible_pin = "IS_ACLK_INVERTED" *)
|
|
input ACLK;
|
|
input [36:0] ARADDR;
|
|
input [1:0] ARBURST;
|
|
(* invertible_pin = "IS_ARESET_N_INVERTED" *)
|
|
input ARESET_N;
|
|
input [5:0] ARID;
|
|
input [3:0] ARLEN;
|
|
input [2:0] ARSIZE;
|
|
input ARVALID;
|
|
input [36:0] AWADDR;
|
|
input [1:0] AWBURST;
|
|
input [5:0] AWID;
|
|
input [3:0] AWLEN;
|
|
input [2:0] AWSIZE;
|
|
input AWVALID;
|
|
input BREADY;
|
|
input BSCAN_CK;
|
|
input DFI_LP_PWR_X_REQ;
|
|
input MBIST_EN;
|
|
input RREADY;
|
|
input [255:0] WDATA;
|
|
input [31:0] WDATA_PARITY;
|
|
input WLAST;
|
|
input [31:0] WSTRB;
|
|
input WVALID;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module HBM_ONE_STACK_INTF(APB_0_PRDATA, APB_0_PREADY, APB_0_PSLVERR, AXI_00_ARREADY, AXI_00_AWREADY, AXI_00_BID, AXI_00_BRESP, AXI_00_BVALID, AXI_00_DFI_AW_AERR_N, AXI_00_DFI_CLK_BUF, AXI_00_DFI_DBI_BYTE_DISABLE, AXI_00_DFI_DW_RDDATA_DBI, AXI_00_DFI_DW_RDDATA_DERR, AXI_00_DFI_DW_RDDATA_VALID, AXI_00_DFI_INIT_COMPLETE, AXI_00_DFI_PHYUPD_REQ, AXI_00_DFI_PHY_LP_STATE, AXI_00_DFI_RST_N_BUF, AXI_00_MC_STATUS, AXI_00_PHY_STATUS, AXI_00_RDATA
|
|
, AXI_00_RDATA_PARITY, AXI_00_RID, AXI_00_RLAST, AXI_00_RRESP, AXI_00_RVALID, AXI_00_WREADY, AXI_01_ARREADY, AXI_01_AWREADY, AXI_01_BID, AXI_01_BRESP, AXI_01_BVALID, AXI_01_DFI_AW_AERR_N, AXI_01_DFI_CLK_BUF, AXI_01_DFI_DBI_BYTE_DISABLE, AXI_01_DFI_DW_RDDATA_DBI, AXI_01_DFI_DW_RDDATA_DERR, AXI_01_DFI_DW_RDDATA_VALID, AXI_01_DFI_INIT_COMPLETE, AXI_01_DFI_PHYUPD_REQ, AXI_01_DFI_PHY_LP_STATE, AXI_01_DFI_RST_N_BUF
|
|
, AXI_01_RDATA, AXI_01_RDATA_PARITY, AXI_01_RID, AXI_01_RLAST, AXI_01_RRESP, AXI_01_RVALID, AXI_01_WREADY, AXI_02_ARREADY, AXI_02_AWREADY, AXI_02_BID, AXI_02_BRESP, AXI_02_BVALID, AXI_02_DFI_AW_AERR_N, AXI_02_DFI_CLK_BUF, AXI_02_DFI_DBI_BYTE_DISABLE, AXI_02_DFI_DW_RDDATA_DBI, AXI_02_DFI_DW_RDDATA_DERR, AXI_02_DFI_DW_RDDATA_VALID, AXI_02_DFI_INIT_COMPLETE, AXI_02_DFI_PHYUPD_REQ, AXI_02_DFI_PHY_LP_STATE
|
|
, AXI_02_DFI_RST_N_BUF, AXI_02_MC_STATUS, AXI_02_PHY_STATUS, AXI_02_RDATA, AXI_02_RDATA_PARITY, AXI_02_RID, AXI_02_RLAST, AXI_02_RRESP, AXI_02_RVALID, AXI_02_WREADY, AXI_03_ARREADY, AXI_03_AWREADY, AXI_03_BID, AXI_03_BRESP, AXI_03_BVALID, AXI_03_DFI_AW_AERR_N, AXI_03_DFI_CLK_BUF, AXI_03_DFI_DBI_BYTE_DISABLE, AXI_03_DFI_DW_RDDATA_DBI, AXI_03_DFI_DW_RDDATA_DERR, AXI_03_DFI_DW_RDDATA_VALID
|
|
, AXI_03_DFI_INIT_COMPLETE, AXI_03_DFI_PHYUPD_REQ, AXI_03_DFI_PHY_LP_STATE, AXI_03_DFI_RST_N_BUF, AXI_03_RDATA, AXI_03_RDATA_PARITY, AXI_03_RID, AXI_03_RLAST, AXI_03_RRESP, AXI_03_RVALID, AXI_03_WREADY, AXI_04_ARREADY, AXI_04_AWREADY, AXI_04_BID, AXI_04_BRESP, AXI_04_BVALID, AXI_04_DFI_AW_AERR_N, AXI_04_DFI_CLK_BUF, AXI_04_DFI_DBI_BYTE_DISABLE, AXI_04_DFI_DW_RDDATA_DBI, AXI_04_DFI_DW_RDDATA_DERR
|
|
, AXI_04_DFI_DW_RDDATA_VALID, AXI_04_DFI_INIT_COMPLETE, AXI_04_DFI_PHYUPD_REQ, AXI_04_DFI_PHY_LP_STATE, AXI_04_DFI_RST_N_BUF, AXI_04_MC_STATUS, AXI_04_PHY_STATUS, AXI_04_RDATA, AXI_04_RDATA_PARITY, AXI_04_RID, AXI_04_RLAST, AXI_04_RRESP, AXI_04_RVALID, AXI_04_WREADY, AXI_05_ARREADY, AXI_05_AWREADY, AXI_05_BID, AXI_05_BRESP, AXI_05_BVALID, AXI_05_DFI_AW_AERR_N, AXI_05_DFI_CLK_BUF
|
|
, AXI_05_DFI_DBI_BYTE_DISABLE, AXI_05_DFI_DW_RDDATA_DBI, AXI_05_DFI_DW_RDDATA_DERR, AXI_05_DFI_DW_RDDATA_VALID, AXI_05_DFI_INIT_COMPLETE, AXI_05_DFI_PHYUPD_REQ, AXI_05_DFI_PHY_LP_STATE, AXI_05_DFI_RST_N_BUF, AXI_05_RDATA, AXI_05_RDATA_PARITY, AXI_05_RID, AXI_05_RLAST, AXI_05_RRESP, AXI_05_RVALID, AXI_05_WREADY, AXI_06_ARREADY, AXI_06_AWREADY, AXI_06_BID, AXI_06_BRESP, AXI_06_BVALID, AXI_06_DFI_AW_AERR_N
|
|
, AXI_06_DFI_CLK_BUF, AXI_06_DFI_DBI_BYTE_DISABLE, AXI_06_DFI_DW_RDDATA_DBI, AXI_06_DFI_DW_RDDATA_DERR, AXI_06_DFI_DW_RDDATA_VALID, AXI_06_DFI_INIT_COMPLETE, AXI_06_DFI_PHYUPD_REQ, AXI_06_DFI_PHY_LP_STATE, AXI_06_DFI_RST_N_BUF, AXI_06_MC_STATUS, AXI_06_PHY_STATUS, AXI_06_RDATA, AXI_06_RDATA_PARITY, AXI_06_RID, AXI_06_RLAST, AXI_06_RRESP, AXI_06_RVALID, AXI_06_WREADY, AXI_07_ARREADY, AXI_07_AWREADY, AXI_07_BID
|
|
, AXI_07_BRESP, AXI_07_BVALID, AXI_07_DFI_AW_AERR_N, AXI_07_DFI_CLK_BUF, AXI_07_DFI_DBI_BYTE_DISABLE, AXI_07_DFI_DW_RDDATA_DBI, AXI_07_DFI_DW_RDDATA_DERR, AXI_07_DFI_DW_RDDATA_VALID, AXI_07_DFI_INIT_COMPLETE, AXI_07_DFI_PHYUPD_REQ, AXI_07_DFI_PHY_LP_STATE, AXI_07_DFI_RST_N_BUF, AXI_07_RDATA, AXI_07_RDATA_PARITY, AXI_07_RID, AXI_07_RLAST, AXI_07_RRESP, AXI_07_RVALID, AXI_07_WREADY, AXI_08_ARREADY, AXI_08_AWREADY
|
|
, AXI_08_BID, AXI_08_BRESP, AXI_08_BVALID, AXI_08_DFI_AW_AERR_N, AXI_08_DFI_CLK_BUF, AXI_08_DFI_DBI_BYTE_DISABLE, AXI_08_DFI_DW_RDDATA_DBI, AXI_08_DFI_DW_RDDATA_DERR, AXI_08_DFI_DW_RDDATA_VALID, AXI_08_DFI_INIT_COMPLETE, AXI_08_DFI_PHYUPD_REQ, AXI_08_DFI_PHY_LP_STATE, AXI_08_DFI_RST_N_BUF, AXI_08_MC_STATUS, AXI_08_PHY_STATUS, AXI_08_RDATA, AXI_08_RDATA_PARITY, AXI_08_RID, AXI_08_RLAST, AXI_08_RRESP, AXI_08_RVALID
|
|
, AXI_08_WREADY, AXI_09_ARREADY, AXI_09_AWREADY, AXI_09_BID, AXI_09_BRESP, AXI_09_BVALID, AXI_09_DFI_AW_AERR_N, AXI_09_DFI_CLK_BUF, AXI_09_DFI_DBI_BYTE_DISABLE, AXI_09_DFI_DW_RDDATA_DBI, AXI_09_DFI_DW_RDDATA_DERR, AXI_09_DFI_DW_RDDATA_VALID, AXI_09_DFI_INIT_COMPLETE, AXI_09_DFI_PHYUPD_REQ, AXI_09_DFI_PHY_LP_STATE, AXI_09_DFI_RST_N_BUF, AXI_09_RDATA, AXI_09_RDATA_PARITY, AXI_09_RID, AXI_09_RLAST, AXI_09_RRESP
|
|
, AXI_09_RVALID, AXI_09_WREADY, AXI_10_ARREADY, AXI_10_AWREADY, AXI_10_BID, AXI_10_BRESP, AXI_10_BVALID, AXI_10_DFI_AW_AERR_N, AXI_10_DFI_CLK_BUF, AXI_10_DFI_DBI_BYTE_DISABLE, AXI_10_DFI_DW_RDDATA_DBI, AXI_10_DFI_DW_RDDATA_DERR, AXI_10_DFI_DW_RDDATA_VALID, AXI_10_DFI_INIT_COMPLETE, AXI_10_DFI_PHYUPD_REQ, AXI_10_DFI_PHY_LP_STATE, AXI_10_DFI_RST_N_BUF, AXI_10_MC_STATUS, AXI_10_PHY_STATUS, AXI_10_RDATA, AXI_10_RDATA_PARITY
|
|
, AXI_10_RID, AXI_10_RLAST, AXI_10_RRESP, AXI_10_RVALID, AXI_10_WREADY, AXI_11_ARREADY, AXI_11_AWREADY, AXI_11_BID, AXI_11_BRESP, AXI_11_BVALID, AXI_11_DFI_AW_AERR_N, AXI_11_DFI_CLK_BUF, AXI_11_DFI_DBI_BYTE_DISABLE, AXI_11_DFI_DW_RDDATA_DBI, AXI_11_DFI_DW_RDDATA_DERR, AXI_11_DFI_DW_RDDATA_VALID, AXI_11_DFI_INIT_COMPLETE, AXI_11_DFI_PHYUPD_REQ, AXI_11_DFI_PHY_LP_STATE, AXI_11_DFI_RST_N_BUF, AXI_11_RDATA
|
|
, AXI_11_RDATA_PARITY, AXI_11_RID, AXI_11_RLAST, AXI_11_RRESP, AXI_11_RVALID, AXI_11_WREADY, AXI_12_ARREADY, AXI_12_AWREADY, AXI_12_BID, AXI_12_BRESP, AXI_12_BVALID, AXI_12_DFI_AW_AERR_N, AXI_12_DFI_CLK_BUF, AXI_12_DFI_DBI_BYTE_DISABLE, AXI_12_DFI_DW_RDDATA_DBI, AXI_12_DFI_DW_RDDATA_DERR, AXI_12_DFI_DW_RDDATA_VALID, AXI_12_DFI_INIT_COMPLETE, AXI_12_DFI_PHYUPD_REQ, AXI_12_DFI_PHY_LP_STATE, AXI_12_DFI_RST_N_BUF
|
|
, AXI_12_MC_STATUS, AXI_12_PHY_STATUS, AXI_12_RDATA, AXI_12_RDATA_PARITY, AXI_12_RID, AXI_12_RLAST, AXI_12_RRESP, AXI_12_RVALID, AXI_12_WREADY, AXI_13_ARREADY, AXI_13_AWREADY, AXI_13_BID, AXI_13_BRESP, AXI_13_BVALID, AXI_13_DFI_AW_AERR_N, AXI_13_DFI_CLK_BUF, AXI_13_DFI_DBI_BYTE_DISABLE, AXI_13_DFI_DW_RDDATA_DBI, AXI_13_DFI_DW_RDDATA_DERR, AXI_13_DFI_DW_RDDATA_VALID, AXI_13_DFI_INIT_COMPLETE
|
|
, AXI_13_DFI_PHYUPD_REQ, AXI_13_DFI_PHY_LP_STATE, AXI_13_DFI_RST_N_BUF, AXI_13_RDATA, AXI_13_RDATA_PARITY, AXI_13_RID, AXI_13_RLAST, AXI_13_RRESP, AXI_13_RVALID, AXI_13_WREADY, AXI_14_ARREADY, AXI_14_AWREADY, AXI_14_BID, AXI_14_BRESP, AXI_14_BVALID, AXI_14_DFI_AW_AERR_N, AXI_14_DFI_CLK_BUF, AXI_14_DFI_DBI_BYTE_DISABLE, AXI_14_DFI_DW_RDDATA_DBI, AXI_14_DFI_DW_RDDATA_DERR, AXI_14_DFI_DW_RDDATA_VALID
|
|
, AXI_14_DFI_INIT_COMPLETE, AXI_14_DFI_PHYUPD_REQ, AXI_14_DFI_PHY_LP_STATE, AXI_14_DFI_RST_N_BUF, AXI_14_MC_STATUS, AXI_14_PHY_STATUS, AXI_14_RDATA, AXI_14_RDATA_PARITY, AXI_14_RID, AXI_14_RLAST, AXI_14_RRESP, AXI_14_RVALID, AXI_14_WREADY, AXI_15_ARREADY, AXI_15_AWREADY, AXI_15_BID, AXI_15_BRESP, AXI_15_BVALID, AXI_15_DFI_AW_AERR_N, AXI_15_DFI_CLK_BUF, AXI_15_DFI_DBI_BYTE_DISABLE
|
|
, AXI_15_DFI_DW_RDDATA_DBI, AXI_15_DFI_DW_RDDATA_DERR, AXI_15_DFI_DW_RDDATA_VALID, AXI_15_DFI_INIT_COMPLETE, AXI_15_DFI_PHYUPD_REQ, AXI_15_DFI_PHY_LP_STATE, AXI_15_DFI_RST_N_BUF, AXI_15_RDATA, AXI_15_RDATA_PARITY, AXI_15_RID, AXI_15_RLAST, AXI_15_RRESP, AXI_15_RVALID, AXI_15_WREADY, DRAM_0_STAT_CATTRIP, DRAM_0_STAT_TEMP, APB_0_PADDR, APB_0_PCLK, APB_0_PENABLE, APB_0_PRESET_N, APB_0_PSEL
|
|
, APB_0_PWDATA, APB_0_PWRITE, AXI_00_ACLK, AXI_00_ARADDR, AXI_00_ARBURST, AXI_00_ARESET_N, AXI_00_ARID, AXI_00_ARLEN, AXI_00_ARSIZE, AXI_00_ARVALID, AXI_00_AWADDR, AXI_00_AWBURST, AXI_00_AWID, AXI_00_AWLEN, AXI_00_AWSIZE, AXI_00_AWVALID, AXI_00_BREADY, AXI_00_DFI_LP_PWR_X_REQ, AXI_00_RREADY, AXI_00_WDATA, AXI_00_WDATA_PARITY
|
|
, AXI_00_WLAST, AXI_00_WSTRB, AXI_00_WVALID, AXI_01_ACLK, AXI_01_ARADDR, AXI_01_ARBURST, AXI_01_ARESET_N, AXI_01_ARID, AXI_01_ARLEN, AXI_01_ARSIZE, AXI_01_ARVALID, AXI_01_AWADDR, AXI_01_AWBURST, AXI_01_AWID, AXI_01_AWLEN, AXI_01_AWSIZE, AXI_01_AWVALID, AXI_01_BREADY, AXI_01_DFI_LP_PWR_X_REQ, AXI_01_RREADY, AXI_01_WDATA
|
|
, AXI_01_WDATA_PARITY, AXI_01_WLAST, AXI_01_WSTRB, AXI_01_WVALID, AXI_02_ACLK, AXI_02_ARADDR, AXI_02_ARBURST, AXI_02_ARESET_N, AXI_02_ARID, AXI_02_ARLEN, AXI_02_ARSIZE, AXI_02_ARVALID, AXI_02_AWADDR, AXI_02_AWBURST, AXI_02_AWID, AXI_02_AWLEN, AXI_02_AWSIZE, AXI_02_AWVALID, AXI_02_BREADY, AXI_02_DFI_LP_PWR_X_REQ, AXI_02_RREADY
|
|
, AXI_02_WDATA, AXI_02_WDATA_PARITY, AXI_02_WLAST, AXI_02_WSTRB, AXI_02_WVALID, AXI_03_ACLK, AXI_03_ARADDR, AXI_03_ARBURST, AXI_03_ARESET_N, AXI_03_ARID, AXI_03_ARLEN, AXI_03_ARSIZE, AXI_03_ARVALID, AXI_03_AWADDR, AXI_03_AWBURST, AXI_03_AWID, AXI_03_AWLEN, AXI_03_AWSIZE, AXI_03_AWVALID, AXI_03_BREADY, AXI_03_DFI_LP_PWR_X_REQ
|
|
, AXI_03_RREADY, AXI_03_WDATA, AXI_03_WDATA_PARITY, AXI_03_WLAST, AXI_03_WSTRB, AXI_03_WVALID, AXI_04_ACLK, AXI_04_ARADDR, AXI_04_ARBURST, AXI_04_ARESET_N, AXI_04_ARID, AXI_04_ARLEN, AXI_04_ARSIZE, AXI_04_ARVALID, AXI_04_AWADDR, AXI_04_AWBURST, AXI_04_AWID, AXI_04_AWLEN, AXI_04_AWSIZE, AXI_04_AWVALID, AXI_04_BREADY
|
|
, AXI_04_DFI_LP_PWR_X_REQ, AXI_04_RREADY, AXI_04_WDATA, AXI_04_WDATA_PARITY, AXI_04_WLAST, AXI_04_WSTRB, AXI_04_WVALID, AXI_05_ACLK, AXI_05_ARADDR, AXI_05_ARBURST, AXI_05_ARESET_N, AXI_05_ARID, AXI_05_ARLEN, AXI_05_ARSIZE, AXI_05_ARVALID, AXI_05_AWADDR, AXI_05_AWBURST, AXI_05_AWID, AXI_05_AWLEN, AXI_05_AWSIZE, AXI_05_AWVALID
|
|
, AXI_05_BREADY, AXI_05_DFI_LP_PWR_X_REQ, AXI_05_RREADY, AXI_05_WDATA, AXI_05_WDATA_PARITY, AXI_05_WLAST, AXI_05_WSTRB, AXI_05_WVALID, AXI_06_ACLK, AXI_06_ARADDR, AXI_06_ARBURST, AXI_06_ARESET_N, AXI_06_ARID, AXI_06_ARLEN, AXI_06_ARSIZE, AXI_06_ARVALID, AXI_06_AWADDR, AXI_06_AWBURST, AXI_06_AWID, AXI_06_AWLEN, AXI_06_AWSIZE
|
|
, AXI_06_AWVALID, AXI_06_BREADY, AXI_06_DFI_LP_PWR_X_REQ, AXI_06_RREADY, AXI_06_WDATA, AXI_06_WDATA_PARITY, AXI_06_WLAST, AXI_06_WSTRB, AXI_06_WVALID, AXI_07_ACLK, AXI_07_ARADDR, AXI_07_ARBURST, AXI_07_ARESET_N, AXI_07_ARID, AXI_07_ARLEN, AXI_07_ARSIZE, AXI_07_ARVALID, AXI_07_AWADDR, AXI_07_AWBURST, AXI_07_AWID, AXI_07_AWLEN
|
|
, AXI_07_AWSIZE, AXI_07_AWVALID, AXI_07_BREADY, AXI_07_DFI_LP_PWR_X_REQ, AXI_07_RREADY, AXI_07_WDATA, AXI_07_WDATA_PARITY, AXI_07_WLAST, AXI_07_WSTRB, AXI_07_WVALID, AXI_08_ACLK, AXI_08_ARADDR, AXI_08_ARBURST, AXI_08_ARESET_N, AXI_08_ARID, AXI_08_ARLEN, AXI_08_ARSIZE, AXI_08_ARVALID, AXI_08_AWADDR, AXI_08_AWBURST, AXI_08_AWID
|
|
, AXI_08_AWLEN, AXI_08_AWSIZE, AXI_08_AWVALID, AXI_08_BREADY, AXI_08_DFI_LP_PWR_X_REQ, AXI_08_RREADY, AXI_08_WDATA, AXI_08_WDATA_PARITY, AXI_08_WLAST, AXI_08_WSTRB, AXI_08_WVALID, AXI_09_ACLK, AXI_09_ARADDR, AXI_09_ARBURST, AXI_09_ARESET_N, AXI_09_ARID, AXI_09_ARLEN, AXI_09_ARSIZE, AXI_09_ARVALID, AXI_09_AWADDR, AXI_09_AWBURST
|
|
, AXI_09_AWID, AXI_09_AWLEN, AXI_09_AWSIZE, AXI_09_AWVALID, AXI_09_BREADY, AXI_09_DFI_LP_PWR_X_REQ, AXI_09_RREADY, AXI_09_WDATA, AXI_09_WDATA_PARITY, AXI_09_WLAST, AXI_09_WSTRB, AXI_09_WVALID, AXI_10_ACLK, AXI_10_ARADDR, AXI_10_ARBURST, AXI_10_ARESET_N, AXI_10_ARID, AXI_10_ARLEN, AXI_10_ARSIZE, AXI_10_ARVALID, AXI_10_AWADDR
|
|
, AXI_10_AWBURST, AXI_10_AWID, AXI_10_AWLEN, AXI_10_AWSIZE, AXI_10_AWVALID, AXI_10_BREADY, AXI_10_DFI_LP_PWR_X_REQ, AXI_10_RREADY, AXI_10_WDATA, AXI_10_WDATA_PARITY, AXI_10_WLAST, AXI_10_WSTRB, AXI_10_WVALID, AXI_11_ACLK, AXI_11_ARADDR, AXI_11_ARBURST, AXI_11_ARESET_N, AXI_11_ARID, AXI_11_ARLEN, AXI_11_ARSIZE, AXI_11_ARVALID
|
|
, AXI_11_AWADDR, AXI_11_AWBURST, AXI_11_AWID, AXI_11_AWLEN, AXI_11_AWSIZE, AXI_11_AWVALID, AXI_11_BREADY, AXI_11_DFI_LP_PWR_X_REQ, AXI_11_RREADY, AXI_11_WDATA, AXI_11_WDATA_PARITY, AXI_11_WLAST, AXI_11_WSTRB, AXI_11_WVALID, AXI_12_ACLK, AXI_12_ARADDR, AXI_12_ARBURST, AXI_12_ARESET_N, AXI_12_ARID, AXI_12_ARLEN, AXI_12_ARSIZE
|
|
, AXI_12_ARVALID, AXI_12_AWADDR, AXI_12_AWBURST, AXI_12_AWID, AXI_12_AWLEN, AXI_12_AWSIZE, AXI_12_AWVALID, AXI_12_BREADY, AXI_12_DFI_LP_PWR_X_REQ, AXI_12_RREADY, AXI_12_WDATA, AXI_12_WDATA_PARITY, AXI_12_WLAST, AXI_12_WSTRB, AXI_12_WVALID, AXI_13_ACLK, AXI_13_ARADDR, AXI_13_ARBURST, AXI_13_ARESET_N, AXI_13_ARID, AXI_13_ARLEN
|
|
, AXI_13_ARSIZE, AXI_13_ARVALID, AXI_13_AWADDR, AXI_13_AWBURST, AXI_13_AWID, AXI_13_AWLEN, AXI_13_AWSIZE, AXI_13_AWVALID, AXI_13_BREADY, AXI_13_DFI_LP_PWR_X_REQ, AXI_13_RREADY, AXI_13_WDATA, AXI_13_WDATA_PARITY, AXI_13_WLAST, AXI_13_WSTRB, AXI_13_WVALID, AXI_14_ACLK, AXI_14_ARADDR, AXI_14_ARBURST, AXI_14_ARESET_N, AXI_14_ARID
|
|
, AXI_14_ARLEN, AXI_14_ARSIZE, AXI_14_ARVALID, AXI_14_AWADDR, AXI_14_AWBURST, AXI_14_AWID, AXI_14_AWLEN, AXI_14_AWSIZE, AXI_14_AWVALID, AXI_14_BREADY, AXI_14_DFI_LP_PWR_X_REQ, AXI_14_RREADY, AXI_14_WDATA, AXI_14_WDATA_PARITY, AXI_14_WLAST, AXI_14_WSTRB, AXI_14_WVALID, AXI_15_ACLK, AXI_15_ARADDR, AXI_15_ARBURST, AXI_15_ARESET_N
|
|
, AXI_15_ARID, AXI_15_ARLEN, AXI_15_ARSIZE, AXI_15_ARVALID, AXI_15_AWADDR, AXI_15_AWBURST, AXI_15_AWID, AXI_15_AWLEN, AXI_15_AWSIZE, AXI_15_AWVALID, AXI_15_BREADY, AXI_15_DFI_LP_PWR_X_REQ, AXI_15_RREADY, AXI_15_WDATA, AXI_15_WDATA_PARITY, AXI_15_WLAST, AXI_15_WSTRB, AXI_15_WVALID, BSCAN_DRCK, BSCAN_TCK, HBM_REF_CLK
|
|
, MBIST_EN_00, MBIST_EN_01, MBIST_EN_02, MBIST_EN_03, MBIST_EN_04, MBIST_EN_05, MBIST_EN_06, MBIST_EN_07);
|
|
parameter CLK_SEL_00 = "FALSE";
|
|
parameter CLK_SEL_01 = "FALSE";
|
|
parameter CLK_SEL_02 = "FALSE";
|
|
parameter CLK_SEL_03 = "FALSE";
|
|
parameter CLK_SEL_04 = "FALSE";
|
|
parameter CLK_SEL_05 = "FALSE";
|
|
parameter CLK_SEL_06 = "FALSE";
|
|
parameter CLK_SEL_07 = "FALSE";
|
|
parameter CLK_SEL_08 = "FALSE";
|
|
parameter CLK_SEL_09 = "FALSE";
|
|
parameter CLK_SEL_10 = "FALSE";
|
|
parameter CLK_SEL_11 = "FALSE";
|
|
parameter CLK_SEL_12 = "FALSE";
|
|
parameter CLK_SEL_13 = "FALSE";
|
|
parameter CLK_SEL_14 = "FALSE";
|
|
parameter CLK_SEL_15 = "FALSE";
|
|
parameter integer DATARATE_00 = 1800;
|
|
parameter integer DATARATE_01 = 1800;
|
|
parameter integer DATARATE_02 = 1800;
|
|
parameter integer DATARATE_03 = 1800;
|
|
parameter integer DATARATE_04 = 1800;
|
|
parameter integer DATARATE_05 = 1800;
|
|
parameter integer DATARATE_06 = 1800;
|
|
parameter integer DATARATE_07 = 1800;
|
|
parameter DA_LOCKOUT = "FALSE";
|
|
parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0;
|
|
parameter MC_ENABLE_0 = "FALSE";
|
|
parameter MC_ENABLE_1 = "FALSE";
|
|
parameter MC_ENABLE_2 = "FALSE";
|
|
parameter MC_ENABLE_3 = "FALSE";
|
|
parameter MC_ENABLE_4 = "FALSE";
|
|
parameter MC_ENABLE_5 = "FALSE";
|
|
parameter MC_ENABLE_6 = "FALSE";
|
|
parameter MC_ENABLE_7 = "FALSE";
|
|
parameter MC_ENABLE_APB = "FALSE";
|
|
parameter integer PAGEHIT_PERCENT_00 = 75;
|
|
parameter PHY_ENABLE_00 = "FALSE";
|
|
parameter PHY_ENABLE_01 = "FALSE";
|
|
parameter PHY_ENABLE_02 = "FALSE";
|
|
parameter PHY_ENABLE_03 = "FALSE";
|
|
parameter PHY_ENABLE_04 = "FALSE";
|
|
parameter PHY_ENABLE_05 = "FALSE";
|
|
parameter PHY_ENABLE_06 = "FALSE";
|
|
parameter PHY_ENABLE_07 = "FALSE";
|
|
parameter PHY_ENABLE_08 = "FALSE";
|
|
parameter PHY_ENABLE_09 = "FALSE";
|
|
parameter PHY_ENABLE_10 = "FALSE";
|
|
parameter PHY_ENABLE_11 = "FALSE";
|
|
parameter PHY_ENABLE_12 = "FALSE";
|
|
parameter PHY_ENABLE_13 = "FALSE";
|
|
parameter PHY_ENABLE_14 = "FALSE";
|
|
parameter PHY_ENABLE_15 = "FALSE";
|
|
parameter PHY_ENABLE_APB = "FALSE";
|
|
parameter PHY_PCLK_INVERT_01 = "FALSE";
|
|
parameter integer READ_PERCENT_00 = 50;
|
|
parameter integer READ_PERCENT_01 = 50;
|
|
parameter integer READ_PERCENT_02 = 50;
|
|
parameter integer READ_PERCENT_03 = 50;
|
|
parameter integer READ_PERCENT_04 = 50;
|
|
parameter integer READ_PERCENT_05 = 50;
|
|
parameter integer READ_PERCENT_06 = 50;
|
|
parameter integer READ_PERCENT_07 = 50;
|
|
parameter integer READ_PERCENT_08 = 50;
|
|
parameter integer READ_PERCENT_09 = 50;
|
|
parameter integer READ_PERCENT_10 = 50;
|
|
parameter integer READ_PERCENT_11 = 50;
|
|
parameter integer READ_PERCENT_12 = 50;
|
|
parameter integer READ_PERCENT_13 = 50;
|
|
parameter integer READ_PERCENT_14 = 50;
|
|
parameter integer READ_PERCENT_15 = 50;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter integer STACK_LOCATION = 0;
|
|
parameter SWITCH_ENABLE = "FALSE";
|
|
parameter integer WRITE_PERCENT_00 = 50;
|
|
parameter integer WRITE_PERCENT_01 = 50;
|
|
parameter integer WRITE_PERCENT_02 = 50;
|
|
parameter integer WRITE_PERCENT_03 = 50;
|
|
parameter integer WRITE_PERCENT_04 = 50;
|
|
parameter integer WRITE_PERCENT_05 = 50;
|
|
parameter integer WRITE_PERCENT_06 = 50;
|
|
parameter integer WRITE_PERCENT_07 = 50;
|
|
parameter integer WRITE_PERCENT_08 = 50;
|
|
parameter integer WRITE_PERCENT_09 = 50;
|
|
parameter integer WRITE_PERCENT_10 = 50;
|
|
parameter integer WRITE_PERCENT_11 = 50;
|
|
parameter integer WRITE_PERCENT_12 = 50;
|
|
parameter integer WRITE_PERCENT_13 = 50;
|
|
parameter integer WRITE_PERCENT_14 = 50;
|
|
parameter integer WRITE_PERCENT_15 = 50;
|
|
output [31:0] APB_0_PRDATA;
|
|
output APB_0_PREADY;
|
|
output APB_0_PSLVERR;
|
|
output AXI_00_ARREADY;
|
|
output AXI_00_AWREADY;
|
|
output [5:0] AXI_00_BID;
|
|
output [1:0] AXI_00_BRESP;
|
|
output AXI_00_BVALID;
|
|
output [1:0] AXI_00_DFI_AW_AERR_N;
|
|
output AXI_00_DFI_CLK_BUF;
|
|
output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_00_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_00_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_00_DFI_DW_RDDATA_VALID;
|
|
output AXI_00_DFI_INIT_COMPLETE;
|
|
output AXI_00_DFI_PHYUPD_REQ;
|
|
output AXI_00_DFI_PHY_LP_STATE;
|
|
output AXI_00_DFI_RST_N_BUF;
|
|
output [5:0] AXI_00_MC_STATUS;
|
|
output [7:0] AXI_00_PHY_STATUS;
|
|
output [255:0] AXI_00_RDATA;
|
|
output [31:0] AXI_00_RDATA_PARITY;
|
|
output [5:0] AXI_00_RID;
|
|
output AXI_00_RLAST;
|
|
output [1:0] AXI_00_RRESP;
|
|
output AXI_00_RVALID;
|
|
output AXI_00_WREADY;
|
|
output AXI_01_ARREADY;
|
|
output AXI_01_AWREADY;
|
|
output [5:0] AXI_01_BID;
|
|
output [1:0] AXI_01_BRESP;
|
|
output AXI_01_BVALID;
|
|
output [1:0] AXI_01_DFI_AW_AERR_N;
|
|
output AXI_01_DFI_CLK_BUF;
|
|
output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_01_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_01_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_01_DFI_DW_RDDATA_VALID;
|
|
output AXI_01_DFI_INIT_COMPLETE;
|
|
output AXI_01_DFI_PHYUPD_REQ;
|
|
output AXI_01_DFI_PHY_LP_STATE;
|
|
output AXI_01_DFI_RST_N_BUF;
|
|
output [255:0] AXI_01_RDATA;
|
|
output [31:0] AXI_01_RDATA_PARITY;
|
|
output [5:0] AXI_01_RID;
|
|
output AXI_01_RLAST;
|
|
output [1:0] AXI_01_RRESP;
|
|
output AXI_01_RVALID;
|
|
output AXI_01_WREADY;
|
|
output AXI_02_ARREADY;
|
|
output AXI_02_AWREADY;
|
|
output [5:0] AXI_02_BID;
|
|
output [1:0] AXI_02_BRESP;
|
|
output AXI_02_BVALID;
|
|
output [1:0] AXI_02_DFI_AW_AERR_N;
|
|
output AXI_02_DFI_CLK_BUF;
|
|
output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_02_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_02_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_02_DFI_DW_RDDATA_VALID;
|
|
output AXI_02_DFI_INIT_COMPLETE;
|
|
output AXI_02_DFI_PHYUPD_REQ;
|
|
output AXI_02_DFI_PHY_LP_STATE;
|
|
output AXI_02_DFI_RST_N_BUF;
|
|
output [5:0] AXI_02_MC_STATUS;
|
|
output [7:0] AXI_02_PHY_STATUS;
|
|
output [255:0] AXI_02_RDATA;
|
|
output [31:0] AXI_02_RDATA_PARITY;
|
|
output [5:0] AXI_02_RID;
|
|
output AXI_02_RLAST;
|
|
output [1:0] AXI_02_RRESP;
|
|
output AXI_02_RVALID;
|
|
output AXI_02_WREADY;
|
|
output AXI_03_ARREADY;
|
|
output AXI_03_AWREADY;
|
|
output [5:0] AXI_03_BID;
|
|
output [1:0] AXI_03_BRESP;
|
|
output AXI_03_BVALID;
|
|
output [1:0] AXI_03_DFI_AW_AERR_N;
|
|
output AXI_03_DFI_CLK_BUF;
|
|
output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_03_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_03_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_03_DFI_DW_RDDATA_VALID;
|
|
output AXI_03_DFI_INIT_COMPLETE;
|
|
output AXI_03_DFI_PHYUPD_REQ;
|
|
output AXI_03_DFI_PHY_LP_STATE;
|
|
output AXI_03_DFI_RST_N_BUF;
|
|
output [255:0] AXI_03_RDATA;
|
|
output [31:0] AXI_03_RDATA_PARITY;
|
|
output [5:0] AXI_03_RID;
|
|
output AXI_03_RLAST;
|
|
output [1:0] AXI_03_RRESP;
|
|
output AXI_03_RVALID;
|
|
output AXI_03_WREADY;
|
|
output AXI_04_ARREADY;
|
|
output AXI_04_AWREADY;
|
|
output [5:0] AXI_04_BID;
|
|
output [1:0] AXI_04_BRESP;
|
|
output AXI_04_BVALID;
|
|
output [1:0] AXI_04_DFI_AW_AERR_N;
|
|
output AXI_04_DFI_CLK_BUF;
|
|
output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_04_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_04_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_04_DFI_DW_RDDATA_VALID;
|
|
output AXI_04_DFI_INIT_COMPLETE;
|
|
output AXI_04_DFI_PHYUPD_REQ;
|
|
output AXI_04_DFI_PHY_LP_STATE;
|
|
output AXI_04_DFI_RST_N_BUF;
|
|
output [5:0] AXI_04_MC_STATUS;
|
|
output [7:0] AXI_04_PHY_STATUS;
|
|
output [255:0] AXI_04_RDATA;
|
|
output [31:0] AXI_04_RDATA_PARITY;
|
|
output [5:0] AXI_04_RID;
|
|
output AXI_04_RLAST;
|
|
output [1:0] AXI_04_RRESP;
|
|
output AXI_04_RVALID;
|
|
output AXI_04_WREADY;
|
|
output AXI_05_ARREADY;
|
|
output AXI_05_AWREADY;
|
|
output [5:0] AXI_05_BID;
|
|
output [1:0] AXI_05_BRESP;
|
|
output AXI_05_BVALID;
|
|
output [1:0] AXI_05_DFI_AW_AERR_N;
|
|
output AXI_05_DFI_CLK_BUF;
|
|
output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_05_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_05_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_05_DFI_DW_RDDATA_VALID;
|
|
output AXI_05_DFI_INIT_COMPLETE;
|
|
output AXI_05_DFI_PHYUPD_REQ;
|
|
output AXI_05_DFI_PHY_LP_STATE;
|
|
output AXI_05_DFI_RST_N_BUF;
|
|
output [255:0] AXI_05_RDATA;
|
|
output [31:0] AXI_05_RDATA_PARITY;
|
|
output [5:0] AXI_05_RID;
|
|
output AXI_05_RLAST;
|
|
output [1:0] AXI_05_RRESP;
|
|
output AXI_05_RVALID;
|
|
output AXI_05_WREADY;
|
|
output AXI_06_ARREADY;
|
|
output AXI_06_AWREADY;
|
|
output [5:0] AXI_06_BID;
|
|
output [1:0] AXI_06_BRESP;
|
|
output AXI_06_BVALID;
|
|
output [1:0] AXI_06_DFI_AW_AERR_N;
|
|
output AXI_06_DFI_CLK_BUF;
|
|
output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_06_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_06_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_06_DFI_DW_RDDATA_VALID;
|
|
output AXI_06_DFI_INIT_COMPLETE;
|
|
output AXI_06_DFI_PHYUPD_REQ;
|
|
output AXI_06_DFI_PHY_LP_STATE;
|
|
output AXI_06_DFI_RST_N_BUF;
|
|
output [5:0] AXI_06_MC_STATUS;
|
|
output [7:0] AXI_06_PHY_STATUS;
|
|
output [255:0] AXI_06_RDATA;
|
|
output [31:0] AXI_06_RDATA_PARITY;
|
|
output [5:0] AXI_06_RID;
|
|
output AXI_06_RLAST;
|
|
output [1:0] AXI_06_RRESP;
|
|
output AXI_06_RVALID;
|
|
output AXI_06_WREADY;
|
|
output AXI_07_ARREADY;
|
|
output AXI_07_AWREADY;
|
|
output [5:0] AXI_07_BID;
|
|
output [1:0] AXI_07_BRESP;
|
|
output AXI_07_BVALID;
|
|
output [1:0] AXI_07_DFI_AW_AERR_N;
|
|
output AXI_07_DFI_CLK_BUF;
|
|
output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_07_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_07_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_07_DFI_DW_RDDATA_VALID;
|
|
output AXI_07_DFI_INIT_COMPLETE;
|
|
output AXI_07_DFI_PHYUPD_REQ;
|
|
output AXI_07_DFI_PHY_LP_STATE;
|
|
output AXI_07_DFI_RST_N_BUF;
|
|
output [255:0] AXI_07_RDATA;
|
|
output [31:0] AXI_07_RDATA_PARITY;
|
|
output [5:0] AXI_07_RID;
|
|
output AXI_07_RLAST;
|
|
output [1:0] AXI_07_RRESP;
|
|
output AXI_07_RVALID;
|
|
output AXI_07_WREADY;
|
|
output AXI_08_ARREADY;
|
|
output AXI_08_AWREADY;
|
|
output [5:0] AXI_08_BID;
|
|
output [1:0] AXI_08_BRESP;
|
|
output AXI_08_BVALID;
|
|
output [1:0] AXI_08_DFI_AW_AERR_N;
|
|
output AXI_08_DFI_CLK_BUF;
|
|
output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_08_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_08_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_08_DFI_DW_RDDATA_VALID;
|
|
output AXI_08_DFI_INIT_COMPLETE;
|
|
output AXI_08_DFI_PHYUPD_REQ;
|
|
output AXI_08_DFI_PHY_LP_STATE;
|
|
output AXI_08_DFI_RST_N_BUF;
|
|
output [5:0] AXI_08_MC_STATUS;
|
|
output [7:0] AXI_08_PHY_STATUS;
|
|
output [255:0] AXI_08_RDATA;
|
|
output [31:0] AXI_08_RDATA_PARITY;
|
|
output [5:0] AXI_08_RID;
|
|
output AXI_08_RLAST;
|
|
output [1:0] AXI_08_RRESP;
|
|
output AXI_08_RVALID;
|
|
output AXI_08_WREADY;
|
|
output AXI_09_ARREADY;
|
|
output AXI_09_AWREADY;
|
|
output [5:0] AXI_09_BID;
|
|
output [1:0] AXI_09_BRESP;
|
|
output AXI_09_BVALID;
|
|
output [1:0] AXI_09_DFI_AW_AERR_N;
|
|
output AXI_09_DFI_CLK_BUF;
|
|
output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_09_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_09_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_09_DFI_DW_RDDATA_VALID;
|
|
output AXI_09_DFI_INIT_COMPLETE;
|
|
output AXI_09_DFI_PHYUPD_REQ;
|
|
output AXI_09_DFI_PHY_LP_STATE;
|
|
output AXI_09_DFI_RST_N_BUF;
|
|
output [255:0] AXI_09_RDATA;
|
|
output [31:0] AXI_09_RDATA_PARITY;
|
|
output [5:0] AXI_09_RID;
|
|
output AXI_09_RLAST;
|
|
output [1:0] AXI_09_RRESP;
|
|
output AXI_09_RVALID;
|
|
output AXI_09_WREADY;
|
|
output AXI_10_ARREADY;
|
|
output AXI_10_AWREADY;
|
|
output [5:0] AXI_10_BID;
|
|
output [1:0] AXI_10_BRESP;
|
|
output AXI_10_BVALID;
|
|
output [1:0] AXI_10_DFI_AW_AERR_N;
|
|
output AXI_10_DFI_CLK_BUF;
|
|
output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_10_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_10_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_10_DFI_DW_RDDATA_VALID;
|
|
output AXI_10_DFI_INIT_COMPLETE;
|
|
output AXI_10_DFI_PHYUPD_REQ;
|
|
output AXI_10_DFI_PHY_LP_STATE;
|
|
output AXI_10_DFI_RST_N_BUF;
|
|
output [5:0] AXI_10_MC_STATUS;
|
|
output [7:0] AXI_10_PHY_STATUS;
|
|
output [255:0] AXI_10_RDATA;
|
|
output [31:0] AXI_10_RDATA_PARITY;
|
|
output [5:0] AXI_10_RID;
|
|
output AXI_10_RLAST;
|
|
output [1:0] AXI_10_RRESP;
|
|
output AXI_10_RVALID;
|
|
output AXI_10_WREADY;
|
|
output AXI_11_ARREADY;
|
|
output AXI_11_AWREADY;
|
|
output [5:0] AXI_11_BID;
|
|
output [1:0] AXI_11_BRESP;
|
|
output AXI_11_BVALID;
|
|
output [1:0] AXI_11_DFI_AW_AERR_N;
|
|
output AXI_11_DFI_CLK_BUF;
|
|
output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_11_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_11_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_11_DFI_DW_RDDATA_VALID;
|
|
output AXI_11_DFI_INIT_COMPLETE;
|
|
output AXI_11_DFI_PHYUPD_REQ;
|
|
output AXI_11_DFI_PHY_LP_STATE;
|
|
output AXI_11_DFI_RST_N_BUF;
|
|
output [255:0] AXI_11_RDATA;
|
|
output [31:0] AXI_11_RDATA_PARITY;
|
|
output [5:0] AXI_11_RID;
|
|
output AXI_11_RLAST;
|
|
output [1:0] AXI_11_RRESP;
|
|
output AXI_11_RVALID;
|
|
output AXI_11_WREADY;
|
|
output AXI_12_ARREADY;
|
|
output AXI_12_AWREADY;
|
|
output [5:0] AXI_12_BID;
|
|
output [1:0] AXI_12_BRESP;
|
|
output AXI_12_BVALID;
|
|
output [1:0] AXI_12_DFI_AW_AERR_N;
|
|
output AXI_12_DFI_CLK_BUF;
|
|
output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_12_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_12_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_12_DFI_DW_RDDATA_VALID;
|
|
output AXI_12_DFI_INIT_COMPLETE;
|
|
output AXI_12_DFI_PHYUPD_REQ;
|
|
output AXI_12_DFI_PHY_LP_STATE;
|
|
output AXI_12_DFI_RST_N_BUF;
|
|
output [5:0] AXI_12_MC_STATUS;
|
|
output [7:0] AXI_12_PHY_STATUS;
|
|
output [255:0] AXI_12_RDATA;
|
|
output [31:0] AXI_12_RDATA_PARITY;
|
|
output [5:0] AXI_12_RID;
|
|
output AXI_12_RLAST;
|
|
output [1:0] AXI_12_RRESP;
|
|
output AXI_12_RVALID;
|
|
output AXI_12_WREADY;
|
|
output AXI_13_ARREADY;
|
|
output AXI_13_AWREADY;
|
|
output [5:0] AXI_13_BID;
|
|
output [1:0] AXI_13_BRESP;
|
|
output AXI_13_BVALID;
|
|
output [1:0] AXI_13_DFI_AW_AERR_N;
|
|
output AXI_13_DFI_CLK_BUF;
|
|
output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_13_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_13_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_13_DFI_DW_RDDATA_VALID;
|
|
output AXI_13_DFI_INIT_COMPLETE;
|
|
output AXI_13_DFI_PHYUPD_REQ;
|
|
output AXI_13_DFI_PHY_LP_STATE;
|
|
output AXI_13_DFI_RST_N_BUF;
|
|
output [255:0] AXI_13_RDATA;
|
|
output [31:0] AXI_13_RDATA_PARITY;
|
|
output [5:0] AXI_13_RID;
|
|
output AXI_13_RLAST;
|
|
output [1:0] AXI_13_RRESP;
|
|
output AXI_13_RVALID;
|
|
output AXI_13_WREADY;
|
|
output AXI_14_ARREADY;
|
|
output AXI_14_AWREADY;
|
|
output [5:0] AXI_14_BID;
|
|
output [1:0] AXI_14_BRESP;
|
|
output AXI_14_BVALID;
|
|
output [1:0] AXI_14_DFI_AW_AERR_N;
|
|
output AXI_14_DFI_CLK_BUF;
|
|
output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_14_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_14_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_14_DFI_DW_RDDATA_VALID;
|
|
output AXI_14_DFI_INIT_COMPLETE;
|
|
output AXI_14_DFI_PHYUPD_REQ;
|
|
output AXI_14_DFI_PHY_LP_STATE;
|
|
output AXI_14_DFI_RST_N_BUF;
|
|
output [5:0] AXI_14_MC_STATUS;
|
|
output [7:0] AXI_14_PHY_STATUS;
|
|
output [255:0] AXI_14_RDATA;
|
|
output [31:0] AXI_14_RDATA_PARITY;
|
|
output [5:0] AXI_14_RID;
|
|
output AXI_14_RLAST;
|
|
output [1:0] AXI_14_RRESP;
|
|
output AXI_14_RVALID;
|
|
output AXI_14_WREADY;
|
|
output AXI_15_ARREADY;
|
|
output AXI_15_AWREADY;
|
|
output [5:0] AXI_15_BID;
|
|
output [1:0] AXI_15_BRESP;
|
|
output AXI_15_BVALID;
|
|
output [1:0] AXI_15_DFI_AW_AERR_N;
|
|
output AXI_15_DFI_CLK_BUF;
|
|
output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_15_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_15_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_15_DFI_DW_RDDATA_VALID;
|
|
output AXI_15_DFI_INIT_COMPLETE;
|
|
output AXI_15_DFI_PHYUPD_REQ;
|
|
output AXI_15_DFI_PHY_LP_STATE;
|
|
output AXI_15_DFI_RST_N_BUF;
|
|
output [255:0] AXI_15_RDATA;
|
|
output [31:0] AXI_15_RDATA_PARITY;
|
|
output [5:0] AXI_15_RID;
|
|
output AXI_15_RLAST;
|
|
output [1:0] AXI_15_RRESP;
|
|
output AXI_15_RVALID;
|
|
output AXI_15_WREADY;
|
|
output DRAM_0_STAT_CATTRIP;
|
|
output [2:0] DRAM_0_STAT_TEMP;
|
|
input [21:0] APB_0_PADDR;
|
|
(* invertible_pin = "IS_APB_0_PCLK_INVERTED" *)
|
|
input APB_0_PCLK;
|
|
input APB_0_PENABLE;
|
|
(* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *)
|
|
input APB_0_PRESET_N;
|
|
input APB_0_PSEL;
|
|
input [31:0] APB_0_PWDATA;
|
|
input APB_0_PWRITE;
|
|
(* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *)
|
|
input AXI_00_ACLK;
|
|
input [36:0] AXI_00_ARADDR;
|
|
input [1:0] AXI_00_ARBURST;
|
|
(* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *)
|
|
input AXI_00_ARESET_N;
|
|
input [5:0] AXI_00_ARID;
|
|
input [3:0] AXI_00_ARLEN;
|
|
input [2:0] AXI_00_ARSIZE;
|
|
input AXI_00_ARVALID;
|
|
input [36:0] AXI_00_AWADDR;
|
|
input [1:0] AXI_00_AWBURST;
|
|
input [5:0] AXI_00_AWID;
|
|
input [3:0] AXI_00_AWLEN;
|
|
input [2:0] AXI_00_AWSIZE;
|
|
input AXI_00_AWVALID;
|
|
input AXI_00_BREADY;
|
|
input AXI_00_DFI_LP_PWR_X_REQ;
|
|
input AXI_00_RREADY;
|
|
input [255:0] AXI_00_WDATA;
|
|
input [31:0] AXI_00_WDATA_PARITY;
|
|
input AXI_00_WLAST;
|
|
input [31:0] AXI_00_WSTRB;
|
|
input AXI_00_WVALID;
|
|
(* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *)
|
|
input AXI_01_ACLK;
|
|
input [36:0] AXI_01_ARADDR;
|
|
input [1:0] AXI_01_ARBURST;
|
|
(* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *)
|
|
input AXI_01_ARESET_N;
|
|
input [5:0] AXI_01_ARID;
|
|
input [3:0] AXI_01_ARLEN;
|
|
input [2:0] AXI_01_ARSIZE;
|
|
input AXI_01_ARVALID;
|
|
input [36:0] AXI_01_AWADDR;
|
|
input [1:0] AXI_01_AWBURST;
|
|
input [5:0] AXI_01_AWID;
|
|
input [3:0] AXI_01_AWLEN;
|
|
input [2:0] AXI_01_AWSIZE;
|
|
input AXI_01_AWVALID;
|
|
input AXI_01_BREADY;
|
|
input AXI_01_DFI_LP_PWR_X_REQ;
|
|
input AXI_01_RREADY;
|
|
input [255:0] AXI_01_WDATA;
|
|
input [31:0] AXI_01_WDATA_PARITY;
|
|
input AXI_01_WLAST;
|
|
input [31:0] AXI_01_WSTRB;
|
|
input AXI_01_WVALID;
|
|
(* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *)
|
|
input AXI_02_ACLK;
|
|
input [36:0] AXI_02_ARADDR;
|
|
input [1:0] AXI_02_ARBURST;
|
|
(* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *)
|
|
input AXI_02_ARESET_N;
|
|
input [5:0] AXI_02_ARID;
|
|
input [3:0] AXI_02_ARLEN;
|
|
input [2:0] AXI_02_ARSIZE;
|
|
input AXI_02_ARVALID;
|
|
input [36:0] AXI_02_AWADDR;
|
|
input [1:0] AXI_02_AWBURST;
|
|
input [5:0] AXI_02_AWID;
|
|
input [3:0] AXI_02_AWLEN;
|
|
input [2:0] AXI_02_AWSIZE;
|
|
input AXI_02_AWVALID;
|
|
input AXI_02_BREADY;
|
|
input AXI_02_DFI_LP_PWR_X_REQ;
|
|
input AXI_02_RREADY;
|
|
input [255:0] AXI_02_WDATA;
|
|
input [31:0] AXI_02_WDATA_PARITY;
|
|
input AXI_02_WLAST;
|
|
input [31:0] AXI_02_WSTRB;
|
|
input AXI_02_WVALID;
|
|
(* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *)
|
|
input AXI_03_ACLK;
|
|
input [36:0] AXI_03_ARADDR;
|
|
input [1:0] AXI_03_ARBURST;
|
|
(* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *)
|
|
input AXI_03_ARESET_N;
|
|
input [5:0] AXI_03_ARID;
|
|
input [3:0] AXI_03_ARLEN;
|
|
input [2:0] AXI_03_ARSIZE;
|
|
input AXI_03_ARVALID;
|
|
input [36:0] AXI_03_AWADDR;
|
|
input [1:0] AXI_03_AWBURST;
|
|
input [5:0] AXI_03_AWID;
|
|
input [3:0] AXI_03_AWLEN;
|
|
input [2:0] AXI_03_AWSIZE;
|
|
input AXI_03_AWVALID;
|
|
input AXI_03_BREADY;
|
|
input AXI_03_DFI_LP_PWR_X_REQ;
|
|
input AXI_03_RREADY;
|
|
input [255:0] AXI_03_WDATA;
|
|
input [31:0] AXI_03_WDATA_PARITY;
|
|
input AXI_03_WLAST;
|
|
input [31:0] AXI_03_WSTRB;
|
|
input AXI_03_WVALID;
|
|
(* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *)
|
|
input AXI_04_ACLK;
|
|
input [36:0] AXI_04_ARADDR;
|
|
input [1:0] AXI_04_ARBURST;
|
|
(* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *)
|
|
input AXI_04_ARESET_N;
|
|
input [5:0] AXI_04_ARID;
|
|
input [3:0] AXI_04_ARLEN;
|
|
input [2:0] AXI_04_ARSIZE;
|
|
input AXI_04_ARVALID;
|
|
input [36:0] AXI_04_AWADDR;
|
|
input [1:0] AXI_04_AWBURST;
|
|
input [5:0] AXI_04_AWID;
|
|
input [3:0] AXI_04_AWLEN;
|
|
input [2:0] AXI_04_AWSIZE;
|
|
input AXI_04_AWVALID;
|
|
input AXI_04_BREADY;
|
|
input AXI_04_DFI_LP_PWR_X_REQ;
|
|
input AXI_04_RREADY;
|
|
input [255:0] AXI_04_WDATA;
|
|
input [31:0] AXI_04_WDATA_PARITY;
|
|
input AXI_04_WLAST;
|
|
input [31:0] AXI_04_WSTRB;
|
|
input AXI_04_WVALID;
|
|
(* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *)
|
|
input AXI_05_ACLK;
|
|
input [36:0] AXI_05_ARADDR;
|
|
input [1:0] AXI_05_ARBURST;
|
|
(* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *)
|
|
input AXI_05_ARESET_N;
|
|
input [5:0] AXI_05_ARID;
|
|
input [3:0] AXI_05_ARLEN;
|
|
input [2:0] AXI_05_ARSIZE;
|
|
input AXI_05_ARVALID;
|
|
input [36:0] AXI_05_AWADDR;
|
|
input [1:0] AXI_05_AWBURST;
|
|
input [5:0] AXI_05_AWID;
|
|
input [3:0] AXI_05_AWLEN;
|
|
input [2:0] AXI_05_AWSIZE;
|
|
input AXI_05_AWVALID;
|
|
input AXI_05_BREADY;
|
|
input AXI_05_DFI_LP_PWR_X_REQ;
|
|
input AXI_05_RREADY;
|
|
input [255:0] AXI_05_WDATA;
|
|
input [31:0] AXI_05_WDATA_PARITY;
|
|
input AXI_05_WLAST;
|
|
input [31:0] AXI_05_WSTRB;
|
|
input AXI_05_WVALID;
|
|
(* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *)
|
|
input AXI_06_ACLK;
|
|
input [36:0] AXI_06_ARADDR;
|
|
input [1:0] AXI_06_ARBURST;
|
|
(* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *)
|
|
input AXI_06_ARESET_N;
|
|
input [5:0] AXI_06_ARID;
|
|
input [3:0] AXI_06_ARLEN;
|
|
input [2:0] AXI_06_ARSIZE;
|
|
input AXI_06_ARVALID;
|
|
input [36:0] AXI_06_AWADDR;
|
|
input [1:0] AXI_06_AWBURST;
|
|
input [5:0] AXI_06_AWID;
|
|
input [3:0] AXI_06_AWLEN;
|
|
input [2:0] AXI_06_AWSIZE;
|
|
input AXI_06_AWVALID;
|
|
input AXI_06_BREADY;
|
|
input AXI_06_DFI_LP_PWR_X_REQ;
|
|
input AXI_06_RREADY;
|
|
input [255:0] AXI_06_WDATA;
|
|
input [31:0] AXI_06_WDATA_PARITY;
|
|
input AXI_06_WLAST;
|
|
input [31:0] AXI_06_WSTRB;
|
|
input AXI_06_WVALID;
|
|
(* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *)
|
|
input AXI_07_ACLK;
|
|
input [36:0] AXI_07_ARADDR;
|
|
input [1:0] AXI_07_ARBURST;
|
|
(* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *)
|
|
input AXI_07_ARESET_N;
|
|
input [5:0] AXI_07_ARID;
|
|
input [3:0] AXI_07_ARLEN;
|
|
input [2:0] AXI_07_ARSIZE;
|
|
input AXI_07_ARVALID;
|
|
input [36:0] AXI_07_AWADDR;
|
|
input [1:0] AXI_07_AWBURST;
|
|
input [5:0] AXI_07_AWID;
|
|
input [3:0] AXI_07_AWLEN;
|
|
input [2:0] AXI_07_AWSIZE;
|
|
input AXI_07_AWVALID;
|
|
input AXI_07_BREADY;
|
|
input AXI_07_DFI_LP_PWR_X_REQ;
|
|
input AXI_07_RREADY;
|
|
input [255:0] AXI_07_WDATA;
|
|
input [31:0] AXI_07_WDATA_PARITY;
|
|
input AXI_07_WLAST;
|
|
input [31:0] AXI_07_WSTRB;
|
|
input AXI_07_WVALID;
|
|
(* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *)
|
|
input AXI_08_ACLK;
|
|
input [36:0] AXI_08_ARADDR;
|
|
input [1:0] AXI_08_ARBURST;
|
|
(* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *)
|
|
input AXI_08_ARESET_N;
|
|
input [5:0] AXI_08_ARID;
|
|
input [3:0] AXI_08_ARLEN;
|
|
input [2:0] AXI_08_ARSIZE;
|
|
input AXI_08_ARVALID;
|
|
input [36:0] AXI_08_AWADDR;
|
|
input [1:0] AXI_08_AWBURST;
|
|
input [5:0] AXI_08_AWID;
|
|
input [3:0] AXI_08_AWLEN;
|
|
input [2:0] AXI_08_AWSIZE;
|
|
input AXI_08_AWVALID;
|
|
input AXI_08_BREADY;
|
|
input AXI_08_DFI_LP_PWR_X_REQ;
|
|
input AXI_08_RREADY;
|
|
input [255:0] AXI_08_WDATA;
|
|
input [31:0] AXI_08_WDATA_PARITY;
|
|
input AXI_08_WLAST;
|
|
input [31:0] AXI_08_WSTRB;
|
|
input AXI_08_WVALID;
|
|
(* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *)
|
|
input AXI_09_ACLK;
|
|
input [36:0] AXI_09_ARADDR;
|
|
input [1:0] AXI_09_ARBURST;
|
|
(* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *)
|
|
input AXI_09_ARESET_N;
|
|
input [5:0] AXI_09_ARID;
|
|
input [3:0] AXI_09_ARLEN;
|
|
input [2:0] AXI_09_ARSIZE;
|
|
input AXI_09_ARVALID;
|
|
input [36:0] AXI_09_AWADDR;
|
|
input [1:0] AXI_09_AWBURST;
|
|
input [5:0] AXI_09_AWID;
|
|
input [3:0] AXI_09_AWLEN;
|
|
input [2:0] AXI_09_AWSIZE;
|
|
input AXI_09_AWVALID;
|
|
input AXI_09_BREADY;
|
|
input AXI_09_DFI_LP_PWR_X_REQ;
|
|
input AXI_09_RREADY;
|
|
input [255:0] AXI_09_WDATA;
|
|
input [31:0] AXI_09_WDATA_PARITY;
|
|
input AXI_09_WLAST;
|
|
input [31:0] AXI_09_WSTRB;
|
|
input AXI_09_WVALID;
|
|
(* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *)
|
|
input AXI_10_ACLK;
|
|
input [36:0] AXI_10_ARADDR;
|
|
input [1:0] AXI_10_ARBURST;
|
|
(* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *)
|
|
input AXI_10_ARESET_N;
|
|
input [5:0] AXI_10_ARID;
|
|
input [3:0] AXI_10_ARLEN;
|
|
input [2:0] AXI_10_ARSIZE;
|
|
input AXI_10_ARVALID;
|
|
input [36:0] AXI_10_AWADDR;
|
|
input [1:0] AXI_10_AWBURST;
|
|
input [5:0] AXI_10_AWID;
|
|
input [3:0] AXI_10_AWLEN;
|
|
input [2:0] AXI_10_AWSIZE;
|
|
input AXI_10_AWVALID;
|
|
input AXI_10_BREADY;
|
|
input AXI_10_DFI_LP_PWR_X_REQ;
|
|
input AXI_10_RREADY;
|
|
input [255:0] AXI_10_WDATA;
|
|
input [31:0] AXI_10_WDATA_PARITY;
|
|
input AXI_10_WLAST;
|
|
input [31:0] AXI_10_WSTRB;
|
|
input AXI_10_WVALID;
|
|
(* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *)
|
|
input AXI_11_ACLK;
|
|
input [36:0] AXI_11_ARADDR;
|
|
input [1:0] AXI_11_ARBURST;
|
|
(* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *)
|
|
input AXI_11_ARESET_N;
|
|
input [5:0] AXI_11_ARID;
|
|
input [3:0] AXI_11_ARLEN;
|
|
input [2:0] AXI_11_ARSIZE;
|
|
input AXI_11_ARVALID;
|
|
input [36:0] AXI_11_AWADDR;
|
|
input [1:0] AXI_11_AWBURST;
|
|
input [5:0] AXI_11_AWID;
|
|
input [3:0] AXI_11_AWLEN;
|
|
input [2:0] AXI_11_AWSIZE;
|
|
input AXI_11_AWVALID;
|
|
input AXI_11_BREADY;
|
|
input AXI_11_DFI_LP_PWR_X_REQ;
|
|
input AXI_11_RREADY;
|
|
input [255:0] AXI_11_WDATA;
|
|
input [31:0] AXI_11_WDATA_PARITY;
|
|
input AXI_11_WLAST;
|
|
input [31:0] AXI_11_WSTRB;
|
|
input AXI_11_WVALID;
|
|
(* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *)
|
|
input AXI_12_ACLK;
|
|
input [36:0] AXI_12_ARADDR;
|
|
input [1:0] AXI_12_ARBURST;
|
|
(* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *)
|
|
input AXI_12_ARESET_N;
|
|
input [5:0] AXI_12_ARID;
|
|
input [3:0] AXI_12_ARLEN;
|
|
input [2:0] AXI_12_ARSIZE;
|
|
input AXI_12_ARVALID;
|
|
input [36:0] AXI_12_AWADDR;
|
|
input [1:0] AXI_12_AWBURST;
|
|
input [5:0] AXI_12_AWID;
|
|
input [3:0] AXI_12_AWLEN;
|
|
input [2:0] AXI_12_AWSIZE;
|
|
input AXI_12_AWVALID;
|
|
input AXI_12_BREADY;
|
|
input AXI_12_DFI_LP_PWR_X_REQ;
|
|
input AXI_12_RREADY;
|
|
input [255:0] AXI_12_WDATA;
|
|
input [31:0] AXI_12_WDATA_PARITY;
|
|
input AXI_12_WLAST;
|
|
input [31:0] AXI_12_WSTRB;
|
|
input AXI_12_WVALID;
|
|
(* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *)
|
|
input AXI_13_ACLK;
|
|
input [36:0] AXI_13_ARADDR;
|
|
input [1:0] AXI_13_ARBURST;
|
|
(* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *)
|
|
input AXI_13_ARESET_N;
|
|
input [5:0] AXI_13_ARID;
|
|
input [3:0] AXI_13_ARLEN;
|
|
input [2:0] AXI_13_ARSIZE;
|
|
input AXI_13_ARVALID;
|
|
input [36:0] AXI_13_AWADDR;
|
|
input [1:0] AXI_13_AWBURST;
|
|
input [5:0] AXI_13_AWID;
|
|
input [3:0] AXI_13_AWLEN;
|
|
input [2:0] AXI_13_AWSIZE;
|
|
input AXI_13_AWVALID;
|
|
input AXI_13_BREADY;
|
|
input AXI_13_DFI_LP_PWR_X_REQ;
|
|
input AXI_13_RREADY;
|
|
input [255:0] AXI_13_WDATA;
|
|
input [31:0] AXI_13_WDATA_PARITY;
|
|
input AXI_13_WLAST;
|
|
input [31:0] AXI_13_WSTRB;
|
|
input AXI_13_WVALID;
|
|
(* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *)
|
|
input AXI_14_ACLK;
|
|
input [36:0] AXI_14_ARADDR;
|
|
input [1:0] AXI_14_ARBURST;
|
|
(* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *)
|
|
input AXI_14_ARESET_N;
|
|
input [5:0] AXI_14_ARID;
|
|
input [3:0] AXI_14_ARLEN;
|
|
input [2:0] AXI_14_ARSIZE;
|
|
input AXI_14_ARVALID;
|
|
input [36:0] AXI_14_AWADDR;
|
|
input [1:0] AXI_14_AWBURST;
|
|
input [5:0] AXI_14_AWID;
|
|
input [3:0] AXI_14_AWLEN;
|
|
input [2:0] AXI_14_AWSIZE;
|
|
input AXI_14_AWVALID;
|
|
input AXI_14_BREADY;
|
|
input AXI_14_DFI_LP_PWR_X_REQ;
|
|
input AXI_14_RREADY;
|
|
input [255:0] AXI_14_WDATA;
|
|
input [31:0] AXI_14_WDATA_PARITY;
|
|
input AXI_14_WLAST;
|
|
input [31:0] AXI_14_WSTRB;
|
|
input AXI_14_WVALID;
|
|
(* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *)
|
|
input AXI_15_ACLK;
|
|
input [36:0] AXI_15_ARADDR;
|
|
input [1:0] AXI_15_ARBURST;
|
|
(* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *)
|
|
input AXI_15_ARESET_N;
|
|
input [5:0] AXI_15_ARID;
|
|
input [3:0] AXI_15_ARLEN;
|
|
input [2:0] AXI_15_ARSIZE;
|
|
input AXI_15_ARVALID;
|
|
input [36:0] AXI_15_AWADDR;
|
|
input [1:0] AXI_15_AWBURST;
|
|
input [5:0] AXI_15_AWID;
|
|
input [3:0] AXI_15_AWLEN;
|
|
input [2:0] AXI_15_AWSIZE;
|
|
input AXI_15_AWVALID;
|
|
input AXI_15_BREADY;
|
|
input AXI_15_DFI_LP_PWR_X_REQ;
|
|
input AXI_15_RREADY;
|
|
input [255:0] AXI_15_WDATA;
|
|
input [31:0] AXI_15_WDATA_PARITY;
|
|
input AXI_15_WLAST;
|
|
input [31:0] AXI_15_WSTRB;
|
|
input AXI_15_WVALID;
|
|
input BSCAN_DRCK;
|
|
input BSCAN_TCK;
|
|
input HBM_REF_CLK;
|
|
input MBIST_EN_00;
|
|
input MBIST_EN_01;
|
|
input MBIST_EN_02;
|
|
input MBIST_EN_03;
|
|
input MBIST_EN_04;
|
|
input MBIST_EN_05;
|
|
input MBIST_EN_06;
|
|
input MBIST_EN_07;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module HBM_TWO_STACK_INTF(APB_0_PRDATA, APB_0_PREADY, APB_0_PSLVERR, APB_1_PRDATA, APB_1_PREADY, APB_1_PSLVERR, AXI_00_ARREADY, AXI_00_AWREADY, AXI_00_BID, AXI_00_BRESP, AXI_00_BVALID, AXI_00_DFI_AW_AERR_N, AXI_00_DFI_CLK_BUF, AXI_00_DFI_DBI_BYTE_DISABLE, AXI_00_DFI_DW_RDDATA_DBI, AXI_00_DFI_DW_RDDATA_DERR, AXI_00_DFI_DW_RDDATA_VALID, AXI_00_DFI_INIT_COMPLETE, AXI_00_DFI_PHYUPD_REQ, AXI_00_DFI_PHY_LP_STATE, AXI_00_DFI_RST_N_BUF
|
|
, AXI_00_MC_STATUS, AXI_00_PHY_STATUS, AXI_00_RDATA, AXI_00_RDATA_PARITY, AXI_00_RID, AXI_00_RLAST, AXI_00_RRESP, AXI_00_RVALID, AXI_00_WREADY, AXI_01_ARREADY, AXI_01_AWREADY, AXI_01_BID, AXI_01_BRESP, AXI_01_BVALID, AXI_01_DFI_AW_AERR_N, AXI_01_DFI_CLK_BUF, AXI_01_DFI_DBI_BYTE_DISABLE, AXI_01_DFI_DW_RDDATA_DBI, AXI_01_DFI_DW_RDDATA_DERR, AXI_01_DFI_DW_RDDATA_VALID, AXI_01_DFI_INIT_COMPLETE
|
|
, AXI_01_DFI_PHYUPD_REQ, AXI_01_DFI_PHY_LP_STATE, AXI_01_DFI_RST_N_BUF, AXI_01_RDATA, AXI_01_RDATA_PARITY, AXI_01_RID, AXI_01_RLAST, AXI_01_RRESP, AXI_01_RVALID, AXI_01_WREADY, AXI_02_ARREADY, AXI_02_AWREADY, AXI_02_BID, AXI_02_BRESP, AXI_02_BVALID, AXI_02_DFI_AW_AERR_N, AXI_02_DFI_CLK_BUF, AXI_02_DFI_DBI_BYTE_DISABLE, AXI_02_DFI_DW_RDDATA_DBI, AXI_02_DFI_DW_RDDATA_DERR, AXI_02_DFI_DW_RDDATA_VALID
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, AXI_02_DFI_INIT_COMPLETE, AXI_02_DFI_PHYUPD_REQ, AXI_02_DFI_PHY_LP_STATE, AXI_02_DFI_RST_N_BUF, AXI_02_MC_STATUS, AXI_02_PHY_STATUS, AXI_02_RDATA, AXI_02_RDATA_PARITY, AXI_02_RID, AXI_02_RLAST, AXI_02_RRESP, AXI_02_RVALID, AXI_02_WREADY, AXI_03_ARREADY, AXI_03_AWREADY, AXI_03_BID, AXI_03_BRESP, AXI_03_BVALID, AXI_03_DFI_AW_AERR_N, AXI_03_DFI_CLK_BUF, AXI_03_DFI_DBI_BYTE_DISABLE
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, AXI_03_DFI_DW_RDDATA_DBI, AXI_03_DFI_DW_RDDATA_DERR, AXI_03_DFI_DW_RDDATA_VALID, AXI_03_DFI_INIT_COMPLETE, AXI_03_DFI_PHYUPD_REQ, AXI_03_DFI_PHY_LP_STATE, AXI_03_DFI_RST_N_BUF, AXI_03_RDATA, AXI_03_RDATA_PARITY, AXI_03_RID, AXI_03_RLAST, AXI_03_RRESP, AXI_03_RVALID, AXI_03_WREADY, AXI_04_ARREADY, AXI_04_AWREADY, AXI_04_BID, AXI_04_BRESP, AXI_04_BVALID, AXI_04_DFI_AW_AERR_N, AXI_04_DFI_CLK_BUF
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, AXI_04_DFI_DBI_BYTE_DISABLE, AXI_04_DFI_DW_RDDATA_DBI, AXI_04_DFI_DW_RDDATA_DERR, AXI_04_DFI_DW_RDDATA_VALID, AXI_04_DFI_INIT_COMPLETE, AXI_04_DFI_PHYUPD_REQ, AXI_04_DFI_PHY_LP_STATE, AXI_04_DFI_RST_N_BUF, AXI_04_MC_STATUS, AXI_04_PHY_STATUS, AXI_04_RDATA, AXI_04_RDATA_PARITY, AXI_04_RID, AXI_04_RLAST, AXI_04_RRESP, AXI_04_RVALID, AXI_04_WREADY, AXI_05_ARREADY, AXI_05_AWREADY, AXI_05_BID, AXI_05_BRESP
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, AXI_05_BVALID, AXI_05_DFI_AW_AERR_N, AXI_05_DFI_CLK_BUF, AXI_05_DFI_DBI_BYTE_DISABLE, AXI_05_DFI_DW_RDDATA_DBI, AXI_05_DFI_DW_RDDATA_DERR, AXI_05_DFI_DW_RDDATA_VALID, AXI_05_DFI_INIT_COMPLETE, AXI_05_DFI_PHYUPD_REQ, AXI_05_DFI_PHY_LP_STATE, AXI_05_DFI_RST_N_BUF, AXI_05_RDATA, AXI_05_RDATA_PARITY, AXI_05_RID, AXI_05_RLAST, AXI_05_RRESP, AXI_05_RVALID, AXI_05_WREADY, AXI_06_ARREADY, AXI_06_AWREADY, AXI_06_BID
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, AXI_06_BRESP, AXI_06_BVALID, AXI_06_DFI_AW_AERR_N, AXI_06_DFI_CLK_BUF, AXI_06_DFI_DBI_BYTE_DISABLE, AXI_06_DFI_DW_RDDATA_DBI, AXI_06_DFI_DW_RDDATA_DERR, AXI_06_DFI_DW_RDDATA_VALID, AXI_06_DFI_INIT_COMPLETE, AXI_06_DFI_PHYUPD_REQ, AXI_06_DFI_PHY_LP_STATE, AXI_06_DFI_RST_N_BUF, AXI_06_MC_STATUS, AXI_06_PHY_STATUS, AXI_06_RDATA, AXI_06_RDATA_PARITY, AXI_06_RID, AXI_06_RLAST, AXI_06_RRESP, AXI_06_RVALID, AXI_06_WREADY
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, AXI_07_ARREADY, AXI_07_AWREADY, AXI_07_BID, AXI_07_BRESP, AXI_07_BVALID, AXI_07_DFI_AW_AERR_N, AXI_07_DFI_CLK_BUF, AXI_07_DFI_DBI_BYTE_DISABLE, AXI_07_DFI_DW_RDDATA_DBI, AXI_07_DFI_DW_RDDATA_DERR, AXI_07_DFI_DW_RDDATA_VALID, AXI_07_DFI_INIT_COMPLETE, AXI_07_DFI_PHYUPD_REQ, AXI_07_DFI_PHY_LP_STATE, AXI_07_DFI_RST_N_BUF, AXI_07_RDATA, AXI_07_RDATA_PARITY, AXI_07_RID, AXI_07_RLAST, AXI_07_RRESP, AXI_07_RVALID
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, AXI_07_WREADY, AXI_08_ARREADY, AXI_08_AWREADY, AXI_08_BID, AXI_08_BRESP, AXI_08_BVALID, AXI_08_DFI_AW_AERR_N, AXI_08_DFI_CLK_BUF, AXI_08_DFI_DBI_BYTE_DISABLE, AXI_08_DFI_DW_RDDATA_DBI, AXI_08_DFI_DW_RDDATA_DERR, AXI_08_DFI_DW_RDDATA_VALID, AXI_08_DFI_INIT_COMPLETE, AXI_08_DFI_PHYUPD_REQ, AXI_08_DFI_PHY_LP_STATE, AXI_08_DFI_RST_N_BUF, AXI_08_MC_STATUS, AXI_08_PHY_STATUS, AXI_08_RDATA, AXI_08_RDATA_PARITY, AXI_08_RID
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, AXI_08_RLAST, AXI_08_RRESP, AXI_08_RVALID, AXI_08_WREADY, AXI_09_ARREADY, AXI_09_AWREADY, AXI_09_BID, AXI_09_BRESP, AXI_09_BVALID, AXI_09_DFI_AW_AERR_N, AXI_09_DFI_CLK_BUF, AXI_09_DFI_DBI_BYTE_DISABLE, AXI_09_DFI_DW_RDDATA_DBI, AXI_09_DFI_DW_RDDATA_DERR, AXI_09_DFI_DW_RDDATA_VALID, AXI_09_DFI_INIT_COMPLETE, AXI_09_DFI_PHYUPD_REQ, AXI_09_DFI_PHY_LP_STATE, AXI_09_DFI_RST_N_BUF, AXI_09_RDATA, AXI_09_RDATA_PARITY
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, AXI_09_RID, AXI_09_RLAST, AXI_09_RRESP, AXI_09_RVALID, AXI_09_WREADY, AXI_10_ARREADY, AXI_10_AWREADY, AXI_10_BID, AXI_10_BRESP, AXI_10_BVALID, AXI_10_DFI_AW_AERR_N, AXI_10_DFI_CLK_BUF, AXI_10_DFI_DBI_BYTE_DISABLE, AXI_10_DFI_DW_RDDATA_DBI, AXI_10_DFI_DW_RDDATA_DERR, AXI_10_DFI_DW_RDDATA_VALID, AXI_10_DFI_INIT_COMPLETE, AXI_10_DFI_PHYUPD_REQ, AXI_10_DFI_PHY_LP_STATE, AXI_10_DFI_RST_N_BUF, AXI_10_MC_STATUS
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, AXI_10_PHY_STATUS, AXI_10_RDATA, AXI_10_RDATA_PARITY, AXI_10_RID, AXI_10_RLAST, AXI_10_RRESP, AXI_10_RVALID, AXI_10_WREADY, AXI_11_ARREADY, AXI_11_AWREADY, AXI_11_BID, AXI_11_BRESP, AXI_11_BVALID, AXI_11_DFI_AW_AERR_N, AXI_11_DFI_CLK_BUF, AXI_11_DFI_DBI_BYTE_DISABLE, AXI_11_DFI_DW_RDDATA_DBI, AXI_11_DFI_DW_RDDATA_DERR, AXI_11_DFI_DW_RDDATA_VALID, AXI_11_DFI_INIT_COMPLETE, AXI_11_DFI_PHYUPD_REQ
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, AXI_11_DFI_PHY_LP_STATE, AXI_11_DFI_RST_N_BUF, AXI_11_RDATA, AXI_11_RDATA_PARITY, AXI_11_RID, AXI_11_RLAST, AXI_11_RRESP, AXI_11_RVALID, AXI_11_WREADY, AXI_12_ARREADY, AXI_12_AWREADY, AXI_12_BID, AXI_12_BRESP, AXI_12_BVALID, AXI_12_DFI_AW_AERR_N, AXI_12_DFI_CLK_BUF, AXI_12_DFI_DBI_BYTE_DISABLE, AXI_12_DFI_DW_RDDATA_DBI, AXI_12_DFI_DW_RDDATA_DERR, AXI_12_DFI_DW_RDDATA_VALID, AXI_12_DFI_INIT_COMPLETE
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, AXI_12_DFI_PHYUPD_REQ, AXI_12_DFI_PHY_LP_STATE, AXI_12_DFI_RST_N_BUF, AXI_12_MC_STATUS, AXI_12_PHY_STATUS, AXI_12_RDATA, AXI_12_RDATA_PARITY, AXI_12_RID, AXI_12_RLAST, AXI_12_RRESP, AXI_12_RVALID, AXI_12_WREADY, AXI_13_ARREADY, AXI_13_AWREADY, AXI_13_BID, AXI_13_BRESP, AXI_13_BVALID, AXI_13_DFI_AW_AERR_N, AXI_13_DFI_CLK_BUF, AXI_13_DFI_DBI_BYTE_DISABLE, AXI_13_DFI_DW_RDDATA_DBI
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, AXI_13_DFI_DW_RDDATA_DERR, AXI_13_DFI_DW_RDDATA_VALID, AXI_13_DFI_INIT_COMPLETE, AXI_13_DFI_PHYUPD_REQ, AXI_13_DFI_PHY_LP_STATE, AXI_13_DFI_RST_N_BUF, AXI_13_RDATA, AXI_13_RDATA_PARITY, AXI_13_RID, AXI_13_RLAST, AXI_13_RRESP, AXI_13_RVALID, AXI_13_WREADY, AXI_14_ARREADY, AXI_14_AWREADY, AXI_14_BID, AXI_14_BRESP, AXI_14_BVALID, AXI_14_DFI_AW_AERR_N, AXI_14_DFI_CLK_BUF, AXI_14_DFI_DBI_BYTE_DISABLE
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, AXI_14_DFI_DW_RDDATA_DBI, AXI_14_DFI_DW_RDDATA_DERR, AXI_14_DFI_DW_RDDATA_VALID, AXI_14_DFI_INIT_COMPLETE, AXI_14_DFI_PHYUPD_REQ, AXI_14_DFI_PHY_LP_STATE, AXI_14_DFI_RST_N_BUF, AXI_14_MC_STATUS, AXI_14_PHY_STATUS, AXI_14_RDATA, AXI_14_RDATA_PARITY, AXI_14_RID, AXI_14_RLAST, AXI_14_RRESP, AXI_14_RVALID, AXI_14_WREADY, AXI_15_ARREADY, AXI_15_AWREADY, AXI_15_BID, AXI_15_BRESP, AXI_15_BVALID
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, AXI_15_DFI_AW_AERR_N, AXI_15_DFI_CLK_BUF, AXI_15_DFI_DBI_BYTE_DISABLE, AXI_15_DFI_DW_RDDATA_DBI, AXI_15_DFI_DW_RDDATA_DERR, AXI_15_DFI_DW_RDDATA_VALID, AXI_15_DFI_INIT_COMPLETE, AXI_15_DFI_PHYUPD_REQ, AXI_15_DFI_PHY_LP_STATE, AXI_15_DFI_RST_N_BUF, AXI_15_RDATA, AXI_15_RDATA_PARITY, AXI_15_RID, AXI_15_RLAST, AXI_15_RRESP, AXI_15_RVALID, AXI_15_WREADY, AXI_16_ARREADY, AXI_16_AWREADY, AXI_16_BID, AXI_16_BRESP
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, AXI_16_BVALID, AXI_16_DFI_AW_AERR_N, AXI_16_DFI_CLK_BUF, AXI_16_DFI_DBI_BYTE_DISABLE, AXI_16_DFI_DW_RDDATA_DBI, AXI_16_DFI_DW_RDDATA_DERR, AXI_16_DFI_DW_RDDATA_VALID, AXI_16_DFI_INIT_COMPLETE, AXI_16_DFI_PHYUPD_REQ, AXI_16_DFI_PHY_LP_STATE, AXI_16_DFI_RST_N_BUF, AXI_16_MC_STATUS, AXI_16_PHY_STATUS, AXI_16_RDATA, AXI_16_RDATA_PARITY, AXI_16_RID, AXI_16_RLAST, AXI_16_RRESP, AXI_16_RVALID, AXI_16_WREADY, AXI_17_ARREADY
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, AXI_17_AWREADY, AXI_17_BID, AXI_17_BRESP, AXI_17_BVALID, AXI_17_DFI_AW_AERR_N, AXI_17_DFI_CLK_BUF, AXI_17_DFI_DBI_BYTE_DISABLE, AXI_17_DFI_DW_RDDATA_DBI, AXI_17_DFI_DW_RDDATA_DERR, AXI_17_DFI_DW_RDDATA_VALID, AXI_17_DFI_INIT_COMPLETE, AXI_17_DFI_PHYUPD_REQ, AXI_17_DFI_PHY_LP_STATE, AXI_17_DFI_RST_N_BUF, AXI_17_RDATA, AXI_17_RDATA_PARITY, AXI_17_RID, AXI_17_RLAST, AXI_17_RRESP, AXI_17_RVALID, AXI_17_WREADY
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, AXI_18_ARREADY, AXI_18_AWREADY, AXI_18_BID, AXI_18_BRESP, AXI_18_BVALID, AXI_18_DFI_AW_AERR_N, AXI_18_DFI_CLK_BUF, AXI_18_DFI_DBI_BYTE_DISABLE, AXI_18_DFI_DW_RDDATA_DBI, AXI_18_DFI_DW_RDDATA_DERR, AXI_18_DFI_DW_RDDATA_VALID, AXI_18_DFI_INIT_COMPLETE, AXI_18_DFI_PHYUPD_REQ, AXI_18_DFI_PHY_LP_STATE, AXI_18_DFI_RST_N_BUF, AXI_18_MC_STATUS, AXI_18_PHY_STATUS, AXI_18_RDATA, AXI_18_RDATA_PARITY, AXI_18_RID, AXI_18_RLAST
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, AXI_18_RRESP, AXI_18_RVALID, AXI_18_WREADY, AXI_19_ARREADY, AXI_19_AWREADY, AXI_19_BID, AXI_19_BRESP, AXI_19_BVALID, AXI_19_DFI_AW_AERR_N, AXI_19_DFI_CLK_BUF, AXI_19_DFI_DBI_BYTE_DISABLE, AXI_19_DFI_DW_RDDATA_DBI, AXI_19_DFI_DW_RDDATA_DERR, AXI_19_DFI_DW_RDDATA_VALID, AXI_19_DFI_INIT_COMPLETE, AXI_19_DFI_PHYUPD_REQ, AXI_19_DFI_PHY_LP_STATE, AXI_19_DFI_RST_N_BUF, AXI_19_RDATA, AXI_19_RDATA_PARITY, AXI_19_RID
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, AXI_19_RLAST, AXI_19_RRESP, AXI_19_RVALID, AXI_19_WREADY, AXI_20_ARREADY, AXI_20_AWREADY, AXI_20_BID, AXI_20_BRESP, AXI_20_BVALID, AXI_20_DFI_AW_AERR_N, AXI_20_DFI_CLK_BUF, AXI_20_DFI_DBI_BYTE_DISABLE, AXI_20_DFI_DW_RDDATA_DBI, AXI_20_DFI_DW_RDDATA_DERR, AXI_20_DFI_DW_RDDATA_VALID, AXI_20_DFI_INIT_COMPLETE, AXI_20_DFI_PHYUPD_REQ, AXI_20_DFI_PHY_LP_STATE, AXI_20_DFI_RST_N_BUF, AXI_20_MC_STATUS, AXI_20_PHY_STATUS
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, AXI_20_RDATA, AXI_20_RDATA_PARITY, AXI_20_RID, AXI_20_RLAST, AXI_20_RRESP, AXI_20_RVALID, AXI_20_WREADY, AXI_21_ARREADY, AXI_21_AWREADY, AXI_21_BID, AXI_21_BRESP, AXI_21_BVALID, AXI_21_DFI_AW_AERR_N, AXI_21_DFI_CLK_BUF, AXI_21_DFI_DBI_BYTE_DISABLE, AXI_21_DFI_DW_RDDATA_DBI, AXI_21_DFI_DW_RDDATA_DERR, AXI_21_DFI_DW_RDDATA_VALID, AXI_21_DFI_INIT_COMPLETE, AXI_21_DFI_PHYUPD_REQ, AXI_21_DFI_PHY_LP_STATE
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, AXI_21_DFI_RST_N_BUF, AXI_21_RDATA, AXI_21_RDATA_PARITY, AXI_21_RID, AXI_21_RLAST, AXI_21_RRESP, AXI_21_RVALID, AXI_21_WREADY, AXI_22_ARREADY, AXI_22_AWREADY, AXI_22_BID, AXI_22_BRESP, AXI_22_BVALID, AXI_22_DFI_AW_AERR_N, AXI_22_DFI_CLK_BUF, AXI_22_DFI_DBI_BYTE_DISABLE, AXI_22_DFI_DW_RDDATA_DBI, AXI_22_DFI_DW_RDDATA_DERR, AXI_22_DFI_DW_RDDATA_VALID, AXI_22_DFI_INIT_COMPLETE, AXI_22_DFI_PHYUPD_REQ
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, AXI_22_DFI_PHY_LP_STATE, AXI_22_DFI_RST_N_BUF, AXI_22_MC_STATUS, AXI_22_PHY_STATUS, AXI_22_RDATA, AXI_22_RDATA_PARITY, AXI_22_RID, AXI_22_RLAST, AXI_22_RRESP, AXI_22_RVALID, AXI_22_WREADY, AXI_23_ARREADY, AXI_23_AWREADY, AXI_23_BID, AXI_23_BRESP, AXI_23_BVALID, AXI_23_DFI_AW_AERR_N, AXI_23_DFI_CLK_BUF, AXI_23_DFI_DBI_BYTE_DISABLE, AXI_23_DFI_DW_RDDATA_DBI, AXI_23_DFI_DW_RDDATA_DERR
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, AXI_23_DFI_DW_RDDATA_VALID, AXI_23_DFI_INIT_COMPLETE, AXI_23_DFI_PHYUPD_REQ, AXI_23_DFI_PHY_LP_STATE, AXI_23_DFI_RST_N_BUF, AXI_23_RDATA, AXI_23_RDATA_PARITY, AXI_23_RID, AXI_23_RLAST, AXI_23_RRESP, AXI_23_RVALID, AXI_23_WREADY, AXI_24_ARREADY, AXI_24_AWREADY, AXI_24_BID, AXI_24_BRESP, AXI_24_BVALID, AXI_24_DFI_AW_AERR_N, AXI_24_DFI_CLK_BUF, AXI_24_DFI_DBI_BYTE_DISABLE, AXI_24_DFI_DW_RDDATA_DBI
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, AXI_24_DFI_DW_RDDATA_DERR, AXI_24_DFI_DW_RDDATA_VALID, AXI_24_DFI_INIT_COMPLETE, AXI_24_DFI_PHYUPD_REQ, AXI_24_DFI_PHY_LP_STATE, AXI_24_DFI_RST_N_BUF, AXI_24_MC_STATUS, AXI_24_PHY_STATUS, AXI_24_RDATA, AXI_24_RDATA_PARITY, AXI_24_RID, AXI_24_RLAST, AXI_24_RRESP, AXI_24_RVALID, AXI_24_WREADY, AXI_25_ARREADY, AXI_25_AWREADY, AXI_25_BID, AXI_25_BRESP, AXI_25_BVALID, AXI_25_DFI_AW_AERR_N
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, AXI_25_DFI_CLK_BUF, AXI_25_DFI_DBI_BYTE_DISABLE, AXI_25_DFI_DW_RDDATA_DBI, AXI_25_DFI_DW_RDDATA_DERR, AXI_25_DFI_DW_RDDATA_VALID, AXI_25_DFI_INIT_COMPLETE, AXI_25_DFI_PHYUPD_REQ, AXI_25_DFI_PHY_LP_STATE, AXI_25_DFI_RST_N_BUF, AXI_25_RDATA, AXI_25_RDATA_PARITY, AXI_25_RID, AXI_25_RLAST, AXI_25_RRESP, AXI_25_RVALID, AXI_25_WREADY, AXI_26_ARREADY, AXI_26_AWREADY, AXI_26_BID, AXI_26_BRESP, AXI_26_BVALID
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, AXI_26_DFI_AW_AERR_N, AXI_26_DFI_CLK_BUF, AXI_26_DFI_DBI_BYTE_DISABLE, AXI_26_DFI_DW_RDDATA_DBI, AXI_26_DFI_DW_RDDATA_DERR, AXI_26_DFI_DW_RDDATA_VALID, AXI_26_DFI_INIT_COMPLETE, AXI_26_DFI_PHYUPD_REQ, AXI_26_DFI_PHY_LP_STATE, AXI_26_DFI_RST_N_BUF, AXI_26_MC_STATUS, AXI_26_PHY_STATUS, AXI_26_RDATA, AXI_26_RDATA_PARITY, AXI_26_RID, AXI_26_RLAST, AXI_26_RRESP, AXI_26_RVALID, AXI_26_WREADY, AXI_27_ARREADY, AXI_27_AWREADY
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, AXI_27_BID, AXI_27_BRESP, AXI_27_BVALID, AXI_27_DFI_AW_AERR_N, AXI_27_DFI_CLK_BUF, AXI_27_DFI_DBI_BYTE_DISABLE, AXI_27_DFI_DW_RDDATA_DBI, AXI_27_DFI_DW_RDDATA_DERR, AXI_27_DFI_DW_RDDATA_VALID, AXI_27_DFI_INIT_COMPLETE, AXI_27_DFI_PHYUPD_REQ, AXI_27_DFI_PHY_LP_STATE, AXI_27_DFI_RST_N_BUF, AXI_27_RDATA, AXI_27_RDATA_PARITY, AXI_27_RID, AXI_27_RLAST, AXI_27_RRESP, AXI_27_RVALID, AXI_27_WREADY, AXI_28_ARREADY
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, AXI_28_AWREADY, AXI_28_BID, AXI_28_BRESP, AXI_28_BVALID, AXI_28_DFI_AW_AERR_N, AXI_28_DFI_CLK_BUF, AXI_28_DFI_DBI_BYTE_DISABLE, AXI_28_DFI_DW_RDDATA_DBI, AXI_28_DFI_DW_RDDATA_DERR, AXI_28_DFI_DW_RDDATA_VALID, AXI_28_DFI_INIT_COMPLETE, AXI_28_DFI_PHYUPD_REQ, AXI_28_DFI_PHY_LP_STATE, AXI_28_DFI_RST_N_BUF, AXI_28_MC_STATUS, AXI_28_PHY_STATUS, AXI_28_RDATA, AXI_28_RDATA_PARITY, AXI_28_RID, AXI_28_RLAST, AXI_28_RRESP
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, AXI_28_RVALID, AXI_28_WREADY, AXI_29_ARREADY, AXI_29_AWREADY, AXI_29_BID, AXI_29_BRESP, AXI_29_BVALID, AXI_29_DFI_AW_AERR_N, AXI_29_DFI_CLK_BUF, AXI_29_DFI_DBI_BYTE_DISABLE, AXI_29_DFI_DW_RDDATA_DBI, AXI_29_DFI_DW_RDDATA_DERR, AXI_29_DFI_DW_RDDATA_VALID, AXI_29_DFI_INIT_COMPLETE, AXI_29_DFI_PHYUPD_REQ, AXI_29_DFI_PHY_LP_STATE, AXI_29_DFI_RST_N_BUF, AXI_29_RDATA, AXI_29_RDATA_PARITY, AXI_29_RID, AXI_29_RLAST
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, AXI_29_RRESP, AXI_29_RVALID, AXI_29_WREADY, AXI_30_ARREADY, AXI_30_AWREADY, AXI_30_BID, AXI_30_BRESP, AXI_30_BVALID, AXI_30_DFI_AW_AERR_N, AXI_30_DFI_CLK_BUF, AXI_30_DFI_DBI_BYTE_DISABLE, AXI_30_DFI_DW_RDDATA_DBI, AXI_30_DFI_DW_RDDATA_DERR, AXI_30_DFI_DW_RDDATA_VALID, AXI_30_DFI_INIT_COMPLETE, AXI_30_DFI_PHYUPD_REQ, AXI_30_DFI_PHY_LP_STATE, AXI_30_DFI_RST_N_BUF, AXI_30_MC_STATUS, AXI_30_PHY_STATUS, AXI_30_RDATA
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, AXI_30_RDATA_PARITY, AXI_30_RID, AXI_30_RLAST, AXI_30_RRESP, AXI_30_RVALID, AXI_30_WREADY, AXI_31_ARREADY, AXI_31_AWREADY, AXI_31_BID, AXI_31_BRESP, AXI_31_BVALID, AXI_31_DFI_AW_AERR_N, AXI_31_DFI_CLK_BUF, AXI_31_DFI_DBI_BYTE_DISABLE, AXI_31_DFI_DW_RDDATA_DBI, AXI_31_DFI_DW_RDDATA_DERR, AXI_31_DFI_DW_RDDATA_VALID, AXI_31_DFI_INIT_COMPLETE, AXI_31_DFI_PHYUPD_REQ, AXI_31_DFI_PHY_LP_STATE, AXI_31_DFI_RST_N_BUF
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, AXI_31_RDATA, AXI_31_RDATA_PARITY, AXI_31_RID, AXI_31_RLAST, AXI_31_RRESP, AXI_31_RVALID, AXI_31_WREADY, DRAM_0_STAT_CATTRIP, DRAM_0_STAT_TEMP, DRAM_1_STAT_CATTRIP, DRAM_1_STAT_TEMP, APB_0_PADDR, APB_0_PCLK, APB_0_PENABLE, APB_0_PRESET_N, APB_0_PSEL, APB_0_PWDATA, APB_0_PWRITE, APB_1_PADDR, APB_1_PCLK, APB_1_PENABLE
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, APB_1_PRESET_N, APB_1_PSEL, APB_1_PWDATA, APB_1_PWRITE, AXI_00_ACLK, AXI_00_ARADDR, AXI_00_ARBURST, AXI_00_ARESET_N, AXI_00_ARID, AXI_00_ARLEN, AXI_00_ARSIZE, AXI_00_ARVALID, AXI_00_AWADDR, AXI_00_AWBURST, AXI_00_AWID, AXI_00_AWLEN, AXI_00_AWSIZE, AXI_00_AWVALID, AXI_00_BREADY, AXI_00_DFI_LP_PWR_X_REQ, AXI_00_RREADY
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, AXI_00_WDATA, AXI_00_WDATA_PARITY, AXI_00_WLAST, AXI_00_WSTRB, AXI_00_WVALID, AXI_01_ACLK, AXI_01_ARADDR, AXI_01_ARBURST, AXI_01_ARESET_N, AXI_01_ARID, AXI_01_ARLEN, AXI_01_ARSIZE, AXI_01_ARVALID, AXI_01_AWADDR, AXI_01_AWBURST, AXI_01_AWID, AXI_01_AWLEN, AXI_01_AWSIZE, AXI_01_AWVALID, AXI_01_BREADY, AXI_01_DFI_LP_PWR_X_REQ
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, AXI_01_RREADY, AXI_01_WDATA, AXI_01_WDATA_PARITY, AXI_01_WLAST, AXI_01_WSTRB, AXI_01_WVALID, AXI_02_ACLK, AXI_02_ARADDR, AXI_02_ARBURST, AXI_02_ARESET_N, AXI_02_ARID, AXI_02_ARLEN, AXI_02_ARSIZE, AXI_02_ARVALID, AXI_02_AWADDR, AXI_02_AWBURST, AXI_02_AWID, AXI_02_AWLEN, AXI_02_AWSIZE, AXI_02_AWVALID, AXI_02_BREADY
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|
, AXI_02_DFI_LP_PWR_X_REQ, AXI_02_RREADY, AXI_02_WDATA, AXI_02_WDATA_PARITY, AXI_02_WLAST, AXI_02_WSTRB, AXI_02_WVALID, AXI_03_ACLK, AXI_03_ARADDR, AXI_03_ARBURST, AXI_03_ARESET_N, AXI_03_ARID, AXI_03_ARLEN, AXI_03_ARSIZE, AXI_03_ARVALID, AXI_03_AWADDR, AXI_03_AWBURST, AXI_03_AWID, AXI_03_AWLEN, AXI_03_AWSIZE, AXI_03_AWVALID
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|
, AXI_03_BREADY, AXI_03_DFI_LP_PWR_X_REQ, AXI_03_RREADY, AXI_03_WDATA, AXI_03_WDATA_PARITY, AXI_03_WLAST, AXI_03_WSTRB, AXI_03_WVALID, AXI_04_ACLK, AXI_04_ARADDR, AXI_04_ARBURST, AXI_04_ARESET_N, AXI_04_ARID, AXI_04_ARLEN, AXI_04_ARSIZE, AXI_04_ARVALID, AXI_04_AWADDR, AXI_04_AWBURST, AXI_04_AWID, AXI_04_AWLEN, AXI_04_AWSIZE
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|
, AXI_04_AWVALID, AXI_04_BREADY, AXI_04_DFI_LP_PWR_X_REQ, AXI_04_RREADY, AXI_04_WDATA, AXI_04_WDATA_PARITY, AXI_04_WLAST, AXI_04_WSTRB, AXI_04_WVALID, AXI_05_ACLK, AXI_05_ARADDR, AXI_05_ARBURST, AXI_05_ARESET_N, AXI_05_ARID, AXI_05_ARLEN, AXI_05_ARSIZE, AXI_05_ARVALID, AXI_05_AWADDR, AXI_05_AWBURST, AXI_05_AWID, AXI_05_AWLEN
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|
, AXI_05_AWSIZE, AXI_05_AWVALID, AXI_05_BREADY, AXI_05_DFI_LP_PWR_X_REQ, AXI_05_RREADY, AXI_05_WDATA, AXI_05_WDATA_PARITY, AXI_05_WLAST, AXI_05_WSTRB, AXI_05_WVALID, AXI_06_ACLK, AXI_06_ARADDR, AXI_06_ARBURST, AXI_06_ARESET_N, AXI_06_ARID, AXI_06_ARLEN, AXI_06_ARSIZE, AXI_06_ARVALID, AXI_06_AWADDR, AXI_06_AWBURST, AXI_06_AWID
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|
, AXI_06_AWLEN, AXI_06_AWSIZE, AXI_06_AWVALID, AXI_06_BREADY, AXI_06_DFI_LP_PWR_X_REQ, AXI_06_RREADY, AXI_06_WDATA, AXI_06_WDATA_PARITY, AXI_06_WLAST, AXI_06_WSTRB, AXI_06_WVALID, AXI_07_ACLK, AXI_07_ARADDR, AXI_07_ARBURST, AXI_07_ARESET_N, AXI_07_ARID, AXI_07_ARLEN, AXI_07_ARSIZE, AXI_07_ARVALID, AXI_07_AWADDR, AXI_07_AWBURST
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|
, AXI_07_AWID, AXI_07_AWLEN, AXI_07_AWSIZE, AXI_07_AWVALID, AXI_07_BREADY, AXI_07_DFI_LP_PWR_X_REQ, AXI_07_RREADY, AXI_07_WDATA, AXI_07_WDATA_PARITY, AXI_07_WLAST, AXI_07_WSTRB, AXI_07_WVALID, AXI_08_ACLK, AXI_08_ARADDR, AXI_08_ARBURST, AXI_08_ARESET_N, AXI_08_ARID, AXI_08_ARLEN, AXI_08_ARSIZE, AXI_08_ARVALID, AXI_08_AWADDR
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|
, AXI_08_AWBURST, AXI_08_AWID, AXI_08_AWLEN, AXI_08_AWSIZE, AXI_08_AWVALID, AXI_08_BREADY, AXI_08_DFI_LP_PWR_X_REQ, AXI_08_RREADY, AXI_08_WDATA, AXI_08_WDATA_PARITY, AXI_08_WLAST, AXI_08_WSTRB, AXI_08_WVALID, AXI_09_ACLK, AXI_09_ARADDR, AXI_09_ARBURST, AXI_09_ARESET_N, AXI_09_ARID, AXI_09_ARLEN, AXI_09_ARSIZE, AXI_09_ARVALID
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|
, AXI_09_AWADDR, AXI_09_AWBURST, AXI_09_AWID, AXI_09_AWLEN, AXI_09_AWSIZE, AXI_09_AWVALID, AXI_09_BREADY, AXI_09_DFI_LP_PWR_X_REQ, AXI_09_RREADY, AXI_09_WDATA, AXI_09_WDATA_PARITY, AXI_09_WLAST, AXI_09_WSTRB, AXI_09_WVALID, AXI_10_ACLK, AXI_10_ARADDR, AXI_10_ARBURST, AXI_10_ARESET_N, AXI_10_ARID, AXI_10_ARLEN, AXI_10_ARSIZE
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, AXI_10_ARVALID, AXI_10_AWADDR, AXI_10_AWBURST, AXI_10_AWID, AXI_10_AWLEN, AXI_10_AWSIZE, AXI_10_AWVALID, AXI_10_BREADY, AXI_10_DFI_LP_PWR_X_REQ, AXI_10_RREADY, AXI_10_WDATA, AXI_10_WDATA_PARITY, AXI_10_WLAST, AXI_10_WSTRB, AXI_10_WVALID, AXI_11_ACLK, AXI_11_ARADDR, AXI_11_ARBURST, AXI_11_ARESET_N, AXI_11_ARID, AXI_11_ARLEN
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, AXI_11_ARSIZE, AXI_11_ARVALID, AXI_11_AWADDR, AXI_11_AWBURST, AXI_11_AWID, AXI_11_AWLEN, AXI_11_AWSIZE, AXI_11_AWVALID, AXI_11_BREADY, AXI_11_DFI_LP_PWR_X_REQ, AXI_11_RREADY, AXI_11_WDATA, AXI_11_WDATA_PARITY, AXI_11_WLAST, AXI_11_WSTRB, AXI_11_WVALID, AXI_12_ACLK, AXI_12_ARADDR, AXI_12_ARBURST, AXI_12_ARESET_N, AXI_12_ARID
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, AXI_12_ARLEN, AXI_12_ARSIZE, AXI_12_ARVALID, AXI_12_AWADDR, AXI_12_AWBURST, AXI_12_AWID, AXI_12_AWLEN, AXI_12_AWSIZE, AXI_12_AWVALID, AXI_12_BREADY, AXI_12_DFI_LP_PWR_X_REQ, AXI_12_RREADY, AXI_12_WDATA, AXI_12_WDATA_PARITY, AXI_12_WLAST, AXI_12_WSTRB, AXI_12_WVALID, AXI_13_ACLK, AXI_13_ARADDR, AXI_13_ARBURST, AXI_13_ARESET_N
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, AXI_13_ARID, AXI_13_ARLEN, AXI_13_ARSIZE, AXI_13_ARVALID, AXI_13_AWADDR, AXI_13_AWBURST, AXI_13_AWID, AXI_13_AWLEN, AXI_13_AWSIZE, AXI_13_AWVALID, AXI_13_BREADY, AXI_13_DFI_LP_PWR_X_REQ, AXI_13_RREADY, AXI_13_WDATA, AXI_13_WDATA_PARITY, AXI_13_WLAST, AXI_13_WSTRB, AXI_13_WVALID, AXI_14_ACLK, AXI_14_ARADDR, AXI_14_ARBURST
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, AXI_14_ARESET_N, AXI_14_ARID, AXI_14_ARLEN, AXI_14_ARSIZE, AXI_14_ARVALID, AXI_14_AWADDR, AXI_14_AWBURST, AXI_14_AWID, AXI_14_AWLEN, AXI_14_AWSIZE, AXI_14_AWVALID, AXI_14_BREADY, AXI_14_DFI_LP_PWR_X_REQ, AXI_14_RREADY, AXI_14_WDATA, AXI_14_WDATA_PARITY, AXI_14_WLAST, AXI_14_WSTRB, AXI_14_WVALID, AXI_15_ACLK, AXI_15_ARADDR
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, AXI_15_ARBURST, AXI_15_ARESET_N, AXI_15_ARID, AXI_15_ARLEN, AXI_15_ARSIZE, AXI_15_ARVALID, AXI_15_AWADDR, AXI_15_AWBURST, AXI_15_AWID, AXI_15_AWLEN, AXI_15_AWSIZE, AXI_15_AWVALID, AXI_15_BREADY, AXI_15_DFI_LP_PWR_X_REQ, AXI_15_RREADY, AXI_15_WDATA, AXI_15_WDATA_PARITY, AXI_15_WLAST, AXI_15_WSTRB, AXI_15_WVALID, AXI_16_ACLK
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|
, AXI_16_ARADDR, AXI_16_ARBURST, AXI_16_ARESET_N, AXI_16_ARID, AXI_16_ARLEN, AXI_16_ARSIZE, AXI_16_ARVALID, AXI_16_AWADDR, AXI_16_AWBURST, AXI_16_AWID, AXI_16_AWLEN, AXI_16_AWSIZE, AXI_16_AWVALID, AXI_16_BREADY, AXI_16_DFI_LP_PWR_X_REQ, AXI_16_RREADY, AXI_16_WDATA, AXI_16_WDATA_PARITY, AXI_16_WLAST, AXI_16_WSTRB, AXI_16_WVALID
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, AXI_17_ACLK, AXI_17_ARADDR, AXI_17_ARBURST, AXI_17_ARESET_N, AXI_17_ARID, AXI_17_ARLEN, AXI_17_ARSIZE, AXI_17_ARVALID, AXI_17_AWADDR, AXI_17_AWBURST, AXI_17_AWID, AXI_17_AWLEN, AXI_17_AWSIZE, AXI_17_AWVALID, AXI_17_BREADY, AXI_17_DFI_LP_PWR_X_REQ, AXI_17_RREADY, AXI_17_WDATA, AXI_17_WDATA_PARITY, AXI_17_WLAST, AXI_17_WSTRB
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|
, AXI_17_WVALID, AXI_18_ACLK, AXI_18_ARADDR, AXI_18_ARBURST, AXI_18_ARESET_N, AXI_18_ARID, AXI_18_ARLEN, AXI_18_ARSIZE, AXI_18_ARVALID, AXI_18_AWADDR, AXI_18_AWBURST, AXI_18_AWID, AXI_18_AWLEN, AXI_18_AWSIZE, AXI_18_AWVALID, AXI_18_BREADY, AXI_18_DFI_LP_PWR_X_REQ, AXI_18_RREADY, AXI_18_WDATA, AXI_18_WDATA_PARITY, AXI_18_WLAST
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, AXI_18_WSTRB, AXI_18_WVALID, AXI_19_ACLK, AXI_19_ARADDR, AXI_19_ARBURST, AXI_19_ARESET_N, AXI_19_ARID, AXI_19_ARLEN, AXI_19_ARSIZE, AXI_19_ARVALID, AXI_19_AWADDR, AXI_19_AWBURST, AXI_19_AWID, AXI_19_AWLEN, AXI_19_AWSIZE, AXI_19_AWVALID, AXI_19_BREADY, AXI_19_DFI_LP_PWR_X_REQ, AXI_19_RREADY, AXI_19_WDATA, AXI_19_WDATA_PARITY
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|
, AXI_19_WLAST, AXI_19_WSTRB, AXI_19_WVALID, AXI_20_ACLK, AXI_20_ARADDR, AXI_20_ARBURST, AXI_20_ARESET_N, AXI_20_ARID, AXI_20_ARLEN, AXI_20_ARSIZE, AXI_20_ARVALID, AXI_20_AWADDR, AXI_20_AWBURST, AXI_20_AWID, AXI_20_AWLEN, AXI_20_AWSIZE, AXI_20_AWVALID, AXI_20_BREADY, AXI_20_DFI_LP_PWR_X_REQ, AXI_20_RREADY, AXI_20_WDATA
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|
, AXI_20_WDATA_PARITY, AXI_20_WLAST, AXI_20_WSTRB, AXI_20_WVALID, AXI_21_ACLK, AXI_21_ARADDR, AXI_21_ARBURST, AXI_21_ARESET_N, AXI_21_ARID, AXI_21_ARLEN, AXI_21_ARSIZE, AXI_21_ARVALID, AXI_21_AWADDR, AXI_21_AWBURST, AXI_21_AWID, AXI_21_AWLEN, AXI_21_AWSIZE, AXI_21_AWVALID, AXI_21_BREADY, AXI_21_DFI_LP_PWR_X_REQ, AXI_21_RREADY
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, AXI_21_WDATA, AXI_21_WDATA_PARITY, AXI_21_WLAST, AXI_21_WSTRB, AXI_21_WVALID, AXI_22_ACLK, AXI_22_ARADDR, AXI_22_ARBURST, AXI_22_ARESET_N, AXI_22_ARID, AXI_22_ARLEN, AXI_22_ARSIZE, AXI_22_ARVALID, AXI_22_AWADDR, AXI_22_AWBURST, AXI_22_AWID, AXI_22_AWLEN, AXI_22_AWSIZE, AXI_22_AWVALID, AXI_22_BREADY, AXI_22_DFI_LP_PWR_X_REQ
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, AXI_22_RREADY, AXI_22_WDATA, AXI_22_WDATA_PARITY, AXI_22_WLAST, AXI_22_WSTRB, AXI_22_WVALID, AXI_23_ACLK, AXI_23_ARADDR, AXI_23_ARBURST, AXI_23_ARESET_N, AXI_23_ARID, AXI_23_ARLEN, AXI_23_ARSIZE, AXI_23_ARVALID, AXI_23_AWADDR, AXI_23_AWBURST, AXI_23_AWID, AXI_23_AWLEN, AXI_23_AWSIZE, AXI_23_AWVALID, AXI_23_BREADY
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, AXI_23_DFI_LP_PWR_X_REQ, AXI_23_RREADY, AXI_23_WDATA, AXI_23_WDATA_PARITY, AXI_23_WLAST, AXI_23_WSTRB, AXI_23_WVALID, AXI_24_ACLK, AXI_24_ARADDR, AXI_24_ARBURST, AXI_24_ARESET_N, AXI_24_ARID, AXI_24_ARLEN, AXI_24_ARSIZE, AXI_24_ARVALID, AXI_24_AWADDR, AXI_24_AWBURST, AXI_24_AWID, AXI_24_AWLEN, AXI_24_AWSIZE, AXI_24_AWVALID
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, AXI_24_BREADY, AXI_24_DFI_LP_PWR_X_REQ, AXI_24_RREADY, AXI_24_WDATA, AXI_24_WDATA_PARITY, AXI_24_WLAST, AXI_24_WSTRB, AXI_24_WVALID, AXI_25_ACLK, AXI_25_ARADDR, AXI_25_ARBURST, AXI_25_ARESET_N, AXI_25_ARID, AXI_25_ARLEN, AXI_25_ARSIZE, AXI_25_ARVALID, AXI_25_AWADDR, AXI_25_AWBURST, AXI_25_AWID, AXI_25_AWLEN, AXI_25_AWSIZE
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|
, AXI_25_AWVALID, AXI_25_BREADY, AXI_25_DFI_LP_PWR_X_REQ, AXI_25_RREADY, AXI_25_WDATA, AXI_25_WDATA_PARITY, AXI_25_WLAST, AXI_25_WSTRB, AXI_25_WVALID, AXI_26_ACLK, AXI_26_ARADDR, AXI_26_ARBURST, AXI_26_ARESET_N, AXI_26_ARID, AXI_26_ARLEN, AXI_26_ARSIZE, AXI_26_ARVALID, AXI_26_AWADDR, AXI_26_AWBURST, AXI_26_AWID, AXI_26_AWLEN
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|
, AXI_26_AWSIZE, AXI_26_AWVALID, AXI_26_BREADY, AXI_26_DFI_LP_PWR_X_REQ, AXI_26_RREADY, AXI_26_WDATA, AXI_26_WDATA_PARITY, AXI_26_WLAST, AXI_26_WSTRB, AXI_26_WVALID, AXI_27_ACLK, AXI_27_ARADDR, AXI_27_ARBURST, AXI_27_ARESET_N, AXI_27_ARID, AXI_27_ARLEN, AXI_27_ARSIZE, AXI_27_ARVALID, AXI_27_AWADDR, AXI_27_AWBURST, AXI_27_AWID
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, AXI_27_AWLEN, AXI_27_AWSIZE, AXI_27_AWVALID, AXI_27_BREADY, AXI_27_DFI_LP_PWR_X_REQ, AXI_27_RREADY, AXI_27_WDATA, AXI_27_WDATA_PARITY, AXI_27_WLAST, AXI_27_WSTRB, AXI_27_WVALID, AXI_28_ACLK, AXI_28_ARADDR, AXI_28_ARBURST, AXI_28_ARESET_N, AXI_28_ARID, AXI_28_ARLEN, AXI_28_ARSIZE, AXI_28_ARVALID, AXI_28_AWADDR, AXI_28_AWBURST
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, AXI_28_AWID, AXI_28_AWLEN, AXI_28_AWSIZE, AXI_28_AWVALID, AXI_28_BREADY, AXI_28_DFI_LP_PWR_X_REQ, AXI_28_RREADY, AXI_28_WDATA, AXI_28_WDATA_PARITY, AXI_28_WLAST, AXI_28_WSTRB, AXI_28_WVALID, AXI_29_ACLK, AXI_29_ARADDR, AXI_29_ARBURST, AXI_29_ARESET_N, AXI_29_ARID, AXI_29_ARLEN, AXI_29_ARSIZE, AXI_29_ARVALID, AXI_29_AWADDR
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, AXI_29_AWBURST, AXI_29_AWID, AXI_29_AWLEN, AXI_29_AWSIZE, AXI_29_AWVALID, AXI_29_BREADY, AXI_29_DFI_LP_PWR_X_REQ, AXI_29_RREADY, AXI_29_WDATA, AXI_29_WDATA_PARITY, AXI_29_WLAST, AXI_29_WSTRB, AXI_29_WVALID, AXI_30_ACLK, AXI_30_ARADDR, AXI_30_ARBURST, AXI_30_ARESET_N, AXI_30_ARID, AXI_30_ARLEN, AXI_30_ARSIZE, AXI_30_ARVALID
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, AXI_30_AWADDR, AXI_30_AWBURST, AXI_30_AWID, AXI_30_AWLEN, AXI_30_AWSIZE, AXI_30_AWVALID, AXI_30_BREADY, AXI_30_DFI_LP_PWR_X_REQ, AXI_30_RREADY, AXI_30_WDATA, AXI_30_WDATA_PARITY, AXI_30_WLAST, AXI_30_WSTRB, AXI_30_WVALID, AXI_31_ACLK, AXI_31_ARADDR, AXI_31_ARBURST, AXI_31_ARESET_N, AXI_31_ARID, AXI_31_ARLEN, AXI_31_ARSIZE
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, AXI_31_ARVALID, AXI_31_AWADDR, AXI_31_AWBURST, AXI_31_AWID, AXI_31_AWLEN, AXI_31_AWSIZE, AXI_31_AWVALID, AXI_31_BREADY, AXI_31_DFI_LP_PWR_X_REQ, AXI_31_RREADY, AXI_31_WDATA, AXI_31_WDATA_PARITY, AXI_31_WLAST, AXI_31_WSTRB, AXI_31_WVALID, BSCAN_DRCK_0, BSCAN_DRCK_1, BSCAN_TCK_0, BSCAN_TCK_1, HBM_REF_CLK_0, HBM_REF_CLK_1
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|
, MBIST_EN_00, MBIST_EN_01, MBIST_EN_02, MBIST_EN_03, MBIST_EN_04, MBIST_EN_05, MBIST_EN_06, MBIST_EN_07, MBIST_EN_08, MBIST_EN_09, MBIST_EN_10, MBIST_EN_11, MBIST_EN_12, MBIST_EN_13, MBIST_EN_14, MBIST_EN_15);
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parameter CLK_SEL_00 = "FALSE";
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parameter CLK_SEL_01 = "FALSE";
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parameter CLK_SEL_02 = "FALSE";
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parameter CLK_SEL_03 = "FALSE";
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parameter CLK_SEL_04 = "FALSE";
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parameter CLK_SEL_05 = "FALSE";
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parameter CLK_SEL_06 = "FALSE";
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parameter CLK_SEL_07 = "FALSE";
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parameter CLK_SEL_08 = "FALSE";
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parameter CLK_SEL_09 = "FALSE";
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parameter CLK_SEL_10 = "FALSE";
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parameter CLK_SEL_11 = "FALSE";
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parameter CLK_SEL_12 = "FALSE";
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parameter CLK_SEL_13 = "FALSE";
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parameter CLK_SEL_14 = "FALSE";
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parameter CLK_SEL_15 = "FALSE";
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parameter CLK_SEL_16 = "FALSE";
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parameter CLK_SEL_17 = "FALSE";
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parameter CLK_SEL_18 = "FALSE";
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parameter CLK_SEL_19 = "FALSE";
|
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parameter CLK_SEL_20 = "FALSE";
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parameter CLK_SEL_21 = "FALSE";
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parameter CLK_SEL_22 = "FALSE";
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parameter CLK_SEL_23 = "FALSE";
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parameter CLK_SEL_24 = "FALSE";
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parameter CLK_SEL_25 = "FALSE";
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parameter CLK_SEL_26 = "FALSE";
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parameter CLK_SEL_27 = "FALSE";
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parameter CLK_SEL_28 = "FALSE";
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parameter CLK_SEL_29 = "FALSE";
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parameter CLK_SEL_30 = "FALSE";
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parameter CLK_SEL_31 = "FALSE";
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parameter integer DATARATE_00 = 1800;
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parameter integer DATARATE_01 = 1800;
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parameter integer DATARATE_02 = 1800;
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parameter integer DATARATE_03 = 1800;
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parameter integer DATARATE_04 = 1800;
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parameter integer DATARATE_05 = 1800;
|
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parameter integer DATARATE_06 = 1800;
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parameter integer DATARATE_07 = 1800;
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parameter integer DATARATE_08 = 1800;
|
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parameter integer DATARATE_09 = 1800;
|
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parameter integer DATARATE_10 = 1800;
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parameter integer DATARATE_11 = 1800;
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parameter integer DATARATE_12 = 1800;
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parameter integer DATARATE_13 = 1800;
|
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parameter integer DATARATE_14 = 1800;
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parameter integer DATARATE_15 = 1800;
|
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parameter DA_LOCKOUT_0 = "FALSE";
|
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parameter DA_LOCKOUT_1 = "FALSE";
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parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0;
|
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parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0;
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parameter [0:0] IS_APB_1_PCLK_INVERTED = 1'b0;
|
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parameter [0:0] IS_APB_1_PRESET_N_INVERTED = 1'b0;
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parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0;
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parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0;
|
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parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0;
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parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0;
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parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0;
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parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0;
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parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0;
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parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0;
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parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_16_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_16_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_17_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_17_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_18_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_18_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_19_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_19_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_20_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_20_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_21_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_21_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_22_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_22_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_23_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_23_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_24_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_24_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_25_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_25_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_26_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_26_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_27_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_27_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_28_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_28_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_29_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_29_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_30_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_30_ARESET_N_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_31_ACLK_INVERTED = 1'b0;
|
|
parameter [0:0] IS_AXI_31_ARESET_N_INVERTED = 1'b0;
|
|
parameter MC_ENABLE_00 = "FALSE";
|
|
parameter MC_ENABLE_01 = "FALSE";
|
|
parameter MC_ENABLE_02 = "FALSE";
|
|
parameter MC_ENABLE_03 = "FALSE";
|
|
parameter MC_ENABLE_04 = "FALSE";
|
|
parameter MC_ENABLE_05 = "FALSE";
|
|
parameter MC_ENABLE_06 = "FALSE";
|
|
parameter MC_ENABLE_07 = "FALSE";
|
|
parameter MC_ENABLE_08 = "FALSE";
|
|
parameter MC_ENABLE_09 = "FALSE";
|
|
parameter MC_ENABLE_10 = "FALSE";
|
|
parameter MC_ENABLE_11 = "FALSE";
|
|
parameter MC_ENABLE_12 = "FALSE";
|
|
parameter MC_ENABLE_13 = "FALSE";
|
|
parameter MC_ENABLE_14 = "FALSE";
|
|
parameter MC_ENABLE_15 = "FALSE";
|
|
parameter MC_ENABLE_APB_00 = "FALSE";
|
|
parameter MC_ENABLE_APB_01 = "FALSE";
|
|
parameter integer PAGEHIT_PERCENT_00 = 75;
|
|
parameter integer PAGEHIT_PERCENT_01 = 75;
|
|
parameter PHY_ENABLE_00 = "FALSE";
|
|
parameter PHY_ENABLE_01 = "FALSE";
|
|
parameter PHY_ENABLE_02 = "FALSE";
|
|
parameter PHY_ENABLE_03 = "FALSE";
|
|
parameter PHY_ENABLE_04 = "FALSE";
|
|
parameter PHY_ENABLE_05 = "FALSE";
|
|
parameter PHY_ENABLE_06 = "FALSE";
|
|
parameter PHY_ENABLE_07 = "FALSE";
|
|
parameter PHY_ENABLE_08 = "FALSE";
|
|
parameter PHY_ENABLE_09 = "FALSE";
|
|
parameter PHY_ENABLE_10 = "FALSE";
|
|
parameter PHY_ENABLE_11 = "FALSE";
|
|
parameter PHY_ENABLE_12 = "FALSE";
|
|
parameter PHY_ENABLE_13 = "FALSE";
|
|
parameter PHY_ENABLE_14 = "FALSE";
|
|
parameter PHY_ENABLE_15 = "FALSE";
|
|
parameter PHY_ENABLE_16 = "FALSE";
|
|
parameter PHY_ENABLE_17 = "FALSE";
|
|
parameter PHY_ENABLE_18 = "FALSE";
|
|
parameter PHY_ENABLE_19 = "FALSE";
|
|
parameter PHY_ENABLE_20 = "FALSE";
|
|
parameter PHY_ENABLE_21 = "FALSE";
|
|
parameter PHY_ENABLE_22 = "FALSE";
|
|
parameter PHY_ENABLE_23 = "FALSE";
|
|
parameter PHY_ENABLE_24 = "FALSE";
|
|
parameter PHY_ENABLE_25 = "FALSE";
|
|
parameter PHY_ENABLE_26 = "FALSE";
|
|
parameter PHY_ENABLE_27 = "FALSE";
|
|
parameter PHY_ENABLE_28 = "FALSE";
|
|
parameter PHY_ENABLE_29 = "FALSE";
|
|
parameter PHY_ENABLE_30 = "FALSE";
|
|
parameter PHY_ENABLE_31 = "FALSE";
|
|
parameter PHY_ENABLE_APB_00 = "FALSE";
|
|
parameter PHY_ENABLE_APB_01 = "FALSE";
|
|
parameter PHY_PCLK_INVERT_01 = "FALSE";
|
|
parameter PHY_PCLK_INVERT_02 = "FALSE";
|
|
parameter integer READ_PERCENT_00 = 50;
|
|
parameter integer READ_PERCENT_01 = 50;
|
|
parameter integer READ_PERCENT_02 = 50;
|
|
parameter integer READ_PERCENT_03 = 50;
|
|
parameter integer READ_PERCENT_04 = 50;
|
|
parameter integer READ_PERCENT_05 = 50;
|
|
parameter integer READ_PERCENT_06 = 50;
|
|
parameter integer READ_PERCENT_07 = 50;
|
|
parameter integer READ_PERCENT_08 = 50;
|
|
parameter integer READ_PERCENT_09 = 50;
|
|
parameter integer READ_PERCENT_10 = 50;
|
|
parameter integer READ_PERCENT_11 = 50;
|
|
parameter integer READ_PERCENT_12 = 50;
|
|
parameter integer READ_PERCENT_13 = 50;
|
|
parameter integer READ_PERCENT_14 = 50;
|
|
parameter integer READ_PERCENT_15 = 50;
|
|
parameter integer READ_PERCENT_16 = 50;
|
|
parameter integer READ_PERCENT_17 = 50;
|
|
parameter integer READ_PERCENT_18 = 50;
|
|
parameter integer READ_PERCENT_19 = 50;
|
|
parameter integer READ_PERCENT_20 = 50;
|
|
parameter integer READ_PERCENT_21 = 50;
|
|
parameter integer READ_PERCENT_22 = 50;
|
|
parameter integer READ_PERCENT_23 = 50;
|
|
parameter integer READ_PERCENT_24 = 50;
|
|
parameter integer READ_PERCENT_25 = 50;
|
|
parameter integer READ_PERCENT_26 = 50;
|
|
parameter integer READ_PERCENT_27 = 50;
|
|
parameter integer READ_PERCENT_28 = 50;
|
|
parameter integer READ_PERCENT_29 = 50;
|
|
parameter integer READ_PERCENT_30 = 50;
|
|
parameter integer READ_PERCENT_31 = 50;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter SWITCH_ENABLE_00 = "FALSE";
|
|
parameter SWITCH_ENABLE_01 = "FALSE";
|
|
parameter integer WRITE_PERCENT_00 = 50;
|
|
parameter integer WRITE_PERCENT_01 = 50;
|
|
parameter integer WRITE_PERCENT_02 = 50;
|
|
parameter integer WRITE_PERCENT_03 = 50;
|
|
parameter integer WRITE_PERCENT_04 = 50;
|
|
parameter integer WRITE_PERCENT_05 = 50;
|
|
parameter integer WRITE_PERCENT_06 = 50;
|
|
parameter integer WRITE_PERCENT_07 = 50;
|
|
parameter integer WRITE_PERCENT_08 = 50;
|
|
parameter integer WRITE_PERCENT_09 = 50;
|
|
parameter integer WRITE_PERCENT_10 = 50;
|
|
parameter integer WRITE_PERCENT_11 = 50;
|
|
parameter integer WRITE_PERCENT_12 = 50;
|
|
parameter integer WRITE_PERCENT_13 = 50;
|
|
parameter integer WRITE_PERCENT_14 = 50;
|
|
parameter integer WRITE_PERCENT_15 = 50;
|
|
parameter integer WRITE_PERCENT_16 = 50;
|
|
parameter integer WRITE_PERCENT_17 = 50;
|
|
parameter integer WRITE_PERCENT_18 = 50;
|
|
parameter integer WRITE_PERCENT_19 = 50;
|
|
parameter integer WRITE_PERCENT_20 = 50;
|
|
parameter integer WRITE_PERCENT_21 = 50;
|
|
parameter integer WRITE_PERCENT_22 = 50;
|
|
parameter integer WRITE_PERCENT_23 = 50;
|
|
parameter integer WRITE_PERCENT_24 = 50;
|
|
parameter integer WRITE_PERCENT_25 = 50;
|
|
parameter integer WRITE_PERCENT_26 = 50;
|
|
parameter integer WRITE_PERCENT_27 = 50;
|
|
parameter integer WRITE_PERCENT_28 = 50;
|
|
parameter integer WRITE_PERCENT_29 = 50;
|
|
parameter integer WRITE_PERCENT_30 = 50;
|
|
parameter integer WRITE_PERCENT_31 = 50;
|
|
output [31:0] APB_0_PRDATA;
|
|
output APB_0_PREADY;
|
|
output APB_0_PSLVERR;
|
|
output [31:0] APB_1_PRDATA;
|
|
output APB_1_PREADY;
|
|
output APB_1_PSLVERR;
|
|
output AXI_00_ARREADY;
|
|
output AXI_00_AWREADY;
|
|
output [5:0] AXI_00_BID;
|
|
output [1:0] AXI_00_BRESP;
|
|
output AXI_00_BVALID;
|
|
output [1:0] AXI_00_DFI_AW_AERR_N;
|
|
output AXI_00_DFI_CLK_BUF;
|
|
output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_00_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_00_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_00_DFI_DW_RDDATA_VALID;
|
|
output AXI_00_DFI_INIT_COMPLETE;
|
|
output AXI_00_DFI_PHYUPD_REQ;
|
|
output AXI_00_DFI_PHY_LP_STATE;
|
|
output AXI_00_DFI_RST_N_BUF;
|
|
output [5:0] AXI_00_MC_STATUS;
|
|
output [7:0] AXI_00_PHY_STATUS;
|
|
output [255:0] AXI_00_RDATA;
|
|
output [31:0] AXI_00_RDATA_PARITY;
|
|
output [5:0] AXI_00_RID;
|
|
output AXI_00_RLAST;
|
|
output [1:0] AXI_00_RRESP;
|
|
output AXI_00_RVALID;
|
|
output AXI_00_WREADY;
|
|
output AXI_01_ARREADY;
|
|
output AXI_01_AWREADY;
|
|
output [5:0] AXI_01_BID;
|
|
output [1:0] AXI_01_BRESP;
|
|
output AXI_01_BVALID;
|
|
output [1:0] AXI_01_DFI_AW_AERR_N;
|
|
output AXI_01_DFI_CLK_BUF;
|
|
output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_01_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_01_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_01_DFI_DW_RDDATA_VALID;
|
|
output AXI_01_DFI_INIT_COMPLETE;
|
|
output AXI_01_DFI_PHYUPD_REQ;
|
|
output AXI_01_DFI_PHY_LP_STATE;
|
|
output AXI_01_DFI_RST_N_BUF;
|
|
output [255:0] AXI_01_RDATA;
|
|
output [31:0] AXI_01_RDATA_PARITY;
|
|
output [5:0] AXI_01_RID;
|
|
output AXI_01_RLAST;
|
|
output [1:0] AXI_01_RRESP;
|
|
output AXI_01_RVALID;
|
|
output AXI_01_WREADY;
|
|
output AXI_02_ARREADY;
|
|
output AXI_02_AWREADY;
|
|
output [5:0] AXI_02_BID;
|
|
output [1:0] AXI_02_BRESP;
|
|
output AXI_02_BVALID;
|
|
output [1:0] AXI_02_DFI_AW_AERR_N;
|
|
output AXI_02_DFI_CLK_BUF;
|
|
output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_02_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_02_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_02_DFI_DW_RDDATA_VALID;
|
|
output AXI_02_DFI_INIT_COMPLETE;
|
|
output AXI_02_DFI_PHYUPD_REQ;
|
|
output AXI_02_DFI_PHY_LP_STATE;
|
|
output AXI_02_DFI_RST_N_BUF;
|
|
output [5:0] AXI_02_MC_STATUS;
|
|
output [7:0] AXI_02_PHY_STATUS;
|
|
output [255:0] AXI_02_RDATA;
|
|
output [31:0] AXI_02_RDATA_PARITY;
|
|
output [5:0] AXI_02_RID;
|
|
output AXI_02_RLAST;
|
|
output [1:0] AXI_02_RRESP;
|
|
output AXI_02_RVALID;
|
|
output AXI_02_WREADY;
|
|
output AXI_03_ARREADY;
|
|
output AXI_03_AWREADY;
|
|
output [5:0] AXI_03_BID;
|
|
output [1:0] AXI_03_BRESP;
|
|
output AXI_03_BVALID;
|
|
output [1:0] AXI_03_DFI_AW_AERR_N;
|
|
output AXI_03_DFI_CLK_BUF;
|
|
output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_03_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_03_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_03_DFI_DW_RDDATA_VALID;
|
|
output AXI_03_DFI_INIT_COMPLETE;
|
|
output AXI_03_DFI_PHYUPD_REQ;
|
|
output AXI_03_DFI_PHY_LP_STATE;
|
|
output AXI_03_DFI_RST_N_BUF;
|
|
output [255:0] AXI_03_RDATA;
|
|
output [31:0] AXI_03_RDATA_PARITY;
|
|
output [5:0] AXI_03_RID;
|
|
output AXI_03_RLAST;
|
|
output [1:0] AXI_03_RRESP;
|
|
output AXI_03_RVALID;
|
|
output AXI_03_WREADY;
|
|
output AXI_04_ARREADY;
|
|
output AXI_04_AWREADY;
|
|
output [5:0] AXI_04_BID;
|
|
output [1:0] AXI_04_BRESP;
|
|
output AXI_04_BVALID;
|
|
output [1:0] AXI_04_DFI_AW_AERR_N;
|
|
output AXI_04_DFI_CLK_BUF;
|
|
output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_04_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_04_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_04_DFI_DW_RDDATA_VALID;
|
|
output AXI_04_DFI_INIT_COMPLETE;
|
|
output AXI_04_DFI_PHYUPD_REQ;
|
|
output AXI_04_DFI_PHY_LP_STATE;
|
|
output AXI_04_DFI_RST_N_BUF;
|
|
output [5:0] AXI_04_MC_STATUS;
|
|
output [7:0] AXI_04_PHY_STATUS;
|
|
output [255:0] AXI_04_RDATA;
|
|
output [31:0] AXI_04_RDATA_PARITY;
|
|
output [5:0] AXI_04_RID;
|
|
output AXI_04_RLAST;
|
|
output [1:0] AXI_04_RRESP;
|
|
output AXI_04_RVALID;
|
|
output AXI_04_WREADY;
|
|
output AXI_05_ARREADY;
|
|
output AXI_05_AWREADY;
|
|
output [5:0] AXI_05_BID;
|
|
output [1:0] AXI_05_BRESP;
|
|
output AXI_05_BVALID;
|
|
output [1:0] AXI_05_DFI_AW_AERR_N;
|
|
output AXI_05_DFI_CLK_BUF;
|
|
output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_05_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_05_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_05_DFI_DW_RDDATA_VALID;
|
|
output AXI_05_DFI_INIT_COMPLETE;
|
|
output AXI_05_DFI_PHYUPD_REQ;
|
|
output AXI_05_DFI_PHY_LP_STATE;
|
|
output AXI_05_DFI_RST_N_BUF;
|
|
output [255:0] AXI_05_RDATA;
|
|
output [31:0] AXI_05_RDATA_PARITY;
|
|
output [5:0] AXI_05_RID;
|
|
output AXI_05_RLAST;
|
|
output [1:0] AXI_05_RRESP;
|
|
output AXI_05_RVALID;
|
|
output AXI_05_WREADY;
|
|
output AXI_06_ARREADY;
|
|
output AXI_06_AWREADY;
|
|
output [5:0] AXI_06_BID;
|
|
output [1:0] AXI_06_BRESP;
|
|
output AXI_06_BVALID;
|
|
output [1:0] AXI_06_DFI_AW_AERR_N;
|
|
output AXI_06_DFI_CLK_BUF;
|
|
output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_06_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_06_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_06_DFI_DW_RDDATA_VALID;
|
|
output AXI_06_DFI_INIT_COMPLETE;
|
|
output AXI_06_DFI_PHYUPD_REQ;
|
|
output AXI_06_DFI_PHY_LP_STATE;
|
|
output AXI_06_DFI_RST_N_BUF;
|
|
output [5:0] AXI_06_MC_STATUS;
|
|
output [7:0] AXI_06_PHY_STATUS;
|
|
output [255:0] AXI_06_RDATA;
|
|
output [31:0] AXI_06_RDATA_PARITY;
|
|
output [5:0] AXI_06_RID;
|
|
output AXI_06_RLAST;
|
|
output [1:0] AXI_06_RRESP;
|
|
output AXI_06_RVALID;
|
|
output AXI_06_WREADY;
|
|
output AXI_07_ARREADY;
|
|
output AXI_07_AWREADY;
|
|
output [5:0] AXI_07_BID;
|
|
output [1:0] AXI_07_BRESP;
|
|
output AXI_07_BVALID;
|
|
output [1:0] AXI_07_DFI_AW_AERR_N;
|
|
output AXI_07_DFI_CLK_BUF;
|
|
output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_07_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_07_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_07_DFI_DW_RDDATA_VALID;
|
|
output AXI_07_DFI_INIT_COMPLETE;
|
|
output AXI_07_DFI_PHYUPD_REQ;
|
|
output AXI_07_DFI_PHY_LP_STATE;
|
|
output AXI_07_DFI_RST_N_BUF;
|
|
output [255:0] AXI_07_RDATA;
|
|
output [31:0] AXI_07_RDATA_PARITY;
|
|
output [5:0] AXI_07_RID;
|
|
output AXI_07_RLAST;
|
|
output [1:0] AXI_07_RRESP;
|
|
output AXI_07_RVALID;
|
|
output AXI_07_WREADY;
|
|
output AXI_08_ARREADY;
|
|
output AXI_08_AWREADY;
|
|
output [5:0] AXI_08_BID;
|
|
output [1:0] AXI_08_BRESP;
|
|
output AXI_08_BVALID;
|
|
output [1:0] AXI_08_DFI_AW_AERR_N;
|
|
output AXI_08_DFI_CLK_BUF;
|
|
output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_08_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_08_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_08_DFI_DW_RDDATA_VALID;
|
|
output AXI_08_DFI_INIT_COMPLETE;
|
|
output AXI_08_DFI_PHYUPD_REQ;
|
|
output AXI_08_DFI_PHY_LP_STATE;
|
|
output AXI_08_DFI_RST_N_BUF;
|
|
output [5:0] AXI_08_MC_STATUS;
|
|
output [7:0] AXI_08_PHY_STATUS;
|
|
output [255:0] AXI_08_RDATA;
|
|
output [31:0] AXI_08_RDATA_PARITY;
|
|
output [5:0] AXI_08_RID;
|
|
output AXI_08_RLAST;
|
|
output [1:0] AXI_08_RRESP;
|
|
output AXI_08_RVALID;
|
|
output AXI_08_WREADY;
|
|
output AXI_09_ARREADY;
|
|
output AXI_09_AWREADY;
|
|
output [5:0] AXI_09_BID;
|
|
output [1:0] AXI_09_BRESP;
|
|
output AXI_09_BVALID;
|
|
output [1:0] AXI_09_DFI_AW_AERR_N;
|
|
output AXI_09_DFI_CLK_BUF;
|
|
output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_09_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_09_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_09_DFI_DW_RDDATA_VALID;
|
|
output AXI_09_DFI_INIT_COMPLETE;
|
|
output AXI_09_DFI_PHYUPD_REQ;
|
|
output AXI_09_DFI_PHY_LP_STATE;
|
|
output AXI_09_DFI_RST_N_BUF;
|
|
output [255:0] AXI_09_RDATA;
|
|
output [31:0] AXI_09_RDATA_PARITY;
|
|
output [5:0] AXI_09_RID;
|
|
output AXI_09_RLAST;
|
|
output [1:0] AXI_09_RRESP;
|
|
output AXI_09_RVALID;
|
|
output AXI_09_WREADY;
|
|
output AXI_10_ARREADY;
|
|
output AXI_10_AWREADY;
|
|
output [5:0] AXI_10_BID;
|
|
output [1:0] AXI_10_BRESP;
|
|
output AXI_10_BVALID;
|
|
output [1:0] AXI_10_DFI_AW_AERR_N;
|
|
output AXI_10_DFI_CLK_BUF;
|
|
output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_10_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_10_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_10_DFI_DW_RDDATA_VALID;
|
|
output AXI_10_DFI_INIT_COMPLETE;
|
|
output AXI_10_DFI_PHYUPD_REQ;
|
|
output AXI_10_DFI_PHY_LP_STATE;
|
|
output AXI_10_DFI_RST_N_BUF;
|
|
output [5:0] AXI_10_MC_STATUS;
|
|
output [7:0] AXI_10_PHY_STATUS;
|
|
output [255:0] AXI_10_RDATA;
|
|
output [31:0] AXI_10_RDATA_PARITY;
|
|
output [5:0] AXI_10_RID;
|
|
output AXI_10_RLAST;
|
|
output [1:0] AXI_10_RRESP;
|
|
output AXI_10_RVALID;
|
|
output AXI_10_WREADY;
|
|
output AXI_11_ARREADY;
|
|
output AXI_11_AWREADY;
|
|
output [5:0] AXI_11_BID;
|
|
output [1:0] AXI_11_BRESP;
|
|
output AXI_11_BVALID;
|
|
output [1:0] AXI_11_DFI_AW_AERR_N;
|
|
output AXI_11_DFI_CLK_BUF;
|
|
output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_11_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_11_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_11_DFI_DW_RDDATA_VALID;
|
|
output AXI_11_DFI_INIT_COMPLETE;
|
|
output AXI_11_DFI_PHYUPD_REQ;
|
|
output AXI_11_DFI_PHY_LP_STATE;
|
|
output AXI_11_DFI_RST_N_BUF;
|
|
output [255:0] AXI_11_RDATA;
|
|
output [31:0] AXI_11_RDATA_PARITY;
|
|
output [5:0] AXI_11_RID;
|
|
output AXI_11_RLAST;
|
|
output [1:0] AXI_11_RRESP;
|
|
output AXI_11_RVALID;
|
|
output AXI_11_WREADY;
|
|
output AXI_12_ARREADY;
|
|
output AXI_12_AWREADY;
|
|
output [5:0] AXI_12_BID;
|
|
output [1:0] AXI_12_BRESP;
|
|
output AXI_12_BVALID;
|
|
output [1:0] AXI_12_DFI_AW_AERR_N;
|
|
output AXI_12_DFI_CLK_BUF;
|
|
output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_12_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_12_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_12_DFI_DW_RDDATA_VALID;
|
|
output AXI_12_DFI_INIT_COMPLETE;
|
|
output AXI_12_DFI_PHYUPD_REQ;
|
|
output AXI_12_DFI_PHY_LP_STATE;
|
|
output AXI_12_DFI_RST_N_BUF;
|
|
output [5:0] AXI_12_MC_STATUS;
|
|
output [7:0] AXI_12_PHY_STATUS;
|
|
output [255:0] AXI_12_RDATA;
|
|
output [31:0] AXI_12_RDATA_PARITY;
|
|
output [5:0] AXI_12_RID;
|
|
output AXI_12_RLAST;
|
|
output [1:0] AXI_12_RRESP;
|
|
output AXI_12_RVALID;
|
|
output AXI_12_WREADY;
|
|
output AXI_13_ARREADY;
|
|
output AXI_13_AWREADY;
|
|
output [5:0] AXI_13_BID;
|
|
output [1:0] AXI_13_BRESP;
|
|
output AXI_13_BVALID;
|
|
output [1:0] AXI_13_DFI_AW_AERR_N;
|
|
output AXI_13_DFI_CLK_BUF;
|
|
output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_13_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_13_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_13_DFI_DW_RDDATA_VALID;
|
|
output AXI_13_DFI_INIT_COMPLETE;
|
|
output AXI_13_DFI_PHYUPD_REQ;
|
|
output AXI_13_DFI_PHY_LP_STATE;
|
|
output AXI_13_DFI_RST_N_BUF;
|
|
output [255:0] AXI_13_RDATA;
|
|
output [31:0] AXI_13_RDATA_PARITY;
|
|
output [5:0] AXI_13_RID;
|
|
output AXI_13_RLAST;
|
|
output [1:0] AXI_13_RRESP;
|
|
output AXI_13_RVALID;
|
|
output AXI_13_WREADY;
|
|
output AXI_14_ARREADY;
|
|
output AXI_14_AWREADY;
|
|
output [5:0] AXI_14_BID;
|
|
output [1:0] AXI_14_BRESP;
|
|
output AXI_14_BVALID;
|
|
output [1:0] AXI_14_DFI_AW_AERR_N;
|
|
output AXI_14_DFI_CLK_BUF;
|
|
output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_14_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_14_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_14_DFI_DW_RDDATA_VALID;
|
|
output AXI_14_DFI_INIT_COMPLETE;
|
|
output AXI_14_DFI_PHYUPD_REQ;
|
|
output AXI_14_DFI_PHY_LP_STATE;
|
|
output AXI_14_DFI_RST_N_BUF;
|
|
output [5:0] AXI_14_MC_STATUS;
|
|
output [7:0] AXI_14_PHY_STATUS;
|
|
output [255:0] AXI_14_RDATA;
|
|
output [31:0] AXI_14_RDATA_PARITY;
|
|
output [5:0] AXI_14_RID;
|
|
output AXI_14_RLAST;
|
|
output [1:0] AXI_14_RRESP;
|
|
output AXI_14_RVALID;
|
|
output AXI_14_WREADY;
|
|
output AXI_15_ARREADY;
|
|
output AXI_15_AWREADY;
|
|
output [5:0] AXI_15_BID;
|
|
output [1:0] AXI_15_BRESP;
|
|
output AXI_15_BVALID;
|
|
output [1:0] AXI_15_DFI_AW_AERR_N;
|
|
output AXI_15_DFI_CLK_BUF;
|
|
output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_15_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_15_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_15_DFI_DW_RDDATA_VALID;
|
|
output AXI_15_DFI_INIT_COMPLETE;
|
|
output AXI_15_DFI_PHYUPD_REQ;
|
|
output AXI_15_DFI_PHY_LP_STATE;
|
|
output AXI_15_DFI_RST_N_BUF;
|
|
output [255:0] AXI_15_RDATA;
|
|
output [31:0] AXI_15_RDATA_PARITY;
|
|
output [5:0] AXI_15_RID;
|
|
output AXI_15_RLAST;
|
|
output [1:0] AXI_15_RRESP;
|
|
output AXI_15_RVALID;
|
|
output AXI_15_WREADY;
|
|
output AXI_16_ARREADY;
|
|
output AXI_16_AWREADY;
|
|
output [5:0] AXI_16_BID;
|
|
output [1:0] AXI_16_BRESP;
|
|
output AXI_16_BVALID;
|
|
output [1:0] AXI_16_DFI_AW_AERR_N;
|
|
output AXI_16_DFI_CLK_BUF;
|
|
output [7:0] AXI_16_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_16_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_16_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_16_DFI_DW_RDDATA_VALID;
|
|
output AXI_16_DFI_INIT_COMPLETE;
|
|
output AXI_16_DFI_PHYUPD_REQ;
|
|
output AXI_16_DFI_PHY_LP_STATE;
|
|
output AXI_16_DFI_RST_N_BUF;
|
|
output [5:0] AXI_16_MC_STATUS;
|
|
output [7:0] AXI_16_PHY_STATUS;
|
|
output [255:0] AXI_16_RDATA;
|
|
output [31:0] AXI_16_RDATA_PARITY;
|
|
output [5:0] AXI_16_RID;
|
|
output AXI_16_RLAST;
|
|
output [1:0] AXI_16_RRESP;
|
|
output AXI_16_RVALID;
|
|
output AXI_16_WREADY;
|
|
output AXI_17_ARREADY;
|
|
output AXI_17_AWREADY;
|
|
output [5:0] AXI_17_BID;
|
|
output [1:0] AXI_17_BRESP;
|
|
output AXI_17_BVALID;
|
|
output [1:0] AXI_17_DFI_AW_AERR_N;
|
|
output AXI_17_DFI_CLK_BUF;
|
|
output [7:0] AXI_17_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_17_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_17_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_17_DFI_DW_RDDATA_VALID;
|
|
output AXI_17_DFI_INIT_COMPLETE;
|
|
output AXI_17_DFI_PHYUPD_REQ;
|
|
output AXI_17_DFI_PHY_LP_STATE;
|
|
output AXI_17_DFI_RST_N_BUF;
|
|
output [255:0] AXI_17_RDATA;
|
|
output [31:0] AXI_17_RDATA_PARITY;
|
|
output [5:0] AXI_17_RID;
|
|
output AXI_17_RLAST;
|
|
output [1:0] AXI_17_RRESP;
|
|
output AXI_17_RVALID;
|
|
output AXI_17_WREADY;
|
|
output AXI_18_ARREADY;
|
|
output AXI_18_AWREADY;
|
|
output [5:0] AXI_18_BID;
|
|
output [1:0] AXI_18_BRESP;
|
|
output AXI_18_BVALID;
|
|
output [1:0] AXI_18_DFI_AW_AERR_N;
|
|
output AXI_18_DFI_CLK_BUF;
|
|
output [7:0] AXI_18_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_18_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_18_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_18_DFI_DW_RDDATA_VALID;
|
|
output AXI_18_DFI_INIT_COMPLETE;
|
|
output AXI_18_DFI_PHYUPD_REQ;
|
|
output AXI_18_DFI_PHY_LP_STATE;
|
|
output AXI_18_DFI_RST_N_BUF;
|
|
output [5:0] AXI_18_MC_STATUS;
|
|
output [7:0] AXI_18_PHY_STATUS;
|
|
output [255:0] AXI_18_RDATA;
|
|
output [31:0] AXI_18_RDATA_PARITY;
|
|
output [5:0] AXI_18_RID;
|
|
output AXI_18_RLAST;
|
|
output [1:0] AXI_18_RRESP;
|
|
output AXI_18_RVALID;
|
|
output AXI_18_WREADY;
|
|
output AXI_19_ARREADY;
|
|
output AXI_19_AWREADY;
|
|
output [5:0] AXI_19_BID;
|
|
output [1:0] AXI_19_BRESP;
|
|
output AXI_19_BVALID;
|
|
output [1:0] AXI_19_DFI_AW_AERR_N;
|
|
output AXI_19_DFI_CLK_BUF;
|
|
output [7:0] AXI_19_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_19_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_19_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_19_DFI_DW_RDDATA_VALID;
|
|
output AXI_19_DFI_INIT_COMPLETE;
|
|
output AXI_19_DFI_PHYUPD_REQ;
|
|
output AXI_19_DFI_PHY_LP_STATE;
|
|
output AXI_19_DFI_RST_N_BUF;
|
|
output [255:0] AXI_19_RDATA;
|
|
output [31:0] AXI_19_RDATA_PARITY;
|
|
output [5:0] AXI_19_RID;
|
|
output AXI_19_RLAST;
|
|
output [1:0] AXI_19_RRESP;
|
|
output AXI_19_RVALID;
|
|
output AXI_19_WREADY;
|
|
output AXI_20_ARREADY;
|
|
output AXI_20_AWREADY;
|
|
output [5:0] AXI_20_BID;
|
|
output [1:0] AXI_20_BRESP;
|
|
output AXI_20_BVALID;
|
|
output [1:0] AXI_20_DFI_AW_AERR_N;
|
|
output AXI_20_DFI_CLK_BUF;
|
|
output [7:0] AXI_20_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_20_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_20_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_20_DFI_DW_RDDATA_VALID;
|
|
output AXI_20_DFI_INIT_COMPLETE;
|
|
output AXI_20_DFI_PHYUPD_REQ;
|
|
output AXI_20_DFI_PHY_LP_STATE;
|
|
output AXI_20_DFI_RST_N_BUF;
|
|
output [5:0] AXI_20_MC_STATUS;
|
|
output [7:0] AXI_20_PHY_STATUS;
|
|
output [255:0] AXI_20_RDATA;
|
|
output [31:0] AXI_20_RDATA_PARITY;
|
|
output [5:0] AXI_20_RID;
|
|
output AXI_20_RLAST;
|
|
output [1:0] AXI_20_RRESP;
|
|
output AXI_20_RVALID;
|
|
output AXI_20_WREADY;
|
|
output AXI_21_ARREADY;
|
|
output AXI_21_AWREADY;
|
|
output [5:0] AXI_21_BID;
|
|
output [1:0] AXI_21_BRESP;
|
|
output AXI_21_BVALID;
|
|
output [1:0] AXI_21_DFI_AW_AERR_N;
|
|
output AXI_21_DFI_CLK_BUF;
|
|
output [7:0] AXI_21_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_21_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_21_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_21_DFI_DW_RDDATA_VALID;
|
|
output AXI_21_DFI_INIT_COMPLETE;
|
|
output AXI_21_DFI_PHYUPD_REQ;
|
|
output AXI_21_DFI_PHY_LP_STATE;
|
|
output AXI_21_DFI_RST_N_BUF;
|
|
output [255:0] AXI_21_RDATA;
|
|
output [31:0] AXI_21_RDATA_PARITY;
|
|
output [5:0] AXI_21_RID;
|
|
output AXI_21_RLAST;
|
|
output [1:0] AXI_21_RRESP;
|
|
output AXI_21_RVALID;
|
|
output AXI_21_WREADY;
|
|
output AXI_22_ARREADY;
|
|
output AXI_22_AWREADY;
|
|
output [5:0] AXI_22_BID;
|
|
output [1:0] AXI_22_BRESP;
|
|
output AXI_22_BVALID;
|
|
output [1:0] AXI_22_DFI_AW_AERR_N;
|
|
output AXI_22_DFI_CLK_BUF;
|
|
output [7:0] AXI_22_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_22_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_22_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_22_DFI_DW_RDDATA_VALID;
|
|
output AXI_22_DFI_INIT_COMPLETE;
|
|
output AXI_22_DFI_PHYUPD_REQ;
|
|
output AXI_22_DFI_PHY_LP_STATE;
|
|
output AXI_22_DFI_RST_N_BUF;
|
|
output [5:0] AXI_22_MC_STATUS;
|
|
output [7:0] AXI_22_PHY_STATUS;
|
|
output [255:0] AXI_22_RDATA;
|
|
output [31:0] AXI_22_RDATA_PARITY;
|
|
output [5:0] AXI_22_RID;
|
|
output AXI_22_RLAST;
|
|
output [1:0] AXI_22_RRESP;
|
|
output AXI_22_RVALID;
|
|
output AXI_22_WREADY;
|
|
output AXI_23_ARREADY;
|
|
output AXI_23_AWREADY;
|
|
output [5:0] AXI_23_BID;
|
|
output [1:0] AXI_23_BRESP;
|
|
output AXI_23_BVALID;
|
|
output [1:0] AXI_23_DFI_AW_AERR_N;
|
|
output AXI_23_DFI_CLK_BUF;
|
|
output [7:0] AXI_23_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_23_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_23_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_23_DFI_DW_RDDATA_VALID;
|
|
output AXI_23_DFI_INIT_COMPLETE;
|
|
output AXI_23_DFI_PHYUPD_REQ;
|
|
output AXI_23_DFI_PHY_LP_STATE;
|
|
output AXI_23_DFI_RST_N_BUF;
|
|
output [255:0] AXI_23_RDATA;
|
|
output [31:0] AXI_23_RDATA_PARITY;
|
|
output [5:0] AXI_23_RID;
|
|
output AXI_23_RLAST;
|
|
output [1:0] AXI_23_RRESP;
|
|
output AXI_23_RVALID;
|
|
output AXI_23_WREADY;
|
|
output AXI_24_ARREADY;
|
|
output AXI_24_AWREADY;
|
|
output [5:0] AXI_24_BID;
|
|
output [1:0] AXI_24_BRESP;
|
|
output AXI_24_BVALID;
|
|
output [1:0] AXI_24_DFI_AW_AERR_N;
|
|
output AXI_24_DFI_CLK_BUF;
|
|
output [7:0] AXI_24_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_24_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_24_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_24_DFI_DW_RDDATA_VALID;
|
|
output AXI_24_DFI_INIT_COMPLETE;
|
|
output AXI_24_DFI_PHYUPD_REQ;
|
|
output AXI_24_DFI_PHY_LP_STATE;
|
|
output AXI_24_DFI_RST_N_BUF;
|
|
output [5:0] AXI_24_MC_STATUS;
|
|
output [7:0] AXI_24_PHY_STATUS;
|
|
output [255:0] AXI_24_RDATA;
|
|
output [31:0] AXI_24_RDATA_PARITY;
|
|
output [5:0] AXI_24_RID;
|
|
output AXI_24_RLAST;
|
|
output [1:0] AXI_24_RRESP;
|
|
output AXI_24_RVALID;
|
|
output AXI_24_WREADY;
|
|
output AXI_25_ARREADY;
|
|
output AXI_25_AWREADY;
|
|
output [5:0] AXI_25_BID;
|
|
output [1:0] AXI_25_BRESP;
|
|
output AXI_25_BVALID;
|
|
output [1:0] AXI_25_DFI_AW_AERR_N;
|
|
output AXI_25_DFI_CLK_BUF;
|
|
output [7:0] AXI_25_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_25_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_25_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_25_DFI_DW_RDDATA_VALID;
|
|
output AXI_25_DFI_INIT_COMPLETE;
|
|
output AXI_25_DFI_PHYUPD_REQ;
|
|
output AXI_25_DFI_PHY_LP_STATE;
|
|
output AXI_25_DFI_RST_N_BUF;
|
|
output [255:0] AXI_25_RDATA;
|
|
output [31:0] AXI_25_RDATA_PARITY;
|
|
output [5:0] AXI_25_RID;
|
|
output AXI_25_RLAST;
|
|
output [1:0] AXI_25_RRESP;
|
|
output AXI_25_RVALID;
|
|
output AXI_25_WREADY;
|
|
output AXI_26_ARREADY;
|
|
output AXI_26_AWREADY;
|
|
output [5:0] AXI_26_BID;
|
|
output [1:0] AXI_26_BRESP;
|
|
output AXI_26_BVALID;
|
|
output [1:0] AXI_26_DFI_AW_AERR_N;
|
|
output AXI_26_DFI_CLK_BUF;
|
|
output [7:0] AXI_26_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_26_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_26_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_26_DFI_DW_RDDATA_VALID;
|
|
output AXI_26_DFI_INIT_COMPLETE;
|
|
output AXI_26_DFI_PHYUPD_REQ;
|
|
output AXI_26_DFI_PHY_LP_STATE;
|
|
output AXI_26_DFI_RST_N_BUF;
|
|
output [5:0] AXI_26_MC_STATUS;
|
|
output [7:0] AXI_26_PHY_STATUS;
|
|
output [255:0] AXI_26_RDATA;
|
|
output [31:0] AXI_26_RDATA_PARITY;
|
|
output [5:0] AXI_26_RID;
|
|
output AXI_26_RLAST;
|
|
output [1:0] AXI_26_RRESP;
|
|
output AXI_26_RVALID;
|
|
output AXI_26_WREADY;
|
|
output AXI_27_ARREADY;
|
|
output AXI_27_AWREADY;
|
|
output [5:0] AXI_27_BID;
|
|
output [1:0] AXI_27_BRESP;
|
|
output AXI_27_BVALID;
|
|
output [1:0] AXI_27_DFI_AW_AERR_N;
|
|
output AXI_27_DFI_CLK_BUF;
|
|
output [7:0] AXI_27_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_27_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_27_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_27_DFI_DW_RDDATA_VALID;
|
|
output AXI_27_DFI_INIT_COMPLETE;
|
|
output AXI_27_DFI_PHYUPD_REQ;
|
|
output AXI_27_DFI_PHY_LP_STATE;
|
|
output AXI_27_DFI_RST_N_BUF;
|
|
output [255:0] AXI_27_RDATA;
|
|
output [31:0] AXI_27_RDATA_PARITY;
|
|
output [5:0] AXI_27_RID;
|
|
output AXI_27_RLAST;
|
|
output [1:0] AXI_27_RRESP;
|
|
output AXI_27_RVALID;
|
|
output AXI_27_WREADY;
|
|
output AXI_28_ARREADY;
|
|
output AXI_28_AWREADY;
|
|
output [5:0] AXI_28_BID;
|
|
output [1:0] AXI_28_BRESP;
|
|
output AXI_28_BVALID;
|
|
output [1:0] AXI_28_DFI_AW_AERR_N;
|
|
output AXI_28_DFI_CLK_BUF;
|
|
output [7:0] AXI_28_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_28_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_28_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_28_DFI_DW_RDDATA_VALID;
|
|
output AXI_28_DFI_INIT_COMPLETE;
|
|
output AXI_28_DFI_PHYUPD_REQ;
|
|
output AXI_28_DFI_PHY_LP_STATE;
|
|
output AXI_28_DFI_RST_N_BUF;
|
|
output [5:0] AXI_28_MC_STATUS;
|
|
output [7:0] AXI_28_PHY_STATUS;
|
|
output [255:0] AXI_28_RDATA;
|
|
output [31:0] AXI_28_RDATA_PARITY;
|
|
output [5:0] AXI_28_RID;
|
|
output AXI_28_RLAST;
|
|
output [1:0] AXI_28_RRESP;
|
|
output AXI_28_RVALID;
|
|
output AXI_28_WREADY;
|
|
output AXI_29_ARREADY;
|
|
output AXI_29_AWREADY;
|
|
output [5:0] AXI_29_BID;
|
|
output [1:0] AXI_29_BRESP;
|
|
output AXI_29_BVALID;
|
|
output [1:0] AXI_29_DFI_AW_AERR_N;
|
|
output AXI_29_DFI_CLK_BUF;
|
|
output [7:0] AXI_29_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_29_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_29_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_29_DFI_DW_RDDATA_VALID;
|
|
output AXI_29_DFI_INIT_COMPLETE;
|
|
output AXI_29_DFI_PHYUPD_REQ;
|
|
output AXI_29_DFI_PHY_LP_STATE;
|
|
output AXI_29_DFI_RST_N_BUF;
|
|
output [255:0] AXI_29_RDATA;
|
|
output [31:0] AXI_29_RDATA_PARITY;
|
|
output [5:0] AXI_29_RID;
|
|
output AXI_29_RLAST;
|
|
output [1:0] AXI_29_RRESP;
|
|
output AXI_29_RVALID;
|
|
output AXI_29_WREADY;
|
|
output AXI_30_ARREADY;
|
|
output AXI_30_AWREADY;
|
|
output [5:0] AXI_30_BID;
|
|
output [1:0] AXI_30_BRESP;
|
|
output AXI_30_BVALID;
|
|
output [1:0] AXI_30_DFI_AW_AERR_N;
|
|
output AXI_30_DFI_CLK_BUF;
|
|
output [7:0] AXI_30_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_30_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_30_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_30_DFI_DW_RDDATA_VALID;
|
|
output AXI_30_DFI_INIT_COMPLETE;
|
|
output AXI_30_DFI_PHYUPD_REQ;
|
|
output AXI_30_DFI_PHY_LP_STATE;
|
|
output AXI_30_DFI_RST_N_BUF;
|
|
output [5:0] AXI_30_MC_STATUS;
|
|
output [7:0] AXI_30_PHY_STATUS;
|
|
output [255:0] AXI_30_RDATA;
|
|
output [31:0] AXI_30_RDATA_PARITY;
|
|
output [5:0] AXI_30_RID;
|
|
output AXI_30_RLAST;
|
|
output [1:0] AXI_30_RRESP;
|
|
output AXI_30_RVALID;
|
|
output AXI_30_WREADY;
|
|
output AXI_31_ARREADY;
|
|
output AXI_31_AWREADY;
|
|
output [5:0] AXI_31_BID;
|
|
output [1:0] AXI_31_BRESP;
|
|
output AXI_31_BVALID;
|
|
output [1:0] AXI_31_DFI_AW_AERR_N;
|
|
output AXI_31_DFI_CLK_BUF;
|
|
output [7:0] AXI_31_DFI_DBI_BYTE_DISABLE;
|
|
output [20:0] AXI_31_DFI_DW_RDDATA_DBI;
|
|
output [7:0] AXI_31_DFI_DW_RDDATA_DERR;
|
|
output [1:0] AXI_31_DFI_DW_RDDATA_VALID;
|
|
output AXI_31_DFI_INIT_COMPLETE;
|
|
output AXI_31_DFI_PHYUPD_REQ;
|
|
output AXI_31_DFI_PHY_LP_STATE;
|
|
output AXI_31_DFI_RST_N_BUF;
|
|
output [255:0] AXI_31_RDATA;
|
|
output [31:0] AXI_31_RDATA_PARITY;
|
|
output [5:0] AXI_31_RID;
|
|
output AXI_31_RLAST;
|
|
output [1:0] AXI_31_RRESP;
|
|
output AXI_31_RVALID;
|
|
output AXI_31_WREADY;
|
|
output DRAM_0_STAT_CATTRIP;
|
|
output [2:0] DRAM_0_STAT_TEMP;
|
|
output DRAM_1_STAT_CATTRIP;
|
|
output [2:0] DRAM_1_STAT_TEMP;
|
|
input [21:0] APB_0_PADDR;
|
|
(* invertible_pin = "IS_APB_0_PCLK_INVERTED" *)
|
|
input APB_0_PCLK;
|
|
input APB_0_PENABLE;
|
|
(* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *)
|
|
input APB_0_PRESET_N;
|
|
input APB_0_PSEL;
|
|
input [31:0] APB_0_PWDATA;
|
|
input APB_0_PWRITE;
|
|
input [21:0] APB_1_PADDR;
|
|
(* invertible_pin = "IS_APB_1_PCLK_INVERTED" *)
|
|
input APB_1_PCLK;
|
|
input APB_1_PENABLE;
|
|
(* invertible_pin = "IS_APB_1_PRESET_N_INVERTED" *)
|
|
input APB_1_PRESET_N;
|
|
input APB_1_PSEL;
|
|
input [31:0] APB_1_PWDATA;
|
|
input APB_1_PWRITE;
|
|
(* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *)
|
|
input AXI_00_ACLK;
|
|
input [36:0] AXI_00_ARADDR;
|
|
input [1:0] AXI_00_ARBURST;
|
|
(* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *)
|
|
input AXI_00_ARESET_N;
|
|
input [5:0] AXI_00_ARID;
|
|
input [3:0] AXI_00_ARLEN;
|
|
input [2:0] AXI_00_ARSIZE;
|
|
input AXI_00_ARVALID;
|
|
input [36:0] AXI_00_AWADDR;
|
|
input [1:0] AXI_00_AWBURST;
|
|
input [5:0] AXI_00_AWID;
|
|
input [3:0] AXI_00_AWLEN;
|
|
input [2:0] AXI_00_AWSIZE;
|
|
input AXI_00_AWVALID;
|
|
input AXI_00_BREADY;
|
|
input AXI_00_DFI_LP_PWR_X_REQ;
|
|
input AXI_00_RREADY;
|
|
input [255:0] AXI_00_WDATA;
|
|
input [31:0] AXI_00_WDATA_PARITY;
|
|
input AXI_00_WLAST;
|
|
input [31:0] AXI_00_WSTRB;
|
|
input AXI_00_WVALID;
|
|
(* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *)
|
|
input AXI_01_ACLK;
|
|
input [36:0] AXI_01_ARADDR;
|
|
input [1:0] AXI_01_ARBURST;
|
|
(* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *)
|
|
input AXI_01_ARESET_N;
|
|
input [5:0] AXI_01_ARID;
|
|
input [3:0] AXI_01_ARLEN;
|
|
input [2:0] AXI_01_ARSIZE;
|
|
input AXI_01_ARVALID;
|
|
input [36:0] AXI_01_AWADDR;
|
|
input [1:0] AXI_01_AWBURST;
|
|
input [5:0] AXI_01_AWID;
|
|
input [3:0] AXI_01_AWLEN;
|
|
input [2:0] AXI_01_AWSIZE;
|
|
input AXI_01_AWVALID;
|
|
input AXI_01_BREADY;
|
|
input AXI_01_DFI_LP_PWR_X_REQ;
|
|
input AXI_01_RREADY;
|
|
input [255:0] AXI_01_WDATA;
|
|
input [31:0] AXI_01_WDATA_PARITY;
|
|
input AXI_01_WLAST;
|
|
input [31:0] AXI_01_WSTRB;
|
|
input AXI_01_WVALID;
|
|
(* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *)
|
|
input AXI_02_ACLK;
|
|
input [36:0] AXI_02_ARADDR;
|
|
input [1:0] AXI_02_ARBURST;
|
|
(* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *)
|
|
input AXI_02_ARESET_N;
|
|
input [5:0] AXI_02_ARID;
|
|
input [3:0] AXI_02_ARLEN;
|
|
input [2:0] AXI_02_ARSIZE;
|
|
input AXI_02_ARVALID;
|
|
input [36:0] AXI_02_AWADDR;
|
|
input [1:0] AXI_02_AWBURST;
|
|
input [5:0] AXI_02_AWID;
|
|
input [3:0] AXI_02_AWLEN;
|
|
input [2:0] AXI_02_AWSIZE;
|
|
input AXI_02_AWVALID;
|
|
input AXI_02_BREADY;
|
|
input AXI_02_DFI_LP_PWR_X_REQ;
|
|
input AXI_02_RREADY;
|
|
input [255:0] AXI_02_WDATA;
|
|
input [31:0] AXI_02_WDATA_PARITY;
|
|
input AXI_02_WLAST;
|
|
input [31:0] AXI_02_WSTRB;
|
|
input AXI_02_WVALID;
|
|
(* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *)
|
|
input AXI_03_ACLK;
|
|
input [36:0] AXI_03_ARADDR;
|
|
input [1:0] AXI_03_ARBURST;
|
|
(* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *)
|
|
input AXI_03_ARESET_N;
|
|
input [5:0] AXI_03_ARID;
|
|
input [3:0] AXI_03_ARLEN;
|
|
input [2:0] AXI_03_ARSIZE;
|
|
input AXI_03_ARVALID;
|
|
input [36:0] AXI_03_AWADDR;
|
|
input [1:0] AXI_03_AWBURST;
|
|
input [5:0] AXI_03_AWID;
|
|
input [3:0] AXI_03_AWLEN;
|
|
input [2:0] AXI_03_AWSIZE;
|
|
input AXI_03_AWVALID;
|
|
input AXI_03_BREADY;
|
|
input AXI_03_DFI_LP_PWR_X_REQ;
|
|
input AXI_03_RREADY;
|
|
input [255:0] AXI_03_WDATA;
|
|
input [31:0] AXI_03_WDATA_PARITY;
|
|
input AXI_03_WLAST;
|
|
input [31:0] AXI_03_WSTRB;
|
|
input AXI_03_WVALID;
|
|
(* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *)
|
|
input AXI_04_ACLK;
|
|
input [36:0] AXI_04_ARADDR;
|
|
input [1:0] AXI_04_ARBURST;
|
|
(* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *)
|
|
input AXI_04_ARESET_N;
|
|
input [5:0] AXI_04_ARID;
|
|
input [3:0] AXI_04_ARLEN;
|
|
input [2:0] AXI_04_ARSIZE;
|
|
input AXI_04_ARVALID;
|
|
input [36:0] AXI_04_AWADDR;
|
|
input [1:0] AXI_04_AWBURST;
|
|
input [5:0] AXI_04_AWID;
|
|
input [3:0] AXI_04_AWLEN;
|
|
input [2:0] AXI_04_AWSIZE;
|
|
input AXI_04_AWVALID;
|
|
input AXI_04_BREADY;
|
|
input AXI_04_DFI_LP_PWR_X_REQ;
|
|
input AXI_04_RREADY;
|
|
input [255:0] AXI_04_WDATA;
|
|
input [31:0] AXI_04_WDATA_PARITY;
|
|
input AXI_04_WLAST;
|
|
input [31:0] AXI_04_WSTRB;
|
|
input AXI_04_WVALID;
|
|
(* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *)
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input AXI_05_ACLK;
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input [36:0] AXI_05_ARADDR;
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input [1:0] AXI_05_ARBURST;
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(* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *)
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input AXI_05_ARESET_N;
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|
input [5:0] AXI_05_ARID;
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|
input [3:0] AXI_05_ARLEN;
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|
input [2:0] AXI_05_ARSIZE;
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|
input AXI_05_ARVALID;
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|
input [36:0] AXI_05_AWADDR;
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|
input [1:0] AXI_05_AWBURST;
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input [5:0] AXI_05_AWID;
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input [3:0] AXI_05_AWLEN;
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input [2:0] AXI_05_AWSIZE;
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|
input AXI_05_AWVALID;
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input AXI_05_BREADY;
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input AXI_05_DFI_LP_PWR_X_REQ;
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input AXI_05_RREADY;
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input [255:0] AXI_05_WDATA;
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input [31:0] AXI_05_WDATA_PARITY;
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input AXI_05_WLAST;
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input [31:0] AXI_05_WSTRB;
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input AXI_05_WVALID;
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(* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *)
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input AXI_06_ACLK;
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input [36:0] AXI_06_ARADDR;
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input [1:0] AXI_06_ARBURST;
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(* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *)
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input AXI_06_ARESET_N;
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input [5:0] AXI_06_ARID;
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input [3:0] AXI_06_ARLEN;
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input [2:0] AXI_06_ARSIZE;
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input AXI_06_ARVALID;
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input [36:0] AXI_06_AWADDR;
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input [1:0] AXI_06_AWBURST;
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input [5:0] AXI_06_AWID;
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input [3:0] AXI_06_AWLEN;
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input [2:0] AXI_06_AWSIZE;
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input AXI_06_AWVALID;
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input AXI_06_BREADY;
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input AXI_06_DFI_LP_PWR_X_REQ;
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input AXI_06_RREADY;
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input [255:0] AXI_06_WDATA;
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input [31:0] AXI_06_WDATA_PARITY;
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input AXI_06_WLAST;
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input [31:0] AXI_06_WSTRB;
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input AXI_06_WVALID;
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(* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *)
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input AXI_07_ACLK;
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input [36:0] AXI_07_ARADDR;
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input [1:0] AXI_07_ARBURST;
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(* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *)
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input AXI_07_ARESET_N;
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input [5:0] AXI_07_ARID;
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input [3:0] AXI_07_ARLEN;
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input [2:0] AXI_07_ARSIZE;
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input AXI_07_ARVALID;
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input [36:0] AXI_07_AWADDR;
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input [1:0] AXI_07_AWBURST;
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input [5:0] AXI_07_AWID;
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input [3:0] AXI_07_AWLEN;
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input [2:0] AXI_07_AWSIZE;
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input AXI_07_AWVALID;
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input AXI_07_BREADY;
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input AXI_07_DFI_LP_PWR_X_REQ;
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input AXI_07_RREADY;
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input [255:0] AXI_07_WDATA;
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input [31:0] AXI_07_WDATA_PARITY;
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input AXI_07_WLAST;
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input [31:0] AXI_07_WSTRB;
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input AXI_07_WVALID;
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(* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *)
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input AXI_08_ACLK;
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input [36:0] AXI_08_ARADDR;
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input [1:0] AXI_08_ARBURST;
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(* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *)
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input AXI_08_ARESET_N;
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input [5:0] AXI_08_ARID;
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input [3:0] AXI_08_ARLEN;
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input [2:0] AXI_08_ARSIZE;
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input AXI_08_ARVALID;
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input [36:0] AXI_08_AWADDR;
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input [1:0] AXI_08_AWBURST;
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input [5:0] AXI_08_AWID;
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input [3:0] AXI_08_AWLEN;
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input [2:0] AXI_08_AWSIZE;
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input AXI_08_AWVALID;
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input AXI_08_BREADY;
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input AXI_08_DFI_LP_PWR_X_REQ;
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input AXI_08_RREADY;
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input [255:0] AXI_08_WDATA;
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input [31:0] AXI_08_WDATA_PARITY;
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input AXI_08_WLAST;
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input [31:0] AXI_08_WSTRB;
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input AXI_08_WVALID;
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(* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *)
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input AXI_09_ACLK;
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input [36:0] AXI_09_ARADDR;
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input [1:0] AXI_09_ARBURST;
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(* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *)
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input AXI_09_ARESET_N;
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input [5:0] AXI_09_ARID;
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input [3:0] AXI_09_ARLEN;
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input [2:0] AXI_09_ARSIZE;
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input AXI_09_ARVALID;
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input [36:0] AXI_09_AWADDR;
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|
input [1:0] AXI_09_AWBURST;
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|
input [5:0] AXI_09_AWID;
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|
input [3:0] AXI_09_AWLEN;
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|
input [2:0] AXI_09_AWSIZE;
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|
input AXI_09_AWVALID;
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|
input AXI_09_BREADY;
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|
input AXI_09_DFI_LP_PWR_X_REQ;
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input AXI_09_RREADY;
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|
input [255:0] AXI_09_WDATA;
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|
input [31:0] AXI_09_WDATA_PARITY;
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|
input AXI_09_WLAST;
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|
input [31:0] AXI_09_WSTRB;
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|
input AXI_09_WVALID;
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|
(* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *)
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|
input AXI_10_ACLK;
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input [36:0] AXI_10_ARADDR;
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input [1:0] AXI_10_ARBURST;
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|
(* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *)
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input AXI_10_ARESET_N;
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input [5:0] AXI_10_ARID;
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input [3:0] AXI_10_ARLEN;
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input [2:0] AXI_10_ARSIZE;
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input AXI_10_ARVALID;
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|
input [36:0] AXI_10_AWADDR;
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|
input [1:0] AXI_10_AWBURST;
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|
input [5:0] AXI_10_AWID;
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|
input [3:0] AXI_10_AWLEN;
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|
input [2:0] AXI_10_AWSIZE;
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|
input AXI_10_AWVALID;
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|
input AXI_10_BREADY;
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input AXI_10_DFI_LP_PWR_X_REQ;
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input AXI_10_RREADY;
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input [255:0] AXI_10_WDATA;
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input [31:0] AXI_10_WDATA_PARITY;
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input AXI_10_WLAST;
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input [31:0] AXI_10_WSTRB;
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input AXI_10_WVALID;
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|
(* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *)
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input AXI_11_ACLK;
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input [36:0] AXI_11_ARADDR;
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input [1:0] AXI_11_ARBURST;
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(* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *)
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input AXI_11_ARESET_N;
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input [5:0] AXI_11_ARID;
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input [3:0] AXI_11_ARLEN;
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|
input [2:0] AXI_11_ARSIZE;
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|
input AXI_11_ARVALID;
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|
input [36:0] AXI_11_AWADDR;
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input [1:0] AXI_11_AWBURST;
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|
input [5:0] AXI_11_AWID;
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input [3:0] AXI_11_AWLEN;
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|
input [2:0] AXI_11_AWSIZE;
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|
input AXI_11_AWVALID;
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|
input AXI_11_BREADY;
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input AXI_11_DFI_LP_PWR_X_REQ;
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input AXI_11_RREADY;
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input [255:0] AXI_11_WDATA;
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input [31:0] AXI_11_WDATA_PARITY;
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input AXI_11_WLAST;
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input [31:0] AXI_11_WSTRB;
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input AXI_11_WVALID;
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|
(* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *)
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input AXI_12_ACLK;
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input [36:0] AXI_12_ARADDR;
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input [1:0] AXI_12_ARBURST;
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(* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *)
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input AXI_12_ARESET_N;
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input [5:0] AXI_12_ARID;
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input [3:0] AXI_12_ARLEN;
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input [2:0] AXI_12_ARSIZE;
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input AXI_12_ARVALID;
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input [36:0] AXI_12_AWADDR;
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input [1:0] AXI_12_AWBURST;
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input [5:0] AXI_12_AWID;
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input [3:0] AXI_12_AWLEN;
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input [2:0] AXI_12_AWSIZE;
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input AXI_12_AWVALID;
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input AXI_12_BREADY;
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input AXI_12_DFI_LP_PWR_X_REQ;
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input AXI_12_RREADY;
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input [255:0] AXI_12_WDATA;
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input [31:0] AXI_12_WDATA_PARITY;
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input AXI_12_WLAST;
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input [31:0] AXI_12_WSTRB;
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input AXI_12_WVALID;
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(* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *)
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input AXI_13_ACLK;
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input [36:0] AXI_13_ARADDR;
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input [1:0] AXI_13_ARBURST;
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(* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *)
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input AXI_13_ARESET_N;
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input [5:0] AXI_13_ARID;
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input [3:0] AXI_13_ARLEN;
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input [2:0] AXI_13_ARSIZE;
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input AXI_13_ARVALID;
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input [36:0] AXI_13_AWADDR;
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input [1:0] AXI_13_AWBURST;
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input [5:0] AXI_13_AWID;
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input [3:0] AXI_13_AWLEN;
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input [2:0] AXI_13_AWSIZE;
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input AXI_13_AWVALID;
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input AXI_13_BREADY;
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input AXI_13_DFI_LP_PWR_X_REQ;
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input AXI_13_RREADY;
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input [255:0] AXI_13_WDATA;
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input [31:0] AXI_13_WDATA_PARITY;
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input AXI_13_WLAST;
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input [31:0] AXI_13_WSTRB;
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input AXI_13_WVALID;
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(* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *)
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input AXI_14_ACLK;
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input [36:0] AXI_14_ARADDR;
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input [1:0] AXI_14_ARBURST;
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(* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *)
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input AXI_14_ARESET_N;
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input [5:0] AXI_14_ARID;
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input [3:0] AXI_14_ARLEN;
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|
input [2:0] AXI_14_ARSIZE;
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input AXI_14_ARVALID;
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input [36:0] AXI_14_AWADDR;
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input [1:0] AXI_14_AWBURST;
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|
input [5:0] AXI_14_AWID;
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input [3:0] AXI_14_AWLEN;
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|
input [2:0] AXI_14_AWSIZE;
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|
input AXI_14_AWVALID;
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|
input AXI_14_BREADY;
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|
input AXI_14_DFI_LP_PWR_X_REQ;
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|
input AXI_14_RREADY;
|
|
input [255:0] AXI_14_WDATA;
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|
input [31:0] AXI_14_WDATA_PARITY;
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|
input AXI_14_WLAST;
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|
input [31:0] AXI_14_WSTRB;
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input AXI_14_WVALID;
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|
(* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *)
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input AXI_15_ACLK;
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input [36:0] AXI_15_ARADDR;
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input [1:0] AXI_15_ARBURST;
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|
(* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *)
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input AXI_15_ARESET_N;
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input [5:0] AXI_15_ARID;
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|
input [3:0] AXI_15_ARLEN;
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|
input [2:0] AXI_15_ARSIZE;
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|
input AXI_15_ARVALID;
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input [36:0] AXI_15_AWADDR;
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|
input [1:0] AXI_15_AWBURST;
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|
input [5:0] AXI_15_AWID;
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|
input [3:0] AXI_15_AWLEN;
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|
input [2:0] AXI_15_AWSIZE;
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|
input AXI_15_AWVALID;
|
|
input AXI_15_BREADY;
|
|
input AXI_15_DFI_LP_PWR_X_REQ;
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|
input AXI_15_RREADY;
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|
input [255:0] AXI_15_WDATA;
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|
input [31:0] AXI_15_WDATA_PARITY;
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|
input AXI_15_WLAST;
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|
input [31:0] AXI_15_WSTRB;
|
|
input AXI_15_WVALID;
|
|
(* invertible_pin = "IS_AXI_16_ACLK_INVERTED" *)
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input AXI_16_ACLK;
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input [36:0] AXI_16_ARADDR;
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input [1:0] AXI_16_ARBURST;
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|
(* invertible_pin = "IS_AXI_16_ARESET_N_INVERTED" *)
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|
input AXI_16_ARESET_N;
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|
input [5:0] AXI_16_ARID;
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|
input [3:0] AXI_16_ARLEN;
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|
input [2:0] AXI_16_ARSIZE;
|
|
input AXI_16_ARVALID;
|
|
input [36:0] AXI_16_AWADDR;
|
|
input [1:0] AXI_16_AWBURST;
|
|
input [5:0] AXI_16_AWID;
|
|
input [3:0] AXI_16_AWLEN;
|
|
input [2:0] AXI_16_AWSIZE;
|
|
input AXI_16_AWVALID;
|
|
input AXI_16_BREADY;
|
|
input AXI_16_DFI_LP_PWR_X_REQ;
|
|
input AXI_16_RREADY;
|
|
input [255:0] AXI_16_WDATA;
|
|
input [31:0] AXI_16_WDATA_PARITY;
|
|
input AXI_16_WLAST;
|
|
input [31:0] AXI_16_WSTRB;
|
|
input AXI_16_WVALID;
|
|
(* invertible_pin = "IS_AXI_17_ACLK_INVERTED" *)
|
|
input AXI_17_ACLK;
|
|
input [36:0] AXI_17_ARADDR;
|
|
input [1:0] AXI_17_ARBURST;
|
|
(* invertible_pin = "IS_AXI_17_ARESET_N_INVERTED" *)
|
|
input AXI_17_ARESET_N;
|
|
input [5:0] AXI_17_ARID;
|
|
input [3:0] AXI_17_ARLEN;
|
|
input [2:0] AXI_17_ARSIZE;
|
|
input AXI_17_ARVALID;
|
|
input [36:0] AXI_17_AWADDR;
|
|
input [1:0] AXI_17_AWBURST;
|
|
input [5:0] AXI_17_AWID;
|
|
input [3:0] AXI_17_AWLEN;
|
|
input [2:0] AXI_17_AWSIZE;
|
|
input AXI_17_AWVALID;
|
|
input AXI_17_BREADY;
|
|
input AXI_17_DFI_LP_PWR_X_REQ;
|
|
input AXI_17_RREADY;
|
|
input [255:0] AXI_17_WDATA;
|
|
input [31:0] AXI_17_WDATA_PARITY;
|
|
input AXI_17_WLAST;
|
|
input [31:0] AXI_17_WSTRB;
|
|
input AXI_17_WVALID;
|
|
(* invertible_pin = "IS_AXI_18_ACLK_INVERTED" *)
|
|
input AXI_18_ACLK;
|
|
input [36:0] AXI_18_ARADDR;
|
|
input [1:0] AXI_18_ARBURST;
|
|
(* invertible_pin = "IS_AXI_18_ARESET_N_INVERTED" *)
|
|
input AXI_18_ARESET_N;
|
|
input [5:0] AXI_18_ARID;
|
|
input [3:0] AXI_18_ARLEN;
|
|
input [2:0] AXI_18_ARSIZE;
|
|
input AXI_18_ARVALID;
|
|
input [36:0] AXI_18_AWADDR;
|
|
input [1:0] AXI_18_AWBURST;
|
|
input [5:0] AXI_18_AWID;
|
|
input [3:0] AXI_18_AWLEN;
|
|
input [2:0] AXI_18_AWSIZE;
|
|
input AXI_18_AWVALID;
|
|
input AXI_18_BREADY;
|
|
input AXI_18_DFI_LP_PWR_X_REQ;
|
|
input AXI_18_RREADY;
|
|
input [255:0] AXI_18_WDATA;
|
|
input [31:0] AXI_18_WDATA_PARITY;
|
|
input AXI_18_WLAST;
|
|
input [31:0] AXI_18_WSTRB;
|
|
input AXI_18_WVALID;
|
|
(* invertible_pin = "IS_AXI_19_ACLK_INVERTED" *)
|
|
input AXI_19_ACLK;
|
|
input [36:0] AXI_19_ARADDR;
|
|
input [1:0] AXI_19_ARBURST;
|
|
(* invertible_pin = "IS_AXI_19_ARESET_N_INVERTED" *)
|
|
input AXI_19_ARESET_N;
|
|
input [5:0] AXI_19_ARID;
|
|
input [3:0] AXI_19_ARLEN;
|
|
input [2:0] AXI_19_ARSIZE;
|
|
input AXI_19_ARVALID;
|
|
input [36:0] AXI_19_AWADDR;
|
|
input [1:0] AXI_19_AWBURST;
|
|
input [5:0] AXI_19_AWID;
|
|
input [3:0] AXI_19_AWLEN;
|
|
input [2:0] AXI_19_AWSIZE;
|
|
input AXI_19_AWVALID;
|
|
input AXI_19_BREADY;
|
|
input AXI_19_DFI_LP_PWR_X_REQ;
|
|
input AXI_19_RREADY;
|
|
input [255:0] AXI_19_WDATA;
|
|
input [31:0] AXI_19_WDATA_PARITY;
|
|
input AXI_19_WLAST;
|
|
input [31:0] AXI_19_WSTRB;
|
|
input AXI_19_WVALID;
|
|
(* invertible_pin = "IS_AXI_20_ACLK_INVERTED" *)
|
|
input AXI_20_ACLK;
|
|
input [36:0] AXI_20_ARADDR;
|
|
input [1:0] AXI_20_ARBURST;
|
|
(* invertible_pin = "IS_AXI_20_ARESET_N_INVERTED" *)
|
|
input AXI_20_ARESET_N;
|
|
input [5:0] AXI_20_ARID;
|
|
input [3:0] AXI_20_ARLEN;
|
|
input [2:0] AXI_20_ARSIZE;
|
|
input AXI_20_ARVALID;
|
|
input [36:0] AXI_20_AWADDR;
|
|
input [1:0] AXI_20_AWBURST;
|
|
input [5:0] AXI_20_AWID;
|
|
input [3:0] AXI_20_AWLEN;
|
|
input [2:0] AXI_20_AWSIZE;
|
|
input AXI_20_AWVALID;
|
|
input AXI_20_BREADY;
|
|
input AXI_20_DFI_LP_PWR_X_REQ;
|
|
input AXI_20_RREADY;
|
|
input [255:0] AXI_20_WDATA;
|
|
input [31:0] AXI_20_WDATA_PARITY;
|
|
input AXI_20_WLAST;
|
|
input [31:0] AXI_20_WSTRB;
|
|
input AXI_20_WVALID;
|
|
(* invertible_pin = "IS_AXI_21_ACLK_INVERTED" *)
|
|
input AXI_21_ACLK;
|
|
input [36:0] AXI_21_ARADDR;
|
|
input [1:0] AXI_21_ARBURST;
|
|
(* invertible_pin = "IS_AXI_21_ARESET_N_INVERTED" *)
|
|
input AXI_21_ARESET_N;
|
|
input [5:0] AXI_21_ARID;
|
|
input [3:0] AXI_21_ARLEN;
|
|
input [2:0] AXI_21_ARSIZE;
|
|
input AXI_21_ARVALID;
|
|
input [36:0] AXI_21_AWADDR;
|
|
input [1:0] AXI_21_AWBURST;
|
|
input [5:0] AXI_21_AWID;
|
|
input [3:0] AXI_21_AWLEN;
|
|
input [2:0] AXI_21_AWSIZE;
|
|
input AXI_21_AWVALID;
|
|
input AXI_21_BREADY;
|
|
input AXI_21_DFI_LP_PWR_X_REQ;
|
|
input AXI_21_RREADY;
|
|
input [255:0] AXI_21_WDATA;
|
|
input [31:0] AXI_21_WDATA_PARITY;
|
|
input AXI_21_WLAST;
|
|
input [31:0] AXI_21_WSTRB;
|
|
input AXI_21_WVALID;
|
|
(* invertible_pin = "IS_AXI_22_ACLK_INVERTED" *)
|
|
input AXI_22_ACLK;
|
|
input [36:0] AXI_22_ARADDR;
|
|
input [1:0] AXI_22_ARBURST;
|
|
(* invertible_pin = "IS_AXI_22_ARESET_N_INVERTED" *)
|
|
input AXI_22_ARESET_N;
|
|
input [5:0] AXI_22_ARID;
|
|
input [3:0] AXI_22_ARLEN;
|
|
input [2:0] AXI_22_ARSIZE;
|
|
input AXI_22_ARVALID;
|
|
input [36:0] AXI_22_AWADDR;
|
|
input [1:0] AXI_22_AWBURST;
|
|
input [5:0] AXI_22_AWID;
|
|
input [3:0] AXI_22_AWLEN;
|
|
input [2:0] AXI_22_AWSIZE;
|
|
input AXI_22_AWVALID;
|
|
input AXI_22_BREADY;
|
|
input AXI_22_DFI_LP_PWR_X_REQ;
|
|
input AXI_22_RREADY;
|
|
input [255:0] AXI_22_WDATA;
|
|
input [31:0] AXI_22_WDATA_PARITY;
|
|
input AXI_22_WLAST;
|
|
input [31:0] AXI_22_WSTRB;
|
|
input AXI_22_WVALID;
|
|
(* invertible_pin = "IS_AXI_23_ACLK_INVERTED" *)
|
|
input AXI_23_ACLK;
|
|
input [36:0] AXI_23_ARADDR;
|
|
input [1:0] AXI_23_ARBURST;
|
|
(* invertible_pin = "IS_AXI_23_ARESET_N_INVERTED" *)
|
|
input AXI_23_ARESET_N;
|
|
input [5:0] AXI_23_ARID;
|
|
input [3:0] AXI_23_ARLEN;
|
|
input [2:0] AXI_23_ARSIZE;
|
|
input AXI_23_ARVALID;
|
|
input [36:0] AXI_23_AWADDR;
|
|
input [1:0] AXI_23_AWBURST;
|
|
input [5:0] AXI_23_AWID;
|
|
input [3:0] AXI_23_AWLEN;
|
|
input [2:0] AXI_23_AWSIZE;
|
|
input AXI_23_AWVALID;
|
|
input AXI_23_BREADY;
|
|
input AXI_23_DFI_LP_PWR_X_REQ;
|
|
input AXI_23_RREADY;
|
|
input [255:0] AXI_23_WDATA;
|
|
input [31:0] AXI_23_WDATA_PARITY;
|
|
input AXI_23_WLAST;
|
|
input [31:0] AXI_23_WSTRB;
|
|
input AXI_23_WVALID;
|
|
(* invertible_pin = "IS_AXI_24_ACLK_INVERTED" *)
|
|
input AXI_24_ACLK;
|
|
input [36:0] AXI_24_ARADDR;
|
|
input [1:0] AXI_24_ARBURST;
|
|
(* invertible_pin = "IS_AXI_24_ARESET_N_INVERTED" *)
|
|
input AXI_24_ARESET_N;
|
|
input [5:0] AXI_24_ARID;
|
|
input [3:0] AXI_24_ARLEN;
|
|
input [2:0] AXI_24_ARSIZE;
|
|
input AXI_24_ARVALID;
|
|
input [36:0] AXI_24_AWADDR;
|
|
input [1:0] AXI_24_AWBURST;
|
|
input [5:0] AXI_24_AWID;
|
|
input [3:0] AXI_24_AWLEN;
|
|
input [2:0] AXI_24_AWSIZE;
|
|
input AXI_24_AWVALID;
|
|
input AXI_24_BREADY;
|
|
input AXI_24_DFI_LP_PWR_X_REQ;
|
|
input AXI_24_RREADY;
|
|
input [255:0] AXI_24_WDATA;
|
|
input [31:0] AXI_24_WDATA_PARITY;
|
|
input AXI_24_WLAST;
|
|
input [31:0] AXI_24_WSTRB;
|
|
input AXI_24_WVALID;
|
|
(* invertible_pin = "IS_AXI_25_ACLK_INVERTED" *)
|
|
input AXI_25_ACLK;
|
|
input [36:0] AXI_25_ARADDR;
|
|
input [1:0] AXI_25_ARBURST;
|
|
(* invertible_pin = "IS_AXI_25_ARESET_N_INVERTED" *)
|
|
input AXI_25_ARESET_N;
|
|
input [5:0] AXI_25_ARID;
|
|
input [3:0] AXI_25_ARLEN;
|
|
input [2:0] AXI_25_ARSIZE;
|
|
input AXI_25_ARVALID;
|
|
input [36:0] AXI_25_AWADDR;
|
|
input [1:0] AXI_25_AWBURST;
|
|
input [5:0] AXI_25_AWID;
|
|
input [3:0] AXI_25_AWLEN;
|
|
input [2:0] AXI_25_AWSIZE;
|
|
input AXI_25_AWVALID;
|
|
input AXI_25_BREADY;
|
|
input AXI_25_DFI_LP_PWR_X_REQ;
|
|
input AXI_25_RREADY;
|
|
input [255:0] AXI_25_WDATA;
|
|
input [31:0] AXI_25_WDATA_PARITY;
|
|
input AXI_25_WLAST;
|
|
input [31:0] AXI_25_WSTRB;
|
|
input AXI_25_WVALID;
|
|
(* invertible_pin = "IS_AXI_26_ACLK_INVERTED" *)
|
|
input AXI_26_ACLK;
|
|
input [36:0] AXI_26_ARADDR;
|
|
input [1:0] AXI_26_ARBURST;
|
|
(* invertible_pin = "IS_AXI_26_ARESET_N_INVERTED" *)
|
|
input AXI_26_ARESET_N;
|
|
input [5:0] AXI_26_ARID;
|
|
input [3:0] AXI_26_ARLEN;
|
|
input [2:0] AXI_26_ARSIZE;
|
|
input AXI_26_ARVALID;
|
|
input [36:0] AXI_26_AWADDR;
|
|
input [1:0] AXI_26_AWBURST;
|
|
input [5:0] AXI_26_AWID;
|
|
input [3:0] AXI_26_AWLEN;
|
|
input [2:0] AXI_26_AWSIZE;
|
|
input AXI_26_AWVALID;
|
|
input AXI_26_BREADY;
|
|
input AXI_26_DFI_LP_PWR_X_REQ;
|
|
input AXI_26_RREADY;
|
|
input [255:0] AXI_26_WDATA;
|
|
input [31:0] AXI_26_WDATA_PARITY;
|
|
input AXI_26_WLAST;
|
|
input [31:0] AXI_26_WSTRB;
|
|
input AXI_26_WVALID;
|
|
(* invertible_pin = "IS_AXI_27_ACLK_INVERTED" *)
|
|
input AXI_27_ACLK;
|
|
input [36:0] AXI_27_ARADDR;
|
|
input [1:0] AXI_27_ARBURST;
|
|
(* invertible_pin = "IS_AXI_27_ARESET_N_INVERTED" *)
|
|
input AXI_27_ARESET_N;
|
|
input [5:0] AXI_27_ARID;
|
|
input [3:0] AXI_27_ARLEN;
|
|
input [2:0] AXI_27_ARSIZE;
|
|
input AXI_27_ARVALID;
|
|
input [36:0] AXI_27_AWADDR;
|
|
input [1:0] AXI_27_AWBURST;
|
|
input [5:0] AXI_27_AWID;
|
|
input [3:0] AXI_27_AWLEN;
|
|
input [2:0] AXI_27_AWSIZE;
|
|
input AXI_27_AWVALID;
|
|
input AXI_27_BREADY;
|
|
input AXI_27_DFI_LP_PWR_X_REQ;
|
|
input AXI_27_RREADY;
|
|
input [255:0] AXI_27_WDATA;
|
|
input [31:0] AXI_27_WDATA_PARITY;
|
|
input AXI_27_WLAST;
|
|
input [31:0] AXI_27_WSTRB;
|
|
input AXI_27_WVALID;
|
|
(* invertible_pin = "IS_AXI_28_ACLK_INVERTED" *)
|
|
input AXI_28_ACLK;
|
|
input [36:0] AXI_28_ARADDR;
|
|
input [1:0] AXI_28_ARBURST;
|
|
(* invertible_pin = "IS_AXI_28_ARESET_N_INVERTED" *)
|
|
input AXI_28_ARESET_N;
|
|
input [5:0] AXI_28_ARID;
|
|
input [3:0] AXI_28_ARLEN;
|
|
input [2:0] AXI_28_ARSIZE;
|
|
input AXI_28_ARVALID;
|
|
input [36:0] AXI_28_AWADDR;
|
|
input [1:0] AXI_28_AWBURST;
|
|
input [5:0] AXI_28_AWID;
|
|
input [3:0] AXI_28_AWLEN;
|
|
input [2:0] AXI_28_AWSIZE;
|
|
input AXI_28_AWVALID;
|
|
input AXI_28_BREADY;
|
|
input AXI_28_DFI_LP_PWR_X_REQ;
|
|
input AXI_28_RREADY;
|
|
input [255:0] AXI_28_WDATA;
|
|
input [31:0] AXI_28_WDATA_PARITY;
|
|
input AXI_28_WLAST;
|
|
input [31:0] AXI_28_WSTRB;
|
|
input AXI_28_WVALID;
|
|
(* invertible_pin = "IS_AXI_29_ACLK_INVERTED" *)
|
|
input AXI_29_ACLK;
|
|
input [36:0] AXI_29_ARADDR;
|
|
input [1:0] AXI_29_ARBURST;
|
|
(* invertible_pin = "IS_AXI_29_ARESET_N_INVERTED" *)
|
|
input AXI_29_ARESET_N;
|
|
input [5:0] AXI_29_ARID;
|
|
input [3:0] AXI_29_ARLEN;
|
|
input [2:0] AXI_29_ARSIZE;
|
|
input AXI_29_ARVALID;
|
|
input [36:0] AXI_29_AWADDR;
|
|
input [1:0] AXI_29_AWBURST;
|
|
input [5:0] AXI_29_AWID;
|
|
input [3:0] AXI_29_AWLEN;
|
|
input [2:0] AXI_29_AWSIZE;
|
|
input AXI_29_AWVALID;
|
|
input AXI_29_BREADY;
|
|
input AXI_29_DFI_LP_PWR_X_REQ;
|
|
input AXI_29_RREADY;
|
|
input [255:0] AXI_29_WDATA;
|
|
input [31:0] AXI_29_WDATA_PARITY;
|
|
input AXI_29_WLAST;
|
|
input [31:0] AXI_29_WSTRB;
|
|
input AXI_29_WVALID;
|
|
(* invertible_pin = "IS_AXI_30_ACLK_INVERTED" *)
|
|
input AXI_30_ACLK;
|
|
input [36:0] AXI_30_ARADDR;
|
|
input [1:0] AXI_30_ARBURST;
|
|
(* invertible_pin = "IS_AXI_30_ARESET_N_INVERTED" *)
|
|
input AXI_30_ARESET_N;
|
|
input [5:0] AXI_30_ARID;
|
|
input [3:0] AXI_30_ARLEN;
|
|
input [2:0] AXI_30_ARSIZE;
|
|
input AXI_30_ARVALID;
|
|
input [36:0] AXI_30_AWADDR;
|
|
input [1:0] AXI_30_AWBURST;
|
|
input [5:0] AXI_30_AWID;
|
|
input [3:0] AXI_30_AWLEN;
|
|
input [2:0] AXI_30_AWSIZE;
|
|
input AXI_30_AWVALID;
|
|
input AXI_30_BREADY;
|
|
input AXI_30_DFI_LP_PWR_X_REQ;
|
|
input AXI_30_RREADY;
|
|
input [255:0] AXI_30_WDATA;
|
|
input [31:0] AXI_30_WDATA_PARITY;
|
|
input AXI_30_WLAST;
|
|
input [31:0] AXI_30_WSTRB;
|
|
input AXI_30_WVALID;
|
|
(* invertible_pin = "IS_AXI_31_ACLK_INVERTED" *)
|
|
input AXI_31_ACLK;
|
|
input [36:0] AXI_31_ARADDR;
|
|
input [1:0] AXI_31_ARBURST;
|
|
(* invertible_pin = "IS_AXI_31_ARESET_N_INVERTED" *)
|
|
input AXI_31_ARESET_N;
|
|
input [5:0] AXI_31_ARID;
|
|
input [3:0] AXI_31_ARLEN;
|
|
input [2:0] AXI_31_ARSIZE;
|
|
input AXI_31_ARVALID;
|
|
input [36:0] AXI_31_AWADDR;
|
|
input [1:0] AXI_31_AWBURST;
|
|
input [5:0] AXI_31_AWID;
|
|
input [3:0] AXI_31_AWLEN;
|
|
input [2:0] AXI_31_AWSIZE;
|
|
input AXI_31_AWVALID;
|
|
input AXI_31_BREADY;
|
|
input AXI_31_DFI_LP_PWR_X_REQ;
|
|
input AXI_31_RREADY;
|
|
input [255:0] AXI_31_WDATA;
|
|
input [31:0] AXI_31_WDATA_PARITY;
|
|
input AXI_31_WLAST;
|
|
input [31:0] AXI_31_WSTRB;
|
|
input AXI_31_WVALID;
|
|
input BSCAN_DRCK_0;
|
|
input BSCAN_DRCK_1;
|
|
input BSCAN_TCK_0;
|
|
input BSCAN_TCK_1;
|
|
input HBM_REF_CLK_0;
|
|
input HBM_REF_CLK_1;
|
|
input MBIST_EN_00;
|
|
input MBIST_EN_01;
|
|
input MBIST_EN_02;
|
|
input MBIST_EN_03;
|
|
input MBIST_EN_04;
|
|
input MBIST_EN_05;
|
|
input MBIST_EN_06;
|
|
input MBIST_EN_07;
|
|
input MBIST_EN_08;
|
|
input MBIST_EN_09;
|
|
input MBIST_EN_10;
|
|
input MBIST_EN_11;
|
|
input MBIST_EN_12;
|
|
input MBIST_EN_13;
|
|
input MBIST_EN_14;
|
|
input MBIST_EN_15;
|
|
endmodule
|
|
|
|
module PPC405_ADV(APUFCMDECODED, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRVALID, APUFCMLOADDVALID, APUFCMOPERANDVALID, APUFCMWRITEBACKOK, APUFCMXERCA, C405CPMCORESLEEPREQ, C405CPMMSRCE, C405CPMMSREE, C405CPMTIMERIRQ, C405CPMTIMERRESETREQ, C405DBGLOADDATAONAPUDBUS, C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, C405JTGCAPTUREDR, C405JTGEXTEST
|
|
, C405JTGPGMOUT, C405JTGSHIFTDR, C405JTGTDO, C405JTGTDOEN, C405JTGUPDATEDR, C405PLBDCUABORT, C405PLBDCUCACHEABLE, C405PLBDCUGUARDED, C405PLBDCUREQUEST, C405PLBDCURNW, C405PLBDCUSIZE2, C405PLBDCUU0ATTR, C405PLBDCUWRITETHRU, C405PLBICUABORT, C405PLBICUCACHEABLE, C405PLBICUREQUEST, C405PLBICUU0ATTR, C405RSTCHIPRESETREQ, C405RSTCORERESETREQ, C405RSTSYSRESETREQ, C405TRCCYCLE
|
|
, C405TRCTRIGGEREVENTOUT, C405XXXMACHINECHECK, DCREMACCLK, DCREMACENABLER, DCREMACREAD, DCREMACWRITE, DSOCMBRAMEN, DSOCMBUSY, DSOCMRDADDRVALID, DSOCMWRADDRVALID, EXTDCRREAD, EXTDCRWRITE, ISOCMBRAMEN, ISOCMBRAMEVENWRITEEN, ISOCMBRAMODDWRITEEN, ISOCMDCRBRAMEVENEN, ISOCMDCRBRAMODDEN, ISOCMDCRBRAMRDSELECT, C405TRCTRIGGEREVENTTYPE, C405PLBDCUPRIORITY, C405PLBICUPRIORITY
|
|
, C405TRCEVENEXECUTIONSTATUS, C405TRCODDEXECUTIONSTATUS, C405DBGWBIAR, C405PLBICUABUS, APUFCMDECUDI, APUFCMINSTRUCTION, APUFCMLOADDATA, APUFCMRADATA, APUFCMRBDATA, C405PLBDCUABUS, DCREMACDBUS, DSOCMBRAMWRDBUS, EXTDCRDBUSOUT, ISOCMBRAMWRDBUS, APUFCMLOADBYTEEN, C405TRCTRACESTATUS, DSOCMBRAMBYTEWRITE, C405PLBDCUWRDBUS, C405PLBDCUBE, EXTDCRABUS, C405PLBICUSIZE
|
|
, ISOCMBRAMRDABUS, ISOCMBRAMWRABUS, DSOCMBRAMABUS, DCREMACABUS, BRAMDSOCMCLK, BRAMISOCMCLK, CPMC405CLOCK, CPMC405CORECLKINACTIVE, CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405SYNCBYPASS, CPMC405TIMERCLKEN, CPMC405TIMERTICK, CPMDCRCLK, CPMFCMCLK, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT, DSOCMRWCOMPLETE, EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ
|
|
, EMACDCRACK, EXTDCRACK, FCMAPUDCDCREN, FCMAPUDCDFORCEALIGN, FCMAPUDCDFORCEBESTEERING, FCMAPUDCDFPUOP, FCMAPUDCDGPRWRITE, FCMAPUDCDLDSTBYTE, FCMAPUDCDLDSTDW, FCMAPUDCDLDSTHW, FCMAPUDCDLDSTQW, FCMAPUDCDLDSTWD, FCMAPUDCDLOAD, FCMAPUDCDPRIVOP, FCMAPUDCDRAEN, FCMAPUDCDRBEN, FCMAPUDCDSTORE, FCMAPUDCDTRAPBE, FCMAPUDCDTRAPLE, FCMAPUDCDUPDATE, FCMAPUDCDXERCAEN
|
|
, FCMAPUDCDXEROVEN, FCMAPUDECODEBUSY, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUEXEBLOCKINGMCO, FCMAPUEXENONBLOCKINGMCO, FCMAPUINSTRACK, FCMAPULOADWAIT, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, FCMAPUXERCA, FCMAPUXEROV, JTGC405BNDSCANTDO, JTGC405TCK, JTGC405TDI, JTGC405TMS, JTGC405TRSTNEG, MCBCPUCLKEN, MCBJTAGEN, MCBTIMEREN, MCPPCRST
|
|
, PLBC405DCUADDRACK, PLBC405DCUBUSY, PLBC405DCUERR, PLBC405DCURDDACK, PLBC405DCUSSIZE1, PLBC405DCUWRDACK, PLBC405ICUADDRACK, PLBC405ICUBUSY, PLBC405ICUERR, PLBC405ICURDDACK, PLBC405ICUSSIZE1, PLBCLK, RSTC405RESETCHIP, RSTC405RESETCORE, RSTC405RESETSYS, TIEC405DETERMINISTICMULT, TIEC405DISOPERANDFWD, TIEC405MMUEN, TIEPVRBIT10, TIEPVRBIT11, TIEPVRBIT28
|
|
, TIEPVRBIT29, TIEPVRBIT30, TIEPVRBIT31, TIEPVRBIT8, TIEPVRBIT9, TRCC405TRACEDISABLE, TRCC405TRIGGEREVENTIN, TIEAPUCONTROL, TIEAPUUDI1, TIEAPUUDI2, TIEAPUUDI3, TIEAPUUDI4, TIEAPUUDI5, TIEAPUUDI6, TIEAPUUDI7, TIEAPUUDI8, FCMAPUEXECRFIELD, BRAMDSOCMRDDBUS, BRAMISOCMDCRRDDBUS, EMACDCRDBUS, EXTDCRDBUSIN
|
|
, FCMAPURESULT, FCMAPUCR, TIEDCRADDR, BRAMISOCMRDDBUS, PLBC405DCURDDBUS, PLBC405ICURDDBUS, DSARCVALUE, DSCNTLVALUE, ISARCVALUE, ISCNTLVALUE, PLBC405DCURDWDADDR, PLBC405ICURDWDADDR);
|
|
parameter in_delay=100;
|
|
parameter out_delay=100;
|
|
output APUFCMDECODED;
|
|
output APUFCMDECUDIVALID;
|
|
output APUFCMENDIAN;
|
|
output APUFCMFLUSH;
|
|
output APUFCMINSTRVALID;
|
|
output APUFCMLOADDVALID;
|
|
output APUFCMOPERANDVALID;
|
|
output APUFCMWRITEBACKOK;
|
|
output APUFCMXERCA;
|
|
output C405CPMCORESLEEPREQ;
|
|
output C405CPMMSRCE;
|
|
output C405CPMMSREE;
|
|
output C405CPMTIMERIRQ;
|
|
output C405CPMTIMERRESETREQ;
|
|
output C405DBGLOADDATAONAPUDBUS;
|
|
output C405DBGMSRWE;
|
|
output C405DBGSTOPACK;
|
|
output C405DBGWBCOMPLETE;
|
|
output C405DBGWBFULL;
|
|
output C405JTGCAPTUREDR;
|
|
output C405JTGEXTEST;
|
|
output C405JTGPGMOUT;
|
|
output C405JTGSHIFTDR;
|
|
output C405JTGTDO;
|
|
output C405JTGTDOEN;
|
|
output C405JTGUPDATEDR;
|
|
output C405PLBDCUABORT;
|
|
output C405PLBDCUCACHEABLE;
|
|
output C405PLBDCUGUARDED;
|
|
output C405PLBDCUREQUEST;
|
|
output C405PLBDCURNW;
|
|
output C405PLBDCUSIZE2;
|
|
output C405PLBDCUU0ATTR;
|
|
output C405PLBDCUWRITETHRU;
|
|
output C405PLBICUABORT;
|
|
output C405PLBICUCACHEABLE;
|
|
output C405PLBICUREQUEST;
|
|
output C405PLBICUU0ATTR;
|
|
output C405RSTCHIPRESETREQ;
|
|
output C405RSTCORERESETREQ;
|
|
output C405RSTSYSRESETREQ;
|
|
output C405TRCCYCLE;
|
|
output C405TRCTRIGGEREVENTOUT;
|
|
output C405XXXMACHINECHECK;
|
|
output DCREMACCLK;
|
|
output DCREMACENABLER;
|
|
output DCREMACREAD;
|
|
output DCREMACWRITE;
|
|
output DSOCMBRAMEN;
|
|
output DSOCMBUSY;
|
|
output DSOCMRDADDRVALID;
|
|
output DSOCMWRADDRVALID;
|
|
output EXTDCRREAD;
|
|
output EXTDCRWRITE;
|
|
output ISOCMBRAMEN;
|
|
output ISOCMBRAMEVENWRITEEN;
|
|
output ISOCMBRAMODDWRITEEN;
|
|
output ISOCMDCRBRAMEVENEN;
|
|
output ISOCMDCRBRAMODDEN;
|
|
output ISOCMDCRBRAMRDSELECT;
|
|
output [0:10] C405TRCTRIGGEREVENTTYPE;
|
|
output [0:1] C405PLBDCUPRIORITY;
|
|
output [0:1] C405PLBICUPRIORITY;
|
|
output [0:1] C405TRCEVENEXECUTIONSTATUS;
|
|
output [0:1] C405TRCODDEXECUTIONSTATUS;
|
|
output [0:29] C405DBGWBIAR;
|
|
output [0:29] C405PLBICUABUS;
|
|
output [0:2] APUFCMDECUDI;
|
|
output [0:31] APUFCMINSTRUCTION;
|
|
output [0:31] APUFCMLOADDATA;
|
|
output [0:31] APUFCMRADATA;
|
|
output [0:31] APUFCMRBDATA;
|
|
output [0:31] C405PLBDCUABUS;
|
|
output [0:31] DCREMACDBUS;
|
|
output [0:31] DSOCMBRAMWRDBUS;
|
|
output [0:31] EXTDCRDBUSOUT;
|
|
output [0:31] ISOCMBRAMWRDBUS;
|
|
output [0:3] APUFCMLOADBYTEEN;
|
|
output [0:3] C405TRCTRACESTATUS;
|
|
output [0:3] DSOCMBRAMBYTEWRITE;
|
|
output [0:63] C405PLBDCUWRDBUS;
|
|
output [0:7] C405PLBDCUBE;
|
|
output [0:9] EXTDCRABUS;
|
|
output [2:3] C405PLBICUSIZE;
|
|
output [8:28] ISOCMBRAMRDABUS;
|
|
output [8:28] ISOCMBRAMWRABUS;
|
|
output [8:29] DSOCMBRAMABUS;
|
|
output [8:9] DCREMACABUS;
|
|
input BRAMDSOCMCLK;
|
|
input BRAMISOCMCLK;
|
|
input CPMC405CLOCK;
|
|
input CPMC405CORECLKINACTIVE;
|
|
input CPMC405CPUCLKEN;
|
|
input CPMC405JTAGCLKEN;
|
|
input CPMC405SYNCBYPASS;
|
|
input CPMC405TIMERCLKEN;
|
|
input CPMC405TIMERTICK;
|
|
input CPMDCRCLK;
|
|
input CPMFCMCLK;
|
|
input DBGC405DEBUGHALT;
|
|
input DBGC405EXTBUSHOLDACK;
|
|
input DBGC405UNCONDDEBUGEVENT;
|
|
input DSOCMRWCOMPLETE;
|
|
input EICC405CRITINPUTIRQ;
|
|
input EICC405EXTINPUTIRQ;
|
|
input EMACDCRACK;
|
|
input EXTDCRACK;
|
|
input FCMAPUDCDCREN;
|
|
input FCMAPUDCDFORCEALIGN;
|
|
input FCMAPUDCDFORCEBESTEERING;
|
|
input FCMAPUDCDFPUOP;
|
|
input FCMAPUDCDGPRWRITE;
|
|
input FCMAPUDCDLDSTBYTE;
|
|
input FCMAPUDCDLDSTDW;
|
|
input FCMAPUDCDLDSTHW;
|
|
input FCMAPUDCDLDSTQW;
|
|
input FCMAPUDCDLDSTWD;
|
|
input FCMAPUDCDLOAD;
|
|
input FCMAPUDCDPRIVOP;
|
|
input FCMAPUDCDRAEN;
|
|
input FCMAPUDCDRBEN;
|
|
input FCMAPUDCDSTORE;
|
|
input FCMAPUDCDTRAPBE;
|
|
input FCMAPUDCDTRAPLE;
|
|
input FCMAPUDCDUPDATE;
|
|
input FCMAPUDCDXERCAEN;
|
|
input FCMAPUDCDXEROVEN;
|
|
input FCMAPUDECODEBUSY;
|
|
input FCMAPUDONE;
|
|
input FCMAPUEXCEPTION;
|
|
input FCMAPUEXEBLOCKINGMCO;
|
|
input FCMAPUEXENONBLOCKINGMCO;
|
|
input FCMAPUINSTRACK;
|
|
input FCMAPULOADWAIT;
|
|
input FCMAPURESULTVALID;
|
|
input FCMAPUSLEEPNOTREADY;
|
|
input FCMAPUXERCA;
|
|
input FCMAPUXEROV;
|
|
input JTGC405BNDSCANTDO;
|
|
input JTGC405TCK;
|
|
input JTGC405TDI;
|
|
input JTGC405TMS;
|
|
input JTGC405TRSTNEG;
|
|
input MCBCPUCLKEN;
|
|
input MCBJTAGEN;
|
|
input MCBTIMEREN;
|
|
input MCPPCRST;
|
|
input PLBC405DCUADDRACK;
|
|
input PLBC405DCUBUSY;
|
|
input PLBC405DCUERR;
|
|
input PLBC405DCURDDACK;
|
|
input PLBC405DCUSSIZE1;
|
|
input PLBC405DCUWRDACK;
|
|
input PLBC405ICUADDRACK;
|
|
input PLBC405ICUBUSY;
|
|
input PLBC405ICUERR;
|
|
input PLBC405ICURDDACK;
|
|
input PLBC405ICUSSIZE1;
|
|
input PLBCLK;
|
|
input RSTC405RESETCHIP;
|
|
input RSTC405RESETCORE;
|
|
input RSTC405RESETSYS;
|
|
input TIEC405DETERMINISTICMULT;
|
|
input TIEC405DISOPERANDFWD;
|
|
input TIEC405MMUEN;
|
|
input TIEPVRBIT10;
|
|
input TIEPVRBIT11;
|
|
input TIEPVRBIT28;
|
|
input TIEPVRBIT29;
|
|
input TIEPVRBIT30;
|
|
input TIEPVRBIT31;
|
|
input TIEPVRBIT8;
|
|
input TIEPVRBIT9;
|
|
input TRCC405TRACEDISABLE;
|
|
input TRCC405TRIGGEREVENTIN;
|
|
input [0:15] TIEAPUCONTROL;
|
|
input [0:23] TIEAPUUDI1;
|
|
input [0:23] TIEAPUUDI2;
|
|
input [0:23] TIEAPUUDI3;
|
|
input [0:23] TIEAPUUDI4;
|
|
input [0:23] TIEAPUUDI5;
|
|
input [0:23] TIEAPUUDI6;
|
|
input [0:23] TIEAPUUDI7;
|
|
input [0:23] TIEAPUUDI8;
|
|
input [0:2] FCMAPUEXECRFIELD;
|
|
input [0:31] BRAMDSOCMRDDBUS;
|
|
input [0:31] BRAMISOCMDCRRDDBUS;
|
|
input [0:31] EMACDCRDBUS;
|
|
input [0:31] EXTDCRDBUSIN;
|
|
input [0:31] FCMAPURESULT;
|
|
input [0:3] FCMAPUCR;
|
|
input [0:5] TIEDCRADDR;
|
|
input [0:63] BRAMISOCMRDDBUS;
|
|
input [0:63] PLBC405DCURDDBUS;
|
|
input [0:63] PLBC405ICURDDBUS;
|
|
input [0:7] DSARCVALUE;
|
|
input [0:7] DSCNTLVALUE;
|
|
input [0:7] ISARCVALUE;
|
|
input [0:7] ISCNTLVALUE;
|
|
input [1:3] PLBC405DCURDWDADDR;
|
|
input [1:3] PLBC405ICURDWDADDR;
|
|
endmodule
|
|
|
|
module PPC440(APUFCMDECFPUOP, APUFCMDECLOAD, APUFCMDECNONAUTON, APUFCMDECSTORE, APUFCMDECUDIVALID, APUFCMENDIAN, APUFCMFLUSH, APUFCMINSTRVALID, APUFCMLOADDVALID, APUFCMMSRFE0, APUFCMMSRFE1, APUFCMNEXTINSTRREADY, APUFCMOPERANDVALID, APUFCMWRITEBACKOK, C440CPMCORESLEEPREQ, C440CPMDECIRPTREQ, C440CPMFITIRPTREQ, C440CPMMSRCE, C440CPMMSREE, C440CPMTIMERRESETREQ, C440CPMWDIRPTREQ
|
|
, C440JTGTDO, C440JTGTDOEN, C440MACHINECHECK, C440RSTCHIPRESETREQ, C440RSTCORERESETREQ, C440RSTSYSTEMRESETREQ, C440TRCCYCLE, C440TRCTRIGGEREVENTOUT, DMA0LLRSTENGINEACK, DMA0LLRXDSTRDYN, DMA0LLTXEOFN, DMA0LLTXEOPN, DMA0LLTXSOFN, DMA0LLTXSOPN, DMA0LLTXSRCRDYN, DMA0RXIRQ, DMA0TXIRQ, DMA1LLRSTENGINEACK, DMA1LLRXDSTRDYN, DMA1LLTXEOFN, DMA1LLTXEOPN
|
|
, DMA1LLTXSOFN, DMA1LLTXSOPN, DMA1LLTXSRCRDYN, DMA1RXIRQ, DMA1TXIRQ, DMA2LLRSTENGINEACK, DMA2LLRXDSTRDYN, DMA2LLTXEOFN, DMA2LLTXEOPN, DMA2LLTXSOFN, DMA2LLTXSOPN, DMA2LLTXSRCRDYN, DMA2RXIRQ, DMA2TXIRQ, DMA3LLRSTENGINEACK, DMA3LLRXDSTRDYN, DMA3LLTXEOFN, DMA3LLTXEOPN, DMA3LLTXSOFN, DMA3LLTXSOPN, DMA3LLTXSRCRDYN
|
|
, DMA3RXIRQ, DMA3TXIRQ, MIMCADDRESSVALID, MIMCBANKCONFLICT, MIMCREADNOTWRITE, MIMCROWCONFLICT, MIMCWRITEDATAVALID, PPCCPMINTERCONNECTBUSY, PPCDMDCRREAD, PPCDMDCRWRITE, PPCDSDCRACK, PPCDSDCRTIMEOUTWAIT, PPCEICINTERCONNECTIRQ, PPCMPLBABORT, PPCMPLBBUSLOCK, PPCMPLBLOCKERR, PPCMPLBRDBURST, PPCMPLBREQUEST, PPCMPLBRNW, PPCMPLBWRBURST, PPCS0PLBADDRACK
|
|
, PPCS0PLBRDBTERM, PPCS0PLBRDCOMP, PPCS0PLBRDDACK, PPCS0PLBREARBITRATE, PPCS0PLBWAIT, PPCS0PLBWRBTERM, PPCS0PLBWRCOMP, PPCS0PLBWRDACK, PPCS1PLBADDRACK, PPCS1PLBRDBTERM, PPCS1PLBRDCOMP, PPCS1PLBRDDACK, PPCS1PLBREARBITRATE, PPCS1PLBWAIT, PPCS1PLBWRBTERM, PPCS1PLBWRCOMP, PPCS1PLBWRDACK, APUFCMLOADDATA, MIMCWRITEDATA, PPCMPLBWRDBUS, PPCS0PLBRDDBUS
|
|
, PPCS1PLBRDDBUS, C440TRCTRIGGEREVENTTYPE, MIMCBYTEENABLE, PPCMPLBBE, PPCMPLBTATTRIBUTE, PPCMPLBPRIORITY, PPCS0PLBSSIZE, PPCS1PLBSSIZE, APUFCMDECLDSTXFERSIZE, C440TRCBRANCHSTATUS, PPCMPLBTYPE, APUFCMINSTRUCTION, APUFCMRADATA, APUFCMRBDATA, DMA0LLTXD, DMA1LLTXD, DMA2LLTXD, DMA3LLTXD, PPCDMDCRDBUSOUT, PPCDSDCRDBUSIN, PPCMPLBABUS
|
|
, MIMCADDRESS, APUFCMDECUDI, APUFCMLOADBYTEADDR, DMA0LLTXREM, DMA1LLTXREM, DMA2LLTXREM, DMA3LLTXREM, PPCMPLBSIZE, PPCS0PLBMBUSY, PPCS0PLBMIRQ, PPCS0PLBMRDERR, PPCS0PLBMWRERR, PPCS0PLBRDWDADDR, PPCS1PLBMBUSY, PPCS1PLBMIRQ, PPCS1PLBMRDERR, PPCS1PLBMWRERR, PPCS1PLBRDWDADDR, C440TRCEXECUTIONSTATUS, C440TRCTRACESTATUS, C440DBGSYSTEMCONTROL
|
|
, PPCDMDCRABUS, PPCDMDCRUABUS, PPCMPLBUABUS, CPMC440CLK, CPMC440CLKEN, CPMC440CORECLOCKINACTIVE, CPMC440TIMERCLOCK, CPMDCRCLK, CPMDMA0LLCLK, CPMDMA1LLCLK, CPMDMA2LLCLK, CPMDMA3LLCLK, CPMFCMCLK, CPMINTERCONNECTCLK, CPMINTERCONNECTCLKEN, CPMINTERCONNECTCLKNTO1, CPMMCCLK, CPMPPCMPLBCLK, CPMPPCS0PLBCLK, CPMPPCS1PLBCLK, DBGC440DEBUGHALT
|
|
, DBGC440UNCONDDEBUGEVENT, DCRPPCDMACK, DCRPPCDMTIMEOUTWAIT, DCRPPCDSREAD, DCRPPCDSWRITE, EICC440CRITIRQ, EICC440EXTIRQ, FCMAPUCONFIRMINSTR, FCMAPUDONE, FCMAPUEXCEPTION, FCMAPUFPSCRFEX, FCMAPURESULTVALID, FCMAPUSLEEPNOTREADY, JTGC440TCK, JTGC440TDI, JTGC440TMS, JTGC440TRSTNEG, LLDMA0RSTENGINEREQ, LLDMA0RXEOFN, LLDMA0RXEOPN, LLDMA0RXSOFN
|
|
, LLDMA0RXSOPN, LLDMA0RXSRCRDYN, LLDMA0TXDSTRDYN, LLDMA1RSTENGINEREQ, LLDMA1RXEOFN, LLDMA1RXEOPN, LLDMA1RXSOFN, LLDMA1RXSOPN, LLDMA1RXSRCRDYN, LLDMA1TXDSTRDYN, LLDMA2RSTENGINEREQ, LLDMA2RXEOFN, LLDMA2RXEOPN, LLDMA2RXSOFN, LLDMA2RXSOPN, LLDMA2RXSRCRDYN, LLDMA2TXDSTRDYN, LLDMA3RSTENGINEREQ, LLDMA3RXEOFN, LLDMA3RXEOPN, LLDMA3RXSOFN
|
|
, LLDMA3RXSOPN, LLDMA3RXSRCRDYN, LLDMA3TXDSTRDYN, MCMIADDRREADYTOACCEPT, MCMIREADDATAERR, MCMIREADDATAVALID, PLBPPCMADDRACK, PLBPPCMMBUSY, PLBPPCMMIRQ, PLBPPCMMRDERR, PLBPPCMMWRERR, PLBPPCMRDBTERM, PLBPPCMRDDACK, PLBPPCMRDPENDREQ, PLBPPCMREARBITRATE, PLBPPCMTIMEOUT, PLBPPCMWRBTERM, PLBPPCMWRDACK, PLBPPCMWRPENDREQ, PLBPPCS0ABORT, PLBPPCS0BUSLOCK
|
|
, PLBPPCS0LOCKERR, PLBPPCS0PAVALID, PLBPPCS0RDBURST, PLBPPCS0RDPENDREQ, PLBPPCS0RDPRIM, PLBPPCS0RNW, PLBPPCS0SAVALID, PLBPPCS0WRBURST, PLBPPCS0WRPENDREQ, PLBPPCS0WRPRIM, PLBPPCS1ABORT, PLBPPCS1BUSLOCK, PLBPPCS1LOCKERR, PLBPPCS1PAVALID, PLBPPCS1RDBURST, PLBPPCS1RDPENDREQ, PLBPPCS1RDPRIM, PLBPPCS1RNW, PLBPPCS1SAVALID, PLBPPCS1WRBURST, PLBPPCS1WRPENDREQ
|
|
, PLBPPCS1WRPRIM, RSTC440RESETCHIP, RSTC440RESETCORE, RSTC440RESETSYSTEM, TIEC440ENDIANRESET, TRCC440TRACEDISABLE, TRCC440TRIGGEREVENTIN, FCMAPUSTOREDATA, MCMIREADDATA, PLBPPCMRDDBUS, PLBPPCS0WRDBUS, PLBPPCS1WRDBUS, PLBPPCS0BE, PLBPPCS0TATTRIBUTE, PLBPPCS1BE, PLBPPCS1TATTRIBUTE, PLBPPCMRDPENDPRI, PLBPPCMREQPRI, PLBPPCMSSIZE, PLBPPCMWRPENDPRI, PLBPPCS0MASTERID
|
|
, PLBPPCS0MSIZE, PLBPPCS0RDPENDPRI, PLBPPCS0REQPRI, PLBPPCS0WRPENDPRI, PLBPPCS1MASTERID, PLBPPCS1MSIZE, PLBPPCS1RDPENDPRI, PLBPPCS1REQPRI, PLBPPCS1WRPENDPRI, TIEC440DCURDLDCACHEPLBPRIO, TIEC440DCURDNONCACHEPLBPRIO, TIEC440DCURDTOUCHPLBPRIO, TIEC440DCURDURGENTPLBPRIO, TIEC440DCUWRFLUSHPLBPRIO, TIEC440DCUWRSTOREPLBPRIO, TIEC440DCUWRURGENTPLBPRIO, TIEC440ICURDFETCHPLBPRIO, TIEC440ICURDSPECPLBPRIO, TIEC440ICURDTOUCHPLBPRIO, TIEDCRBASEADDR, PLBPPCS0TYPE
|
|
, PLBPPCS1TYPE, DCRPPCDMDBUSIN, DCRPPCDSDBUSOUT, FCMAPURESULT, LLDMA0RXD, LLDMA1RXD, LLDMA2RXD, LLDMA3RXD, PLBPPCS0ABUS, PLBPPCS1ABUS, FCMAPUCR, LLDMA0RXREM, LLDMA1RXREM, LLDMA2RXREM, LLDMA3RXREM, PLBPPCMRDWDADDR, PLBPPCS0SIZE, PLBPPCS1SIZE, TIEC440ERPNRESET, TIEC440USERRESET, DBGC440SYSTEMSTATUS
|
|
, DCRPPCDSABUS, PLBPPCS0UABUS, PLBPPCS1UABUS, TIEC440PIR, TIEC440PVR);
|
|
parameter CLOCK_DELAY = "FALSE";
|
|
parameter DCR_AUTOLOCK_ENABLE = "TRUE";
|
|
parameter PPCDM_ASYNCMODE = "FALSE";
|
|
parameter PPCDS_ASYNCMODE = "FALSE";
|
|
parameter PPCS0_WIDTH_128N64 = "TRUE";
|
|
parameter PPCS1_WIDTH_128N64 = "TRUE";
|
|
parameter [0:16] APU_CONTROL = 17'h02000;
|
|
parameter [0:23] APU_UDI0 = 24'h000000;
|
|
parameter [0:23] APU_UDI1 = 24'h000000;
|
|
parameter [0:23] APU_UDI10 = 24'h000000;
|
|
parameter [0:23] APU_UDI11 = 24'h000000;
|
|
parameter [0:23] APU_UDI12 = 24'h000000;
|
|
parameter [0:23] APU_UDI13 = 24'h000000;
|
|
parameter [0:23] APU_UDI14 = 24'h000000;
|
|
parameter [0:23] APU_UDI15 = 24'h000000;
|
|
parameter [0:23] APU_UDI2 = 24'h000000;
|
|
parameter [0:23] APU_UDI3 = 24'h000000;
|
|
parameter [0:23] APU_UDI4 = 24'h000000;
|
|
parameter [0:23] APU_UDI5 = 24'h000000;
|
|
parameter [0:23] APU_UDI6 = 24'h000000;
|
|
parameter [0:23] APU_UDI7 = 24'h000000;
|
|
parameter [0:23] APU_UDI8 = 24'h000000;
|
|
parameter [0:23] APU_UDI9 = 24'h000000;
|
|
parameter [0:31] DMA0_RXCHANNELCTRL = 32'h01010000;
|
|
parameter [0:31] DMA0_TXCHANNELCTRL = 32'h01010000;
|
|
parameter [0:31] DMA1_RXCHANNELCTRL = 32'h01010000;
|
|
parameter [0:31] DMA1_TXCHANNELCTRL = 32'h01010000;
|
|
parameter [0:31] DMA2_RXCHANNELCTRL = 32'h01010000;
|
|
parameter [0:31] DMA2_TXCHANNELCTRL = 32'h01010000;
|
|
parameter [0:31] DMA3_RXCHANNELCTRL = 32'h01010000;
|
|
parameter [0:31] DMA3_TXCHANNELCTRL = 32'h01010000;
|
|
parameter [0:31] INTERCONNECT_IMASK = 32'hFFFFFFFF;
|
|
parameter [0:31] INTERCONNECT_TMPL_SEL = 32'h3FFFFFFF;
|
|
parameter [0:31] MI_ARBCONFIG = 32'h00432010;
|
|
parameter [0:31] MI_BANKCONFLICT_MASK = 32'h00000000;
|
|
parameter [0:31] MI_CONTROL = 32'h0000008F;
|
|
parameter [0:31] MI_ROWCONFLICT_MASK = 32'h00000000;
|
|
parameter [0:31] PPCM_ARBCONFIG = 32'h00432010;
|
|
parameter [0:31] PPCM_CONTROL = 32'h8000019F;
|
|
parameter [0:31] PPCM_COUNTER = 32'h00000500;
|
|
parameter [0:31] PPCS0_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
|
|
parameter [0:31] PPCS0_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
|
|
parameter [0:31] PPCS0_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
|
|
parameter [0:31] PPCS0_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
|
|
parameter [0:31] PPCS0_CONTROL = 32'h8033336C;
|
|
parameter [0:31] PPCS1_ADDRMAP_TMPL0 = 32'hFFFFFFFF;
|
|
parameter [0:31] PPCS1_ADDRMAP_TMPL1 = 32'hFFFFFFFF;
|
|
parameter [0:31] PPCS1_ADDRMAP_TMPL2 = 32'hFFFFFFFF;
|
|
parameter [0:31] PPCS1_ADDRMAP_TMPL3 = 32'hFFFFFFFF;
|
|
parameter [0:31] PPCS1_CONTROL = 32'h8033336C;
|
|
parameter [0:31] XBAR_ADDRMAP_TMPL0 = 32'hFFFF0000;
|
|
parameter [0:31] XBAR_ADDRMAP_TMPL1 = 32'h00000000;
|
|
parameter [0:31] XBAR_ADDRMAP_TMPL2 = 32'h00000000;
|
|
parameter [0:31] XBAR_ADDRMAP_TMPL3 = 32'h00000000;
|
|
parameter [0:7] DMA0_CONTROL = 8'h00;
|
|
parameter [0:7] DMA1_CONTROL = 8'h00;
|
|
parameter [0:7] DMA2_CONTROL = 8'h00;
|
|
parameter [0:7] DMA3_CONTROL = 8'h00;
|
|
parameter [0:9] DMA0_RXIRQTIMER = 10'h3FF;
|
|
parameter [0:9] DMA0_TXIRQTIMER = 10'h3FF;
|
|
parameter [0:9] DMA1_RXIRQTIMER = 10'h3FF;
|
|
parameter [0:9] DMA1_TXIRQTIMER = 10'h3FF;
|
|
parameter [0:9] DMA2_RXIRQTIMER = 10'h3FF;
|
|
parameter [0:9] DMA2_TXIRQTIMER = 10'h3FF;
|
|
parameter [0:9] DMA3_RXIRQTIMER = 10'h3FF;
|
|
parameter [0:9] DMA3_TXIRQTIMER = 10'h3FF;
|
|
output APUFCMDECFPUOP;
|
|
output APUFCMDECLOAD;
|
|
output APUFCMDECNONAUTON;
|
|
output APUFCMDECSTORE;
|
|
output APUFCMDECUDIVALID;
|
|
output APUFCMENDIAN;
|
|
output APUFCMFLUSH;
|
|
output APUFCMINSTRVALID;
|
|
output APUFCMLOADDVALID;
|
|
output APUFCMMSRFE0;
|
|
output APUFCMMSRFE1;
|
|
output APUFCMNEXTINSTRREADY;
|
|
output APUFCMOPERANDVALID;
|
|
output APUFCMWRITEBACKOK;
|
|
output C440CPMCORESLEEPREQ;
|
|
output C440CPMDECIRPTREQ;
|
|
output C440CPMFITIRPTREQ;
|
|
output C440CPMMSRCE;
|
|
output C440CPMMSREE;
|
|
output C440CPMTIMERRESETREQ;
|
|
output C440CPMWDIRPTREQ;
|
|
output C440JTGTDO;
|
|
output C440JTGTDOEN;
|
|
output C440MACHINECHECK;
|
|
output C440RSTCHIPRESETREQ;
|
|
output C440RSTCORERESETREQ;
|
|
output C440RSTSYSTEMRESETREQ;
|
|
output C440TRCCYCLE;
|
|
output C440TRCTRIGGEREVENTOUT;
|
|
output DMA0LLRSTENGINEACK;
|
|
output DMA0LLRXDSTRDYN;
|
|
output DMA0LLTXEOFN;
|
|
output DMA0LLTXEOPN;
|
|
output DMA0LLTXSOFN;
|
|
output DMA0LLTXSOPN;
|
|
output DMA0LLTXSRCRDYN;
|
|
output DMA0RXIRQ;
|
|
output DMA0TXIRQ;
|
|
output DMA1LLRSTENGINEACK;
|
|
output DMA1LLRXDSTRDYN;
|
|
output DMA1LLTXEOFN;
|
|
output DMA1LLTXEOPN;
|
|
output DMA1LLTXSOFN;
|
|
output DMA1LLTXSOPN;
|
|
output DMA1LLTXSRCRDYN;
|
|
output DMA1RXIRQ;
|
|
output DMA1TXIRQ;
|
|
output DMA2LLRSTENGINEACK;
|
|
output DMA2LLRXDSTRDYN;
|
|
output DMA2LLTXEOFN;
|
|
output DMA2LLTXEOPN;
|
|
output DMA2LLTXSOFN;
|
|
output DMA2LLTXSOPN;
|
|
output DMA2LLTXSRCRDYN;
|
|
output DMA2RXIRQ;
|
|
output DMA2TXIRQ;
|
|
output DMA3LLRSTENGINEACK;
|
|
output DMA3LLRXDSTRDYN;
|
|
output DMA3LLTXEOFN;
|
|
output DMA3LLTXEOPN;
|
|
output DMA3LLTXSOFN;
|
|
output DMA3LLTXSOPN;
|
|
output DMA3LLTXSRCRDYN;
|
|
output DMA3RXIRQ;
|
|
output DMA3TXIRQ;
|
|
output MIMCADDRESSVALID;
|
|
output MIMCBANKCONFLICT;
|
|
output MIMCREADNOTWRITE;
|
|
output MIMCROWCONFLICT;
|
|
output MIMCWRITEDATAVALID;
|
|
output PPCCPMINTERCONNECTBUSY;
|
|
output PPCDMDCRREAD;
|
|
output PPCDMDCRWRITE;
|
|
output PPCDSDCRACK;
|
|
output PPCDSDCRTIMEOUTWAIT;
|
|
output PPCEICINTERCONNECTIRQ;
|
|
output PPCMPLBABORT;
|
|
output PPCMPLBBUSLOCK;
|
|
output PPCMPLBLOCKERR;
|
|
output PPCMPLBRDBURST;
|
|
output PPCMPLBREQUEST;
|
|
output PPCMPLBRNW;
|
|
output PPCMPLBWRBURST;
|
|
output PPCS0PLBADDRACK;
|
|
output PPCS0PLBRDBTERM;
|
|
output PPCS0PLBRDCOMP;
|
|
output PPCS0PLBRDDACK;
|
|
output PPCS0PLBREARBITRATE;
|
|
output PPCS0PLBWAIT;
|
|
output PPCS0PLBWRBTERM;
|
|
output PPCS0PLBWRCOMP;
|
|
output PPCS0PLBWRDACK;
|
|
output PPCS1PLBADDRACK;
|
|
output PPCS1PLBRDBTERM;
|
|
output PPCS1PLBRDCOMP;
|
|
output PPCS1PLBRDDACK;
|
|
output PPCS1PLBREARBITRATE;
|
|
output PPCS1PLBWAIT;
|
|
output PPCS1PLBWRBTERM;
|
|
output PPCS1PLBWRCOMP;
|
|
output PPCS1PLBWRDACK;
|
|
output [0:127] APUFCMLOADDATA;
|
|
output [0:127] MIMCWRITEDATA;
|
|
output [0:127] PPCMPLBWRDBUS;
|
|
output [0:127] PPCS0PLBRDDBUS;
|
|
output [0:127] PPCS1PLBRDDBUS;
|
|
output [0:13] C440TRCTRIGGEREVENTTYPE;
|
|
output [0:15] MIMCBYTEENABLE;
|
|
output [0:15] PPCMPLBBE;
|
|
output [0:15] PPCMPLBTATTRIBUTE;
|
|
output [0:1] PPCMPLBPRIORITY;
|
|
output [0:1] PPCS0PLBSSIZE;
|
|
output [0:1] PPCS1PLBSSIZE;
|
|
output [0:2] APUFCMDECLDSTXFERSIZE;
|
|
output [0:2] C440TRCBRANCHSTATUS;
|
|
output [0:2] PPCMPLBTYPE;
|
|
output [0:31] APUFCMINSTRUCTION;
|
|
output [0:31] APUFCMRADATA;
|
|
output [0:31] APUFCMRBDATA;
|
|
output [0:31] DMA0LLTXD;
|
|
output [0:31] DMA1LLTXD;
|
|
output [0:31] DMA2LLTXD;
|
|
output [0:31] DMA3LLTXD;
|
|
output [0:31] PPCDMDCRDBUSOUT;
|
|
output [0:31] PPCDSDCRDBUSIN;
|
|
output [0:31] PPCMPLBABUS;
|
|
output [0:35] MIMCADDRESS;
|
|
output [0:3] APUFCMDECUDI;
|
|
output [0:3] APUFCMLOADBYTEADDR;
|
|
output [0:3] DMA0LLTXREM;
|
|
output [0:3] DMA1LLTXREM;
|
|
output [0:3] DMA2LLTXREM;
|
|
output [0:3] DMA3LLTXREM;
|
|
output [0:3] PPCMPLBSIZE;
|
|
output [0:3] PPCS0PLBMBUSY;
|
|
output [0:3] PPCS0PLBMIRQ;
|
|
output [0:3] PPCS0PLBMRDERR;
|
|
output [0:3] PPCS0PLBMWRERR;
|
|
output [0:3] PPCS0PLBRDWDADDR;
|
|
output [0:3] PPCS1PLBMBUSY;
|
|
output [0:3] PPCS1PLBMIRQ;
|
|
output [0:3] PPCS1PLBMRDERR;
|
|
output [0:3] PPCS1PLBMWRERR;
|
|
output [0:3] PPCS1PLBRDWDADDR;
|
|
output [0:4] C440TRCEXECUTIONSTATUS;
|
|
output [0:6] C440TRCTRACESTATUS;
|
|
output [0:7] C440DBGSYSTEMCONTROL;
|
|
output [0:9] PPCDMDCRABUS;
|
|
output [20:21] PPCDMDCRUABUS;
|
|
output [28:31] PPCMPLBUABUS;
|
|
input CPMC440CLK;
|
|
input CPMC440CLKEN;
|
|
input CPMC440CORECLOCKINACTIVE;
|
|
input CPMC440TIMERCLOCK;
|
|
input CPMDCRCLK;
|
|
input CPMDMA0LLCLK;
|
|
input CPMDMA1LLCLK;
|
|
input CPMDMA2LLCLK;
|
|
input CPMDMA3LLCLK;
|
|
input CPMFCMCLK;
|
|
input CPMINTERCONNECTCLK;
|
|
input CPMINTERCONNECTCLKEN;
|
|
input CPMINTERCONNECTCLKNTO1;
|
|
input CPMMCCLK;
|
|
input CPMPPCMPLBCLK;
|
|
input CPMPPCS0PLBCLK;
|
|
input CPMPPCS1PLBCLK;
|
|
input DBGC440DEBUGHALT;
|
|
input DBGC440UNCONDDEBUGEVENT;
|
|
input DCRPPCDMACK;
|
|
input DCRPPCDMTIMEOUTWAIT;
|
|
input DCRPPCDSREAD;
|
|
input DCRPPCDSWRITE;
|
|
input EICC440CRITIRQ;
|
|
input EICC440EXTIRQ;
|
|
input FCMAPUCONFIRMINSTR;
|
|
input FCMAPUDONE;
|
|
input FCMAPUEXCEPTION;
|
|
input FCMAPUFPSCRFEX;
|
|
input FCMAPURESULTVALID;
|
|
input FCMAPUSLEEPNOTREADY;
|
|
input JTGC440TCK;
|
|
input JTGC440TDI;
|
|
input JTGC440TMS;
|
|
input JTGC440TRSTNEG;
|
|
input LLDMA0RSTENGINEREQ;
|
|
input LLDMA0RXEOFN;
|
|
input LLDMA0RXEOPN;
|
|
input LLDMA0RXSOFN;
|
|
input LLDMA0RXSOPN;
|
|
input LLDMA0RXSRCRDYN;
|
|
input LLDMA0TXDSTRDYN;
|
|
input LLDMA1RSTENGINEREQ;
|
|
input LLDMA1RXEOFN;
|
|
input LLDMA1RXEOPN;
|
|
input LLDMA1RXSOFN;
|
|
input LLDMA1RXSOPN;
|
|
input LLDMA1RXSRCRDYN;
|
|
input LLDMA1TXDSTRDYN;
|
|
input LLDMA2RSTENGINEREQ;
|
|
input LLDMA2RXEOFN;
|
|
input LLDMA2RXEOPN;
|
|
input LLDMA2RXSOFN;
|
|
input LLDMA2RXSOPN;
|
|
input LLDMA2RXSRCRDYN;
|
|
input LLDMA2TXDSTRDYN;
|
|
input LLDMA3RSTENGINEREQ;
|
|
input LLDMA3RXEOFN;
|
|
input LLDMA3RXEOPN;
|
|
input LLDMA3RXSOFN;
|
|
input LLDMA3RXSOPN;
|
|
input LLDMA3RXSRCRDYN;
|
|
input LLDMA3TXDSTRDYN;
|
|
input MCMIADDRREADYTOACCEPT;
|
|
input MCMIREADDATAERR;
|
|
input MCMIREADDATAVALID;
|
|
input PLBPPCMADDRACK;
|
|
input PLBPPCMMBUSY;
|
|
input PLBPPCMMIRQ;
|
|
input PLBPPCMMRDERR;
|
|
input PLBPPCMMWRERR;
|
|
input PLBPPCMRDBTERM;
|
|
input PLBPPCMRDDACK;
|
|
input PLBPPCMRDPENDREQ;
|
|
input PLBPPCMREARBITRATE;
|
|
input PLBPPCMTIMEOUT;
|
|
input PLBPPCMWRBTERM;
|
|
input PLBPPCMWRDACK;
|
|
input PLBPPCMWRPENDREQ;
|
|
input PLBPPCS0ABORT;
|
|
input PLBPPCS0BUSLOCK;
|
|
input PLBPPCS0LOCKERR;
|
|
input PLBPPCS0PAVALID;
|
|
input PLBPPCS0RDBURST;
|
|
input PLBPPCS0RDPENDREQ;
|
|
input PLBPPCS0RDPRIM;
|
|
input PLBPPCS0RNW;
|
|
input PLBPPCS0SAVALID;
|
|
input PLBPPCS0WRBURST;
|
|
input PLBPPCS0WRPENDREQ;
|
|
input PLBPPCS0WRPRIM;
|
|
input PLBPPCS1ABORT;
|
|
input PLBPPCS1BUSLOCK;
|
|
input PLBPPCS1LOCKERR;
|
|
input PLBPPCS1PAVALID;
|
|
input PLBPPCS1RDBURST;
|
|
input PLBPPCS1RDPENDREQ;
|
|
input PLBPPCS1RDPRIM;
|
|
input PLBPPCS1RNW;
|
|
input PLBPPCS1SAVALID;
|
|
input PLBPPCS1WRBURST;
|
|
input PLBPPCS1WRPENDREQ;
|
|
input PLBPPCS1WRPRIM;
|
|
input RSTC440RESETCHIP;
|
|
input RSTC440RESETCORE;
|
|
input RSTC440RESETSYSTEM;
|
|
input TIEC440ENDIANRESET;
|
|
input TRCC440TRACEDISABLE;
|
|
input TRCC440TRIGGEREVENTIN;
|
|
input [0:127] FCMAPUSTOREDATA;
|
|
input [0:127] MCMIREADDATA;
|
|
input [0:127] PLBPPCMRDDBUS;
|
|
input [0:127] PLBPPCS0WRDBUS;
|
|
input [0:127] PLBPPCS1WRDBUS;
|
|
input [0:15] PLBPPCS0BE;
|
|
input [0:15] PLBPPCS0TATTRIBUTE;
|
|
input [0:15] PLBPPCS1BE;
|
|
input [0:15] PLBPPCS1TATTRIBUTE;
|
|
input [0:1] PLBPPCMRDPENDPRI;
|
|
input [0:1] PLBPPCMREQPRI;
|
|
input [0:1] PLBPPCMSSIZE;
|
|
input [0:1] PLBPPCMWRPENDPRI;
|
|
input [0:1] PLBPPCS0MASTERID;
|
|
input [0:1] PLBPPCS0MSIZE;
|
|
input [0:1] PLBPPCS0RDPENDPRI;
|
|
input [0:1] PLBPPCS0REQPRI;
|
|
input [0:1] PLBPPCS0WRPENDPRI;
|
|
input [0:1] PLBPPCS1MASTERID;
|
|
input [0:1] PLBPPCS1MSIZE;
|
|
input [0:1] PLBPPCS1RDPENDPRI;
|
|
input [0:1] PLBPPCS1REQPRI;
|
|
input [0:1] PLBPPCS1WRPENDPRI;
|
|
input [0:1] TIEC440DCURDLDCACHEPLBPRIO;
|
|
input [0:1] TIEC440DCURDNONCACHEPLBPRIO;
|
|
input [0:1] TIEC440DCURDTOUCHPLBPRIO;
|
|
input [0:1] TIEC440DCURDURGENTPLBPRIO;
|
|
input [0:1] TIEC440DCUWRFLUSHPLBPRIO;
|
|
input [0:1] TIEC440DCUWRSTOREPLBPRIO;
|
|
input [0:1] TIEC440DCUWRURGENTPLBPRIO;
|
|
input [0:1] TIEC440ICURDFETCHPLBPRIO;
|
|
input [0:1] TIEC440ICURDSPECPLBPRIO;
|
|
input [0:1] TIEC440ICURDTOUCHPLBPRIO;
|
|
input [0:1] TIEDCRBASEADDR;
|
|
input [0:2] PLBPPCS0TYPE;
|
|
input [0:2] PLBPPCS1TYPE;
|
|
input [0:31] DCRPPCDMDBUSIN;
|
|
input [0:31] DCRPPCDSDBUSOUT;
|
|
input [0:31] FCMAPURESULT;
|
|
input [0:31] LLDMA0RXD;
|
|
input [0:31] LLDMA1RXD;
|
|
input [0:31] LLDMA2RXD;
|
|
input [0:31] LLDMA3RXD;
|
|
input [0:31] PLBPPCS0ABUS;
|
|
input [0:31] PLBPPCS1ABUS;
|
|
input [0:3] FCMAPUCR;
|
|
input [0:3] LLDMA0RXREM;
|
|
input [0:3] LLDMA1RXREM;
|
|
input [0:3] LLDMA2RXREM;
|
|
input [0:3] LLDMA3RXREM;
|
|
input [0:3] PLBPPCMRDWDADDR;
|
|
input [0:3] PLBPPCS0SIZE;
|
|
input [0:3] PLBPPCS1SIZE;
|
|
input [0:3] TIEC440ERPNRESET;
|
|
input [0:3] TIEC440USERRESET;
|
|
input [0:4] DBGC440SYSTEMSTATUS;
|
|
input [0:9] DCRPPCDSABUS;
|
|
input [28:31] PLBPPCS0UABUS;
|
|
input [28:31] PLBPPCS1UABUS;
|
|
input [28:31] TIEC440PIR;
|
|
input [28:31] TIEC440PVR;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module PS7(DMA0DAVALID, DMA0DRREADY, DMA0RSTN, DMA1DAVALID, DMA1DRREADY, DMA1RSTN, DMA2DAVALID, DMA2DRREADY, DMA2RSTN, DMA3DAVALID, DMA3DRREADY, DMA3RSTN, EMIOCAN0PHYTX, EMIOCAN1PHYTX, EMIOENET0GMIITXEN, EMIOENET0GMIITXER, EMIOENET0MDIOMDC, EMIOENET0MDIOO, EMIOENET0MDIOTN, EMIOENET0PTPDELAYREQRX, EMIOENET0PTPDELAYREQTX
|
|
, EMIOENET0PTPPDELAYREQRX, EMIOENET0PTPPDELAYREQTX, EMIOENET0PTPPDELAYRESPRX, EMIOENET0PTPPDELAYRESPTX, EMIOENET0PTPSYNCFRAMERX, EMIOENET0PTPSYNCFRAMETX, EMIOENET0SOFRX, EMIOENET0SOFTX, EMIOENET1GMIITXEN, EMIOENET1GMIITXER, EMIOENET1MDIOMDC, EMIOENET1MDIOO, EMIOENET1MDIOTN, EMIOENET1PTPDELAYREQRX, EMIOENET1PTPDELAYREQTX, EMIOENET1PTPPDELAYREQRX, EMIOENET1PTPPDELAYREQTX, EMIOENET1PTPPDELAYRESPRX, EMIOENET1PTPPDELAYRESPTX, EMIOENET1PTPSYNCFRAMERX, EMIOENET1PTPSYNCFRAMETX
|
|
, EMIOENET1SOFRX, EMIOENET1SOFTX, EMIOI2C0SCLO, EMIOI2C0SCLTN, EMIOI2C0SDAO, EMIOI2C0SDATN, EMIOI2C1SCLO, EMIOI2C1SCLTN, EMIOI2C1SDAO, EMIOI2C1SDATN, EMIOPJTAGTDO, EMIOPJTAGTDTN, EMIOSDIO0BUSPOW, EMIOSDIO0CLK, EMIOSDIO0CMDO, EMIOSDIO0CMDTN, EMIOSDIO0LED, EMIOSDIO1BUSPOW, EMIOSDIO1CLK, EMIOSDIO1CMDO, EMIOSDIO1CMDTN
|
|
, EMIOSDIO1LED, EMIOSPI0MO, EMIOSPI0MOTN, EMIOSPI0SCLKO, EMIOSPI0SCLKTN, EMIOSPI0SO, EMIOSPI0SSNTN, EMIOSPI0STN, EMIOSPI1MO, EMIOSPI1MOTN, EMIOSPI1SCLKO, EMIOSPI1SCLKTN, EMIOSPI1SO, EMIOSPI1SSNTN, EMIOSPI1STN, EMIOTRACECTL, EMIOUART0DTRN, EMIOUART0RTSN, EMIOUART0TX, EMIOUART1DTRN, EMIOUART1RTSN
|
|
, EMIOUART1TX, EMIOUSB0VBUSPWRSELECT, EMIOUSB1VBUSPWRSELECT, EMIOWDTRSTO, EVENTEVENTO, MAXIGP0ARESETN, MAXIGP0ARVALID, MAXIGP0AWVALID, MAXIGP0BREADY, MAXIGP0RREADY, MAXIGP0WLAST, MAXIGP0WVALID, MAXIGP1ARESETN, MAXIGP1ARVALID, MAXIGP1AWVALID, MAXIGP1BREADY, MAXIGP1RREADY, MAXIGP1WLAST, MAXIGP1WVALID, SAXIACPARESETN, SAXIACPARREADY
|
|
, SAXIACPAWREADY, SAXIACPBVALID, SAXIACPRLAST, SAXIACPRVALID, SAXIACPWREADY, SAXIGP0ARESETN, SAXIGP0ARREADY, SAXIGP0AWREADY, SAXIGP0BVALID, SAXIGP0RLAST, SAXIGP0RVALID, SAXIGP0WREADY, SAXIGP1ARESETN, SAXIGP1ARREADY, SAXIGP1AWREADY, SAXIGP1BVALID, SAXIGP1RLAST, SAXIGP1RVALID, SAXIGP1WREADY, SAXIHP0ARESETN, SAXIHP0ARREADY
|
|
, SAXIHP0AWREADY, SAXIHP0BVALID, SAXIHP0RLAST, SAXIHP0RVALID, SAXIHP0WREADY, SAXIHP1ARESETN, SAXIHP1ARREADY, SAXIHP1AWREADY, SAXIHP1BVALID, SAXIHP1RLAST, SAXIHP1RVALID, SAXIHP1WREADY, SAXIHP2ARESETN, SAXIHP2ARREADY, SAXIHP2AWREADY, SAXIHP2BVALID, SAXIHP2RLAST, SAXIHP2RVALID, SAXIHP2WREADY, SAXIHP3ARESETN, SAXIHP3ARREADY
|
|
, SAXIHP3AWREADY, SAXIHP3BVALID, SAXIHP3RLAST, SAXIHP3RVALID, SAXIHP3WREADY, MAXIGP0ARID, MAXIGP0AWID, MAXIGP0WID, MAXIGP1ARID, MAXIGP1AWID, MAXIGP1WID, DMA0DATYPE, DMA1DATYPE, DMA2DATYPE, DMA3DATYPE, EMIOUSB0PORTINDCTL, EMIOUSB1PORTINDCTL, EVENTSTANDBYWFE, EVENTSTANDBYWFI, MAXIGP0ARBURST, MAXIGP0ARLOCK
|
|
, MAXIGP0ARSIZE, MAXIGP0AWBURST, MAXIGP0AWLOCK, MAXIGP0AWSIZE, MAXIGP1ARBURST, MAXIGP1ARLOCK, MAXIGP1ARSIZE, MAXIGP1AWBURST, MAXIGP1AWLOCK, MAXIGP1AWSIZE, SAXIACPBRESP, SAXIACPRRESP, SAXIGP0BRESP, SAXIGP0RRESP, SAXIGP1BRESP, SAXIGP1RRESP, SAXIHP0BRESP, SAXIHP0RRESP, SAXIHP1BRESP, SAXIHP1RRESP, SAXIHP2BRESP
|
|
, SAXIHP2RRESP, SAXIHP3BRESP, SAXIHP3RRESP, IRQP2F, EMIOSDIO0BUSVOLT, EMIOSDIO1BUSVOLT, EMIOSPI0SSON, EMIOSPI1SSON, EMIOTTC0WAVEO, EMIOTTC1WAVEO, MAXIGP0ARPROT, MAXIGP0AWPROT, MAXIGP1ARPROT, MAXIGP1AWPROT, SAXIACPBID, SAXIACPRID, SAXIHP0RACOUNT, SAXIHP1RACOUNT, SAXIHP2RACOUNT, SAXIHP3RACOUNT, EMIOTRACEDATA
|
|
, FTMTP2FDEBUG, MAXIGP0ARADDR, MAXIGP0AWADDR, MAXIGP0WDATA, MAXIGP1ARADDR, MAXIGP1AWADDR, MAXIGP1WDATA, SAXIGP0RDATA, SAXIGP1RDATA, EMIOSDIO0DATAO, EMIOSDIO0DATATN, EMIOSDIO1DATAO, EMIOSDIO1DATATN, FCLKCLK, FCLKRESETN, FTMTF2PTRIGACK, FTMTP2FTRIG, MAXIGP0ARCACHE, MAXIGP0ARLEN, MAXIGP0ARQOS, MAXIGP0AWCACHE
|
|
, MAXIGP0AWLEN, MAXIGP0AWQOS, MAXIGP0WSTRB, MAXIGP1ARCACHE, MAXIGP1ARLEN, MAXIGP1ARQOS, MAXIGP1AWCACHE, MAXIGP1AWLEN, MAXIGP1AWQOS, MAXIGP1WSTRB, SAXIGP0BID, SAXIGP0RID, SAXIGP1BID, SAXIGP1RID, SAXIHP0BID, SAXIHP0RID, SAXIHP0WACOUNT, SAXIHP1BID, SAXIHP1RID, SAXIHP1WACOUNT, SAXIHP2BID
|
|
, SAXIHP2RID, SAXIHP2WACOUNT, SAXIHP3BID, SAXIHP3RID, SAXIHP3WACOUNT, EMIOGPIOO, EMIOGPIOTN, SAXIACPRDATA, SAXIHP0RDATA, SAXIHP1RDATA, SAXIHP2RDATA, SAXIHP3RDATA, EMIOENET0GMIITXD, EMIOENET1GMIITXD, SAXIHP0RCOUNT, SAXIHP0WCOUNT, SAXIHP1RCOUNT, SAXIHP1WCOUNT, SAXIHP2RCOUNT, SAXIHP2WCOUNT, SAXIHP3RCOUNT
|
|
, SAXIHP3WCOUNT, DDRCASB, DDRCKE, DDRCKN, DDRCKP, DDRCSB, DDRDRSTB, DDRODT, DDRRASB, DDRVRN, DDRVRP, DDRWEB, PSCLK, PSPORB, PSSRSTB, DDRA, DDRBA, DDRDQ, DDRDM, DDRDQSN, DDRDQSP
|
|
, MIO, DMA0ACLK, DMA0DAREADY, DMA0DRLAST, DMA0DRVALID, DMA1ACLK, DMA1DAREADY, DMA1DRLAST, DMA1DRVALID, DMA2ACLK, DMA2DAREADY, DMA2DRLAST, DMA2DRVALID, DMA3ACLK, DMA3DAREADY, DMA3DRLAST, DMA3DRVALID, EMIOCAN0PHYRX, EMIOCAN1PHYRX, EMIOENET0EXTINTIN, EMIOENET0GMIICOL
|
|
, EMIOENET0GMIICRS, EMIOENET0GMIIRXCLK, EMIOENET0GMIIRXDV, EMIOENET0GMIIRXER, EMIOENET0GMIITXCLK, EMIOENET0MDIOI, EMIOENET1EXTINTIN, EMIOENET1GMIICOL, EMIOENET1GMIICRS, EMIOENET1GMIIRXCLK, EMIOENET1GMIIRXDV, EMIOENET1GMIIRXER, EMIOENET1GMIITXCLK, EMIOENET1MDIOI, EMIOI2C0SCLI, EMIOI2C0SDAI, EMIOI2C1SCLI, EMIOI2C1SDAI, EMIOPJTAGTCK, EMIOPJTAGTDI, EMIOPJTAGTMS
|
|
, EMIOSDIO0CDN, EMIOSDIO0CLKFB, EMIOSDIO0CMDI, EMIOSDIO0WP, EMIOSDIO1CDN, EMIOSDIO1CLKFB, EMIOSDIO1CMDI, EMIOSDIO1WP, EMIOSPI0MI, EMIOSPI0SCLKI, EMIOSPI0SI, EMIOSPI0SSIN, EMIOSPI1MI, EMIOSPI1SCLKI, EMIOSPI1SI, EMIOSPI1SSIN, EMIOSRAMINTIN, EMIOTRACECLK, EMIOUART0CTSN, EMIOUART0DCDN, EMIOUART0DSRN
|
|
, EMIOUART0RIN, EMIOUART0RX, EMIOUART1CTSN, EMIOUART1DCDN, EMIOUART1DSRN, EMIOUART1RIN, EMIOUART1RX, EMIOUSB0VBUSPWRFAULT, EMIOUSB1VBUSPWRFAULT, EMIOWDTCLKI, EVENTEVENTI, FPGAIDLEN, FTMDTRACEINCLOCK, FTMDTRACEINVALID, MAXIGP0ACLK, MAXIGP0ARREADY, MAXIGP0AWREADY, MAXIGP0BVALID, MAXIGP0RLAST, MAXIGP0RVALID, MAXIGP0WREADY
|
|
, MAXIGP1ACLK, MAXIGP1ARREADY, MAXIGP1AWREADY, MAXIGP1BVALID, MAXIGP1RLAST, MAXIGP1RVALID, MAXIGP1WREADY, SAXIACPACLK, SAXIACPARVALID, SAXIACPAWVALID, SAXIACPBREADY, SAXIACPRREADY, SAXIACPWLAST, SAXIACPWVALID, SAXIGP0ACLK, SAXIGP0ARVALID, SAXIGP0AWVALID, SAXIGP0BREADY, SAXIGP0RREADY, SAXIGP0WLAST, SAXIGP0WVALID
|
|
, SAXIGP1ACLK, SAXIGP1ARVALID, SAXIGP1AWVALID, SAXIGP1BREADY, SAXIGP1RREADY, SAXIGP1WLAST, SAXIGP1WVALID, SAXIHP0ACLK, SAXIHP0ARVALID, SAXIHP0AWVALID, SAXIHP0BREADY, SAXIHP0RDISSUECAP1EN, SAXIHP0RREADY, SAXIHP0WLAST, SAXIHP0WRISSUECAP1EN, SAXIHP0WVALID, SAXIHP1ACLK, SAXIHP1ARVALID, SAXIHP1AWVALID, SAXIHP1BREADY, SAXIHP1RDISSUECAP1EN
|
|
, SAXIHP1RREADY, SAXIHP1WLAST, SAXIHP1WRISSUECAP1EN, SAXIHP1WVALID, SAXIHP2ACLK, SAXIHP2ARVALID, SAXIHP2AWVALID, SAXIHP2BREADY, SAXIHP2RDISSUECAP1EN, SAXIHP2RREADY, SAXIHP2WLAST, SAXIHP2WRISSUECAP1EN, SAXIHP2WVALID, SAXIHP3ACLK, SAXIHP3ARVALID, SAXIHP3AWVALID, SAXIHP3BREADY, SAXIHP3RDISSUECAP1EN, SAXIHP3RREADY, SAXIHP3WLAST, SAXIHP3WRISSUECAP1EN
|
|
, SAXIHP3WVALID, MAXIGP0BID, MAXIGP0RID, MAXIGP1BID, MAXIGP1RID, IRQF2P, DMA0DRTYPE, DMA1DRTYPE, DMA2DRTYPE, DMA3DRTYPE, MAXIGP0BRESP, MAXIGP0RRESP, MAXIGP1BRESP, MAXIGP1RRESP, SAXIACPARBURST, SAXIACPARLOCK, SAXIACPARSIZE, SAXIACPAWBURST, SAXIACPAWLOCK, SAXIACPAWSIZE, SAXIGP0ARBURST
|
|
, SAXIGP0ARLOCK, SAXIGP0ARSIZE, SAXIGP0AWBURST, SAXIGP0AWLOCK, SAXIGP0AWSIZE, SAXIGP1ARBURST, SAXIGP1ARLOCK, SAXIGP1ARSIZE, SAXIGP1AWBURST, SAXIGP1AWLOCK, SAXIGP1AWSIZE, SAXIHP0ARBURST, SAXIHP0ARLOCK, SAXIHP0ARSIZE, SAXIHP0AWBURST, SAXIHP0AWLOCK, SAXIHP0AWSIZE, SAXIHP1ARBURST, SAXIHP1ARLOCK, SAXIHP1ARSIZE, SAXIHP1AWBURST
|
|
, SAXIHP1AWLOCK, SAXIHP1AWSIZE, SAXIHP2ARBURST, SAXIHP2ARLOCK, SAXIHP2ARSIZE, SAXIHP2AWBURST, SAXIHP2AWLOCK, SAXIHP2AWSIZE, SAXIHP3ARBURST, SAXIHP3ARLOCK, SAXIHP3ARSIZE, SAXIHP3AWBURST, SAXIHP3AWLOCK, SAXIHP3AWSIZE, EMIOTTC0CLKI, EMIOTTC1CLKI, SAXIACPARID, SAXIACPARPROT, SAXIACPAWID, SAXIACPAWPROT, SAXIACPWID
|
|
, SAXIGP0ARPROT, SAXIGP0AWPROT, SAXIGP1ARPROT, SAXIGP1AWPROT, SAXIHP0ARPROT, SAXIHP0AWPROT, SAXIHP1ARPROT, SAXIHP1AWPROT, SAXIHP2ARPROT, SAXIHP2AWPROT, SAXIHP3ARPROT, SAXIHP3AWPROT, FTMDTRACEINDATA, FTMTF2PDEBUG, MAXIGP0RDATA, MAXIGP1RDATA, SAXIACPARADDR, SAXIACPAWADDR, SAXIGP0ARADDR, SAXIGP0AWADDR, SAXIGP0WDATA
|
|
, SAXIGP1ARADDR, SAXIGP1AWADDR, SAXIGP1WDATA, SAXIHP0ARADDR, SAXIHP0AWADDR, SAXIHP1ARADDR, SAXIHP1AWADDR, SAXIHP2ARADDR, SAXIHP2AWADDR, SAXIHP3ARADDR, SAXIHP3AWADDR, DDRARB, EMIOSDIO0DATAI, EMIOSDIO1DATAI, FCLKCLKTRIGN, FTMDTRACEINATID, FTMTF2PTRIG, FTMTP2FTRIGACK, SAXIACPARCACHE, SAXIACPARLEN, SAXIACPARQOS
|
|
, SAXIACPAWCACHE, SAXIACPAWLEN, SAXIACPAWQOS, SAXIGP0ARCACHE, SAXIGP0ARLEN, SAXIGP0ARQOS, SAXIGP0AWCACHE, SAXIGP0AWLEN, SAXIGP0AWQOS, SAXIGP0WSTRB, SAXIGP1ARCACHE, SAXIGP1ARLEN, SAXIGP1ARQOS, SAXIGP1AWCACHE, SAXIGP1AWLEN, SAXIGP1AWQOS, SAXIGP1WSTRB, SAXIHP0ARCACHE, SAXIHP0ARLEN, SAXIHP0ARQOS, SAXIHP0AWCACHE
|
|
, SAXIHP0AWLEN, SAXIHP0AWQOS, SAXIHP1ARCACHE, SAXIHP1ARLEN, SAXIHP1ARQOS, SAXIHP1AWCACHE, SAXIHP1AWLEN, SAXIHP1AWQOS, SAXIHP2ARCACHE, SAXIHP2ARLEN, SAXIHP2ARQOS, SAXIHP2AWCACHE, SAXIHP2AWLEN, SAXIHP2AWQOS, SAXIHP3ARCACHE, SAXIHP3ARLEN, SAXIHP3ARQOS, SAXIHP3AWCACHE, SAXIHP3AWLEN, SAXIHP3AWQOS, SAXIACPARUSER
|
|
, SAXIACPAWUSER, SAXIGP0ARID, SAXIGP0AWID, SAXIGP0WID, SAXIGP1ARID, SAXIGP1AWID, SAXIGP1WID, SAXIHP0ARID, SAXIHP0AWID, SAXIHP0WID, SAXIHP1ARID, SAXIHP1AWID, SAXIHP1WID, SAXIHP2ARID, SAXIHP2AWID, SAXIHP2WID, SAXIHP3ARID, SAXIHP3AWID, SAXIHP3WID, EMIOGPIOI, SAXIACPWDATA
|
|
, SAXIHP0WDATA, SAXIHP1WDATA, SAXIHP2WDATA, SAXIHP3WDATA, EMIOENET0GMIIRXD, EMIOENET1GMIIRXD, SAXIACPWSTRB, SAXIHP0WSTRB, SAXIHP1WSTRB, SAXIHP2WSTRB, SAXIHP3WSTRB);
|
|
output DMA0DAVALID;
|
|
output DMA0DRREADY;
|
|
output DMA0RSTN;
|
|
output DMA1DAVALID;
|
|
output DMA1DRREADY;
|
|
output DMA1RSTN;
|
|
output DMA2DAVALID;
|
|
output DMA2DRREADY;
|
|
output DMA2RSTN;
|
|
output DMA3DAVALID;
|
|
output DMA3DRREADY;
|
|
output DMA3RSTN;
|
|
output EMIOCAN0PHYTX;
|
|
output EMIOCAN1PHYTX;
|
|
output EMIOENET0GMIITXEN;
|
|
output EMIOENET0GMIITXER;
|
|
output EMIOENET0MDIOMDC;
|
|
output EMIOENET0MDIOO;
|
|
output EMIOENET0MDIOTN;
|
|
output EMIOENET0PTPDELAYREQRX;
|
|
output EMIOENET0PTPDELAYREQTX;
|
|
output EMIOENET0PTPPDELAYREQRX;
|
|
output EMIOENET0PTPPDELAYREQTX;
|
|
output EMIOENET0PTPPDELAYRESPRX;
|
|
output EMIOENET0PTPPDELAYRESPTX;
|
|
output EMIOENET0PTPSYNCFRAMERX;
|
|
output EMIOENET0PTPSYNCFRAMETX;
|
|
output EMIOENET0SOFRX;
|
|
output EMIOENET0SOFTX;
|
|
output EMIOENET1GMIITXEN;
|
|
output EMIOENET1GMIITXER;
|
|
output EMIOENET1MDIOMDC;
|
|
output EMIOENET1MDIOO;
|
|
output EMIOENET1MDIOTN;
|
|
output EMIOENET1PTPDELAYREQRX;
|
|
output EMIOENET1PTPDELAYREQTX;
|
|
output EMIOENET1PTPPDELAYREQRX;
|
|
output EMIOENET1PTPPDELAYREQTX;
|
|
output EMIOENET1PTPPDELAYRESPRX;
|
|
output EMIOENET1PTPPDELAYRESPTX;
|
|
output EMIOENET1PTPSYNCFRAMERX;
|
|
output EMIOENET1PTPSYNCFRAMETX;
|
|
output EMIOENET1SOFRX;
|
|
output EMIOENET1SOFTX;
|
|
output EMIOI2C0SCLO;
|
|
output EMIOI2C0SCLTN;
|
|
output EMIOI2C0SDAO;
|
|
output EMIOI2C0SDATN;
|
|
output EMIOI2C1SCLO;
|
|
output EMIOI2C1SCLTN;
|
|
output EMIOI2C1SDAO;
|
|
output EMIOI2C1SDATN;
|
|
output EMIOPJTAGTDO;
|
|
output EMIOPJTAGTDTN;
|
|
output EMIOSDIO0BUSPOW;
|
|
output EMIOSDIO0CLK;
|
|
output EMIOSDIO0CMDO;
|
|
output EMIOSDIO0CMDTN;
|
|
output EMIOSDIO0LED;
|
|
output EMIOSDIO1BUSPOW;
|
|
output EMIOSDIO1CLK;
|
|
output EMIOSDIO1CMDO;
|
|
output EMIOSDIO1CMDTN;
|
|
output EMIOSDIO1LED;
|
|
output EMIOSPI0MO;
|
|
output EMIOSPI0MOTN;
|
|
output EMIOSPI0SCLKO;
|
|
output EMIOSPI0SCLKTN;
|
|
output EMIOSPI0SO;
|
|
output EMIOSPI0SSNTN;
|
|
output EMIOSPI0STN;
|
|
output EMIOSPI1MO;
|
|
output EMIOSPI1MOTN;
|
|
output EMIOSPI1SCLKO;
|
|
output EMIOSPI1SCLKTN;
|
|
output EMIOSPI1SO;
|
|
output EMIOSPI1SSNTN;
|
|
output EMIOSPI1STN;
|
|
output EMIOTRACECTL;
|
|
output EMIOUART0DTRN;
|
|
output EMIOUART0RTSN;
|
|
output EMIOUART0TX;
|
|
output EMIOUART1DTRN;
|
|
output EMIOUART1RTSN;
|
|
output EMIOUART1TX;
|
|
output EMIOUSB0VBUSPWRSELECT;
|
|
output EMIOUSB1VBUSPWRSELECT;
|
|
output EMIOWDTRSTO;
|
|
output EVENTEVENTO;
|
|
output MAXIGP0ARESETN;
|
|
output MAXIGP0ARVALID;
|
|
output MAXIGP0AWVALID;
|
|
output MAXIGP0BREADY;
|
|
output MAXIGP0RREADY;
|
|
output MAXIGP0WLAST;
|
|
output MAXIGP0WVALID;
|
|
output MAXIGP1ARESETN;
|
|
output MAXIGP1ARVALID;
|
|
output MAXIGP1AWVALID;
|
|
output MAXIGP1BREADY;
|
|
output MAXIGP1RREADY;
|
|
output MAXIGP1WLAST;
|
|
output MAXIGP1WVALID;
|
|
output SAXIACPARESETN;
|
|
output SAXIACPARREADY;
|
|
output SAXIACPAWREADY;
|
|
output SAXIACPBVALID;
|
|
output SAXIACPRLAST;
|
|
output SAXIACPRVALID;
|
|
output SAXIACPWREADY;
|
|
output SAXIGP0ARESETN;
|
|
output SAXIGP0ARREADY;
|
|
output SAXIGP0AWREADY;
|
|
output SAXIGP0BVALID;
|
|
output SAXIGP0RLAST;
|
|
output SAXIGP0RVALID;
|
|
output SAXIGP0WREADY;
|
|
output SAXIGP1ARESETN;
|
|
output SAXIGP1ARREADY;
|
|
output SAXIGP1AWREADY;
|
|
output SAXIGP1BVALID;
|
|
output SAXIGP1RLAST;
|
|
output SAXIGP1RVALID;
|
|
output SAXIGP1WREADY;
|
|
output SAXIHP0ARESETN;
|
|
output SAXIHP0ARREADY;
|
|
output SAXIHP0AWREADY;
|
|
output SAXIHP0BVALID;
|
|
output SAXIHP0RLAST;
|
|
output SAXIHP0RVALID;
|
|
output SAXIHP0WREADY;
|
|
output SAXIHP1ARESETN;
|
|
output SAXIHP1ARREADY;
|
|
output SAXIHP1AWREADY;
|
|
output SAXIHP1BVALID;
|
|
output SAXIHP1RLAST;
|
|
output SAXIHP1RVALID;
|
|
output SAXIHP1WREADY;
|
|
output SAXIHP2ARESETN;
|
|
output SAXIHP2ARREADY;
|
|
output SAXIHP2AWREADY;
|
|
output SAXIHP2BVALID;
|
|
output SAXIHP2RLAST;
|
|
output SAXIHP2RVALID;
|
|
output SAXIHP2WREADY;
|
|
output SAXIHP3ARESETN;
|
|
output SAXIHP3ARREADY;
|
|
output SAXIHP3AWREADY;
|
|
output SAXIHP3BVALID;
|
|
output SAXIHP3RLAST;
|
|
output SAXIHP3RVALID;
|
|
output SAXIHP3WREADY;
|
|
output [11:0] MAXIGP0ARID;
|
|
output [11:0] MAXIGP0AWID;
|
|
output [11:0] MAXIGP0WID;
|
|
output [11:0] MAXIGP1ARID;
|
|
output [11:0] MAXIGP1AWID;
|
|
output [11:0] MAXIGP1WID;
|
|
output [1:0] DMA0DATYPE;
|
|
output [1:0] DMA1DATYPE;
|
|
output [1:0] DMA2DATYPE;
|
|
output [1:0] DMA3DATYPE;
|
|
output [1:0] EMIOUSB0PORTINDCTL;
|
|
output [1:0] EMIOUSB1PORTINDCTL;
|
|
output [1:0] EVENTSTANDBYWFE;
|
|
output [1:0] EVENTSTANDBYWFI;
|
|
output [1:0] MAXIGP0ARBURST;
|
|
output [1:0] MAXIGP0ARLOCK;
|
|
output [1:0] MAXIGP0ARSIZE;
|
|
output [1:0] MAXIGP0AWBURST;
|
|
output [1:0] MAXIGP0AWLOCK;
|
|
output [1:0] MAXIGP0AWSIZE;
|
|
output [1:0] MAXIGP1ARBURST;
|
|
output [1:0] MAXIGP1ARLOCK;
|
|
output [1:0] MAXIGP1ARSIZE;
|
|
output [1:0] MAXIGP1AWBURST;
|
|
output [1:0] MAXIGP1AWLOCK;
|
|
output [1:0] MAXIGP1AWSIZE;
|
|
output [1:0] SAXIACPBRESP;
|
|
output [1:0] SAXIACPRRESP;
|
|
output [1:0] SAXIGP0BRESP;
|
|
output [1:0] SAXIGP0RRESP;
|
|
output [1:0] SAXIGP1BRESP;
|
|
output [1:0] SAXIGP1RRESP;
|
|
output [1:0] SAXIHP0BRESP;
|
|
output [1:0] SAXIHP0RRESP;
|
|
output [1:0] SAXIHP1BRESP;
|
|
output [1:0] SAXIHP1RRESP;
|
|
output [1:0] SAXIHP2BRESP;
|
|
output [1:0] SAXIHP2RRESP;
|
|
output [1:0] SAXIHP3BRESP;
|
|
output [1:0] SAXIHP3RRESP;
|
|
output [28:0] IRQP2F;
|
|
output [2:0] EMIOSDIO0BUSVOLT;
|
|
output [2:0] EMIOSDIO1BUSVOLT;
|
|
output [2:0] EMIOSPI0SSON;
|
|
output [2:0] EMIOSPI1SSON;
|
|
output [2:0] EMIOTTC0WAVEO;
|
|
output [2:0] EMIOTTC1WAVEO;
|
|
output [2:0] MAXIGP0ARPROT;
|
|
output [2:0] MAXIGP0AWPROT;
|
|
output [2:0] MAXIGP1ARPROT;
|
|
output [2:0] MAXIGP1AWPROT;
|
|
output [2:0] SAXIACPBID;
|
|
output [2:0] SAXIACPRID;
|
|
output [2:0] SAXIHP0RACOUNT;
|
|
output [2:0] SAXIHP1RACOUNT;
|
|
output [2:0] SAXIHP2RACOUNT;
|
|
output [2:0] SAXIHP3RACOUNT;
|
|
output [31:0] EMIOTRACEDATA;
|
|
output [31:0] FTMTP2FDEBUG;
|
|
output [31:0] MAXIGP0ARADDR;
|
|
output [31:0] MAXIGP0AWADDR;
|
|
output [31:0] MAXIGP0WDATA;
|
|
output [31:0] MAXIGP1ARADDR;
|
|
output [31:0] MAXIGP1AWADDR;
|
|
output [31:0] MAXIGP1WDATA;
|
|
output [31:0] SAXIGP0RDATA;
|
|
output [31:0] SAXIGP1RDATA;
|
|
output [3:0] EMIOSDIO0DATAO;
|
|
output [3:0] EMIOSDIO0DATATN;
|
|
output [3:0] EMIOSDIO1DATAO;
|
|
output [3:0] EMIOSDIO1DATATN;
|
|
output [3:0] FCLKCLK;
|
|
output [3:0] FCLKRESETN;
|
|
output [3:0] FTMTF2PTRIGACK;
|
|
output [3:0] FTMTP2FTRIG;
|
|
output [3:0] MAXIGP0ARCACHE;
|
|
output [3:0] MAXIGP0ARLEN;
|
|
output [3:0] MAXIGP0ARQOS;
|
|
output [3:0] MAXIGP0AWCACHE;
|
|
output [3:0] MAXIGP0AWLEN;
|
|
output [3:0] MAXIGP0AWQOS;
|
|
output [3:0] MAXIGP0WSTRB;
|
|
output [3:0] MAXIGP1ARCACHE;
|
|
output [3:0] MAXIGP1ARLEN;
|
|
output [3:0] MAXIGP1ARQOS;
|
|
output [3:0] MAXIGP1AWCACHE;
|
|
output [3:0] MAXIGP1AWLEN;
|
|
output [3:0] MAXIGP1AWQOS;
|
|
output [3:0] MAXIGP1WSTRB;
|
|
output [5:0] SAXIGP0BID;
|
|
output [5:0] SAXIGP0RID;
|
|
output [5:0] SAXIGP1BID;
|
|
output [5:0] SAXIGP1RID;
|
|
output [5:0] SAXIHP0BID;
|
|
output [5:0] SAXIHP0RID;
|
|
output [5:0] SAXIHP0WACOUNT;
|
|
output [5:0] SAXIHP1BID;
|
|
output [5:0] SAXIHP1RID;
|
|
output [5:0] SAXIHP1WACOUNT;
|
|
output [5:0] SAXIHP2BID;
|
|
output [5:0] SAXIHP2RID;
|
|
output [5:0] SAXIHP2WACOUNT;
|
|
output [5:0] SAXIHP3BID;
|
|
output [5:0] SAXIHP3RID;
|
|
output [5:0] SAXIHP3WACOUNT;
|
|
output [63:0] EMIOGPIOO;
|
|
output [63:0] EMIOGPIOTN;
|
|
output [63:0] SAXIACPRDATA;
|
|
output [63:0] SAXIHP0RDATA;
|
|
output [63:0] SAXIHP1RDATA;
|
|
output [63:0] SAXIHP2RDATA;
|
|
output [63:0] SAXIHP3RDATA;
|
|
output [7:0] EMIOENET0GMIITXD;
|
|
output [7:0] EMIOENET1GMIITXD;
|
|
output [7:0] SAXIHP0RCOUNT;
|
|
output [7:0] SAXIHP0WCOUNT;
|
|
output [7:0] SAXIHP1RCOUNT;
|
|
output [7:0] SAXIHP1WCOUNT;
|
|
output [7:0] SAXIHP2RCOUNT;
|
|
output [7:0] SAXIHP2WCOUNT;
|
|
output [7:0] SAXIHP3RCOUNT;
|
|
output [7:0] SAXIHP3WCOUNT;
|
|
inout DDRCASB;
|
|
inout DDRCKE;
|
|
inout DDRCKN;
|
|
inout DDRCKP;
|
|
inout DDRCSB;
|
|
inout DDRDRSTB;
|
|
inout DDRODT;
|
|
inout DDRRASB;
|
|
inout DDRVRN;
|
|
inout DDRVRP;
|
|
inout DDRWEB;
|
|
inout PSCLK;
|
|
inout PSPORB;
|
|
inout PSSRSTB;
|
|
inout [14:0] DDRA;
|
|
inout [2:0] DDRBA;
|
|
inout [31:0] DDRDQ;
|
|
inout [3:0] DDRDM;
|
|
inout [3:0] DDRDQSN;
|
|
inout [3:0] DDRDQSP;
|
|
inout [53:0] MIO;
|
|
input DMA0ACLK;
|
|
input DMA0DAREADY;
|
|
input DMA0DRLAST;
|
|
input DMA0DRVALID;
|
|
input DMA1ACLK;
|
|
input DMA1DAREADY;
|
|
input DMA1DRLAST;
|
|
input DMA1DRVALID;
|
|
input DMA2ACLK;
|
|
input DMA2DAREADY;
|
|
input DMA2DRLAST;
|
|
input DMA2DRVALID;
|
|
input DMA3ACLK;
|
|
input DMA3DAREADY;
|
|
input DMA3DRLAST;
|
|
input DMA3DRVALID;
|
|
input EMIOCAN0PHYRX;
|
|
input EMIOCAN1PHYRX;
|
|
input EMIOENET0EXTINTIN;
|
|
input EMIOENET0GMIICOL;
|
|
input EMIOENET0GMIICRS;
|
|
input EMIOENET0GMIIRXCLK;
|
|
input EMIOENET0GMIIRXDV;
|
|
input EMIOENET0GMIIRXER;
|
|
input EMIOENET0GMIITXCLK;
|
|
input EMIOENET0MDIOI;
|
|
input EMIOENET1EXTINTIN;
|
|
input EMIOENET1GMIICOL;
|
|
input EMIOENET1GMIICRS;
|
|
input EMIOENET1GMIIRXCLK;
|
|
input EMIOENET1GMIIRXDV;
|
|
input EMIOENET1GMIIRXER;
|
|
input EMIOENET1GMIITXCLK;
|
|
input EMIOENET1MDIOI;
|
|
input EMIOI2C0SCLI;
|
|
input EMIOI2C0SDAI;
|
|
input EMIOI2C1SCLI;
|
|
input EMIOI2C1SDAI;
|
|
input EMIOPJTAGTCK;
|
|
input EMIOPJTAGTDI;
|
|
input EMIOPJTAGTMS;
|
|
input EMIOSDIO0CDN;
|
|
input EMIOSDIO0CLKFB;
|
|
input EMIOSDIO0CMDI;
|
|
input EMIOSDIO0WP;
|
|
input EMIOSDIO1CDN;
|
|
input EMIOSDIO1CLKFB;
|
|
input EMIOSDIO1CMDI;
|
|
input EMIOSDIO1WP;
|
|
input EMIOSPI0MI;
|
|
input EMIOSPI0SCLKI;
|
|
input EMIOSPI0SI;
|
|
input EMIOSPI0SSIN;
|
|
input EMIOSPI1MI;
|
|
input EMIOSPI1SCLKI;
|
|
input EMIOSPI1SI;
|
|
input EMIOSPI1SSIN;
|
|
input EMIOSRAMINTIN;
|
|
input EMIOTRACECLK;
|
|
input EMIOUART0CTSN;
|
|
input EMIOUART0DCDN;
|
|
input EMIOUART0DSRN;
|
|
input EMIOUART0RIN;
|
|
input EMIOUART0RX;
|
|
input EMIOUART1CTSN;
|
|
input EMIOUART1DCDN;
|
|
input EMIOUART1DSRN;
|
|
input EMIOUART1RIN;
|
|
input EMIOUART1RX;
|
|
input EMIOUSB0VBUSPWRFAULT;
|
|
input EMIOUSB1VBUSPWRFAULT;
|
|
input EMIOWDTCLKI;
|
|
input EVENTEVENTI;
|
|
input FPGAIDLEN;
|
|
input FTMDTRACEINCLOCK;
|
|
input FTMDTRACEINVALID;
|
|
input MAXIGP0ACLK;
|
|
input MAXIGP0ARREADY;
|
|
input MAXIGP0AWREADY;
|
|
input MAXIGP0BVALID;
|
|
input MAXIGP0RLAST;
|
|
input MAXIGP0RVALID;
|
|
input MAXIGP0WREADY;
|
|
input MAXIGP1ACLK;
|
|
input MAXIGP1ARREADY;
|
|
input MAXIGP1AWREADY;
|
|
input MAXIGP1BVALID;
|
|
input MAXIGP1RLAST;
|
|
input MAXIGP1RVALID;
|
|
input MAXIGP1WREADY;
|
|
input SAXIACPACLK;
|
|
input SAXIACPARVALID;
|
|
input SAXIACPAWVALID;
|
|
input SAXIACPBREADY;
|
|
input SAXIACPRREADY;
|
|
input SAXIACPWLAST;
|
|
input SAXIACPWVALID;
|
|
input SAXIGP0ACLK;
|
|
input SAXIGP0ARVALID;
|
|
input SAXIGP0AWVALID;
|
|
input SAXIGP0BREADY;
|
|
input SAXIGP0RREADY;
|
|
input SAXIGP0WLAST;
|
|
input SAXIGP0WVALID;
|
|
input SAXIGP1ACLK;
|
|
input SAXIGP1ARVALID;
|
|
input SAXIGP1AWVALID;
|
|
input SAXIGP1BREADY;
|
|
input SAXIGP1RREADY;
|
|
input SAXIGP1WLAST;
|
|
input SAXIGP1WVALID;
|
|
input SAXIHP0ACLK;
|
|
input SAXIHP0ARVALID;
|
|
input SAXIHP0AWVALID;
|
|
input SAXIHP0BREADY;
|
|
input SAXIHP0RDISSUECAP1EN;
|
|
input SAXIHP0RREADY;
|
|
input SAXIHP0WLAST;
|
|
input SAXIHP0WRISSUECAP1EN;
|
|
input SAXIHP0WVALID;
|
|
input SAXIHP1ACLK;
|
|
input SAXIHP1ARVALID;
|
|
input SAXIHP1AWVALID;
|
|
input SAXIHP1BREADY;
|
|
input SAXIHP1RDISSUECAP1EN;
|
|
input SAXIHP1RREADY;
|
|
input SAXIHP1WLAST;
|
|
input SAXIHP1WRISSUECAP1EN;
|
|
input SAXIHP1WVALID;
|
|
input SAXIHP2ACLK;
|
|
input SAXIHP2ARVALID;
|
|
input SAXIHP2AWVALID;
|
|
input SAXIHP2BREADY;
|
|
input SAXIHP2RDISSUECAP1EN;
|
|
input SAXIHP2RREADY;
|
|
input SAXIHP2WLAST;
|
|
input SAXIHP2WRISSUECAP1EN;
|
|
input SAXIHP2WVALID;
|
|
input SAXIHP3ACLK;
|
|
input SAXIHP3ARVALID;
|
|
input SAXIHP3AWVALID;
|
|
input SAXIHP3BREADY;
|
|
input SAXIHP3RDISSUECAP1EN;
|
|
input SAXIHP3RREADY;
|
|
input SAXIHP3WLAST;
|
|
input SAXIHP3WRISSUECAP1EN;
|
|
input SAXIHP3WVALID;
|
|
input [11:0] MAXIGP0BID;
|
|
input [11:0] MAXIGP0RID;
|
|
input [11:0] MAXIGP1BID;
|
|
input [11:0] MAXIGP1RID;
|
|
input [19:0] IRQF2P;
|
|
input [1:0] DMA0DRTYPE;
|
|
input [1:0] DMA1DRTYPE;
|
|
input [1:0] DMA2DRTYPE;
|
|
input [1:0] DMA3DRTYPE;
|
|
input [1:0] MAXIGP0BRESP;
|
|
input [1:0] MAXIGP0RRESP;
|
|
input [1:0] MAXIGP1BRESP;
|
|
input [1:0] MAXIGP1RRESP;
|
|
input [1:0] SAXIACPARBURST;
|
|
input [1:0] SAXIACPARLOCK;
|
|
input [1:0] SAXIACPARSIZE;
|
|
input [1:0] SAXIACPAWBURST;
|
|
input [1:0] SAXIACPAWLOCK;
|
|
input [1:0] SAXIACPAWSIZE;
|
|
input [1:0] SAXIGP0ARBURST;
|
|
input [1:0] SAXIGP0ARLOCK;
|
|
input [1:0] SAXIGP0ARSIZE;
|
|
input [1:0] SAXIGP0AWBURST;
|
|
input [1:0] SAXIGP0AWLOCK;
|
|
input [1:0] SAXIGP0AWSIZE;
|
|
input [1:0] SAXIGP1ARBURST;
|
|
input [1:0] SAXIGP1ARLOCK;
|
|
input [1:0] SAXIGP1ARSIZE;
|
|
input [1:0] SAXIGP1AWBURST;
|
|
input [1:0] SAXIGP1AWLOCK;
|
|
input [1:0] SAXIGP1AWSIZE;
|
|
input [1:0] SAXIHP0ARBURST;
|
|
input [1:0] SAXIHP0ARLOCK;
|
|
input [1:0] SAXIHP0ARSIZE;
|
|
input [1:0] SAXIHP0AWBURST;
|
|
input [1:0] SAXIHP0AWLOCK;
|
|
input [1:0] SAXIHP0AWSIZE;
|
|
input [1:0] SAXIHP1ARBURST;
|
|
input [1:0] SAXIHP1ARLOCK;
|
|
input [1:0] SAXIHP1ARSIZE;
|
|
input [1:0] SAXIHP1AWBURST;
|
|
input [1:0] SAXIHP1AWLOCK;
|
|
input [1:0] SAXIHP1AWSIZE;
|
|
input [1:0] SAXIHP2ARBURST;
|
|
input [1:0] SAXIHP2ARLOCK;
|
|
input [1:0] SAXIHP2ARSIZE;
|
|
input [1:0] SAXIHP2AWBURST;
|
|
input [1:0] SAXIHP2AWLOCK;
|
|
input [1:0] SAXIHP2AWSIZE;
|
|
input [1:0] SAXIHP3ARBURST;
|
|
input [1:0] SAXIHP3ARLOCK;
|
|
input [1:0] SAXIHP3ARSIZE;
|
|
input [1:0] SAXIHP3AWBURST;
|
|
input [1:0] SAXIHP3AWLOCK;
|
|
input [1:0] SAXIHP3AWSIZE;
|
|
input [2:0] EMIOTTC0CLKI;
|
|
input [2:0] EMIOTTC1CLKI;
|
|
input [2:0] SAXIACPARID;
|
|
input [2:0] SAXIACPARPROT;
|
|
input [2:0] SAXIACPAWID;
|
|
input [2:0] SAXIACPAWPROT;
|
|
input [2:0] SAXIACPWID;
|
|
input [2:0] SAXIGP0ARPROT;
|
|
input [2:0] SAXIGP0AWPROT;
|
|
input [2:0] SAXIGP1ARPROT;
|
|
input [2:0] SAXIGP1AWPROT;
|
|
input [2:0] SAXIHP0ARPROT;
|
|
input [2:0] SAXIHP0AWPROT;
|
|
input [2:0] SAXIHP1ARPROT;
|
|
input [2:0] SAXIHP1AWPROT;
|
|
input [2:0] SAXIHP2ARPROT;
|
|
input [2:0] SAXIHP2AWPROT;
|
|
input [2:0] SAXIHP3ARPROT;
|
|
input [2:0] SAXIHP3AWPROT;
|
|
input [31:0] FTMDTRACEINDATA;
|
|
input [31:0] FTMTF2PDEBUG;
|
|
input [31:0] MAXIGP0RDATA;
|
|
input [31:0] MAXIGP1RDATA;
|
|
input [31:0] SAXIACPARADDR;
|
|
input [31:0] SAXIACPAWADDR;
|
|
input [31:0] SAXIGP0ARADDR;
|
|
input [31:0] SAXIGP0AWADDR;
|
|
input [31:0] SAXIGP0WDATA;
|
|
input [31:0] SAXIGP1ARADDR;
|
|
input [31:0] SAXIGP1AWADDR;
|
|
input [31:0] SAXIGP1WDATA;
|
|
input [31:0] SAXIHP0ARADDR;
|
|
input [31:0] SAXIHP0AWADDR;
|
|
input [31:0] SAXIHP1ARADDR;
|
|
input [31:0] SAXIHP1AWADDR;
|
|
input [31:0] SAXIHP2ARADDR;
|
|
input [31:0] SAXIHP2AWADDR;
|
|
input [31:0] SAXIHP3ARADDR;
|
|
input [31:0] SAXIHP3AWADDR;
|
|
input [3:0] DDRARB;
|
|
input [3:0] EMIOSDIO0DATAI;
|
|
input [3:0] EMIOSDIO1DATAI;
|
|
input [3:0] FCLKCLKTRIGN;
|
|
input [3:0] FTMDTRACEINATID;
|
|
input [3:0] FTMTF2PTRIG;
|
|
input [3:0] FTMTP2FTRIGACK;
|
|
input [3:0] SAXIACPARCACHE;
|
|
input [3:0] SAXIACPARLEN;
|
|
input [3:0] SAXIACPARQOS;
|
|
input [3:0] SAXIACPAWCACHE;
|
|
input [3:0] SAXIACPAWLEN;
|
|
input [3:0] SAXIACPAWQOS;
|
|
input [3:0] SAXIGP0ARCACHE;
|
|
input [3:0] SAXIGP0ARLEN;
|
|
input [3:0] SAXIGP0ARQOS;
|
|
input [3:0] SAXIGP0AWCACHE;
|
|
input [3:0] SAXIGP0AWLEN;
|
|
input [3:0] SAXIGP0AWQOS;
|
|
input [3:0] SAXIGP0WSTRB;
|
|
input [3:0] SAXIGP1ARCACHE;
|
|
input [3:0] SAXIGP1ARLEN;
|
|
input [3:0] SAXIGP1ARQOS;
|
|
input [3:0] SAXIGP1AWCACHE;
|
|
input [3:0] SAXIGP1AWLEN;
|
|
input [3:0] SAXIGP1AWQOS;
|
|
input [3:0] SAXIGP1WSTRB;
|
|
input [3:0] SAXIHP0ARCACHE;
|
|
input [3:0] SAXIHP0ARLEN;
|
|
input [3:0] SAXIHP0ARQOS;
|
|
input [3:0] SAXIHP0AWCACHE;
|
|
input [3:0] SAXIHP0AWLEN;
|
|
input [3:0] SAXIHP0AWQOS;
|
|
input [3:0] SAXIHP1ARCACHE;
|
|
input [3:0] SAXIHP1ARLEN;
|
|
input [3:0] SAXIHP1ARQOS;
|
|
input [3:0] SAXIHP1AWCACHE;
|
|
input [3:0] SAXIHP1AWLEN;
|
|
input [3:0] SAXIHP1AWQOS;
|
|
input [3:0] SAXIHP2ARCACHE;
|
|
input [3:0] SAXIHP2ARLEN;
|
|
input [3:0] SAXIHP2ARQOS;
|
|
input [3:0] SAXIHP2AWCACHE;
|
|
input [3:0] SAXIHP2AWLEN;
|
|
input [3:0] SAXIHP2AWQOS;
|
|
input [3:0] SAXIHP3ARCACHE;
|
|
input [3:0] SAXIHP3ARLEN;
|
|
input [3:0] SAXIHP3ARQOS;
|
|
input [3:0] SAXIHP3AWCACHE;
|
|
input [3:0] SAXIHP3AWLEN;
|
|
input [3:0] SAXIHP3AWQOS;
|
|
input [4:0] SAXIACPARUSER;
|
|
input [4:0] SAXIACPAWUSER;
|
|
input [5:0] SAXIGP0ARID;
|
|
input [5:0] SAXIGP0AWID;
|
|
input [5:0] SAXIGP0WID;
|
|
input [5:0] SAXIGP1ARID;
|
|
input [5:0] SAXIGP1AWID;
|
|
input [5:0] SAXIGP1WID;
|
|
input [5:0] SAXIHP0ARID;
|
|
input [5:0] SAXIHP0AWID;
|
|
input [5:0] SAXIHP0WID;
|
|
input [5:0] SAXIHP1ARID;
|
|
input [5:0] SAXIHP1AWID;
|
|
input [5:0] SAXIHP1WID;
|
|
input [5:0] SAXIHP2ARID;
|
|
input [5:0] SAXIHP2AWID;
|
|
input [5:0] SAXIHP2WID;
|
|
input [5:0] SAXIHP3ARID;
|
|
input [5:0] SAXIHP3AWID;
|
|
input [5:0] SAXIHP3WID;
|
|
input [63:0] EMIOGPIOI;
|
|
input [63:0] SAXIACPWDATA;
|
|
input [63:0] SAXIHP0WDATA;
|
|
input [63:0] SAXIHP1WDATA;
|
|
input [63:0] SAXIHP2WDATA;
|
|
input [63:0] SAXIHP3WDATA;
|
|
input [7:0] EMIOENET0GMIIRXD;
|
|
input [7:0] EMIOENET1GMIIRXD;
|
|
input [7:0] SAXIACPWSTRB;
|
|
input [7:0] SAXIHP0WSTRB;
|
|
input [7:0] SAXIHP1WSTRB;
|
|
input [7:0] SAXIHP2WSTRB;
|
|
input [7:0] SAXIHP3WSTRB;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module PS8(ADMA2PLCACK, ADMA2PLTVLD, DPAUDIOREFCLK, DPAUXDATAOEN, DPAUXDATAOUT, DPLIVEVIDEODEOUT, DPMAXISMIXEDAUDIOTDATA, DPMAXISMIXEDAUDIOTID, DPMAXISMIXEDAUDIOTVALID, DPSAXISAUDIOTREADY, DPVIDEOOUTHSYNC, DPVIDEOOUTPIXEL1, DPVIDEOOUTVSYNC, DPVIDEOREFCLK, EMIOCAN0PHYTX, EMIOCAN1PHYTX, EMIOENET0DMABUSWIDTH, EMIOENET0DMATXENDTOG, EMIOENET0GEMTSUTIMERCNT, EMIOENET0GMIITXD, EMIOENET0GMIITXEN
|
|
, EMIOENET0GMIITXER, EMIOENET0MDIOMDC, EMIOENET0MDIOO, EMIOENET0MDIOTN, EMIOENET0RXWDATA, EMIOENET0RXWEOP, EMIOENET0RXWERR, EMIOENET0RXWFLUSH, EMIOENET0RXWSOP, EMIOENET0RXWSTATUS, EMIOENET0RXWWR, EMIOENET0SPEEDMODE, EMIOENET0TXRRD, EMIOENET0TXRSTATUS, EMIOENET1DMABUSWIDTH, EMIOENET1DMATXENDTOG, EMIOENET1GMIITXD, EMIOENET1GMIITXEN, EMIOENET1GMIITXER, EMIOENET1MDIOMDC, EMIOENET1MDIOO
|
|
, EMIOENET1MDIOTN, EMIOENET1RXWDATA, EMIOENET1RXWEOP, EMIOENET1RXWERR, EMIOENET1RXWFLUSH, EMIOENET1RXWSOP, EMIOENET1RXWSTATUS, EMIOENET1RXWWR, EMIOENET1SPEEDMODE, EMIOENET1TXRRD, EMIOENET1TXRSTATUS, EMIOENET2DMABUSWIDTH, EMIOENET2DMATXENDTOG, EMIOENET2GMIITXD, EMIOENET2GMIITXEN, EMIOENET2GMIITXER, EMIOENET2MDIOMDC, EMIOENET2MDIOO, EMIOENET2MDIOTN, EMIOENET2RXWDATA, EMIOENET2RXWEOP
|
|
, EMIOENET2RXWERR, EMIOENET2RXWFLUSH, EMIOENET2RXWSOP, EMIOENET2RXWSTATUS, EMIOENET2RXWWR, EMIOENET2SPEEDMODE, EMIOENET2TXRRD, EMIOENET2TXRSTATUS, EMIOENET3DMABUSWIDTH, EMIOENET3DMATXENDTOG, EMIOENET3GMIITXD, EMIOENET3GMIITXEN, EMIOENET3GMIITXER, EMIOENET3MDIOMDC, EMIOENET3MDIOO, EMIOENET3MDIOTN, EMIOENET3RXWDATA, EMIOENET3RXWEOP, EMIOENET3RXWERR, EMIOENET3RXWFLUSH, EMIOENET3RXWSOP
|
|
, EMIOENET3RXWSTATUS, EMIOENET3RXWWR, EMIOENET3SPEEDMODE, EMIOENET3TXRRD, EMIOENET3TXRSTATUS, EMIOGEM0DELAYREQRX, EMIOGEM0DELAYREQTX, EMIOGEM0PDELAYREQRX, EMIOGEM0PDELAYREQTX, EMIOGEM0PDELAYRESPRX, EMIOGEM0PDELAYRESPTX, EMIOGEM0RXSOF, EMIOGEM0SYNCFRAMERX, EMIOGEM0SYNCFRAMETX, EMIOGEM0TSUTIMERCMPVAL, EMIOGEM0TXRFIXEDLAT, EMIOGEM0TXSOF, EMIOGEM1DELAYREQRX, EMIOGEM1DELAYREQTX, EMIOGEM1PDELAYREQRX, EMIOGEM1PDELAYREQTX
|
|
, EMIOGEM1PDELAYRESPRX, EMIOGEM1PDELAYRESPTX, EMIOGEM1RXSOF, EMIOGEM1SYNCFRAMERX, EMIOGEM1SYNCFRAMETX, EMIOGEM1TSUTIMERCMPVAL, EMIOGEM1TXRFIXEDLAT, EMIOGEM1TXSOF, EMIOGEM2DELAYREQRX, EMIOGEM2DELAYREQTX, EMIOGEM2PDELAYREQRX, EMIOGEM2PDELAYREQTX, EMIOGEM2PDELAYRESPRX, EMIOGEM2PDELAYRESPTX, EMIOGEM2RXSOF, EMIOGEM2SYNCFRAMERX, EMIOGEM2SYNCFRAMETX, EMIOGEM2TSUTIMERCMPVAL, EMIOGEM2TXRFIXEDLAT, EMIOGEM2TXSOF, EMIOGEM3DELAYREQRX
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, EMIOGEM3DELAYREQTX, EMIOGEM3PDELAYREQRX, EMIOGEM3PDELAYREQTX, EMIOGEM3PDELAYRESPRX, EMIOGEM3PDELAYRESPTX, EMIOGEM3RXSOF, EMIOGEM3SYNCFRAMERX, EMIOGEM3SYNCFRAMETX, EMIOGEM3TSUTIMERCMPVAL, EMIOGEM3TXRFIXEDLAT, EMIOGEM3TXSOF, EMIOGPIOO, EMIOGPIOTN, EMIOI2C0SCLO, EMIOI2C0SCLTN, EMIOI2C0SDAO, EMIOI2C0SDATN, EMIOI2C1SCLO, EMIOI2C1SCLTN, EMIOI2C1SDAO, EMIOI2C1SDATN
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, EMIOSDIO0BUSPOWER, EMIOSDIO0BUSVOLT, EMIOSDIO0CLKOUT, EMIOSDIO0CMDENA, EMIOSDIO0CMDOUT, EMIOSDIO0DATAENA, EMIOSDIO0DATAOUT, EMIOSDIO0LEDCONTROL, EMIOSDIO1BUSPOWER, EMIOSDIO1BUSVOLT, EMIOSDIO1CLKOUT, EMIOSDIO1CMDENA, EMIOSDIO1CMDOUT, EMIOSDIO1DATAENA, EMIOSDIO1DATAOUT, EMIOSDIO1LEDCONTROL, EMIOSPI0MO, EMIOSPI0MOTN, EMIOSPI0SCLKO, EMIOSPI0SCLKTN, EMIOSPI0SO
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, EMIOSPI0SSNTN, EMIOSPI0SSON, EMIOSPI0STN, EMIOSPI1MO, EMIOSPI1MOTN, EMIOSPI1SCLKO, EMIOSPI1SCLKTN, EMIOSPI1SO, EMIOSPI1SSNTN, EMIOSPI1SSON, EMIOSPI1STN, EMIOTTC0WAVEO, EMIOTTC1WAVEO, EMIOTTC2WAVEO, EMIOTTC3WAVEO, EMIOU2DSPORTVBUSCTRLUSB30, EMIOU2DSPORTVBUSCTRLUSB31, EMIOU3DSPORTVBUSCTRLUSB30, EMIOU3DSPORTVBUSCTRLUSB31, EMIOUART0DTRN, EMIOUART0RTSN
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, EMIOUART0TX, EMIOUART1DTRN, EMIOUART1RTSN, EMIOUART1TX, EMIOWDT0RSTO, EMIOWDT1RSTO, FMIOGEM0FIFORXCLKTOPLBUFG, FMIOGEM0FIFOTXCLKTOPLBUFG, FMIOGEM1FIFORXCLKTOPLBUFG, FMIOGEM1FIFOTXCLKTOPLBUFG, FMIOGEM2FIFORXCLKTOPLBUFG, FMIOGEM2FIFOTXCLKTOPLBUFG, FMIOGEM3FIFORXCLKTOPLBUFG, FMIOGEM3FIFOTXCLKTOPLBUFG, FMIOGEMTSUCLKTOPLBUFG, FTMGPO, GDMA2PLCACK, GDMA2PLTVLD, MAXIGP0ARADDR, MAXIGP0ARBURST, MAXIGP0ARCACHE
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, MAXIGP0ARID, MAXIGP0ARLEN, MAXIGP0ARLOCK, MAXIGP0ARPROT, MAXIGP0ARQOS, MAXIGP0ARSIZE, MAXIGP0ARUSER, MAXIGP0ARVALID, MAXIGP0AWADDR, MAXIGP0AWBURST, MAXIGP0AWCACHE, MAXIGP0AWID, MAXIGP0AWLEN, MAXIGP0AWLOCK, MAXIGP0AWPROT, MAXIGP0AWQOS, MAXIGP0AWSIZE, MAXIGP0AWUSER, MAXIGP0AWVALID, MAXIGP0BREADY, MAXIGP0RREADY
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, MAXIGP0WDATA, MAXIGP0WLAST, MAXIGP0WSTRB, MAXIGP0WVALID, MAXIGP1ARADDR, MAXIGP1ARBURST, MAXIGP1ARCACHE, MAXIGP1ARID, MAXIGP1ARLEN, MAXIGP1ARLOCK, MAXIGP1ARPROT, MAXIGP1ARQOS, MAXIGP1ARSIZE, MAXIGP1ARUSER, MAXIGP1ARVALID, MAXIGP1AWADDR, MAXIGP1AWBURST, MAXIGP1AWCACHE, MAXIGP1AWID, MAXIGP1AWLEN, MAXIGP1AWLOCK
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, MAXIGP1AWPROT, MAXIGP1AWQOS, MAXIGP1AWSIZE, MAXIGP1AWUSER, MAXIGP1AWVALID, MAXIGP1BREADY, MAXIGP1RREADY, MAXIGP1WDATA, MAXIGP1WLAST, MAXIGP1WSTRB, MAXIGP1WVALID, MAXIGP2ARADDR, MAXIGP2ARBURST, MAXIGP2ARCACHE, MAXIGP2ARID, MAXIGP2ARLEN, MAXIGP2ARLOCK, MAXIGP2ARPROT, MAXIGP2ARQOS, MAXIGP2ARSIZE, MAXIGP2ARUSER
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, MAXIGP2ARVALID, MAXIGP2AWADDR, MAXIGP2AWBURST, MAXIGP2AWCACHE, MAXIGP2AWID, MAXIGP2AWLEN, MAXIGP2AWLOCK, MAXIGP2AWPROT, MAXIGP2AWQOS, MAXIGP2AWSIZE, MAXIGP2AWUSER, MAXIGP2AWVALID, MAXIGP2BREADY, MAXIGP2RREADY, MAXIGP2WDATA, MAXIGP2WLAST, MAXIGP2WSTRB, MAXIGP2WVALID, OSCRTCCLK, PLCLK, PMUAIBAFIFMFPDREQ
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, PMUAIBAFIFMLPDREQ, PMUERRORTOPL, PMUPLGPO, PSPLEVENTO, PSPLIRQFPD, PSPLIRQLPD, PSPLSTANDBYWFE, PSPLSTANDBYWFI, PSPLTRACECTL, PSPLTRACEDATA, PSPLTRIGACK, PSPLTRIGGER, PSS_ALTO_CORE_PAD_MGTTXN0OUT, PSS_ALTO_CORE_PAD_MGTTXN1OUT, PSS_ALTO_CORE_PAD_MGTTXN2OUT, PSS_ALTO_CORE_PAD_MGTTXN3OUT, PSS_ALTO_CORE_PAD_MGTTXP0OUT, PSS_ALTO_CORE_PAD_MGTTXP1OUT, PSS_ALTO_CORE_PAD_MGTTXP2OUT, PSS_ALTO_CORE_PAD_MGTTXP3OUT, PSS_ALTO_CORE_PAD_PADO
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, RPUEVENTO0, RPUEVENTO1, SACEFPDACADDR, SACEFPDACPROT, SACEFPDACSNOOP, SACEFPDACVALID, SACEFPDARREADY, SACEFPDAWREADY, SACEFPDBID, SACEFPDBRESP, SACEFPDBUSER, SACEFPDBVALID, SACEFPDCDREADY, SACEFPDCRREADY, SACEFPDRDATA, SACEFPDRID, SACEFPDRLAST, SACEFPDRRESP, SACEFPDRUSER, SACEFPDRVALID, SACEFPDWREADY
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|
, SAXIACPARREADY, SAXIACPAWREADY, SAXIACPBID, SAXIACPBRESP, SAXIACPBVALID, SAXIACPRDATA, SAXIACPRID, SAXIACPRLAST, SAXIACPRRESP, SAXIACPRVALID, SAXIACPWREADY, SAXIGP0ARREADY, SAXIGP0AWREADY, SAXIGP0BID, SAXIGP0BRESP, SAXIGP0BVALID, SAXIGP0RACOUNT, SAXIGP0RCOUNT, SAXIGP0RDATA, SAXIGP0RID, SAXIGP0RLAST
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, SAXIGP0RRESP, SAXIGP0RVALID, SAXIGP0WACOUNT, SAXIGP0WCOUNT, SAXIGP0WREADY, SAXIGP1ARREADY, SAXIGP1AWREADY, SAXIGP1BID, SAXIGP1BRESP, SAXIGP1BVALID, SAXIGP1RACOUNT, SAXIGP1RCOUNT, SAXIGP1RDATA, SAXIGP1RID, SAXIGP1RLAST, SAXIGP1RRESP, SAXIGP1RVALID, SAXIGP1WACOUNT, SAXIGP1WCOUNT, SAXIGP1WREADY, SAXIGP2ARREADY
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, SAXIGP2AWREADY, SAXIGP2BID, SAXIGP2BRESP, SAXIGP2BVALID, SAXIGP2RACOUNT, SAXIGP2RCOUNT, SAXIGP2RDATA, SAXIGP2RID, SAXIGP2RLAST, SAXIGP2RRESP, SAXIGP2RVALID, SAXIGP2WACOUNT, SAXIGP2WCOUNT, SAXIGP2WREADY, SAXIGP3ARREADY, SAXIGP3AWREADY, SAXIGP3BID, SAXIGP3BRESP, SAXIGP3BVALID, SAXIGP3RACOUNT, SAXIGP3RCOUNT
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, SAXIGP3RDATA, SAXIGP3RID, SAXIGP3RLAST, SAXIGP3RRESP, SAXIGP3RVALID, SAXIGP3WACOUNT, SAXIGP3WCOUNT, SAXIGP3WREADY, SAXIGP4ARREADY, SAXIGP4AWREADY, SAXIGP4BID, SAXIGP4BRESP, SAXIGP4BVALID, SAXIGP4RACOUNT, SAXIGP4RCOUNT, SAXIGP4RDATA, SAXIGP4RID, SAXIGP4RLAST, SAXIGP4RRESP, SAXIGP4RVALID, SAXIGP4WACOUNT
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, SAXIGP4WCOUNT, SAXIGP4WREADY, SAXIGP5ARREADY, SAXIGP5AWREADY, SAXIGP5BID, SAXIGP5BRESP, SAXIGP5BVALID, SAXIGP5RACOUNT, SAXIGP5RCOUNT, SAXIGP5RDATA, SAXIGP5RID, SAXIGP5RLAST, SAXIGP5RRESP, SAXIGP5RVALID, SAXIGP5WACOUNT, SAXIGP5WCOUNT, SAXIGP5WREADY, SAXIGP6ARREADY, SAXIGP6AWREADY, SAXIGP6BID, SAXIGP6BRESP
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, SAXIGP6BVALID, SAXIGP6RACOUNT, SAXIGP6RCOUNT, SAXIGP6RDATA, SAXIGP6RID, SAXIGP6RLAST, SAXIGP6RRESP, SAXIGP6RVALID, SAXIGP6WACOUNT, SAXIGP6WCOUNT, SAXIGP6WREADY, PSS_ALTO_CORE_PAD_BOOTMODE, PSS_ALTO_CORE_PAD_CLK, PSS_ALTO_CORE_PAD_DONEB, PSS_ALTO_CORE_PAD_DRAMA, PSS_ALTO_CORE_PAD_DRAMACTN, PSS_ALTO_CORE_PAD_DRAMALERTN, PSS_ALTO_CORE_PAD_DRAMBA, PSS_ALTO_CORE_PAD_DRAMBG, PSS_ALTO_CORE_PAD_DRAMCK, PSS_ALTO_CORE_PAD_DRAMCKE
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, PSS_ALTO_CORE_PAD_DRAMCKN, PSS_ALTO_CORE_PAD_DRAMCSN, PSS_ALTO_CORE_PAD_DRAMDM, PSS_ALTO_CORE_PAD_DRAMDQ, PSS_ALTO_CORE_PAD_DRAMDQS, PSS_ALTO_CORE_PAD_DRAMDQSN, PSS_ALTO_CORE_PAD_DRAMODT, PSS_ALTO_CORE_PAD_DRAMPARITY, PSS_ALTO_CORE_PAD_DRAMRAMRSTN, PSS_ALTO_CORE_PAD_ERROROUT, PSS_ALTO_CORE_PAD_ERRORSTATUS, PSS_ALTO_CORE_PAD_INITB, PSS_ALTO_CORE_PAD_JTAGTCK, PSS_ALTO_CORE_PAD_JTAGTDI, PSS_ALTO_CORE_PAD_JTAGTDO, PSS_ALTO_CORE_PAD_JTAGTMS, PSS_ALTO_CORE_PAD_MIO, PSS_ALTO_CORE_PAD_PORB, PSS_ALTO_CORE_PAD_PROGB, PSS_ALTO_CORE_PAD_RCALIBINOUT, PSS_ALTO_CORE_PAD_SRSTB
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, PSS_ALTO_CORE_PAD_ZQ, ADMAFCICLK, AIBPMUAFIFMFPDACK, AIBPMUAFIFMLPDACK, DDRCEXTREFRESHRANK0REQ, DDRCEXTREFRESHRANK1REQ, DDRCREFRESHPLCLK, DPAUXDATAIN, DPEXTERNALCUSTOMEVENT1, DPEXTERNALCUSTOMEVENT2, DPEXTERNALVSYNCEVENT, DPHOTPLUGDETECT, DPLIVEGFXALPHAIN, DPLIVEGFXPIXEL1IN, DPLIVEVIDEOINDE, DPLIVEVIDEOINHSYNC, DPLIVEVIDEOINPIXEL1, DPLIVEVIDEOINVSYNC, DPMAXISMIXEDAUDIOTREADY, DPSAXISAUDIOCLK, DPSAXISAUDIOTDATA
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, DPSAXISAUDIOTID, DPSAXISAUDIOTVALID, DPVIDEOINCLK, EMIOCAN0PHYRX, EMIOCAN1PHYRX, EMIOENET0DMATXSTATUSTOG, EMIOENET0EXTINTIN, EMIOENET0GMIICOL, EMIOENET0GMIICRS, EMIOENET0GMIIRXCLK, EMIOENET0GMIIRXD, EMIOENET0GMIIRXDV, EMIOENET0GMIIRXER, EMIOENET0GMIITXCLK, EMIOENET0MDIOI, EMIOENET0RXWOVERFLOW, EMIOENET0TXRCONTROL, EMIOENET0TXRDATA, EMIOENET0TXRDATARDY, EMIOENET0TXREOP, EMIOENET0TXRERR
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, EMIOENET0TXRFLUSHED, EMIOENET0TXRSOP, EMIOENET0TXRUNDERFLOW, EMIOENET0TXRVALID, EMIOENET1DMATXSTATUSTOG, EMIOENET1EXTINTIN, EMIOENET1GMIICOL, EMIOENET1GMIICRS, EMIOENET1GMIIRXCLK, EMIOENET1GMIIRXD, EMIOENET1GMIIRXDV, EMIOENET1GMIIRXER, EMIOENET1GMIITXCLK, EMIOENET1MDIOI, EMIOENET1RXWOVERFLOW, EMIOENET1TXRCONTROL, EMIOENET1TXRDATA, EMIOENET1TXRDATARDY, EMIOENET1TXREOP, EMIOENET1TXRERR, EMIOENET1TXRFLUSHED
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, EMIOENET1TXRSOP, EMIOENET1TXRUNDERFLOW, EMIOENET1TXRVALID, EMIOENET2DMATXSTATUSTOG, EMIOENET2EXTINTIN, EMIOENET2GMIICOL, EMIOENET2GMIICRS, EMIOENET2GMIIRXCLK, EMIOENET2GMIIRXD, EMIOENET2GMIIRXDV, EMIOENET2GMIIRXER, EMIOENET2GMIITXCLK, EMIOENET2MDIOI, EMIOENET2RXWOVERFLOW, EMIOENET2TXRCONTROL, EMIOENET2TXRDATA, EMIOENET2TXRDATARDY, EMIOENET2TXREOP, EMIOENET2TXRERR, EMIOENET2TXRFLUSHED, EMIOENET2TXRSOP
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, EMIOENET2TXRUNDERFLOW, EMIOENET2TXRVALID, EMIOENET3DMATXSTATUSTOG, EMIOENET3EXTINTIN, EMIOENET3GMIICOL, EMIOENET3GMIICRS, EMIOENET3GMIIRXCLK, EMIOENET3GMIIRXD, EMIOENET3GMIIRXDV, EMIOENET3GMIIRXER, EMIOENET3GMIITXCLK, EMIOENET3MDIOI, EMIOENET3RXWOVERFLOW, EMIOENET3TXRCONTROL, EMIOENET3TXRDATA, EMIOENET3TXRDATARDY, EMIOENET3TXREOP, EMIOENET3TXRERR, EMIOENET3TXRFLUSHED, EMIOENET3TXRSOP, EMIOENET3TXRUNDERFLOW
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, EMIOENET3TXRVALID, EMIOENETTSUCLK, EMIOGEM0TSUINCCTRL, EMIOGEM1TSUINCCTRL, EMIOGEM2TSUINCCTRL, EMIOGEM3TSUINCCTRL, EMIOGPIOI, EMIOHUBPORTOVERCRNTUSB20, EMIOHUBPORTOVERCRNTUSB21, EMIOHUBPORTOVERCRNTUSB30, EMIOHUBPORTOVERCRNTUSB31, EMIOI2C0SCLI, EMIOI2C0SDAI, EMIOI2C1SCLI, EMIOI2C1SDAI, EMIOSDIO0CDN, EMIOSDIO0CMDIN, EMIOSDIO0DATAIN, EMIOSDIO0FBCLKIN, EMIOSDIO0WP, EMIOSDIO1CDN
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, EMIOSDIO1CMDIN, EMIOSDIO1DATAIN, EMIOSDIO1FBCLKIN, EMIOSDIO1WP, EMIOSPI0MI, EMIOSPI0SCLKI, EMIOSPI0SI, EMIOSPI0SSIN, EMIOSPI1MI, EMIOSPI1SCLKI, EMIOSPI1SI, EMIOSPI1SSIN, EMIOTTC0CLKI, EMIOTTC1CLKI, EMIOTTC2CLKI, EMIOTTC3CLKI, EMIOUART0CTSN, EMIOUART0DCDN, EMIOUART0DSRN, EMIOUART0RIN, EMIOUART0RX
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, EMIOUART1CTSN, EMIOUART1DCDN, EMIOUART1DSRN, EMIOUART1RIN, EMIOUART1RX, EMIOWDT0CLKI, EMIOWDT1CLKI, FMIOGEM0FIFORXCLKFROMPL, FMIOGEM0FIFOTXCLKFROMPL, FMIOGEM0SIGNALDETECT, FMIOGEM1FIFORXCLKFROMPL, FMIOGEM1FIFOTXCLKFROMPL, FMIOGEM1SIGNALDETECT, FMIOGEM2FIFORXCLKFROMPL, FMIOGEM2FIFOTXCLKFROMPL, FMIOGEM2SIGNALDETECT, FMIOGEM3FIFORXCLKFROMPL, FMIOGEM3FIFOTXCLKFROMPL, FMIOGEM3SIGNALDETECT, FMIOGEMTSUCLKFROMPL, FTMGPI
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, GDMAFCICLK, MAXIGP0ACLK, MAXIGP0ARREADY, MAXIGP0AWREADY, MAXIGP0BID, MAXIGP0BRESP, MAXIGP0BVALID, MAXIGP0RDATA, MAXIGP0RID, MAXIGP0RLAST, MAXIGP0RRESP, MAXIGP0RVALID, MAXIGP0WREADY, MAXIGP1ACLK, MAXIGP1ARREADY, MAXIGP1AWREADY, MAXIGP1BID, MAXIGP1BRESP, MAXIGP1BVALID, MAXIGP1RDATA, MAXIGP1RID
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, MAXIGP1RLAST, MAXIGP1RRESP, MAXIGP1RVALID, MAXIGP1WREADY, MAXIGP2ACLK, MAXIGP2ARREADY, MAXIGP2AWREADY, MAXIGP2BID, MAXIGP2BRESP, MAXIGP2BVALID, MAXIGP2RDATA, MAXIGP2RID, MAXIGP2RLAST, MAXIGP2RRESP, MAXIGP2RVALID, MAXIGP2WREADY, NFIQ0LPDRPU, NFIQ1LPDRPU, NIRQ0LPDRPU, NIRQ1LPDRPU, PL2ADMACVLD
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, PL2ADMATACK, PL2GDMACVLD, PL2GDMATACK, PLACECLK, PLACPINACT, PLFPGASTOP, PLLAUXREFCLKFPD, PLLAUXREFCLKLPD, PLPMUGPI, PLPSAPUGICFIQ, PLPSAPUGICIRQ, PLPSEVENTI, PLPSIRQ0, PLPSIRQ1, PLPSTRACECLK, PLPSTRIGACK, PLPSTRIGGER, PMUERRORFROMPL, PSS_ALTO_CORE_PAD_MGTRXN0IN, PSS_ALTO_CORE_PAD_MGTRXN1IN, PSS_ALTO_CORE_PAD_MGTRXN2IN
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, PSS_ALTO_CORE_PAD_MGTRXN3IN, PSS_ALTO_CORE_PAD_MGTRXP0IN, PSS_ALTO_CORE_PAD_MGTRXP1IN, PSS_ALTO_CORE_PAD_MGTRXP2IN, PSS_ALTO_CORE_PAD_MGTRXP3IN, PSS_ALTO_CORE_PAD_PADI, PSS_ALTO_CORE_PAD_REFN0IN, PSS_ALTO_CORE_PAD_REFN1IN, PSS_ALTO_CORE_PAD_REFN2IN, PSS_ALTO_CORE_PAD_REFN3IN, PSS_ALTO_CORE_PAD_REFP0IN, PSS_ALTO_CORE_PAD_REFP1IN, PSS_ALTO_CORE_PAD_REFP2IN, PSS_ALTO_CORE_PAD_REFP3IN, RPUEVENTI0, RPUEVENTI1, SACEFPDACREADY, SACEFPDARADDR, SACEFPDARBAR, SACEFPDARBURST, SACEFPDARCACHE
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, SACEFPDARDOMAIN, SACEFPDARID, SACEFPDARLEN, SACEFPDARLOCK, SACEFPDARPROT, SACEFPDARQOS, SACEFPDARREGION, SACEFPDARSIZE, SACEFPDARSNOOP, SACEFPDARUSER, SACEFPDARVALID, SACEFPDAWADDR, SACEFPDAWBAR, SACEFPDAWBURST, SACEFPDAWCACHE, SACEFPDAWDOMAIN, SACEFPDAWID, SACEFPDAWLEN, SACEFPDAWLOCK, SACEFPDAWPROT, SACEFPDAWQOS
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, SACEFPDAWREGION, SACEFPDAWSIZE, SACEFPDAWSNOOP, SACEFPDAWUSER, SACEFPDAWVALID, SACEFPDBREADY, SACEFPDCDDATA, SACEFPDCDLAST, SACEFPDCDVALID, SACEFPDCRRESP, SACEFPDCRVALID, SACEFPDRACK, SACEFPDRREADY, SACEFPDWACK, SACEFPDWDATA, SACEFPDWLAST, SACEFPDWSTRB, SACEFPDWUSER, SACEFPDWVALID, SAXIACPACLK, SAXIACPARADDR
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, SAXIACPARBURST, SAXIACPARCACHE, SAXIACPARID, SAXIACPARLEN, SAXIACPARLOCK, SAXIACPARPROT, SAXIACPARQOS, SAXIACPARSIZE, SAXIACPARUSER, SAXIACPARVALID, SAXIACPAWADDR, SAXIACPAWBURST, SAXIACPAWCACHE, SAXIACPAWID, SAXIACPAWLEN, SAXIACPAWLOCK, SAXIACPAWPROT, SAXIACPAWQOS, SAXIACPAWSIZE, SAXIACPAWUSER, SAXIACPAWVALID
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, SAXIACPBREADY, SAXIACPRREADY, SAXIACPWDATA, SAXIACPWLAST, SAXIACPWSTRB, SAXIACPWVALID, SAXIGP0ARADDR, SAXIGP0ARBURST, SAXIGP0ARCACHE, SAXIGP0ARID, SAXIGP0ARLEN, SAXIGP0ARLOCK, SAXIGP0ARPROT, SAXIGP0ARQOS, SAXIGP0ARSIZE, SAXIGP0ARUSER, SAXIGP0ARVALID, SAXIGP0AWADDR, SAXIGP0AWBURST, SAXIGP0AWCACHE, SAXIGP0AWID
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, SAXIGP0AWLEN, SAXIGP0AWLOCK, SAXIGP0AWPROT, SAXIGP0AWQOS, SAXIGP0AWSIZE, SAXIGP0AWUSER, SAXIGP0AWVALID, SAXIGP0BREADY, SAXIGP0RCLK, SAXIGP0RREADY, SAXIGP0WCLK, SAXIGP0WDATA, SAXIGP0WLAST, SAXIGP0WSTRB, SAXIGP0WVALID, SAXIGP1ARADDR, SAXIGP1ARBURST, SAXIGP1ARCACHE, SAXIGP1ARID, SAXIGP1ARLEN, SAXIGP1ARLOCK
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, SAXIGP1ARPROT, SAXIGP1ARQOS, SAXIGP1ARSIZE, SAXIGP1ARUSER, SAXIGP1ARVALID, SAXIGP1AWADDR, SAXIGP1AWBURST, SAXIGP1AWCACHE, SAXIGP1AWID, SAXIGP1AWLEN, SAXIGP1AWLOCK, SAXIGP1AWPROT, SAXIGP1AWQOS, SAXIGP1AWSIZE, SAXIGP1AWUSER, SAXIGP1AWVALID, SAXIGP1BREADY, SAXIGP1RCLK, SAXIGP1RREADY, SAXIGP1WCLK, SAXIGP1WDATA
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, SAXIGP1WLAST, SAXIGP1WSTRB, SAXIGP1WVALID, SAXIGP2ARADDR, SAXIGP2ARBURST, SAXIGP2ARCACHE, SAXIGP2ARID, SAXIGP2ARLEN, SAXIGP2ARLOCK, SAXIGP2ARPROT, SAXIGP2ARQOS, SAXIGP2ARSIZE, SAXIGP2ARUSER, SAXIGP2ARVALID, SAXIGP2AWADDR, SAXIGP2AWBURST, SAXIGP2AWCACHE, SAXIGP2AWID, SAXIGP2AWLEN, SAXIGP2AWLOCK, SAXIGP2AWPROT
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, SAXIGP2AWQOS, SAXIGP2AWSIZE, SAXIGP2AWUSER, SAXIGP2AWVALID, SAXIGP2BREADY, SAXIGP2RCLK, SAXIGP2RREADY, SAXIGP2WCLK, SAXIGP2WDATA, SAXIGP2WLAST, SAXIGP2WSTRB, SAXIGP2WVALID, SAXIGP3ARADDR, SAXIGP3ARBURST, SAXIGP3ARCACHE, SAXIGP3ARID, SAXIGP3ARLEN, SAXIGP3ARLOCK, SAXIGP3ARPROT, SAXIGP3ARQOS, SAXIGP3ARSIZE
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, SAXIGP3ARUSER, SAXIGP3ARVALID, SAXIGP3AWADDR, SAXIGP3AWBURST, SAXIGP3AWCACHE, SAXIGP3AWID, SAXIGP3AWLEN, SAXIGP3AWLOCK, SAXIGP3AWPROT, SAXIGP3AWQOS, SAXIGP3AWSIZE, SAXIGP3AWUSER, SAXIGP3AWVALID, SAXIGP3BREADY, SAXIGP3RCLK, SAXIGP3RREADY, SAXIGP3WCLK, SAXIGP3WDATA, SAXIGP3WLAST, SAXIGP3WSTRB, SAXIGP3WVALID
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, SAXIGP4ARADDR, SAXIGP4ARBURST, SAXIGP4ARCACHE, SAXIGP4ARID, SAXIGP4ARLEN, SAXIGP4ARLOCK, SAXIGP4ARPROT, SAXIGP4ARQOS, SAXIGP4ARSIZE, SAXIGP4ARUSER, SAXIGP4ARVALID, SAXIGP4AWADDR, SAXIGP4AWBURST, SAXIGP4AWCACHE, SAXIGP4AWID, SAXIGP4AWLEN, SAXIGP4AWLOCK, SAXIGP4AWPROT, SAXIGP4AWQOS, SAXIGP4AWSIZE, SAXIGP4AWUSER
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, SAXIGP4AWVALID, SAXIGP4BREADY, SAXIGP4RCLK, SAXIGP4RREADY, SAXIGP4WCLK, SAXIGP4WDATA, SAXIGP4WLAST, SAXIGP4WSTRB, SAXIGP4WVALID, SAXIGP5ARADDR, SAXIGP5ARBURST, SAXIGP5ARCACHE, SAXIGP5ARID, SAXIGP5ARLEN, SAXIGP5ARLOCK, SAXIGP5ARPROT, SAXIGP5ARQOS, SAXIGP5ARSIZE, SAXIGP5ARUSER, SAXIGP5ARVALID, SAXIGP5AWADDR
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, SAXIGP5AWBURST, SAXIGP5AWCACHE, SAXIGP5AWID, SAXIGP5AWLEN, SAXIGP5AWLOCK, SAXIGP5AWPROT, SAXIGP5AWQOS, SAXIGP5AWSIZE, SAXIGP5AWUSER, SAXIGP5AWVALID, SAXIGP5BREADY, SAXIGP5RCLK, SAXIGP5RREADY, SAXIGP5WCLK, SAXIGP5WDATA, SAXIGP5WLAST, SAXIGP5WSTRB, SAXIGP5WVALID, SAXIGP6ARADDR, SAXIGP6ARBURST, SAXIGP6ARCACHE
|
|
, SAXIGP6ARID, SAXIGP6ARLEN, SAXIGP6ARLOCK, SAXIGP6ARPROT, SAXIGP6ARQOS, SAXIGP6ARSIZE, SAXIGP6ARUSER, SAXIGP6ARVALID, SAXIGP6AWADDR, SAXIGP6AWBURST, SAXIGP6AWCACHE, SAXIGP6AWID, SAXIGP6AWLEN, SAXIGP6AWLOCK, SAXIGP6AWPROT, SAXIGP6AWQOS, SAXIGP6AWSIZE, SAXIGP6AWUSER, SAXIGP6AWVALID, SAXIGP6BREADY, SAXIGP6RCLK
|
|
, SAXIGP6RREADY, SAXIGP6WCLK, SAXIGP6WDATA, SAXIGP6WLAST, SAXIGP6WSTRB, SAXIGP6WVALID, STMEVENT);
|
|
output [7:0] ADMA2PLCACK;
|
|
output [7:0] ADMA2PLTVLD;
|
|
output DPAUDIOREFCLK;
|
|
output DPAUXDATAOEN;
|
|
output DPAUXDATAOUT;
|
|
output DPLIVEVIDEODEOUT;
|
|
output [31:0] DPMAXISMIXEDAUDIOTDATA;
|
|
output DPMAXISMIXEDAUDIOTID;
|
|
output DPMAXISMIXEDAUDIOTVALID;
|
|
output DPSAXISAUDIOTREADY;
|
|
output DPVIDEOOUTHSYNC;
|
|
output [35:0] DPVIDEOOUTPIXEL1;
|
|
output DPVIDEOOUTVSYNC;
|
|
output DPVIDEOREFCLK;
|
|
output EMIOCAN0PHYTX;
|
|
output EMIOCAN1PHYTX;
|
|
output [1:0] EMIOENET0DMABUSWIDTH;
|
|
output EMIOENET0DMATXENDTOG;
|
|
output [93:0] EMIOENET0GEMTSUTIMERCNT;
|
|
output [7:0] EMIOENET0GMIITXD;
|
|
output EMIOENET0GMIITXEN;
|
|
output EMIOENET0GMIITXER;
|
|
output EMIOENET0MDIOMDC;
|
|
output EMIOENET0MDIOO;
|
|
output EMIOENET0MDIOTN;
|
|
output [7:0] EMIOENET0RXWDATA;
|
|
output EMIOENET0RXWEOP;
|
|
output EMIOENET0RXWERR;
|
|
output EMIOENET0RXWFLUSH;
|
|
output EMIOENET0RXWSOP;
|
|
output [44:0] EMIOENET0RXWSTATUS;
|
|
output EMIOENET0RXWWR;
|
|
output [2:0] EMIOENET0SPEEDMODE;
|
|
output EMIOENET0TXRRD;
|
|
output [3:0] EMIOENET0TXRSTATUS;
|
|
output [1:0] EMIOENET1DMABUSWIDTH;
|
|
output EMIOENET1DMATXENDTOG;
|
|
output [7:0] EMIOENET1GMIITXD;
|
|
output EMIOENET1GMIITXEN;
|
|
output EMIOENET1GMIITXER;
|
|
output EMIOENET1MDIOMDC;
|
|
output EMIOENET1MDIOO;
|
|
output EMIOENET1MDIOTN;
|
|
output [7:0] EMIOENET1RXWDATA;
|
|
output EMIOENET1RXWEOP;
|
|
output EMIOENET1RXWERR;
|
|
output EMIOENET1RXWFLUSH;
|
|
output EMIOENET1RXWSOP;
|
|
output [44:0] EMIOENET1RXWSTATUS;
|
|
output EMIOENET1RXWWR;
|
|
output [2:0] EMIOENET1SPEEDMODE;
|
|
output EMIOENET1TXRRD;
|
|
output [3:0] EMIOENET1TXRSTATUS;
|
|
output [1:0] EMIOENET2DMABUSWIDTH;
|
|
output EMIOENET2DMATXENDTOG;
|
|
output [7:0] EMIOENET2GMIITXD;
|
|
output EMIOENET2GMIITXEN;
|
|
output EMIOENET2GMIITXER;
|
|
output EMIOENET2MDIOMDC;
|
|
output EMIOENET2MDIOO;
|
|
output EMIOENET2MDIOTN;
|
|
output [7:0] EMIOENET2RXWDATA;
|
|
output EMIOENET2RXWEOP;
|
|
output EMIOENET2RXWERR;
|
|
output EMIOENET2RXWFLUSH;
|
|
output EMIOENET2RXWSOP;
|
|
output [44:0] EMIOENET2RXWSTATUS;
|
|
output EMIOENET2RXWWR;
|
|
output [2:0] EMIOENET2SPEEDMODE;
|
|
output EMIOENET2TXRRD;
|
|
output [3:0] EMIOENET2TXRSTATUS;
|
|
output [1:0] EMIOENET3DMABUSWIDTH;
|
|
output EMIOENET3DMATXENDTOG;
|
|
output [7:0] EMIOENET3GMIITXD;
|
|
output EMIOENET3GMIITXEN;
|
|
output EMIOENET3GMIITXER;
|
|
output EMIOENET3MDIOMDC;
|
|
output EMIOENET3MDIOO;
|
|
output EMIOENET3MDIOTN;
|
|
output [7:0] EMIOENET3RXWDATA;
|
|
output EMIOENET3RXWEOP;
|
|
output EMIOENET3RXWERR;
|
|
output EMIOENET3RXWFLUSH;
|
|
output EMIOENET3RXWSOP;
|
|
output [44:0] EMIOENET3RXWSTATUS;
|
|
output EMIOENET3RXWWR;
|
|
output [2:0] EMIOENET3SPEEDMODE;
|
|
output EMIOENET3TXRRD;
|
|
output [3:0] EMIOENET3TXRSTATUS;
|
|
output EMIOGEM0DELAYREQRX;
|
|
output EMIOGEM0DELAYREQTX;
|
|
output EMIOGEM0PDELAYREQRX;
|
|
output EMIOGEM0PDELAYREQTX;
|
|
output EMIOGEM0PDELAYRESPRX;
|
|
output EMIOGEM0PDELAYRESPTX;
|
|
output EMIOGEM0RXSOF;
|
|
output EMIOGEM0SYNCFRAMERX;
|
|
output EMIOGEM0SYNCFRAMETX;
|
|
output EMIOGEM0TSUTIMERCMPVAL;
|
|
output EMIOGEM0TXRFIXEDLAT;
|
|
output EMIOGEM0TXSOF;
|
|
output EMIOGEM1DELAYREQRX;
|
|
output EMIOGEM1DELAYREQTX;
|
|
output EMIOGEM1PDELAYREQRX;
|
|
output EMIOGEM1PDELAYREQTX;
|
|
output EMIOGEM1PDELAYRESPRX;
|
|
output EMIOGEM1PDELAYRESPTX;
|
|
output EMIOGEM1RXSOF;
|
|
output EMIOGEM1SYNCFRAMERX;
|
|
output EMIOGEM1SYNCFRAMETX;
|
|
output EMIOGEM1TSUTIMERCMPVAL;
|
|
output EMIOGEM1TXRFIXEDLAT;
|
|
output EMIOGEM1TXSOF;
|
|
output EMIOGEM2DELAYREQRX;
|
|
output EMIOGEM2DELAYREQTX;
|
|
output EMIOGEM2PDELAYREQRX;
|
|
output EMIOGEM2PDELAYREQTX;
|
|
output EMIOGEM2PDELAYRESPRX;
|
|
output EMIOGEM2PDELAYRESPTX;
|
|
output EMIOGEM2RXSOF;
|
|
output EMIOGEM2SYNCFRAMERX;
|
|
output EMIOGEM2SYNCFRAMETX;
|
|
output EMIOGEM2TSUTIMERCMPVAL;
|
|
output EMIOGEM2TXRFIXEDLAT;
|
|
output EMIOGEM2TXSOF;
|
|
output EMIOGEM3DELAYREQRX;
|
|
output EMIOGEM3DELAYREQTX;
|
|
output EMIOGEM3PDELAYREQRX;
|
|
output EMIOGEM3PDELAYREQTX;
|
|
output EMIOGEM3PDELAYRESPRX;
|
|
output EMIOGEM3PDELAYRESPTX;
|
|
output EMIOGEM3RXSOF;
|
|
output EMIOGEM3SYNCFRAMERX;
|
|
output EMIOGEM3SYNCFRAMETX;
|
|
output EMIOGEM3TSUTIMERCMPVAL;
|
|
output EMIOGEM3TXRFIXEDLAT;
|
|
output EMIOGEM3TXSOF;
|
|
output [95:0] EMIOGPIOO;
|
|
output [95:0] EMIOGPIOTN;
|
|
output EMIOI2C0SCLO;
|
|
output EMIOI2C0SCLTN;
|
|
output EMIOI2C0SDAO;
|
|
output EMIOI2C0SDATN;
|
|
output EMIOI2C1SCLO;
|
|
output EMIOI2C1SCLTN;
|
|
output EMIOI2C1SDAO;
|
|
output EMIOI2C1SDATN;
|
|
output EMIOSDIO0BUSPOWER;
|
|
output [2:0] EMIOSDIO0BUSVOLT;
|
|
output EMIOSDIO0CLKOUT;
|
|
output EMIOSDIO0CMDENA;
|
|
output EMIOSDIO0CMDOUT;
|
|
output [7:0] EMIOSDIO0DATAENA;
|
|
output [7:0] EMIOSDIO0DATAOUT;
|
|
output EMIOSDIO0LEDCONTROL;
|
|
output EMIOSDIO1BUSPOWER;
|
|
output [2:0] EMIOSDIO1BUSVOLT;
|
|
output EMIOSDIO1CLKOUT;
|
|
output EMIOSDIO1CMDENA;
|
|
output EMIOSDIO1CMDOUT;
|
|
output [7:0] EMIOSDIO1DATAENA;
|
|
output [7:0] EMIOSDIO1DATAOUT;
|
|
output EMIOSDIO1LEDCONTROL;
|
|
output EMIOSPI0MO;
|
|
output EMIOSPI0MOTN;
|
|
output EMIOSPI0SCLKO;
|
|
output EMIOSPI0SCLKTN;
|
|
output EMIOSPI0SO;
|
|
output EMIOSPI0SSNTN;
|
|
output [2:0] EMIOSPI0SSON;
|
|
output EMIOSPI0STN;
|
|
output EMIOSPI1MO;
|
|
output EMIOSPI1MOTN;
|
|
output EMIOSPI1SCLKO;
|
|
output EMIOSPI1SCLKTN;
|
|
output EMIOSPI1SO;
|
|
output EMIOSPI1SSNTN;
|
|
output [2:0] EMIOSPI1SSON;
|
|
output EMIOSPI1STN;
|
|
output [2:0] EMIOTTC0WAVEO;
|
|
output [2:0] EMIOTTC1WAVEO;
|
|
output [2:0] EMIOTTC2WAVEO;
|
|
output [2:0] EMIOTTC3WAVEO;
|
|
output EMIOU2DSPORTVBUSCTRLUSB30;
|
|
output EMIOU2DSPORTVBUSCTRLUSB31;
|
|
output EMIOU3DSPORTVBUSCTRLUSB30;
|
|
output EMIOU3DSPORTVBUSCTRLUSB31;
|
|
output EMIOUART0DTRN;
|
|
output EMIOUART0RTSN;
|
|
output EMIOUART0TX;
|
|
output EMIOUART1DTRN;
|
|
output EMIOUART1RTSN;
|
|
output EMIOUART1TX;
|
|
output EMIOWDT0RSTO;
|
|
output EMIOWDT1RSTO;
|
|
output FMIOGEM0FIFORXCLKTOPLBUFG;
|
|
output FMIOGEM0FIFOTXCLKTOPLBUFG;
|
|
output FMIOGEM1FIFORXCLKTOPLBUFG;
|
|
output FMIOGEM1FIFOTXCLKTOPLBUFG;
|
|
output FMIOGEM2FIFORXCLKTOPLBUFG;
|
|
output FMIOGEM2FIFOTXCLKTOPLBUFG;
|
|
output FMIOGEM3FIFORXCLKTOPLBUFG;
|
|
output FMIOGEM3FIFOTXCLKTOPLBUFG;
|
|
output FMIOGEMTSUCLKTOPLBUFG;
|
|
output [31:0] FTMGPO;
|
|
output [7:0] GDMA2PLCACK;
|
|
output [7:0] GDMA2PLTVLD;
|
|
output [39:0] MAXIGP0ARADDR;
|
|
output [1:0] MAXIGP0ARBURST;
|
|
output [3:0] MAXIGP0ARCACHE;
|
|
output [15:0] MAXIGP0ARID;
|
|
output [7:0] MAXIGP0ARLEN;
|
|
output MAXIGP0ARLOCK;
|
|
output [2:0] MAXIGP0ARPROT;
|
|
output [3:0] MAXIGP0ARQOS;
|
|
output [2:0] MAXIGP0ARSIZE;
|
|
output [15:0] MAXIGP0ARUSER;
|
|
output MAXIGP0ARVALID;
|
|
output [39:0] MAXIGP0AWADDR;
|
|
output [1:0] MAXIGP0AWBURST;
|
|
output [3:0] MAXIGP0AWCACHE;
|
|
output [15:0] MAXIGP0AWID;
|
|
output [7:0] MAXIGP0AWLEN;
|
|
output MAXIGP0AWLOCK;
|
|
output [2:0] MAXIGP0AWPROT;
|
|
output [3:0] MAXIGP0AWQOS;
|
|
output [2:0] MAXIGP0AWSIZE;
|
|
output [15:0] MAXIGP0AWUSER;
|
|
output MAXIGP0AWVALID;
|
|
output MAXIGP0BREADY;
|
|
output MAXIGP0RREADY;
|
|
output [127:0] MAXIGP0WDATA;
|
|
output MAXIGP0WLAST;
|
|
output [15:0] MAXIGP0WSTRB;
|
|
output MAXIGP0WVALID;
|
|
output [39:0] MAXIGP1ARADDR;
|
|
output [1:0] MAXIGP1ARBURST;
|
|
output [3:0] MAXIGP1ARCACHE;
|
|
output [15:0] MAXIGP1ARID;
|
|
output [7:0] MAXIGP1ARLEN;
|
|
output MAXIGP1ARLOCK;
|
|
output [2:0] MAXIGP1ARPROT;
|
|
output [3:0] MAXIGP1ARQOS;
|
|
output [2:0] MAXIGP1ARSIZE;
|
|
output [15:0] MAXIGP1ARUSER;
|
|
output MAXIGP1ARVALID;
|
|
output [39:0] MAXIGP1AWADDR;
|
|
output [1:0] MAXIGP1AWBURST;
|
|
output [3:0] MAXIGP1AWCACHE;
|
|
output [15:0] MAXIGP1AWID;
|
|
output [7:0] MAXIGP1AWLEN;
|
|
output MAXIGP1AWLOCK;
|
|
output [2:0] MAXIGP1AWPROT;
|
|
output [3:0] MAXIGP1AWQOS;
|
|
output [2:0] MAXIGP1AWSIZE;
|
|
output [15:0] MAXIGP1AWUSER;
|
|
output MAXIGP1AWVALID;
|
|
output MAXIGP1BREADY;
|
|
output MAXIGP1RREADY;
|
|
output [127:0] MAXIGP1WDATA;
|
|
output MAXIGP1WLAST;
|
|
output [15:0] MAXIGP1WSTRB;
|
|
output MAXIGP1WVALID;
|
|
output [39:0] MAXIGP2ARADDR;
|
|
output [1:0] MAXIGP2ARBURST;
|
|
output [3:0] MAXIGP2ARCACHE;
|
|
output [15:0] MAXIGP2ARID;
|
|
output [7:0] MAXIGP2ARLEN;
|
|
output MAXIGP2ARLOCK;
|
|
output [2:0] MAXIGP2ARPROT;
|
|
output [3:0] MAXIGP2ARQOS;
|
|
output [2:0] MAXIGP2ARSIZE;
|
|
output [15:0] MAXIGP2ARUSER;
|
|
output MAXIGP2ARVALID;
|
|
output [39:0] MAXIGP2AWADDR;
|
|
output [1:0] MAXIGP2AWBURST;
|
|
output [3:0] MAXIGP2AWCACHE;
|
|
output [15:0] MAXIGP2AWID;
|
|
output [7:0] MAXIGP2AWLEN;
|
|
output MAXIGP2AWLOCK;
|
|
output [2:0] MAXIGP2AWPROT;
|
|
output [3:0] MAXIGP2AWQOS;
|
|
output [2:0] MAXIGP2AWSIZE;
|
|
output [15:0] MAXIGP2AWUSER;
|
|
output MAXIGP2AWVALID;
|
|
output MAXIGP2BREADY;
|
|
output MAXIGP2RREADY;
|
|
output [127:0] MAXIGP2WDATA;
|
|
output MAXIGP2WLAST;
|
|
output [15:0] MAXIGP2WSTRB;
|
|
output MAXIGP2WVALID;
|
|
output OSCRTCCLK;
|
|
output [3:0] PLCLK;
|
|
output PMUAIBAFIFMFPDREQ;
|
|
output PMUAIBAFIFMLPDREQ;
|
|
output [46:0] PMUERRORTOPL;
|
|
output [31:0] PMUPLGPO;
|
|
output PSPLEVENTO;
|
|
output [63:0] PSPLIRQFPD;
|
|
output [99:0] PSPLIRQLPD;
|
|
output [3:0] PSPLSTANDBYWFE;
|
|
output [3:0] PSPLSTANDBYWFI;
|
|
output PSPLTRACECTL;
|
|
output [31:0] PSPLTRACEDATA;
|
|
output [3:0] PSPLTRIGACK;
|
|
output [3:0] PSPLTRIGGER;
|
|
output PSS_ALTO_CORE_PAD_MGTTXN0OUT;
|
|
output PSS_ALTO_CORE_PAD_MGTTXN1OUT;
|
|
output PSS_ALTO_CORE_PAD_MGTTXN2OUT;
|
|
output PSS_ALTO_CORE_PAD_MGTTXN3OUT;
|
|
output PSS_ALTO_CORE_PAD_MGTTXP0OUT;
|
|
output PSS_ALTO_CORE_PAD_MGTTXP1OUT;
|
|
output PSS_ALTO_CORE_PAD_MGTTXP2OUT;
|
|
output PSS_ALTO_CORE_PAD_MGTTXP3OUT;
|
|
output PSS_ALTO_CORE_PAD_PADO;
|
|
output RPUEVENTO0;
|
|
output RPUEVENTO1;
|
|
output [43:0] SACEFPDACADDR;
|
|
output [2:0] SACEFPDACPROT;
|
|
output [3:0] SACEFPDACSNOOP;
|
|
output SACEFPDACVALID;
|
|
output SACEFPDARREADY;
|
|
output SACEFPDAWREADY;
|
|
output [5:0] SACEFPDBID;
|
|
output [1:0] SACEFPDBRESP;
|
|
output SACEFPDBUSER;
|
|
output SACEFPDBVALID;
|
|
output SACEFPDCDREADY;
|
|
output SACEFPDCRREADY;
|
|
output [127:0] SACEFPDRDATA;
|
|
output [5:0] SACEFPDRID;
|
|
output SACEFPDRLAST;
|
|
output [3:0] SACEFPDRRESP;
|
|
output SACEFPDRUSER;
|
|
output SACEFPDRVALID;
|
|
output SACEFPDWREADY;
|
|
output SAXIACPARREADY;
|
|
output SAXIACPAWREADY;
|
|
output [4:0] SAXIACPBID;
|
|
output [1:0] SAXIACPBRESP;
|
|
output SAXIACPBVALID;
|
|
output [127:0] SAXIACPRDATA;
|
|
output [4:0] SAXIACPRID;
|
|
output SAXIACPRLAST;
|
|
output [1:0] SAXIACPRRESP;
|
|
output SAXIACPRVALID;
|
|
output SAXIACPWREADY;
|
|
output SAXIGP0ARREADY;
|
|
output SAXIGP0AWREADY;
|
|
output [5:0] SAXIGP0BID;
|
|
output [1:0] SAXIGP0BRESP;
|
|
output SAXIGP0BVALID;
|
|
output [3:0] SAXIGP0RACOUNT;
|
|
output [7:0] SAXIGP0RCOUNT;
|
|
output [127:0] SAXIGP0RDATA;
|
|
output [5:0] SAXIGP0RID;
|
|
output SAXIGP0RLAST;
|
|
output [1:0] SAXIGP0RRESP;
|
|
output SAXIGP0RVALID;
|
|
output [3:0] SAXIGP0WACOUNT;
|
|
output [7:0] SAXIGP0WCOUNT;
|
|
output SAXIGP0WREADY;
|
|
output SAXIGP1ARREADY;
|
|
output SAXIGP1AWREADY;
|
|
output [5:0] SAXIGP1BID;
|
|
output [1:0] SAXIGP1BRESP;
|
|
output SAXIGP1BVALID;
|
|
output [3:0] SAXIGP1RACOUNT;
|
|
output [7:0] SAXIGP1RCOUNT;
|
|
output [127:0] SAXIGP1RDATA;
|
|
output [5:0] SAXIGP1RID;
|
|
output SAXIGP1RLAST;
|
|
output [1:0] SAXIGP1RRESP;
|
|
output SAXIGP1RVALID;
|
|
output [3:0] SAXIGP1WACOUNT;
|
|
output [7:0] SAXIGP1WCOUNT;
|
|
output SAXIGP1WREADY;
|
|
output SAXIGP2ARREADY;
|
|
output SAXIGP2AWREADY;
|
|
output [5:0] SAXIGP2BID;
|
|
output [1:0] SAXIGP2BRESP;
|
|
output SAXIGP2BVALID;
|
|
output [3:0] SAXIGP2RACOUNT;
|
|
output [7:0] SAXIGP2RCOUNT;
|
|
output [127:0] SAXIGP2RDATA;
|
|
output [5:0] SAXIGP2RID;
|
|
output SAXIGP2RLAST;
|
|
output [1:0] SAXIGP2RRESP;
|
|
output SAXIGP2RVALID;
|
|
output [3:0] SAXIGP2WACOUNT;
|
|
output [7:0] SAXIGP2WCOUNT;
|
|
output SAXIGP2WREADY;
|
|
output SAXIGP3ARREADY;
|
|
output SAXIGP3AWREADY;
|
|
output [5:0] SAXIGP3BID;
|
|
output [1:0] SAXIGP3BRESP;
|
|
output SAXIGP3BVALID;
|
|
output [3:0] SAXIGP3RACOUNT;
|
|
output [7:0] SAXIGP3RCOUNT;
|
|
output [127:0] SAXIGP3RDATA;
|
|
output [5:0] SAXIGP3RID;
|
|
output SAXIGP3RLAST;
|
|
output [1:0] SAXIGP3RRESP;
|
|
output SAXIGP3RVALID;
|
|
output [3:0] SAXIGP3WACOUNT;
|
|
output [7:0] SAXIGP3WCOUNT;
|
|
output SAXIGP3WREADY;
|
|
output SAXIGP4ARREADY;
|
|
output SAXIGP4AWREADY;
|
|
output [5:0] SAXIGP4BID;
|
|
output [1:0] SAXIGP4BRESP;
|
|
output SAXIGP4BVALID;
|
|
output [3:0] SAXIGP4RACOUNT;
|
|
output [7:0] SAXIGP4RCOUNT;
|
|
output [127:0] SAXIGP4RDATA;
|
|
output [5:0] SAXIGP4RID;
|
|
output SAXIGP4RLAST;
|
|
output [1:0] SAXIGP4RRESP;
|
|
output SAXIGP4RVALID;
|
|
output [3:0] SAXIGP4WACOUNT;
|
|
output [7:0] SAXIGP4WCOUNT;
|
|
output SAXIGP4WREADY;
|
|
output SAXIGP5ARREADY;
|
|
output SAXIGP5AWREADY;
|
|
output [5:0] SAXIGP5BID;
|
|
output [1:0] SAXIGP5BRESP;
|
|
output SAXIGP5BVALID;
|
|
output [3:0] SAXIGP5RACOUNT;
|
|
output [7:0] SAXIGP5RCOUNT;
|
|
output [127:0] SAXIGP5RDATA;
|
|
output [5:0] SAXIGP5RID;
|
|
output SAXIGP5RLAST;
|
|
output [1:0] SAXIGP5RRESP;
|
|
output SAXIGP5RVALID;
|
|
output [3:0] SAXIGP5WACOUNT;
|
|
output [7:0] SAXIGP5WCOUNT;
|
|
output SAXIGP5WREADY;
|
|
output SAXIGP6ARREADY;
|
|
output SAXIGP6AWREADY;
|
|
output [5:0] SAXIGP6BID;
|
|
output [1:0] SAXIGP6BRESP;
|
|
output SAXIGP6BVALID;
|
|
output [3:0] SAXIGP6RACOUNT;
|
|
output [7:0] SAXIGP6RCOUNT;
|
|
output [127:0] SAXIGP6RDATA;
|
|
output [5:0] SAXIGP6RID;
|
|
output SAXIGP6RLAST;
|
|
output [1:0] SAXIGP6RRESP;
|
|
output SAXIGP6RVALID;
|
|
output [3:0] SAXIGP6WACOUNT;
|
|
output [7:0] SAXIGP6WCOUNT;
|
|
output SAXIGP6WREADY;
|
|
inout [3:0] PSS_ALTO_CORE_PAD_BOOTMODE;
|
|
inout PSS_ALTO_CORE_PAD_CLK;
|
|
inout PSS_ALTO_CORE_PAD_DONEB;
|
|
inout [17:0] PSS_ALTO_CORE_PAD_DRAMA;
|
|
inout PSS_ALTO_CORE_PAD_DRAMACTN;
|
|
inout PSS_ALTO_CORE_PAD_DRAMALERTN;
|
|
inout [1:0] PSS_ALTO_CORE_PAD_DRAMBA;
|
|
inout [1:0] PSS_ALTO_CORE_PAD_DRAMBG;
|
|
inout [1:0] PSS_ALTO_CORE_PAD_DRAMCK;
|
|
inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKE;
|
|
inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKN;
|
|
inout [1:0] PSS_ALTO_CORE_PAD_DRAMCSN;
|
|
inout [8:0] PSS_ALTO_CORE_PAD_DRAMDM;
|
|
inout [71:0] PSS_ALTO_CORE_PAD_DRAMDQ;
|
|
inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQS;
|
|
inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQSN;
|
|
inout [1:0] PSS_ALTO_CORE_PAD_DRAMODT;
|
|
inout PSS_ALTO_CORE_PAD_DRAMPARITY;
|
|
inout PSS_ALTO_CORE_PAD_DRAMRAMRSTN;
|
|
inout PSS_ALTO_CORE_PAD_ERROROUT;
|
|
inout PSS_ALTO_CORE_PAD_ERRORSTATUS;
|
|
inout PSS_ALTO_CORE_PAD_INITB;
|
|
inout PSS_ALTO_CORE_PAD_JTAGTCK;
|
|
inout PSS_ALTO_CORE_PAD_JTAGTDI;
|
|
inout PSS_ALTO_CORE_PAD_JTAGTDO;
|
|
inout PSS_ALTO_CORE_PAD_JTAGTMS;
|
|
inout [77:0] PSS_ALTO_CORE_PAD_MIO;
|
|
inout PSS_ALTO_CORE_PAD_PORB;
|
|
inout PSS_ALTO_CORE_PAD_PROGB;
|
|
inout PSS_ALTO_CORE_PAD_RCALIBINOUT;
|
|
inout PSS_ALTO_CORE_PAD_SRSTB;
|
|
inout PSS_ALTO_CORE_PAD_ZQ;
|
|
input [7:0] ADMAFCICLK;
|
|
input AIBPMUAFIFMFPDACK;
|
|
input AIBPMUAFIFMLPDACK;
|
|
input DDRCEXTREFRESHRANK0REQ;
|
|
input DDRCEXTREFRESHRANK1REQ;
|
|
input DDRCREFRESHPLCLK;
|
|
input DPAUXDATAIN;
|
|
input DPEXTERNALCUSTOMEVENT1;
|
|
input DPEXTERNALCUSTOMEVENT2;
|
|
input DPEXTERNALVSYNCEVENT;
|
|
input DPHOTPLUGDETECT;
|
|
input [7:0] DPLIVEGFXALPHAIN;
|
|
input [35:0] DPLIVEGFXPIXEL1IN;
|
|
input DPLIVEVIDEOINDE;
|
|
input DPLIVEVIDEOINHSYNC;
|
|
input [35:0] DPLIVEVIDEOINPIXEL1;
|
|
input DPLIVEVIDEOINVSYNC;
|
|
input DPMAXISMIXEDAUDIOTREADY;
|
|
input DPSAXISAUDIOCLK;
|
|
input [31:0] DPSAXISAUDIOTDATA;
|
|
input DPSAXISAUDIOTID;
|
|
input DPSAXISAUDIOTVALID;
|
|
input DPVIDEOINCLK;
|
|
input EMIOCAN0PHYRX;
|
|
input EMIOCAN1PHYRX;
|
|
input EMIOENET0DMATXSTATUSTOG;
|
|
input EMIOENET0EXTINTIN;
|
|
input EMIOENET0GMIICOL;
|
|
input EMIOENET0GMIICRS;
|
|
input EMIOENET0GMIIRXCLK;
|
|
input [7:0] EMIOENET0GMIIRXD;
|
|
input EMIOENET0GMIIRXDV;
|
|
input EMIOENET0GMIIRXER;
|
|
input EMIOENET0GMIITXCLK;
|
|
input EMIOENET0MDIOI;
|
|
input EMIOENET0RXWOVERFLOW;
|
|
input EMIOENET0TXRCONTROL;
|
|
input [7:0] EMIOENET0TXRDATA;
|
|
input EMIOENET0TXRDATARDY;
|
|
input EMIOENET0TXREOP;
|
|
input EMIOENET0TXRERR;
|
|
input EMIOENET0TXRFLUSHED;
|
|
input EMIOENET0TXRSOP;
|
|
input EMIOENET0TXRUNDERFLOW;
|
|
input EMIOENET0TXRVALID;
|
|
input EMIOENET1DMATXSTATUSTOG;
|
|
input EMIOENET1EXTINTIN;
|
|
input EMIOENET1GMIICOL;
|
|
input EMIOENET1GMIICRS;
|
|
input EMIOENET1GMIIRXCLK;
|
|
input [7:0] EMIOENET1GMIIRXD;
|
|
input EMIOENET1GMIIRXDV;
|
|
input EMIOENET1GMIIRXER;
|
|
input EMIOENET1GMIITXCLK;
|
|
input EMIOENET1MDIOI;
|
|
input EMIOENET1RXWOVERFLOW;
|
|
input EMIOENET1TXRCONTROL;
|
|
input [7:0] EMIOENET1TXRDATA;
|
|
input EMIOENET1TXRDATARDY;
|
|
input EMIOENET1TXREOP;
|
|
input EMIOENET1TXRERR;
|
|
input EMIOENET1TXRFLUSHED;
|
|
input EMIOENET1TXRSOP;
|
|
input EMIOENET1TXRUNDERFLOW;
|
|
input EMIOENET1TXRVALID;
|
|
input EMIOENET2DMATXSTATUSTOG;
|
|
input EMIOENET2EXTINTIN;
|
|
input EMIOENET2GMIICOL;
|
|
input EMIOENET2GMIICRS;
|
|
input EMIOENET2GMIIRXCLK;
|
|
input [7:0] EMIOENET2GMIIRXD;
|
|
input EMIOENET2GMIIRXDV;
|
|
input EMIOENET2GMIIRXER;
|
|
input EMIOENET2GMIITXCLK;
|
|
input EMIOENET2MDIOI;
|
|
input EMIOENET2RXWOVERFLOW;
|
|
input EMIOENET2TXRCONTROL;
|
|
input [7:0] EMIOENET2TXRDATA;
|
|
input EMIOENET2TXRDATARDY;
|
|
input EMIOENET2TXREOP;
|
|
input EMIOENET2TXRERR;
|
|
input EMIOENET2TXRFLUSHED;
|
|
input EMIOENET2TXRSOP;
|
|
input EMIOENET2TXRUNDERFLOW;
|
|
input EMIOENET2TXRVALID;
|
|
input EMIOENET3DMATXSTATUSTOG;
|
|
input EMIOENET3EXTINTIN;
|
|
input EMIOENET3GMIICOL;
|
|
input EMIOENET3GMIICRS;
|
|
input EMIOENET3GMIIRXCLK;
|
|
input [7:0] EMIOENET3GMIIRXD;
|
|
input EMIOENET3GMIIRXDV;
|
|
input EMIOENET3GMIIRXER;
|
|
input EMIOENET3GMIITXCLK;
|
|
input EMIOENET3MDIOI;
|
|
input EMIOENET3RXWOVERFLOW;
|
|
input EMIOENET3TXRCONTROL;
|
|
input [7:0] EMIOENET3TXRDATA;
|
|
input EMIOENET3TXRDATARDY;
|
|
input EMIOENET3TXREOP;
|
|
input EMIOENET3TXRERR;
|
|
input EMIOENET3TXRFLUSHED;
|
|
input EMIOENET3TXRSOP;
|
|
input EMIOENET3TXRUNDERFLOW;
|
|
input EMIOENET3TXRVALID;
|
|
input EMIOENETTSUCLK;
|
|
input [1:0] EMIOGEM0TSUINCCTRL;
|
|
input [1:0] EMIOGEM1TSUINCCTRL;
|
|
input [1:0] EMIOGEM2TSUINCCTRL;
|
|
input [1:0] EMIOGEM3TSUINCCTRL;
|
|
input [95:0] EMIOGPIOI;
|
|
input EMIOHUBPORTOVERCRNTUSB20;
|
|
input EMIOHUBPORTOVERCRNTUSB21;
|
|
input EMIOHUBPORTOVERCRNTUSB30;
|
|
input EMIOHUBPORTOVERCRNTUSB31;
|
|
input EMIOI2C0SCLI;
|
|
input EMIOI2C0SDAI;
|
|
input EMIOI2C1SCLI;
|
|
input EMIOI2C1SDAI;
|
|
input EMIOSDIO0CDN;
|
|
input EMIOSDIO0CMDIN;
|
|
input [7:0] EMIOSDIO0DATAIN;
|
|
input EMIOSDIO0FBCLKIN;
|
|
input EMIOSDIO0WP;
|
|
input EMIOSDIO1CDN;
|
|
input EMIOSDIO1CMDIN;
|
|
input [7:0] EMIOSDIO1DATAIN;
|
|
input EMIOSDIO1FBCLKIN;
|
|
input EMIOSDIO1WP;
|
|
input EMIOSPI0MI;
|
|
input EMIOSPI0SCLKI;
|
|
input EMIOSPI0SI;
|
|
input EMIOSPI0SSIN;
|
|
input EMIOSPI1MI;
|
|
input EMIOSPI1SCLKI;
|
|
input EMIOSPI1SI;
|
|
input EMIOSPI1SSIN;
|
|
input [2:0] EMIOTTC0CLKI;
|
|
input [2:0] EMIOTTC1CLKI;
|
|
input [2:0] EMIOTTC2CLKI;
|
|
input [2:0] EMIOTTC3CLKI;
|
|
input EMIOUART0CTSN;
|
|
input EMIOUART0DCDN;
|
|
input EMIOUART0DSRN;
|
|
input EMIOUART0RIN;
|
|
input EMIOUART0RX;
|
|
input EMIOUART1CTSN;
|
|
input EMIOUART1DCDN;
|
|
input EMIOUART1DSRN;
|
|
input EMIOUART1RIN;
|
|
input EMIOUART1RX;
|
|
input EMIOWDT0CLKI;
|
|
input EMIOWDT1CLKI;
|
|
input FMIOGEM0FIFORXCLKFROMPL;
|
|
input FMIOGEM0FIFOTXCLKFROMPL;
|
|
input FMIOGEM0SIGNALDETECT;
|
|
input FMIOGEM1FIFORXCLKFROMPL;
|
|
input FMIOGEM1FIFOTXCLKFROMPL;
|
|
input FMIOGEM1SIGNALDETECT;
|
|
input FMIOGEM2FIFORXCLKFROMPL;
|
|
input FMIOGEM2FIFOTXCLKFROMPL;
|
|
input FMIOGEM2SIGNALDETECT;
|
|
input FMIOGEM3FIFORXCLKFROMPL;
|
|
input FMIOGEM3FIFOTXCLKFROMPL;
|
|
input FMIOGEM3SIGNALDETECT;
|
|
input FMIOGEMTSUCLKFROMPL;
|
|
input [31:0] FTMGPI;
|
|
input [7:0] GDMAFCICLK;
|
|
input MAXIGP0ACLK;
|
|
input MAXIGP0ARREADY;
|
|
input MAXIGP0AWREADY;
|
|
input [15:0] MAXIGP0BID;
|
|
input [1:0] MAXIGP0BRESP;
|
|
input MAXIGP0BVALID;
|
|
input [127:0] MAXIGP0RDATA;
|
|
input [15:0] MAXIGP0RID;
|
|
input MAXIGP0RLAST;
|
|
input [1:0] MAXIGP0RRESP;
|
|
input MAXIGP0RVALID;
|
|
input MAXIGP0WREADY;
|
|
input MAXIGP1ACLK;
|
|
input MAXIGP1ARREADY;
|
|
input MAXIGP1AWREADY;
|
|
input [15:0] MAXIGP1BID;
|
|
input [1:0] MAXIGP1BRESP;
|
|
input MAXIGP1BVALID;
|
|
input [127:0] MAXIGP1RDATA;
|
|
input [15:0] MAXIGP1RID;
|
|
input MAXIGP1RLAST;
|
|
input [1:0] MAXIGP1RRESP;
|
|
input MAXIGP1RVALID;
|
|
input MAXIGP1WREADY;
|
|
input MAXIGP2ACLK;
|
|
input MAXIGP2ARREADY;
|
|
input MAXIGP2AWREADY;
|
|
input [15:0] MAXIGP2BID;
|
|
input [1:0] MAXIGP2BRESP;
|
|
input MAXIGP2BVALID;
|
|
input [127:0] MAXIGP2RDATA;
|
|
input [15:0] MAXIGP2RID;
|
|
input MAXIGP2RLAST;
|
|
input [1:0] MAXIGP2RRESP;
|
|
input MAXIGP2RVALID;
|
|
input MAXIGP2WREADY;
|
|
input NFIQ0LPDRPU;
|
|
input NFIQ1LPDRPU;
|
|
input NIRQ0LPDRPU;
|
|
input NIRQ1LPDRPU;
|
|
input [7:0] PL2ADMACVLD;
|
|
input [7:0] PL2ADMATACK;
|
|
input [7:0] PL2GDMACVLD;
|
|
input [7:0] PL2GDMATACK;
|
|
input PLACECLK;
|
|
input PLACPINACT;
|
|
input [3:0] PLFPGASTOP;
|
|
input [2:0] PLLAUXREFCLKFPD;
|
|
input [1:0] PLLAUXREFCLKLPD;
|
|
input [31:0] PLPMUGPI;
|
|
input [3:0] PLPSAPUGICFIQ;
|
|
input [3:0] PLPSAPUGICIRQ;
|
|
input PLPSEVENTI;
|
|
input [7:0] PLPSIRQ0;
|
|
input [7:0] PLPSIRQ1;
|
|
input PLPSTRACECLK;
|
|
input [3:0] PLPSTRIGACK;
|
|
input [3:0] PLPSTRIGGER;
|
|
input [3:0] PMUERRORFROMPL;
|
|
input PSS_ALTO_CORE_PAD_MGTRXN0IN;
|
|
input PSS_ALTO_CORE_PAD_MGTRXN1IN;
|
|
input PSS_ALTO_CORE_PAD_MGTRXN2IN;
|
|
input PSS_ALTO_CORE_PAD_MGTRXN3IN;
|
|
input PSS_ALTO_CORE_PAD_MGTRXP0IN;
|
|
input PSS_ALTO_CORE_PAD_MGTRXP1IN;
|
|
input PSS_ALTO_CORE_PAD_MGTRXP2IN;
|
|
input PSS_ALTO_CORE_PAD_MGTRXP3IN;
|
|
input PSS_ALTO_CORE_PAD_PADI;
|
|
input PSS_ALTO_CORE_PAD_REFN0IN;
|
|
input PSS_ALTO_CORE_PAD_REFN1IN;
|
|
input PSS_ALTO_CORE_PAD_REFN2IN;
|
|
input PSS_ALTO_CORE_PAD_REFN3IN;
|
|
input PSS_ALTO_CORE_PAD_REFP0IN;
|
|
input PSS_ALTO_CORE_PAD_REFP1IN;
|
|
input PSS_ALTO_CORE_PAD_REFP2IN;
|
|
input PSS_ALTO_CORE_PAD_REFP3IN;
|
|
input RPUEVENTI0;
|
|
input RPUEVENTI1;
|
|
input SACEFPDACREADY;
|
|
input [43:0] SACEFPDARADDR;
|
|
input [1:0] SACEFPDARBAR;
|
|
input [1:0] SACEFPDARBURST;
|
|
input [3:0] SACEFPDARCACHE;
|
|
input [1:0] SACEFPDARDOMAIN;
|
|
input [5:0] SACEFPDARID;
|
|
input [7:0] SACEFPDARLEN;
|
|
input SACEFPDARLOCK;
|
|
input [2:0] SACEFPDARPROT;
|
|
input [3:0] SACEFPDARQOS;
|
|
input [3:0] SACEFPDARREGION;
|
|
input [2:0] SACEFPDARSIZE;
|
|
input [3:0] SACEFPDARSNOOP;
|
|
input [15:0] SACEFPDARUSER;
|
|
input SACEFPDARVALID;
|
|
input [43:0] SACEFPDAWADDR;
|
|
input [1:0] SACEFPDAWBAR;
|
|
input [1:0] SACEFPDAWBURST;
|
|
input [3:0] SACEFPDAWCACHE;
|
|
input [1:0] SACEFPDAWDOMAIN;
|
|
input [5:0] SACEFPDAWID;
|
|
input [7:0] SACEFPDAWLEN;
|
|
input SACEFPDAWLOCK;
|
|
input [2:0] SACEFPDAWPROT;
|
|
input [3:0] SACEFPDAWQOS;
|
|
input [3:0] SACEFPDAWREGION;
|
|
input [2:0] SACEFPDAWSIZE;
|
|
input [2:0] SACEFPDAWSNOOP;
|
|
input [15:0] SACEFPDAWUSER;
|
|
input SACEFPDAWVALID;
|
|
input SACEFPDBREADY;
|
|
input [127:0] SACEFPDCDDATA;
|
|
input SACEFPDCDLAST;
|
|
input SACEFPDCDVALID;
|
|
input [4:0] SACEFPDCRRESP;
|
|
input SACEFPDCRVALID;
|
|
input SACEFPDRACK;
|
|
input SACEFPDRREADY;
|
|
input SACEFPDWACK;
|
|
input [127:0] SACEFPDWDATA;
|
|
input SACEFPDWLAST;
|
|
input [15:0] SACEFPDWSTRB;
|
|
input SACEFPDWUSER;
|
|
input SACEFPDWVALID;
|
|
input SAXIACPACLK;
|
|
input [39:0] SAXIACPARADDR;
|
|
input [1:0] SAXIACPARBURST;
|
|
input [3:0] SAXIACPARCACHE;
|
|
input [4:0] SAXIACPARID;
|
|
input [7:0] SAXIACPARLEN;
|
|
input SAXIACPARLOCK;
|
|
input [2:0] SAXIACPARPROT;
|
|
input [3:0] SAXIACPARQOS;
|
|
input [2:0] SAXIACPARSIZE;
|
|
input [1:0] SAXIACPARUSER;
|
|
input SAXIACPARVALID;
|
|
input [39:0] SAXIACPAWADDR;
|
|
input [1:0] SAXIACPAWBURST;
|
|
input [3:0] SAXIACPAWCACHE;
|
|
input [4:0] SAXIACPAWID;
|
|
input [7:0] SAXIACPAWLEN;
|
|
input SAXIACPAWLOCK;
|
|
input [2:0] SAXIACPAWPROT;
|
|
input [3:0] SAXIACPAWQOS;
|
|
input [2:0] SAXIACPAWSIZE;
|
|
input [1:0] SAXIACPAWUSER;
|
|
input SAXIACPAWVALID;
|
|
input SAXIACPBREADY;
|
|
input SAXIACPRREADY;
|
|
input [127:0] SAXIACPWDATA;
|
|
input SAXIACPWLAST;
|
|
input [15:0] SAXIACPWSTRB;
|
|
input SAXIACPWVALID;
|
|
input [48:0] SAXIGP0ARADDR;
|
|
input [1:0] SAXIGP0ARBURST;
|
|
input [3:0] SAXIGP0ARCACHE;
|
|
input [5:0] SAXIGP0ARID;
|
|
input [7:0] SAXIGP0ARLEN;
|
|
input SAXIGP0ARLOCK;
|
|
input [2:0] SAXIGP0ARPROT;
|
|
input [3:0] SAXIGP0ARQOS;
|
|
input [2:0] SAXIGP0ARSIZE;
|
|
input SAXIGP0ARUSER;
|
|
input SAXIGP0ARVALID;
|
|
input [48:0] SAXIGP0AWADDR;
|
|
input [1:0] SAXIGP0AWBURST;
|
|
input [3:0] SAXIGP0AWCACHE;
|
|
input [5:0] SAXIGP0AWID;
|
|
input [7:0] SAXIGP0AWLEN;
|
|
input SAXIGP0AWLOCK;
|
|
input [2:0] SAXIGP0AWPROT;
|
|
input [3:0] SAXIGP0AWQOS;
|
|
input [2:0] SAXIGP0AWSIZE;
|
|
input SAXIGP0AWUSER;
|
|
input SAXIGP0AWVALID;
|
|
input SAXIGP0BREADY;
|
|
input SAXIGP0RCLK;
|
|
input SAXIGP0RREADY;
|
|
input SAXIGP0WCLK;
|
|
input [127:0] SAXIGP0WDATA;
|
|
input SAXIGP0WLAST;
|
|
input [15:0] SAXIGP0WSTRB;
|
|
input SAXIGP0WVALID;
|
|
input [48:0] SAXIGP1ARADDR;
|
|
input [1:0] SAXIGP1ARBURST;
|
|
input [3:0] SAXIGP1ARCACHE;
|
|
input [5:0] SAXIGP1ARID;
|
|
input [7:0] SAXIGP1ARLEN;
|
|
input SAXIGP1ARLOCK;
|
|
input [2:0] SAXIGP1ARPROT;
|
|
input [3:0] SAXIGP1ARQOS;
|
|
input [2:0] SAXIGP1ARSIZE;
|
|
input SAXIGP1ARUSER;
|
|
input SAXIGP1ARVALID;
|
|
input [48:0] SAXIGP1AWADDR;
|
|
input [1:0] SAXIGP1AWBURST;
|
|
input [3:0] SAXIGP1AWCACHE;
|
|
input [5:0] SAXIGP1AWID;
|
|
input [7:0] SAXIGP1AWLEN;
|
|
input SAXIGP1AWLOCK;
|
|
input [2:0] SAXIGP1AWPROT;
|
|
input [3:0] SAXIGP1AWQOS;
|
|
input [2:0] SAXIGP1AWSIZE;
|
|
input SAXIGP1AWUSER;
|
|
input SAXIGP1AWVALID;
|
|
input SAXIGP1BREADY;
|
|
input SAXIGP1RCLK;
|
|
input SAXIGP1RREADY;
|
|
input SAXIGP1WCLK;
|
|
input [127:0] SAXIGP1WDATA;
|
|
input SAXIGP1WLAST;
|
|
input [15:0] SAXIGP1WSTRB;
|
|
input SAXIGP1WVALID;
|
|
input [48:0] SAXIGP2ARADDR;
|
|
input [1:0] SAXIGP2ARBURST;
|
|
input [3:0] SAXIGP2ARCACHE;
|
|
input [5:0] SAXIGP2ARID;
|
|
input [7:0] SAXIGP2ARLEN;
|
|
input SAXIGP2ARLOCK;
|
|
input [2:0] SAXIGP2ARPROT;
|
|
input [3:0] SAXIGP2ARQOS;
|
|
input [2:0] SAXIGP2ARSIZE;
|
|
input SAXIGP2ARUSER;
|
|
input SAXIGP2ARVALID;
|
|
input [48:0] SAXIGP2AWADDR;
|
|
input [1:0] SAXIGP2AWBURST;
|
|
input [3:0] SAXIGP2AWCACHE;
|
|
input [5:0] SAXIGP2AWID;
|
|
input [7:0] SAXIGP2AWLEN;
|
|
input SAXIGP2AWLOCK;
|
|
input [2:0] SAXIGP2AWPROT;
|
|
input [3:0] SAXIGP2AWQOS;
|
|
input [2:0] SAXIGP2AWSIZE;
|
|
input SAXIGP2AWUSER;
|
|
input SAXIGP2AWVALID;
|
|
input SAXIGP2BREADY;
|
|
input SAXIGP2RCLK;
|
|
input SAXIGP2RREADY;
|
|
input SAXIGP2WCLK;
|
|
input [127:0] SAXIGP2WDATA;
|
|
input SAXIGP2WLAST;
|
|
input [15:0] SAXIGP2WSTRB;
|
|
input SAXIGP2WVALID;
|
|
input [48:0] SAXIGP3ARADDR;
|
|
input [1:0] SAXIGP3ARBURST;
|
|
input [3:0] SAXIGP3ARCACHE;
|
|
input [5:0] SAXIGP3ARID;
|
|
input [7:0] SAXIGP3ARLEN;
|
|
input SAXIGP3ARLOCK;
|
|
input [2:0] SAXIGP3ARPROT;
|
|
input [3:0] SAXIGP3ARQOS;
|
|
input [2:0] SAXIGP3ARSIZE;
|
|
input SAXIGP3ARUSER;
|
|
input SAXIGP3ARVALID;
|
|
input [48:0] SAXIGP3AWADDR;
|
|
input [1:0] SAXIGP3AWBURST;
|
|
input [3:0] SAXIGP3AWCACHE;
|
|
input [5:0] SAXIGP3AWID;
|
|
input [7:0] SAXIGP3AWLEN;
|
|
input SAXIGP3AWLOCK;
|
|
input [2:0] SAXIGP3AWPROT;
|
|
input [3:0] SAXIGP3AWQOS;
|
|
input [2:0] SAXIGP3AWSIZE;
|
|
input SAXIGP3AWUSER;
|
|
input SAXIGP3AWVALID;
|
|
input SAXIGP3BREADY;
|
|
input SAXIGP3RCLK;
|
|
input SAXIGP3RREADY;
|
|
input SAXIGP3WCLK;
|
|
input [127:0] SAXIGP3WDATA;
|
|
input SAXIGP3WLAST;
|
|
input [15:0] SAXIGP3WSTRB;
|
|
input SAXIGP3WVALID;
|
|
input [48:0] SAXIGP4ARADDR;
|
|
input [1:0] SAXIGP4ARBURST;
|
|
input [3:0] SAXIGP4ARCACHE;
|
|
input [5:0] SAXIGP4ARID;
|
|
input [7:0] SAXIGP4ARLEN;
|
|
input SAXIGP4ARLOCK;
|
|
input [2:0] SAXIGP4ARPROT;
|
|
input [3:0] SAXIGP4ARQOS;
|
|
input [2:0] SAXIGP4ARSIZE;
|
|
input SAXIGP4ARUSER;
|
|
input SAXIGP4ARVALID;
|
|
input [48:0] SAXIGP4AWADDR;
|
|
input [1:0] SAXIGP4AWBURST;
|
|
input [3:0] SAXIGP4AWCACHE;
|
|
input [5:0] SAXIGP4AWID;
|
|
input [7:0] SAXIGP4AWLEN;
|
|
input SAXIGP4AWLOCK;
|
|
input [2:0] SAXIGP4AWPROT;
|
|
input [3:0] SAXIGP4AWQOS;
|
|
input [2:0] SAXIGP4AWSIZE;
|
|
input SAXIGP4AWUSER;
|
|
input SAXIGP4AWVALID;
|
|
input SAXIGP4BREADY;
|
|
input SAXIGP4RCLK;
|
|
input SAXIGP4RREADY;
|
|
input SAXIGP4WCLK;
|
|
input [127:0] SAXIGP4WDATA;
|
|
input SAXIGP4WLAST;
|
|
input [15:0] SAXIGP4WSTRB;
|
|
input SAXIGP4WVALID;
|
|
input [48:0] SAXIGP5ARADDR;
|
|
input [1:0] SAXIGP5ARBURST;
|
|
input [3:0] SAXIGP5ARCACHE;
|
|
input [5:0] SAXIGP5ARID;
|
|
input [7:0] SAXIGP5ARLEN;
|
|
input SAXIGP5ARLOCK;
|
|
input [2:0] SAXIGP5ARPROT;
|
|
input [3:0] SAXIGP5ARQOS;
|
|
input [2:0] SAXIGP5ARSIZE;
|
|
input SAXIGP5ARUSER;
|
|
input SAXIGP5ARVALID;
|
|
input [48:0] SAXIGP5AWADDR;
|
|
input [1:0] SAXIGP5AWBURST;
|
|
input [3:0] SAXIGP5AWCACHE;
|
|
input [5:0] SAXIGP5AWID;
|
|
input [7:0] SAXIGP5AWLEN;
|
|
input SAXIGP5AWLOCK;
|
|
input [2:0] SAXIGP5AWPROT;
|
|
input [3:0] SAXIGP5AWQOS;
|
|
input [2:0] SAXIGP5AWSIZE;
|
|
input SAXIGP5AWUSER;
|
|
input SAXIGP5AWVALID;
|
|
input SAXIGP5BREADY;
|
|
input SAXIGP5RCLK;
|
|
input SAXIGP5RREADY;
|
|
input SAXIGP5WCLK;
|
|
input [127:0] SAXIGP5WDATA;
|
|
input SAXIGP5WLAST;
|
|
input [15:0] SAXIGP5WSTRB;
|
|
input SAXIGP5WVALID;
|
|
input [48:0] SAXIGP6ARADDR;
|
|
input [1:0] SAXIGP6ARBURST;
|
|
input [3:0] SAXIGP6ARCACHE;
|
|
input [5:0] SAXIGP6ARID;
|
|
input [7:0] SAXIGP6ARLEN;
|
|
input SAXIGP6ARLOCK;
|
|
input [2:0] SAXIGP6ARPROT;
|
|
input [3:0] SAXIGP6ARQOS;
|
|
input [2:0] SAXIGP6ARSIZE;
|
|
input SAXIGP6ARUSER;
|
|
input SAXIGP6ARVALID;
|
|
input [48:0] SAXIGP6AWADDR;
|
|
input [1:0] SAXIGP6AWBURST;
|
|
input [3:0] SAXIGP6AWCACHE;
|
|
input [5:0] SAXIGP6AWID;
|
|
input [7:0] SAXIGP6AWLEN;
|
|
input SAXIGP6AWLOCK;
|
|
input [2:0] SAXIGP6AWPROT;
|
|
input [3:0] SAXIGP6AWQOS;
|
|
input [2:0] SAXIGP6AWSIZE;
|
|
input SAXIGP6AWUSER;
|
|
input SAXIGP6AWVALID;
|
|
input SAXIGP6BREADY;
|
|
input SAXIGP6RCLK;
|
|
input SAXIGP6RREADY;
|
|
input SAXIGP6WCLK;
|
|
input [127:0] SAXIGP6WDATA;
|
|
input SAXIGP6WLAST;
|
|
input [15:0] SAXIGP6WSTRB;
|
|
input SAXIGP6WVALID;
|
|
input [59:0] STMEVENT;
|
|
endmodule
|
|
|
|
module ILKN(DRP_DO, DRP_RDY, RX_BYPASS_DATAOUT00, RX_BYPASS_DATAOUT01, RX_BYPASS_DATAOUT02, RX_BYPASS_DATAOUT03, RX_BYPASS_DATAOUT04, RX_BYPASS_DATAOUT05, RX_BYPASS_DATAOUT06, RX_BYPASS_DATAOUT07, RX_BYPASS_DATAOUT08, RX_BYPASS_DATAOUT09, RX_BYPASS_DATAOUT10, RX_BYPASS_DATAOUT11, RX_BYPASS_ENAOUT, RX_BYPASS_IS_AVAILOUT, RX_BYPASS_IS_BADLYFRAMEDOUT, RX_BYPASS_IS_OVERFLOWOUT, RX_BYPASS_IS_SYNCEDOUT, RX_BYPASS_IS_SYNCWORDOUT, RX_CHANOUT0
|
|
, RX_CHANOUT1, RX_CHANOUT2, RX_CHANOUT3, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_MTYOUT0, RX_MTYOUT1
|
|
, RX_MTYOUT2, RX_MTYOUT3, RX_OVFOUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_TYPE_ERR, STAT_RX_BURSTMAX_ERR, STAT_RX_BURST_ERR, STAT_RX_CRC24_ERR, STAT_RX_CRC32_ERR, STAT_RX_CRC32_VALID, STAT_RX_DESCRAM_ERR, STAT_RX_DIAGWORD_INTFSTAT, STAT_RX_DIAGWORD_LANESTAT, STAT_RX_FC_STAT, STAT_RX_FRAMING_ERR, STAT_RX_MEOP_ERR
|
|
, STAT_RX_MF_ERR, STAT_RX_MF_LEN_ERR, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MSOP_ERR, STAT_RX_MUBITS, STAT_RX_MUBITS_UPDATED, STAT_RX_OVERFLOW_ERR, STAT_RX_RETRANS_CRC24_ERR, STAT_RX_RETRANS_DISC, STAT_RX_RETRANS_LATENCY, STAT_RX_RETRANS_REQ, STAT_RX_RETRANS_RETRY_ERR, STAT_RX_RETRANS_SEQ, STAT_RX_RETRANS_SEQ_UPDATED, STAT_RX_RETRANS_STATE, STAT_RX_RETRANS_SUBSEQ, STAT_RX_RETRANS_WDOG_ERR, STAT_RX_RETRANS_WRAP_ERR, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR
|
|
, STAT_RX_WORD_SYNC, STAT_TX_BURST_ERR, STAT_TX_ERRINJ_BITERR_DONE, STAT_TX_OVERFLOW_ERR, STAT_TX_RETRANS_BURST_ERR, STAT_TX_RETRANS_BUSY, STAT_TX_RETRANS_RAM_PERROUT, STAT_TX_RETRANS_RAM_RADDR, STAT_TX_RETRANS_RAM_RD_B0, STAT_TX_RETRANS_RAM_RD_B1, STAT_TX_RETRANS_RAM_RD_B2, STAT_TX_RETRANS_RAM_RD_B3, STAT_TX_RETRANS_RAM_RSEL, STAT_TX_RETRANS_RAM_WADDR, STAT_TX_RETRANS_RAM_WDATA, STAT_TX_RETRANS_RAM_WE_B0, STAT_TX_RETRANS_RAM_WE_B1, STAT_TX_RETRANS_RAM_WE_B2, STAT_TX_RETRANS_RAM_WE_B3, STAT_TX_UNDERFLOW_ERR, TX_OVFOUT
|
|
, TX_RDYOUT, TX_SERDES_DATA00, TX_SERDES_DATA01, TX_SERDES_DATA02, TX_SERDES_DATA03, TX_SERDES_DATA04, TX_SERDES_DATA05, TX_SERDES_DATA06, TX_SERDES_DATA07, TX_SERDES_DATA08, TX_SERDES_DATA09, TX_SERDES_DATA10, TX_SERDES_DATA11, CORE_CLK, CTL_RX_FORCE_RESYNC, CTL_RX_RETRANS_ACK, CTL_RX_RETRANS_ENABLE, CTL_RX_RETRANS_ERRIN, CTL_RX_RETRANS_FORCE_REQ, CTL_RX_RETRANS_RESET, CTL_RX_RETRANS_RESET_MODE
|
|
, CTL_TX_DIAGWORD_INTFSTAT, CTL_TX_DIAGWORD_LANESTAT, CTL_TX_ENABLE, CTL_TX_ERRINJ_BITERR_GO, CTL_TX_ERRINJ_BITERR_LANE, CTL_TX_FC_STAT, CTL_TX_MUBITS, CTL_TX_RETRANS_ENABLE, CTL_TX_RETRANS_RAM_PERRIN, CTL_TX_RETRANS_RAM_RDATA, CTL_TX_RETRANS_REQ, CTL_TX_RETRANS_REQ_VALID, CTL_TX_RLIM_DELTA, CTL_TX_RLIM_ENABLE, CTL_TX_RLIM_INTV, CTL_TX_RLIM_MAX, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN, DRP_WE
|
|
, LBUS_CLK, RX_BYPASS_FORCE_REALIGNIN, RX_BYPASS_RDIN, RX_RESET, RX_SERDES_CLK, RX_SERDES_DATA00, RX_SERDES_DATA01, RX_SERDES_DATA02, RX_SERDES_DATA03, RX_SERDES_DATA04, RX_SERDES_DATA05, RX_SERDES_DATA06, RX_SERDES_DATA07, RX_SERDES_DATA08, RX_SERDES_DATA09, RX_SERDES_DATA10, RX_SERDES_DATA11, RX_SERDES_RESET, TX_BCTLIN0, TX_BCTLIN1, TX_BCTLIN2
|
|
, TX_BCTLIN3, TX_BYPASS_CTRLIN, TX_BYPASS_DATAIN00, TX_BYPASS_DATAIN01, TX_BYPASS_DATAIN02, TX_BYPASS_DATAIN03, TX_BYPASS_DATAIN04, TX_BYPASS_DATAIN05, TX_BYPASS_DATAIN06, TX_BYPASS_DATAIN07, TX_BYPASS_DATAIN08, TX_BYPASS_DATAIN09, TX_BYPASS_DATAIN10, TX_BYPASS_DATAIN11, TX_BYPASS_ENAIN, TX_BYPASS_GEARBOX_SEQIN, TX_BYPASS_MFRAMER_STATEIN, TX_CHANIN0, TX_CHANIN1, TX_CHANIN2, TX_CHANIN3
|
|
, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1, TX_MTYIN2, TX_MTYIN3, TX_RESET
|
|
, TX_SERDES_REFCLK, TX_SERDES_REFCLK_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3);
|
|
parameter BYPASS = "FALSE";
|
|
parameter [1:0] CTL_RX_BURSTMAX = 2'h3;
|
|
parameter [1:0] CTL_RX_CHAN_EXT = 2'h0;
|
|
parameter [3:0] CTL_RX_LAST_LANE = 4'hB;
|
|
parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF;
|
|
parameter CTL_RX_PACKET_MODE = "TRUE";
|
|
parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0;
|
|
parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2;
|
|
parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0000;
|
|
parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0008;
|
|
parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000;
|
|
parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00;
|
|
parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
|
|
parameter [1:0] CTL_TX_BURSTMAX = 2'h3;
|
|
parameter [2:0] CTL_TX_BURSTSHORT = 3'h1;
|
|
parameter [1:0] CTL_TX_CHAN_EXT = 2'h0;
|
|
parameter CTL_TX_DISABLE_SKIPWORD = "TRUE";
|
|
parameter [6:0] CTL_TX_FC_CALLEN = 7'h00;
|
|
parameter [3:0] CTL_TX_LAST_LANE = 4'hB;
|
|
parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF;
|
|
parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800;
|
|
parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0;
|
|
parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3;
|
|
parameter MODE = "TRUE";
|
|
parameter SIM_VERSION = "2.0";
|
|
parameter TEST_MODE_PIN_CHAR = "FALSE";
|
|
output [15:0] DRP_DO;
|
|
output DRP_RDY;
|
|
output [65:0] RX_BYPASS_DATAOUT00;
|
|
output [65:0] RX_BYPASS_DATAOUT01;
|
|
output [65:0] RX_BYPASS_DATAOUT02;
|
|
output [65:0] RX_BYPASS_DATAOUT03;
|
|
output [65:0] RX_BYPASS_DATAOUT04;
|
|
output [65:0] RX_BYPASS_DATAOUT05;
|
|
output [65:0] RX_BYPASS_DATAOUT06;
|
|
output [65:0] RX_BYPASS_DATAOUT07;
|
|
output [65:0] RX_BYPASS_DATAOUT08;
|
|
output [65:0] RX_BYPASS_DATAOUT09;
|
|
output [65:0] RX_BYPASS_DATAOUT10;
|
|
output [65:0] RX_BYPASS_DATAOUT11;
|
|
output [11:0] RX_BYPASS_ENAOUT;
|
|
output [11:0] RX_BYPASS_IS_AVAILOUT;
|
|
output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT;
|
|
output [11:0] RX_BYPASS_IS_OVERFLOWOUT;
|
|
output [11:0] RX_BYPASS_IS_SYNCEDOUT;
|
|
output [11:0] RX_BYPASS_IS_SYNCWORDOUT;
|
|
output [10:0] RX_CHANOUT0;
|
|
output [10:0] RX_CHANOUT1;
|
|
output [10:0] RX_CHANOUT2;
|
|
output [10:0] RX_CHANOUT3;
|
|
output [127:0] RX_DATAOUT0;
|
|
output [127:0] RX_DATAOUT1;
|
|
output [127:0] RX_DATAOUT2;
|
|
output [127:0] RX_DATAOUT3;
|
|
output RX_ENAOUT0;
|
|
output RX_ENAOUT1;
|
|
output RX_ENAOUT2;
|
|
output RX_ENAOUT3;
|
|
output RX_EOPOUT0;
|
|
output RX_EOPOUT1;
|
|
output RX_EOPOUT2;
|
|
output RX_EOPOUT3;
|
|
output RX_ERROUT0;
|
|
output RX_ERROUT1;
|
|
output RX_ERROUT2;
|
|
output RX_ERROUT3;
|
|
output [3:0] RX_MTYOUT0;
|
|
output [3:0] RX_MTYOUT1;
|
|
output [3:0] RX_MTYOUT2;
|
|
output [3:0] RX_MTYOUT3;
|
|
output RX_OVFOUT;
|
|
output RX_SOPOUT0;
|
|
output RX_SOPOUT1;
|
|
output RX_SOPOUT2;
|
|
output RX_SOPOUT3;
|
|
output STAT_RX_ALIGNED;
|
|
output STAT_RX_ALIGNED_ERR;
|
|
output [11:0] STAT_RX_BAD_TYPE_ERR;
|
|
output STAT_RX_BURSTMAX_ERR;
|
|
output STAT_RX_BURST_ERR;
|
|
output STAT_RX_CRC24_ERR;
|
|
output [11:0] STAT_RX_CRC32_ERR;
|
|
output [11:0] STAT_RX_CRC32_VALID;
|
|
output [11:0] STAT_RX_DESCRAM_ERR;
|
|
output [11:0] STAT_RX_DIAGWORD_INTFSTAT;
|
|
output [11:0] STAT_RX_DIAGWORD_LANESTAT;
|
|
output [255:0] STAT_RX_FC_STAT;
|
|
output [11:0] STAT_RX_FRAMING_ERR;
|
|
output STAT_RX_MEOP_ERR;
|
|
output [11:0] STAT_RX_MF_ERR;
|
|
output [11:0] STAT_RX_MF_LEN_ERR;
|
|
output [11:0] STAT_RX_MF_REPEAT_ERR;
|
|
output STAT_RX_MISALIGNED;
|
|
output STAT_RX_MSOP_ERR;
|
|
output [7:0] STAT_RX_MUBITS;
|
|
output STAT_RX_MUBITS_UPDATED;
|
|
output STAT_RX_OVERFLOW_ERR;
|
|
output STAT_RX_RETRANS_CRC24_ERR;
|
|
output STAT_RX_RETRANS_DISC;
|
|
output [15:0] STAT_RX_RETRANS_LATENCY;
|
|
output STAT_RX_RETRANS_REQ;
|
|
output STAT_RX_RETRANS_RETRY_ERR;
|
|
output [7:0] STAT_RX_RETRANS_SEQ;
|
|
output STAT_RX_RETRANS_SEQ_UPDATED;
|
|
output [2:0] STAT_RX_RETRANS_STATE;
|
|
output [4:0] STAT_RX_RETRANS_SUBSEQ;
|
|
output STAT_RX_RETRANS_WDOG_ERR;
|
|
output STAT_RX_RETRANS_WRAP_ERR;
|
|
output [11:0] STAT_RX_SYNCED;
|
|
output [11:0] STAT_RX_SYNCED_ERR;
|
|
output [11:0] STAT_RX_WORD_SYNC;
|
|
output STAT_TX_BURST_ERR;
|
|
output STAT_TX_ERRINJ_BITERR_DONE;
|
|
output STAT_TX_OVERFLOW_ERR;
|
|
output STAT_TX_RETRANS_BURST_ERR;
|
|
output STAT_TX_RETRANS_BUSY;
|
|
output STAT_TX_RETRANS_RAM_PERROUT;
|
|
output [8:0] STAT_TX_RETRANS_RAM_RADDR;
|
|
output STAT_TX_RETRANS_RAM_RD_B0;
|
|
output STAT_TX_RETRANS_RAM_RD_B1;
|
|
output STAT_TX_RETRANS_RAM_RD_B2;
|
|
output STAT_TX_RETRANS_RAM_RD_B3;
|
|
output [1:0] STAT_TX_RETRANS_RAM_RSEL;
|
|
output [8:0] STAT_TX_RETRANS_RAM_WADDR;
|
|
output [643:0] STAT_TX_RETRANS_RAM_WDATA;
|
|
output STAT_TX_RETRANS_RAM_WE_B0;
|
|
output STAT_TX_RETRANS_RAM_WE_B1;
|
|
output STAT_TX_RETRANS_RAM_WE_B2;
|
|
output STAT_TX_RETRANS_RAM_WE_B3;
|
|
output STAT_TX_UNDERFLOW_ERR;
|
|
output TX_OVFOUT;
|
|
output TX_RDYOUT;
|
|
output [63:0] TX_SERDES_DATA00;
|
|
output [63:0] TX_SERDES_DATA01;
|
|
output [63:0] TX_SERDES_DATA02;
|
|
output [63:0] TX_SERDES_DATA03;
|
|
output [63:0] TX_SERDES_DATA04;
|
|
output [63:0] TX_SERDES_DATA05;
|
|
output [63:0] TX_SERDES_DATA06;
|
|
output [63:0] TX_SERDES_DATA07;
|
|
output [63:0] TX_SERDES_DATA08;
|
|
output [63:0] TX_SERDES_DATA09;
|
|
output [63:0] TX_SERDES_DATA10;
|
|
output [63:0] TX_SERDES_DATA11;
|
|
input CORE_CLK;
|
|
input CTL_RX_FORCE_RESYNC;
|
|
input CTL_RX_RETRANS_ACK;
|
|
input CTL_RX_RETRANS_ENABLE;
|
|
input CTL_RX_RETRANS_ERRIN;
|
|
input CTL_RX_RETRANS_FORCE_REQ;
|
|
input CTL_RX_RETRANS_RESET;
|
|
input CTL_RX_RETRANS_RESET_MODE;
|
|
input CTL_TX_DIAGWORD_INTFSTAT;
|
|
input [11:0] CTL_TX_DIAGWORD_LANESTAT;
|
|
input CTL_TX_ENABLE;
|
|
input CTL_TX_ERRINJ_BITERR_GO;
|
|
input [3:0] CTL_TX_ERRINJ_BITERR_LANE;
|
|
input [255:0] CTL_TX_FC_STAT;
|
|
input [7:0] CTL_TX_MUBITS;
|
|
input CTL_TX_RETRANS_ENABLE;
|
|
input CTL_TX_RETRANS_RAM_PERRIN;
|
|
input [643:0] CTL_TX_RETRANS_RAM_RDATA;
|
|
input CTL_TX_RETRANS_REQ;
|
|
input CTL_TX_RETRANS_REQ_VALID;
|
|
input [11:0] CTL_TX_RLIM_DELTA;
|
|
input CTL_TX_RLIM_ENABLE;
|
|
input [7:0] CTL_TX_RLIM_INTV;
|
|
input [11:0] CTL_TX_RLIM_MAX;
|
|
input [9:0] DRP_ADDR;
|
|
input DRP_CLK;
|
|
input [15:0] DRP_DI;
|
|
input DRP_EN;
|
|
input DRP_WE;
|
|
input LBUS_CLK;
|
|
input RX_BYPASS_FORCE_REALIGNIN;
|
|
input RX_BYPASS_RDIN;
|
|
input RX_RESET;
|
|
input [11:0] RX_SERDES_CLK;
|
|
input [63:0] RX_SERDES_DATA00;
|
|
input [63:0] RX_SERDES_DATA01;
|
|
input [63:0] RX_SERDES_DATA02;
|
|
input [63:0] RX_SERDES_DATA03;
|
|
input [63:0] RX_SERDES_DATA04;
|
|
input [63:0] RX_SERDES_DATA05;
|
|
input [63:0] RX_SERDES_DATA06;
|
|
input [63:0] RX_SERDES_DATA07;
|
|
input [63:0] RX_SERDES_DATA08;
|
|
input [63:0] RX_SERDES_DATA09;
|
|
input [63:0] RX_SERDES_DATA10;
|
|
input [63:0] RX_SERDES_DATA11;
|
|
input [11:0] RX_SERDES_RESET;
|
|
input TX_BCTLIN0;
|
|
input TX_BCTLIN1;
|
|
input TX_BCTLIN2;
|
|
input TX_BCTLIN3;
|
|
input [11:0] TX_BYPASS_CTRLIN;
|
|
input [63:0] TX_BYPASS_DATAIN00;
|
|
input [63:0] TX_BYPASS_DATAIN01;
|
|
input [63:0] TX_BYPASS_DATAIN02;
|
|
input [63:0] TX_BYPASS_DATAIN03;
|
|
input [63:0] TX_BYPASS_DATAIN04;
|
|
input [63:0] TX_BYPASS_DATAIN05;
|
|
input [63:0] TX_BYPASS_DATAIN06;
|
|
input [63:0] TX_BYPASS_DATAIN07;
|
|
input [63:0] TX_BYPASS_DATAIN08;
|
|
input [63:0] TX_BYPASS_DATAIN09;
|
|
input [63:0] TX_BYPASS_DATAIN10;
|
|
input [63:0] TX_BYPASS_DATAIN11;
|
|
input TX_BYPASS_ENAIN;
|
|
input [7:0] TX_BYPASS_GEARBOX_SEQIN;
|
|
input [3:0] TX_BYPASS_MFRAMER_STATEIN;
|
|
input [10:0] TX_CHANIN0;
|
|
input [10:0] TX_CHANIN1;
|
|
input [10:0] TX_CHANIN2;
|
|
input [10:0] TX_CHANIN3;
|
|
input [127:0] TX_DATAIN0;
|
|
input [127:0] TX_DATAIN1;
|
|
input [127:0] TX_DATAIN2;
|
|
input [127:0] TX_DATAIN3;
|
|
input TX_ENAIN0;
|
|
input TX_ENAIN1;
|
|
input TX_ENAIN2;
|
|
input TX_ENAIN3;
|
|
input TX_EOPIN0;
|
|
input TX_EOPIN1;
|
|
input TX_EOPIN2;
|
|
input TX_EOPIN3;
|
|
input TX_ERRIN0;
|
|
input TX_ERRIN1;
|
|
input TX_ERRIN2;
|
|
input TX_ERRIN3;
|
|
input [3:0] TX_MTYIN0;
|
|
input [3:0] TX_MTYIN1;
|
|
input [3:0] TX_MTYIN2;
|
|
input [3:0] TX_MTYIN3;
|
|
input TX_RESET;
|
|
input TX_SERDES_REFCLK;
|
|
input TX_SERDES_REFCLK_RESET;
|
|
input TX_SOPIN0;
|
|
input TX_SOPIN1;
|
|
input TX_SOPIN2;
|
|
input TX_SOPIN3;
|
|
endmodule
|
|
|
|
module ILKNE4(DRP_DO, DRP_RDY, RX_BYPASS_DATAOUT00, RX_BYPASS_DATAOUT01, RX_BYPASS_DATAOUT02, RX_BYPASS_DATAOUT03, RX_BYPASS_DATAOUT04, RX_BYPASS_DATAOUT05, RX_BYPASS_DATAOUT06, RX_BYPASS_DATAOUT07, RX_BYPASS_DATAOUT08, RX_BYPASS_DATAOUT09, RX_BYPASS_DATAOUT10, RX_BYPASS_DATAOUT11, RX_BYPASS_ENAOUT, RX_BYPASS_IS_AVAILOUT, RX_BYPASS_IS_BADLYFRAMEDOUT, RX_BYPASS_IS_OVERFLOWOUT, RX_BYPASS_IS_SYNCEDOUT, RX_BYPASS_IS_SYNCWORDOUT, RX_CHANOUT0
|
|
, RX_CHANOUT1, RX_CHANOUT2, RX_CHANOUT3, RX_DATAOUT0, RX_DATAOUT1, RX_DATAOUT2, RX_DATAOUT3, RX_ENAOUT0, RX_ENAOUT1, RX_ENAOUT2, RX_ENAOUT3, RX_EOPOUT0, RX_EOPOUT1, RX_EOPOUT2, RX_EOPOUT3, RX_ERROUT0, RX_ERROUT1, RX_ERROUT2, RX_ERROUT3, RX_MTYOUT0, RX_MTYOUT1
|
|
, RX_MTYOUT2, RX_MTYOUT3, RX_OVFOUT, RX_SOPOUT0, RX_SOPOUT1, RX_SOPOUT2, RX_SOPOUT3, STAT_RX_ALIGNED, STAT_RX_ALIGNED_ERR, STAT_RX_BAD_TYPE_ERR, STAT_RX_BURSTMAX_ERR, STAT_RX_BURST_ERR, STAT_RX_CRC24_ERR, STAT_RX_CRC32_ERR, STAT_RX_CRC32_VALID, STAT_RX_DESCRAM_ERR, STAT_RX_DIAGWORD_INTFSTAT, STAT_RX_DIAGWORD_LANESTAT, STAT_RX_FC_STAT, STAT_RX_FRAMING_ERR, STAT_RX_MEOP_ERR
|
|
, STAT_RX_MF_ERR, STAT_RX_MF_LEN_ERR, STAT_RX_MF_REPEAT_ERR, STAT_RX_MISALIGNED, STAT_RX_MSOP_ERR, STAT_RX_MUBITS, STAT_RX_MUBITS_UPDATED, STAT_RX_OVERFLOW_ERR, STAT_RX_RETRANS_CRC24_ERR, STAT_RX_RETRANS_DISC, STAT_RX_RETRANS_LATENCY, STAT_RX_RETRANS_REQ, STAT_RX_RETRANS_RETRY_ERR, STAT_RX_RETRANS_SEQ, STAT_RX_RETRANS_SEQ_UPDATED, STAT_RX_RETRANS_STATE, STAT_RX_RETRANS_SUBSEQ, STAT_RX_RETRANS_WDOG_ERR, STAT_RX_RETRANS_WRAP_ERR, STAT_RX_SYNCED, STAT_RX_SYNCED_ERR
|
|
, STAT_RX_WORD_SYNC, STAT_TX_BURST_ERR, STAT_TX_ERRINJ_BITERR_DONE, STAT_TX_OVERFLOW_ERR, STAT_TX_RETRANS_BURST_ERR, STAT_TX_RETRANS_BUSY, STAT_TX_RETRANS_RAM_PERROUT, STAT_TX_RETRANS_RAM_RADDR, STAT_TX_RETRANS_RAM_RD_B0, STAT_TX_RETRANS_RAM_RD_B1, STAT_TX_RETRANS_RAM_RD_B2, STAT_TX_RETRANS_RAM_RD_B3, STAT_TX_RETRANS_RAM_RSEL, STAT_TX_RETRANS_RAM_WADDR, STAT_TX_RETRANS_RAM_WDATA, STAT_TX_RETRANS_RAM_WE_B0, STAT_TX_RETRANS_RAM_WE_B1, STAT_TX_RETRANS_RAM_WE_B2, STAT_TX_RETRANS_RAM_WE_B3, STAT_TX_UNDERFLOW_ERR, TX_OVFOUT
|
|
, TX_RDYOUT, TX_SERDES_DATA00, TX_SERDES_DATA01, TX_SERDES_DATA02, TX_SERDES_DATA03, TX_SERDES_DATA04, TX_SERDES_DATA05, TX_SERDES_DATA06, TX_SERDES_DATA07, TX_SERDES_DATA08, TX_SERDES_DATA09, TX_SERDES_DATA10, TX_SERDES_DATA11, CORE_CLK, CTL_RX_FORCE_RESYNC, CTL_RX_RETRANS_ACK, CTL_RX_RETRANS_ENABLE, CTL_RX_RETRANS_ERRIN, CTL_RX_RETRANS_FORCE_REQ, CTL_RX_RETRANS_RESET, CTL_RX_RETRANS_RESET_MODE
|
|
, CTL_TX_DIAGWORD_INTFSTAT, CTL_TX_DIAGWORD_LANESTAT, CTL_TX_ENABLE, CTL_TX_ERRINJ_BITERR_GO, CTL_TX_ERRINJ_BITERR_LANE, CTL_TX_FC_STAT, CTL_TX_MUBITS, CTL_TX_RETRANS_ENABLE, CTL_TX_RETRANS_RAM_PERRIN, CTL_TX_RETRANS_RAM_RDATA, CTL_TX_RETRANS_REQ, CTL_TX_RETRANS_REQ_VALID, CTL_TX_RLIM_DELTA, CTL_TX_RLIM_ENABLE, CTL_TX_RLIM_INTV, CTL_TX_RLIM_MAX, DRP_ADDR, DRP_CLK, DRP_DI, DRP_EN, DRP_WE
|
|
, LBUS_CLK, RX_BYPASS_FORCE_REALIGNIN, RX_BYPASS_RDIN, RX_RESET, RX_SERDES_CLK, RX_SERDES_DATA00, RX_SERDES_DATA01, RX_SERDES_DATA02, RX_SERDES_DATA03, RX_SERDES_DATA04, RX_SERDES_DATA05, RX_SERDES_DATA06, RX_SERDES_DATA07, RX_SERDES_DATA08, RX_SERDES_DATA09, RX_SERDES_DATA10, RX_SERDES_DATA11, RX_SERDES_RESET, TX_BCTLIN0, TX_BCTLIN1, TX_BCTLIN2
|
|
, TX_BCTLIN3, TX_BYPASS_CTRLIN, TX_BYPASS_DATAIN00, TX_BYPASS_DATAIN01, TX_BYPASS_DATAIN02, TX_BYPASS_DATAIN03, TX_BYPASS_DATAIN04, TX_BYPASS_DATAIN05, TX_BYPASS_DATAIN06, TX_BYPASS_DATAIN07, TX_BYPASS_DATAIN08, TX_BYPASS_DATAIN09, TX_BYPASS_DATAIN10, TX_BYPASS_DATAIN11, TX_BYPASS_ENAIN, TX_BYPASS_GEARBOX_SEQIN, TX_BYPASS_MFRAMER_STATEIN, TX_CHANIN0, TX_CHANIN1, TX_CHANIN2, TX_CHANIN3
|
|
, TX_DATAIN0, TX_DATAIN1, TX_DATAIN2, TX_DATAIN3, TX_ENAIN0, TX_ENAIN1, TX_ENAIN2, TX_ENAIN3, TX_EOPIN0, TX_EOPIN1, TX_EOPIN2, TX_EOPIN3, TX_ERRIN0, TX_ERRIN1, TX_ERRIN2, TX_ERRIN3, TX_MTYIN0, TX_MTYIN1, TX_MTYIN2, TX_MTYIN3, TX_RESET
|
|
, TX_SERDES_REFCLK, TX_SERDES_REFCLK_RESET, TX_SOPIN0, TX_SOPIN1, TX_SOPIN2, TX_SOPIN3);
|
|
parameter BYPASS = "FALSE";
|
|
parameter [1:0] CTL_RX_BURSTMAX = 2'h3;
|
|
parameter [1:0] CTL_RX_CHAN_EXT = 2'h0;
|
|
parameter [3:0] CTL_RX_LAST_LANE = 4'hB;
|
|
parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF;
|
|
parameter CTL_RX_PACKET_MODE = "FALSE";
|
|
parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0;
|
|
parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2;
|
|
parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0009;
|
|
parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0000;
|
|
parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000;
|
|
parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00;
|
|
parameter CTL_TEST_MODE_PIN_CHAR = "FALSE";
|
|
parameter [1:0] CTL_TX_BURSTMAX = 2'h3;
|
|
parameter [2:0] CTL_TX_BURSTSHORT = 3'h1;
|
|
parameter [1:0] CTL_TX_CHAN_EXT = 2'h0;
|
|
parameter CTL_TX_DISABLE_SKIPWORD = "FALSE";
|
|
parameter [3:0] CTL_TX_FC_CALLEN = 4'hF;
|
|
parameter [3:0] CTL_TX_LAST_LANE = 4'hB;
|
|
parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF;
|
|
parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800;
|
|
parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0;
|
|
parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3;
|
|
parameter MODE = "TRUE";
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter TEST_MODE_PIN_CHAR = "FALSE";
|
|
output [15:0] DRP_DO;
|
|
output DRP_RDY;
|
|
output [65:0] RX_BYPASS_DATAOUT00;
|
|
output [65:0] RX_BYPASS_DATAOUT01;
|
|
output [65:0] RX_BYPASS_DATAOUT02;
|
|
output [65:0] RX_BYPASS_DATAOUT03;
|
|
output [65:0] RX_BYPASS_DATAOUT04;
|
|
output [65:0] RX_BYPASS_DATAOUT05;
|
|
output [65:0] RX_BYPASS_DATAOUT06;
|
|
output [65:0] RX_BYPASS_DATAOUT07;
|
|
output [65:0] RX_BYPASS_DATAOUT08;
|
|
output [65:0] RX_BYPASS_DATAOUT09;
|
|
output [65:0] RX_BYPASS_DATAOUT10;
|
|
output [65:0] RX_BYPASS_DATAOUT11;
|
|
output [11:0] RX_BYPASS_ENAOUT;
|
|
output [11:0] RX_BYPASS_IS_AVAILOUT;
|
|
output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT;
|
|
output [11:0] RX_BYPASS_IS_OVERFLOWOUT;
|
|
output [11:0] RX_BYPASS_IS_SYNCEDOUT;
|
|
output [11:0] RX_BYPASS_IS_SYNCWORDOUT;
|
|
output [10:0] RX_CHANOUT0;
|
|
output [10:0] RX_CHANOUT1;
|
|
output [10:0] RX_CHANOUT2;
|
|
output [10:0] RX_CHANOUT3;
|
|
output [127:0] RX_DATAOUT0;
|
|
output [127:0] RX_DATAOUT1;
|
|
output [127:0] RX_DATAOUT2;
|
|
output [127:0] RX_DATAOUT3;
|
|
output RX_ENAOUT0;
|
|
output RX_ENAOUT1;
|
|
output RX_ENAOUT2;
|
|
output RX_ENAOUT3;
|
|
output RX_EOPOUT0;
|
|
output RX_EOPOUT1;
|
|
output RX_EOPOUT2;
|
|
output RX_EOPOUT3;
|
|
output RX_ERROUT0;
|
|
output RX_ERROUT1;
|
|
output RX_ERROUT2;
|
|
output RX_ERROUT3;
|
|
output [3:0] RX_MTYOUT0;
|
|
output [3:0] RX_MTYOUT1;
|
|
output [3:0] RX_MTYOUT2;
|
|
output [3:0] RX_MTYOUT3;
|
|
output RX_OVFOUT;
|
|
output RX_SOPOUT0;
|
|
output RX_SOPOUT1;
|
|
output RX_SOPOUT2;
|
|
output RX_SOPOUT3;
|
|
output STAT_RX_ALIGNED;
|
|
output STAT_RX_ALIGNED_ERR;
|
|
output [11:0] STAT_RX_BAD_TYPE_ERR;
|
|
output STAT_RX_BURSTMAX_ERR;
|
|
output STAT_RX_BURST_ERR;
|
|
output STAT_RX_CRC24_ERR;
|
|
output [11:0] STAT_RX_CRC32_ERR;
|
|
output [11:0] STAT_RX_CRC32_VALID;
|
|
output [11:0] STAT_RX_DESCRAM_ERR;
|
|
output [11:0] STAT_RX_DIAGWORD_INTFSTAT;
|
|
output [11:0] STAT_RX_DIAGWORD_LANESTAT;
|
|
output [255:0] STAT_RX_FC_STAT;
|
|
output [11:0] STAT_RX_FRAMING_ERR;
|
|
output STAT_RX_MEOP_ERR;
|
|
output [11:0] STAT_RX_MF_ERR;
|
|
output [11:0] STAT_RX_MF_LEN_ERR;
|
|
output [11:0] STAT_RX_MF_REPEAT_ERR;
|
|
output STAT_RX_MISALIGNED;
|
|
output STAT_RX_MSOP_ERR;
|
|
output [7:0] STAT_RX_MUBITS;
|
|
output STAT_RX_MUBITS_UPDATED;
|
|
output STAT_RX_OVERFLOW_ERR;
|
|
output STAT_RX_RETRANS_CRC24_ERR;
|
|
output STAT_RX_RETRANS_DISC;
|
|
output [15:0] STAT_RX_RETRANS_LATENCY;
|
|
output STAT_RX_RETRANS_REQ;
|
|
output STAT_RX_RETRANS_RETRY_ERR;
|
|
output [7:0] STAT_RX_RETRANS_SEQ;
|
|
output STAT_RX_RETRANS_SEQ_UPDATED;
|
|
output [2:0] STAT_RX_RETRANS_STATE;
|
|
output [4:0] STAT_RX_RETRANS_SUBSEQ;
|
|
output STAT_RX_RETRANS_WDOG_ERR;
|
|
output STAT_RX_RETRANS_WRAP_ERR;
|
|
output [11:0] STAT_RX_SYNCED;
|
|
output [11:0] STAT_RX_SYNCED_ERR;
|
|
output [11:0] STAT_RX_WORD_SYNC;
|
|
output STAT_TX_BURST_ERR;
|
|
output STAT_TX_ERRINJ_BITERR_DONE;
|
|
output STAT_TX_OVERFLOW_ERR;
|
|
output STAT_TX_RETRANS_BURST_ERR;
|
|
output STAT_TX_RETRANS_BUSY;
|
|
output STAT_TX_RETRANS_RAM_PERROUT;
|
|
output [8:0] STAT_TX_RETRANS_RAM_RADDR;
|
|
output STAT_TX_RETRANS_RAM_RD_B0;
|
|
output STAT_TX_RETRANS_RAM_RD_B1;
|
|
output STAT_TX_RETRANS_RAM_RD_B2;
|
|
output STAT_TX_RETRANS_RAM_RD_B3;
|
|
output [1:0] STAT_TX_RETRANS_RAM_RSEL;
|
|
output [8:0] STAT_TX_RETRANS_RAM_WADDR;
|
|
output [643:0] STAT_TX_RETRANS_RAM_WDATA;
|
|
output STAT_TX_RETRANS_RAM_WE_B0;
|
|
output STAT_TX_RETRANS_RAM_WE_B1;
|
|
output STAT_TX_RETRANS_RAM_WE_B2;
|
|
output STAT_TX_RETRANS_RAM_WE_B3;
|
|
output STAT_TX_UNDERFLOW_ERR;
|
|
output TX_OVFOUT;
|
|
output TX_RDYOUT;
|
|
output [63:0] TX_SERDES_DATA00;
|
|
output [63:0] TX_SERDES_DATA01;
|
|
output [63:0] TX_SERDES_DATA02;
|
|
output [63:0] TX_SERDES_DATA03;
|
|
output [63:0] TX_SERDES_DATA04;
|
|
output [63:0] TX_SERDES_DATA05;
|
|
output [63:0] TX_SERDES_DATA06;
|
|
output [63:0] TX_SERDES_DATA07;
|
|
output [63:0] TX_SERDES_DATA08;
|
|
output [63:0] TX_SERDES_DATA09;
|
|
output [63:0] TX_SERDES_DATA10;
|
|
output [63:0] TX_SERDES_DATA11;
|
|
input CORE_CLK;
|
|
input CTL_RX_FORCE_RESYNC;
|
|
input CTL_RX_RETRANS_ACK;
|
|
input CTL_RX_RETRANS_ENABLE;
|
|
input CTL_RX_RETRANS_ERRIN;
|
|
input CTL_RX_RETRANS_FORCE_REQ;
|
|
input CTL_RX_RETRANS_RESET;
|
|
input CTL_RX_RETRANS_RESET_MODE;
|
|
input CTL_TX_DIAGWORD_INTFSTAT;
|
|
input [11:0] CTL_TX_DIAGWORD_LANESTAT;
|
|
input CTL_TX_ENABLE;
|
|
input CTL_TX_ERRINJ_BITERR_GO;
|
|
input [3:0] CTL_TX_ERRINJ_BITERR_LANE;
|
|
input [255:0] CTL_TX_FC_STAT;
|
|
input [7:0] CTL_TX_MUBITS;
|
|
input CTL_TX_RETRANS_ENABLE;
|
|
input CTL_TX_RETRANS_RAM_PERRIN;
|
|
input [643:0] CTL_TX_RETRANS_RAM_RDATA;
|
|
input CTL_TX_RETRANS_REQ;
|
|
input CTL_TX_RETRANS_REQ_VALID;
|
|
input [11:0] CTL_TX_RLIM_DELTA;
|
|
input CTL_TX_RLIM_ENABLE;
|
|
input [7:0] CTL_TX_RLIM_INTV;
|
|
input [11:0] CTL_TX_RLIM_MAX;
|
|
input [9:0] DRP_ADDR;
|
|
input DRP_CLK;
|
|
input [15:0] DRP_DI;
|
|
input DRP_EN;
|
|
input DRP_WE;
|
|
input LBUS_CLK;
|
|
input RX_BYPASS_FORCE_REALIGNIN;
|
|
input RX_BYPASS_RDIN;
|
|
input RX_RESET;
|
|
input [11:0] RX_SERDES_CLK;
|
|
input [63:0] RX_SERDES_DATA00;
|
|
input [63:0] RX_SERDES_DATA01;
|
|
input [63:0] RX_SERDES_DATA02;
|
|
input [63:0] RX_SERDES_DATA03;
|
|
input [63:0] RX_SERDES_DATA04;
|
|
input [63:0] RX_SERDES_DATA05;
|
|
input [63:0] RX_SERDES_DATA06;
|
|
input [63:0] RX_SERDES_DATA07;
|
|
input [63:0] RX_SERDES_DATA08;
|
|
input [63:0] RX_SERDES_DATA09;
|
|
input [63:0] RX_SERDES_DATA10;
|
|
input [63:0] RX_SERDES_DATA11;
|
|
input [11:0] RX_SERDES_RESET;
|
|
input TX_BCTLIN0;
|
|
input TX_BCTLIN1;
|
|
input TX_BCTLIN2;
|
|
input TX_BCTLIN3;
|
|
input [11:0] TX_BYPASS_CTRLIN;
|
|
input [63:0] TX_BYPASS_DATAIN00;
|
|
input [63:0] TX_BYPASS_DATAIN01;
|
|
input [63:0] TX_BYPASS_DATAIN02;
|
|
input [63:0] TX_BYPASS_DATAIN03;
|
|
input [63:0] TX_BYPASS_DATAIN04;
|
|
input [63:0] TX_BYPASS_DATAIN05;
|
|
input [63:0] TX_BYPASS_DATAIN06;
|
|
input [63:0] TX_BYPASS_DATAIN07;
|
|
input [63:0] TX_BYPASS_DATAIN08;
|
|
input [63:0] TX_BYPASS_DATAIN09;
|
|
input [63:0] TX_BYPASS_DATAIN10;
|
|
input [63:0] TX_BYPASS_DATAIN11;
|
|
input TX_BYPASS_ENAIN;
|
|
input [7:0] TX_BYPASS_GEARBOX_SEQIN;
|
|
input [3:0] TX_BYPASS_MFRAMER_STATEIN;
|
|
input [10:0] TX_CHANIN0;
|
|
input [10:0] TX_CHANIN1;
|
|
input [10:0] TX_CHANIN2;
|
|
input [10:0] TX_CHANIN3;
|
|
input [127:0] TX_DATAIN0;
|
|
input [127:0] TX_DATAIN1;
|
|
input [127:0] TX_DATAIN2;
|
|
input [127:0] TX_DATAIN3;
|
|
input TX_ENAIN0;
|
|
input TX_ENAIN1;
|
|
input TX_ENAIN2;
|
|
input TX_ENAIN3;
|
|
input TX_EOPIN0;
|
|
input TX_EOPIN1;
|
|
input TX_EOPIN2;
|
|
input TX_EOPIN3;
|
|
input TX_ERRIN0;
|
|
input TX_ERRIN1;
|
|
input TX_ERRIN2;
|
|
input TX_ERRIN3;
|
|
input [3:0] TX_MTYIN0;
|
|
input [3:0] TX_MTYIN1;
|
|
input [3:0] TX_MTYIN2;
|
|
input [3:0] TX_MTYIN3;
|
|
input TX_RESET;
|
|
input TX_SERDES_REFCLK;
|
|
input TX_SERDES_REFCLK_RESET;
|
|
input TX_SOPIN0;
|
|
input TX_SOPIN1;
|
|
input TX_SOPIN2;
|
|
input TX_SOPIN3;
|
|
endmodule
|
|
|
|
(* keep *)
|
|
module VCU(VCUPLARREADYAXILITEAPB, VCUPLAWREADYAXILITEAPB, VCUPLBRESPAXILITEAPB, VCUPLBVALIDAXILITEAPB, VCUPLCORESTATUSCLKPLL, VCUPLDECARADDR0, VCUPLDECARADDR1, VCUPLDECARBURST0, VCUPLDECARBURST1, VCUPLDECARCACHE0, VCUPLDECARCACHE1, VCUPLDECARID0, VCUPLDECARID1, VCUPLDECARLEN0, VCUPLDECARLEN1, VCUPLDECARPROT0, VCUPLDECARPROT1, VCUPLDECARQOS0, VCUPLDECARQOS1, VCUPLDECARSIZE0, VCUPLDECARSIZE1
|
|
, VCUPLDECARVALID0, VCUPLDECARVALID1, VCUPLDECAWADDR0, VCUPLDECAWADDR1, VCUPLDECAWBURST0, VCUPLDECAWBURST1, VCUPLDECAWCACHE0, VCUPLDECAWCACHE1, VCUPLDECAWID0, VCUPLDECAWID1, VCUPLDECAWLEN0, VCUPLDECAWLEN1, VCUPLDECAWPROT0, VCUPLDECAWPROT1, VCUPLDECAWQOS0, VCUPLDECAWQOS1, VCUPLDECAWSIZE0, VCUPLDECAWSIZE1, VCUPLDECAWVALID0, VCUPLDECAWVALID1, VCUPLDECBREADY0
|
|
, VCUPLDECBREADY1, VCUPLDECRREADY0, VCUPLDECRREADY1, VCUPLDECWDATA0, VCUPLDECWDATA1, VCUPLDECWLAST0, VCUPLDECWLAST1, VCUPLDECWVALID0, VCUPLDECWVALID1, VCUPLENCALL2CADDR, VCUPLENCALL2CRVALID, VCUPLENCALL2CWDATA, VCUPLENCALL2CWVALID, VCUPLENCARADDR0, VCUPLENCARADDR1, VCUPLENCARBURST0, VCUPLENCARBURST1, VCUPLENCARCACHE0, VCUPLENCARCACHE1, VCUPLENCARID0, VCUPLENCARID1
|
|
, VCUPLENCARLEN0, VCUPLENCARLEN1, VCUPLENCARPROT0, VCUPLENCARPROT1, VCUPLENCARQOS0, VCUPLENCARQOS1, VCUPLENCARSIZE0, VCUPLENCARSIZE1, VCUPLENCARVALID0, VCUPLENCARVALID1, VCUPLENCAWADDR0, VCUPLENCAWADDR1, VCUPLENCAWBURST0, VCUPLENCAWBURST1, VCUPLENCAWCACHE0, VCUPLENCAWCACHE1, VCUPLENCAWID0, VCUPLENCAWID1, VCUPLENCAWLEN0, VCUPLENCAWLEN1, VCUPLENCAWPROT0
|
|
, VCUPLENCAWPROT1, VCUPLENCAWQOS0, VCUPLENCAWQOS1, VCUPLENCAWSIZE0, VCUPLENCAWSIZE1, VCUPLENCAWVALID0, VCUPLENCAWVALID1, VCUPLENCBREADY0, VCUPLENCBREADY1, VCUPLENCRREADY0, VCUPLENCRREADY1, VCUPLENCWDATA0, VCUPLENCWDATA1, VCUPLENCWLAST0, VCUPLENCWLAST1, VCUPLENCWVALID0, VCUPLENCWVALID1, VCUPLMCUMAXIICDCARADDR, VCUPLMCUMAXIICDCARBURST, VCUPLMCUMAXIICDCARCACHE, VCUPLMCUMAXIICDCARID
|
|
, VCUPLMCUMAXIICDCARLEN, VCUPLMCUMAXIICDCARLOCK, VCUPLMCUMAXIICDCARPROT, VCUPLMCUMAXIICDCARQOS, VCUPLMCUMAXIICDCARSIZE, VCUPLMCUMAXIICDCARVALID, VCUPLMCUMAXIICDCAWADDR, VCUPLMCUMAXIICDCAWBURST, VCUPLMCUMAXIICDCAWCACHE, VCUPLMCUMAXIICDCAWID, VCUPLMCUMAXIICDCAWLEN, VCUPLMCUMAXIICDCAWLOCK, VCUPLMCUMAXIICDCAWPROT, VCUPLMCUMAXIICDCAWQOS, VCUPLMCUMAXIICDCAWSIZE, VCUPLMCUMAXIICDCAWVALID, VCUPLMCUMAXIICDCBREADY, VCUPLMCUMAXIICDCRREADY, VCUPLMCUMAXIICDCWDATA, VCUPLMCUMAXIICDCWLAST, VCUPLMCUMAXIICDCWSTRB
|
|
, VCUPLMCUMAXIICDCWVALID, VCUPLMCUSTATUSCLKPLL, VCUPLPINTREQ, VCUPLPLLSTATUSPLLLOCK, VCUPLPWRSUPPLYSTATUSVCCAUX, VCUPLPWRSUPPLYSTATUSVCUINT, VCUPLRDATAAXILITEAPB, VCUPLRRESPAXILITEAPB, VCUPLRVALIDAXILITEAPB, VCUPLWREADYAXILITEAPB, INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD, PLVCUARADDRAXILITEAPB, PLVCUARPROTAXILITEAPB, PLVCUARVALIDAXILITEAPB, PLVCUAWADDRAXILITEAPB, PLVCUAWPROTAXILITEAPB, PLVCUAWVALIDAXILITEAPB, PLVCUAXIDECCLK, PLVCUAXIENCCLK, PLVCUAXILITECLK, PLVCUAXIMCUCLK
|
|
, PLVCUBREADYAXILITEAPB, PLVCUCORECLK, PLVCUDECARREADY0, PLVCUDECARREADY1, PLVCUDECAWREADY0, PLVCUDECAWREADY1, PLVCUDECBID0, PLVCUDECBID1, PLVCUDECBRESP0, PLVCUDECBRESP1, PLVCUDECBVALID0, PLVCUDECBVALID1, PLVCUDECRDATA0, PLVCUDECRDATA1, PLVCUDECRID0, PLVCUDECRID1, PLVCUDECRLAST0, PLVCUDECRLAST1, PLVCUDECRRESP0, PLVCUDECRRESP1, PLVCUDECRVALID0
|
|
, PLVCUDECRVALID1, PLVCUDECWREADY0, PLVCUDECWREADY1, PLVCUENCALL2CRDATA, PLVCUENCALL2CRREADY, PLVCUENCARREADY0, PLVCUENCARREADY1, PLVCUENCAWREADY0, PLVCUENCAWREADY1, PLVCUENCBID0, PLVCUENCBID1, PLVCUENCBRESP0, PLVCUENCBRESP1, PLVCUENCBVALID0, PLVCUENCBVALID1, PLVCUENCL2CCLK, PLVCUENCRDATA0, PLVCUENCRDATA1, PLVCUENCRID0, PLVCUENCRID1, PLVCUENCRLAST0
|
|
, PLVCUENCRLAST1, PLVCUENCRRESP0, PLVCUENCRRESP1, PLVCUENCRVALID0, PLVCUENCRVALID1, PLVCUENCWREADY0, PLVCUENCWREADY1, PLVCUMCUCLK, PLVCUMCUMAXIICDCARREADY, PLVCUMCUMAXIICDCAWREADY, PLVCUMCUMAXIICDCBID, PLVCUMCUMAXIICDCBRESP, PLVCUMCUMAXIICDCBVALID, PLVCUMCUMAXIICDCRDATA, PLVCUMCUMAXIICDCRID, PLVCUMCUMAXIICDCRLAST, PLVCUMCUMAXIICDCRRESP, PLVCUMCUMAXIICDCRVALID, PLVCUMCUMAXIICDCWREADY, PLVCUPLLREFCLKPL, PLVCURAWRSTN
|
|
, PLVCURREADYAXILITEAPB, PLVCUWDATAAXILITEAPB, PLVCUWSTRBAXILITEAPB, PLVCUWVALIDAXILITEAPB);
|
|
parameter integer CORECLKREQ = 667;
|
|
parameter integer DECHORRESOLUTION = 3840;
|
|
parameter DECODERCHROMAFORMAT = "4_2_2";
|
|
parameter DECODERCODING = "H.265";
|
|
parameter integer DECODERCOLORDEPTH = 10;
|
|
parameter integer DECODERNUMCORES = 2;
|
|
parameter integer DECVERTRESOLUTION = 2160;
|
|
parameter ENABLEDECODER = "TRUE";
|
|
parameter ENABLEENCODER = "TRUE";
|
|
parameter integer ENCHORRESOLUTION = 3840;
|
|
parameter ENCODERCHROMAFORMAT = "4_2_2";
|
|
parameter ENCODERCODING = "H.265";
|
|
parameter integer ENCODERCOLORDEPTH = 10;
|
|
parameter integer ENCODERNUMCORES = 4;
|
|
parameter integer ENCVERTRESOLUTION = 2160;
|
|
output VCUPLARREADYAXILITEAPB;
|
|
output VCUPLAWREADYAXILITEAPB;
|
|
output [1:0] VCUPLBRESPAXILITEAPB;
|
|
output VCUPLBVALIDAXILITEAPB;
|
|
output VCUPLCORESTATUSCLKPLL;
|
|
output [43:0] VCUPLDECARADDR0;
|
|
output [43:0] VCUPLDECARADDR1;
|
|
output [1:0] VCUPLDECARBURST0;
|
|
output [1:0] VCUPLDECARBURST1;
|
|
output [3:0] VCUPLDECARCACHE0;
|
|
output [3:0] VCUPLDECARCACHE1;
|
|
output [3:0] VCUPLDECARID0;
|
|
output [3:0] VCUPLDECARID1;
|
|
output [7:0] VCUPLDECARLEN0;
|
|
output [7:0] VCUPLDECARLEN1;
|
|
output VCUPLDECARPROT0;
|
|
output VCUPLDECARPROT1;
|
|
output [3:0] VCUPLDECARQOS0;
|
|
output [3:0] VCUPLDECARQOS1;
|
|
output [2:0] VCUPLDECARSIZE0;
|
|
output [2:0] VCUPLDECARSIZE1;
|
|
output VCUPLDECARVALID0;
|
|
output VCUPLDECARVALID1;
|
|
output [43:0] VCUPLDECAWADDR0;
|
|
output [43:0] VCUPLDECAWADDR1;
|
|
output [1:0] VCUPLDECAWBURST0;
|
|
output [1:0] VCUPLDECAWBURST1;
|
|
output [3:0] VCUPLDECAWCACHE0;
|
|
output [3:0] VCUPLDECAWCACHE1;
|
|
output [3:0] VCUPLDECAWID0;
|
|
output [3:0] VCUPLDECAWID1;
|
|
output [7:0] VCUPLDECAWLEN0;
|
|
output [7:0] VCUPLDECAWLEN1;
|
|
output VCUPLDECAWPROT0;
|
|
output VCUPLDECAWPROT1;
|
|
output [3:0] VCUPLDECAWQOS0;
|
|
output [3:0] VCUPLDECAWQOS1;
|
|
output [2:0] VCUPLDECAWSIZE0;
|
|
output [2:0] VCUPLDECAWSIZE1;
|
|
output VCUPLDECAWVALID0;
|
|
output VCUPLDECAWVALID1;
|
|
output VCUPLDECBREADY0;
|
|
output VCUPLDECBREADY1;
|
|
output VCUPLDECRREADY0;
|
|
output VCUPLDECRREADY1;
|
|
output [127:0] VCUPLDECWDATA0;
|
|
output [127:0] VCUPLDECWDATA1;
|
|
output VCUPLDECWLAST0;
|
|
output VCUPLDECWLAST1;
|
|
output VCUPLDECWVALID0;
|
|
output VCUPLDECWVALID1;
|
|
output [16:0] VCUPLENCALL2CADDR;
|
|
output VCUPLENCALL2CRVALID;
|
|
output [319:0] VCUPLENCALL2CWDATA;
|
|
output VCUPLENCALL2CWVALID;
|
|
output [43:0] VCUPLENCARADDR0;
|
|
output [43:0] VCUPLENCARADDR1;
|
|
output [1:0] VCUPLENCARBURST0;
|
|
output [1:0] VCUPLENCARBURST1;
|
|
output [3:0] VCUPLENCARCACHE0;
|
|
output [3:0] VCUPLENCARCACHE1;
|
|
output [3:0] VCUPLENCARID0;
|
|
output [3:0] VCUPLENCARID1;
|
|
output [7:0] VCUPLENCARLEN0;
|
|
output [7:0] VCUPLENCARLEN1;
|
|
output VCUPLENCARPROT0;
|
|
output VCUPLENCARPROT1;
|
|
output [3:0] VCUPLENCARQOS0;
|
|
output [3:0] VCUPLENCARQOS1;
|
|
output [2:0] VCUPLENCARSIZE0;
|
|
output [2:0] VCUPLENCARSIZE1;
|
|
output VCUPLENCARVALID0;
|
|
output VCUPLENCARVALID1;
|
|
output [43:0] VCUPLENCAWADDR0;
|
|
output [43:0] VCUPLENCAWADDR1;
|
|
output [1:0] VCUPLENCAWBURST0;
|
|
output [1:0] VCUPLENCAWBURST1;
|
|
output [3:0] VCUPLENCAWCACHE0;
|
|
output [3:0] VCUPLENCAWCACHE1;
|
|
output [3:0] VCUPLENCAWID0;
|
|
output [3:0] VCUPLENCAWID1;
|
|
output [7:0] VCUPLENCAWLEN0;
|
|
output [7:0] VCUPLENCAWLEN1;
|
|
output VCUPLENCAWPROT0;
|
|
output VCUPLENCAWPROT1;
|
|
output [3:0] VCUPLENCAWQOS0;
|
|
output [3:0] VCUPLENCAWQOS1;
|
|
output [2:0] VCUPLENCAWSIZE0;
|
|
output [2:0] VCUPLENCAWSIZE1;
|
|
output VCUPLENCAWVALID0;
|
|
output VCUPLENCAWVALID1;
|
|
output VCUPLENCBREADY0;
|
|
output VCUPLENCBREADY1;
|
|
output VCUPLENCRREADY0;
|
|
output VCUPLENCRREADY1;
|
|
output [127:0] VCUPLENCWDATA0;
|
|
output [127:0] VCUPLENCWDATA1;
|
|
output VCUPLENCWLAST0;
|
|
output VCUPLENCWLAST1;
|
|
output VCUPLENCWVALID0;
|
|
output VCUPLENCWVALID1;
|
|
output [43:0] VCUPLMCUMAXIICDCARADDR;
|
|
output [1:0] VCUPLMCUMAXIICDCARBURST;
|
|
output [3:0] VCUPLMCUMAXIICDCARCACHE;
|
|
output [2:0] VCUPLMCUMAXIICDCARID;
|
|
output [7:0] VCUPLMCUMAXIICDCARLEN;
|
|
output VCUPLMCUMAXIICDCARLOCK;
|
|
output [2:0] VCUPLMCUMAXIICDCARPROT;
|
|
output [3:0] VCUPLMCUMAXIICDCARQOS;
|
|
output [2:0] VCUPLMCUMAXIICDCARSIZE;
|
|
output VCUPLMCUMAXIICDCARVALID;
|
|
output [43:0] VCUPLMCUMAXIICDCAWADDR;
|
|
output [1:0] VCUPLMCUMAXIICDCAWBURST;
|
|
output [3:0] VCUPLMCUMAXIICDCAWCACHE;
|
|
output [2:0] VCUPLMCUMAXIICDCAWID;
|
|
output [7:0] VCUPLMCUMAXIICDCAWLEN;
|
|
output VCUPLMCUMAXIICDCAWLOCK;
|
|
output [2:0] VCUPLMCUMAXIICDCAWPROT;
|
|
output [3:0] VCUPLMCUMAXIICDCAWQOS;
|
|
output [2:0] VCUPLMCUMAXIICDCAWSIZE;
|
|
output VCUPLMCUMAXIICDCAWVALID;
|
|
output VCUPLMCUMAXIICDCBREADY;
|
|
output VCUPLMCUMAXIICDCRREADY;
|
|
output [31:0] VCUPLMCUMAXIICDCWDATA;
|
|
output VCUPLMCUMAXIICDCWLAST;
|
|
output [3:0] VCUPLMCUMAXIICDCWSTRB;
|
|
output VCUPLMCUMAXIICDCWVALID;
|
|
output VCUPLMCUSTATUSCLKPLL;
|
|
output VCUPLPINTREQ;
|
|
output VCUPLPLLSTATUSPLLLOCK;
|
|
output VCUPLPWRSUPPLYSTATUSVCCAUX;
|
|
output VCUPLPWRSUPPLYSTATUSVCUINT;
|
|
output [31:0] VCUPLRDATAAXILITEAPB;
|
|
output [1:0] VCUPLRRESPAXILITEAPB;
|
|
output VCUPLRVALIDAXILITEAPB;
|
|
output VCUPLWREADYAXILITEAPB;
|
|
input INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD;
|
|
input [19:0] PLVCUARADDRAXILITEAPB;
|
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input [2:0] PLVCUARPROTAXILITEAPB;
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input PLVCUARVALIDAXILITEAPB;
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input [19:0] PLVCUAWADDRAXILITEAPB;
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input [2:0] PLVCUAWPROTAXILITEAPB;
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input PLVCUAWVALIDAXILITEAPB;
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input PLVCUAXIDECCLK;
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input PLVCUAXIENCCLK;
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input PLVCUAXILITECLK;
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input PLVCUAXIMCUCLK;
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input PLVCUBREADYAXILITEAPB;
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input PLVCUCORECLK;
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input PLVCUDECARREADY0;
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input PLVCUDECARREADY1;
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input PLVCUDECAWREADY0;
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input PLVCUDECAWREADY1;
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input [3:0] PLVCUDECBID0;
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input [3:0] PLVCUDECBID1;
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input [1:0] PLVCUDECBRESP0;
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input [1:0] PLVCUDECBRESP1;
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input PLVCUDECBVALID0;
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input PLVCUDECBVALID1;
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input [127:0] PLVCUDECRDATA0;
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input [127:0] PLVCUDECRDATA1;
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input [3:0] PLVCUDECRID0;
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input [3:0] PLVCUDECRID1;
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input PLVCUDECRLAST0;
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input PLVCUDECRLAST1;
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input [1:0] PLVCUDECRRESP0;
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input [1:0] PLVCUDECRRESP1;
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input PLVCUDECRVALID0;
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input PLVCUDECRVALID1;
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input PLVCUDECWREADY0;
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input PLVCUDECWREADY1;
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input [319:0] PLVCUENCALL2CRDATA;
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input PLVCUENCALL2CRREADY;
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input PLVCUENCARREADY0;
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input PLVCUENCARREADY1;
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input PLVCUENCAWREADY0;
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input PLVCUENCAWREADY1;
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input [3:0] PLVCUENCBID0;
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input [3:0] PLVCUENCBID1;
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input [1:0] PLVCUENCBRESP0;
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input [1:0] PLVCUENCBRESP1;
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input PLVCUENCBVALID0;
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input PLVCUENCBVALID1;
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input PLVCUENCL2CCLK;
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input [127:0] PLVCUENCRDATA0;
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input [127:0] PLVCUENCRDATA1;
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input [3:0] PLVCUENCRID0;
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input [3:0] PLVCUENCRID1;
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input PLVCUENCRLAST0;
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input PLVCUENCRLAST1;
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input [1:0] PLVCUENCRRESP0;
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input [1:0] PLVCUENCRRESP1;
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input PLVCUENCRVALID0;
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input PLVCUENCRVALID1;
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|
input PLVCUENCWREADY0;
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|
input PLVCUENCWREADY1;
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|
input PLVCUMCUCLK;
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|
input PLVCUMCUMAXIICDCARREADY;
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|
input PLVCUMCUMAXIICDCAWREADY;
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|
input [2:0] PLVCUMCUMAXIICDCBID;
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|
input [1:0] PLVCUMCUMAXIICDCBRESP;
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|
input PLVCUMCUMAXIICDCBVALID;
|
|
input [31:0] PLVCUMCUMAXIICDCRDATA;
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|
input [2:0] PLVCUMCUMAXIICDCRID;
|
|
input PLVCUMCUMAXIICDCRLAST;
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|
input [1:0] PLVCUMCUMAXIICDCRRESP;
|
|
input PLVCUMCUMAXIICDCRVALID;
|
|
input PLVCUMCUMAXIICDCWREADY;
|
|
input PLVCUPLLREFCLKPL;
|
|
input PLVCURAWRSTN;
|
|
input PLVCURREADYAXILITEAPB;
|
|
input [31:0] PLVCUWDATAAXILITEAPB;
|
|
input [3:0] PLVCUWSTRBAXILITEAPB;
|
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input PLVCUWVALIDAXILITEAPB;
|
|
endmodule
|
|
|
|
module FE(DEBUG_DOUT, DEBUG_PHASE, INTERRUPT, M_AXIS_DOUT_TDATA, M_AXIS_DOUT_TLAST, M_AXIS_DOUT_TVALID, M_AXIS_STATUS_TDATA, M_AXIS_STATUS_TVALID, SPARE_OUT, S_AXIS_CTRL_TREADY, S_AXIS_DIN_TREADY, S_AXIS_DIN_WORDS_TREADY, S_AXIS_DOUT_WORDS_TREADY, S_AXI_ARREADY, S_AXI_AWREADY, S_AXI_BVALID, S_AXI_RDATA, S_AXI_RVALID, S_AXI_WREADY, CORE_CLK, DEBUG_CLK_EN
|
|
, DEBUG_EN, DEBUG_SEL_IN, M_AXIS_DOUT_ACLK, M_AXIS_DOUT_TREADY, M_AXIS_STATUS_ACLK, M_AXIS_STATUS_TREADY, RESET_N, SPARE_IN, S_AXIS_CTRL_ACLK, S_AXIS_CTRL_TDATA, S_AXIS_CTRL_TVALID, S_AXIS_DIN_ACLK, S_AXIS_DIN_TDATA, S_AXIS_DIN_TLAST, S_AXIS_DIN_TVALID, S_AXIS_DIN_WORDS_ACLK, S_AXIS_DIN_WORDS_TDATA, S_AXIS_DIN_WORDS_TLAST, S_AXIS_DIN_WORDS_TVALID, S_AXIS_DOUT_WORDS_ACLK, S_AXIS_DOUT_WORDS_TDATA
|
|
, S_AXIS_DOUT_WORDS_TLAST, S_AXIS_DOUT_WORDS_TVALID, S_AXI_ACLK, S_AXI_ARADDR, S_AXI_ARVALID, S_AXI_AWADDR, S_AXI_AWVALID, S_AXI_BREADY, S_AXI_RREADY, S_AXI_WDATA, S_AXI_WVALID);
|
|
parameter MODE = "TURBO_DECODE";
|
|
parameter real PHYSICAL_UTILIZATION = 100.00;
|
|
parameter SIM_DEVICE = "ULTRASCALE_PLUS";
|
|
parameter STANDARD = "LTE";
|
|
parameter real THROUGHPUT_UTILIZATION = 100.00;
|
|
output [399:0] DEBUG_DOUT;
|
|
output DEBUG_PHASE;
|
|
output INTERRUPT;
|
|
output [511:0] M_AXIS_DOUT_TDATA;
|
|
output M_AXIS_DOUT_TLAST;
|
|
output M_AXIS_DOUT_TVALID;
|
|
output [31:0] M_AXIS_STATUS_TDATA;
|
|
output M_AXIS_STATUS_TVALID;
|
|
output [15:0] SPARE_OUT;
|
|
output S_AXIS_CTRL_TREADY;
|
|
output S_AXIS_DIN_TREADY;
|
|
output S_AXIS_DIN_WORDS_TREADY;
|
|
output S_AXIS_DOUT_WORDS_TREADY;
|
|
output S_AXI_ARREADY;
|
|
output S_AXI_AWREADY;
|
|
output S_AXI_BVALID;
|
|
output [31:0] S_AXI_RDATA;
|
|
output S_AXI_RVALID;
|
|
output S_AXI_WREADY;
|
|
input CORE_CLK;
|
|
input DEBUG_CLK_EN;
|
|
input DEBUG_EN;
|
|
input [3:0] DEBUG_SEL_IN;
|
|
input M_AXIS_DOUT_ACLK;
|
|
input M_AXIS_DOUT_TREADY;
|
|
input M_AXIS_STATUS_ACLK;
|
|
input M_AXIS_STATUS_TREADY;
|
|
input RESET_N;
|
|
input [15:0] SPARE_IN;
|
|
input S_AXIS_CTRL_ACLK;
|
|
input [31:0] S_AXIS_CTRL_TDATA;
|
|
input S_AXIS_CTRL_TVALID;
|
|
input S_AXIS_DIN_ACLK;
|
|
input [511:0] S_AXIS_DIN_TDATA;
|
|
input S_AXIS_DIN_TLAST;
|
|
input S_AXIS_DIN_TVALID;
|
|
input S_AXIS_DIN_WORDS_ACLK;
|
|
input [31:0] S_AXIS_DIN_WORDS_TDATA;
|
|
input S_AXIS_DIN_WORDS_TLAST;
|
|
input S_AXIS_DIN_WORDS_TVALID;
|
|
input S_AXIS_DOUT_WORDS_ACLK;
|
|
input [31:0] S_AXIS_DOUT_WORDS_TDATA;
|
|
input S_AXIS_DOUT_WORDS_TLAST;
|
|
input S_AXIS_DOUT_WORDS_TVALID;
|
|
input S_AXI_ACLK;
|
|
input [17:0] S_AXI_ARADDR;
|
|
input S_AXI_ARVALID;
|
|
input [17:0] S_AXI_AWADDR;
|
|
input S_AXI_AWVALID;
|
|
input S_AXI_BREADY;
|
|
input S_AXI_RREADY;
|
|
input [31:0] S_AXI_WDATA;
|
|
input S_AXI_WVALID;
|
|
endmodule
|
|
|