Jim Lawson 171c425cf9 Fix FIRRTL to Verilog process instance subfield assignment. ... Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)		2019-02-25 16:18:13 -08:00
..
.gitignore	added more .gitignore files (make test)	2013-01-05 11:35:52 +01:00
aes_kexp128.v	initial import	2013-01-05 11:13:26 +01:00
always01.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
always02.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
always03.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
arraycells.v	Fixed typo in tests/simple/arraycells.v	2017-01-04 12:39:01 +01:00
arrays01.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
carryadd.v	Bugfix in name resolution with generate blocks	2014-01-30 15:01:28 +01:00
constmuldivmod.v	Added opt_expr support for div/mod by power-of-two	2016-05-29 12:17:36 +02:00
constpower.v	Fixed handling of power operator	2013-11-07 22:20:00 +01:00
dff_different_styles.v	Another block of spelling fixes	2015-08-14 23:27:05 +02:00
dff_init.v	Extend testcase	2019-02-06 14:02:11 -08:00
fiedler-cooley.v	initial import	2013-01-05 11:13:26 +01:00
forgen01.v	Progress in Verific bindings	2014-03-17 01:56:00 +01:00
forgen02.v	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
fsm.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
generate.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
graphtest.v	Squelch trailing whitespace	2017-04-12 15:11:09 +02:00
hierarchy.v	Another block of spelling fixes	2015-08-14 23:27:05 +02:00
hierdefparam.v	Fix handling of defparam for when default_nettype is none	2019-02-24 20:09:41 +01:00
i2c_master_tests.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
loops.v	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
macros.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
mem2reg.v	Added another mem2reg test case	2016-08-21 13:45:46 +02:00
mem_arst.v	Progress in Verific bindings	2014-03-17 01:56:00 +01:00
memory.v	Fixed bug with memories that do not have a down-to-zero data width	2016-08-22 14:27:46 +02:00
multiplier.v	Added multiplier test case from eda playground	2013-12-18 13:43:53 +01:00
muxtree.v	improvements in muxtree/select_leaves test	2015-01-18 13:24:01 +01:00
omsp_dbg_uart.v	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
operators.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
paramods.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
partsel.v	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
process.v	Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values	2013-04-13 21:19:10 +02:00
realexpr.v	Fixed handling of mixed real/int ternary expressions	2014-06-25 10:05:36 +02:00
repwhile.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
rotate.v	Another block of spelling fixes	2015-08-14 23:27:05 +02:00
run-test.sh	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
scopes.v	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
signedexpr.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
sincos.v	Fix in sincos testbench gen	2013-12-04 09:24:52 +01:00
specify.v	Fix tests/simple/specify.v	2018-03-27 14:34:00 +02:00
subbytes.v	initial import	2013-01-05 11:13:26 +01:00
task_func.v	More bugfixes in handling of parameters in tasks and functions	2015-11-12 13:02:36 +01:00
undef_eqx_nex.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
usb_phy_tests.v	Renamed some of the test cases in tests/simple to avoid name collisions	2014-07-25 13:01:45 +02:00
values.v	Replaced RTLIL::Const::str with generic decoder method	2013-12-04 14:14:05 +01:00
vloghammer.v	Another block of spelling fixes	2015-08-14 23:27:05 +02:00
wreduce.v	Improvements in wreduce	2015-10-31 13:39:30 +01:00
xfirrtl	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00