mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
ab0e3cc05f
All `proc_*` passes now use the same module and process for loops, using `design->all_selected_modules()` and `mod->selected_processes()` respectively. This simplifies the code, and makes the couple `proc_*` passes that were ignoring boxed modules stop doing that (which seems to have been erroneous rather than intentional).
477 lines
13 KiB
C++
477 lines
13 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/bitpattern.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SigSnippets
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{
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idict<SigSpec> sigidx;
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dict<SigBit, int> bit2snippet;
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pool<int> snippets;
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void insert(SigSpec sig)
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{
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if (sig.empty())
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return;
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int key = sigidx(sig);
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if (snippets.count(key))
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return;
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SigSpec new_sig;
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for (int i = 0; i < GetSize(sig); i++)
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{
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int other_key = bit2snippet.at(sig[i], -1);
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if (other_key < 0) {
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new_sig.append(sig[i]);
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continue;
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}
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if (!new_sig.empty()) {
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int new_key = sigidx(new_sig);
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snippets.insert(new_key);
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for (auto bit : new_sig)
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bit2snippet[bit] = new_key;
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new_sig = SigSpec();
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}
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SigSpec other_sig = sigidx[other_key];
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int k = 0, n = 1;
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while (other_sig[k] != sig[i]) {
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k++;
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log_assert(k < GetSize(other_sig));
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}
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while (i+n < GetSize(sig) && k+n < GetSize(other_sig) && sig[i+n] == other_sig[k+n])
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n++;
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SigSpec sig1 = other_sig.extract(0, k);
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SigSpec sig2 = other_sig.extract(k, n);
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SigSpec sig3 = other_sig.extract(k+n, GetSize(other_sig)-k-n);
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for (auto bit : other_sig)
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bit2snippet.erase(bit);
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snippets.erase(other_key);
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insert(sig1);
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insert(sig2);
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insert(sig3);
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i += n-1;
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}
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if (!new_sig.empty()) {
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int new_key = sigidx(new_sig);
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snippets.insert(new_key);
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for (auto bit : new_sig)
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bit2snippet[bit] = new_key;
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}
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}
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void insert(const RTLIL::CaseRule *cs)
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{
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for (auto &action : cs->actions)
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insert(action.first);
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for (auto sw : cs->switches)
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for (auto cs2 : sw->cases)
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insert(cs2);
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}
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};
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struct SnippetSwCache
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{
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dict<RTLIL::SwitchRule*, pool<RTLIL::SigBit>> full_case_bits_cache;
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dict<RTLIL::SwitchRule*, pool<int>> cache;
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const SigSnippets *snippets;
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int current_snippet;
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bool check(RTLIL::SwitchRule *sw)
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{
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return cache[sw].count(current_snippet) != 0;
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}
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void insert(const RTLIL::CaseRule *cs, vector<RTLIL::SwitchRule*> &sw_stack)
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{
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for (auto &action : cs->actions)
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for (auto bit : action.first) {
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int sn = snippets->bit2snippet.at(bit, -1);
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if (sn < 0)
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continue;
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for (auto sw : sw_stack)
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cache[sw].insert(sn);
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}
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for (auto sw : cs->switches) {
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sw_stack.push_back(sw);
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for (auto cs2 : sw->cases)
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insert(cs2, sw_stack);
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sw_stack.pop_back();
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}
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}
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void insert(const RTLIL::CaseRule *cs)
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{
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vector<RTLIL::SwitchRule*> sw_stack;
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insert(cs, sw_stack);
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}
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};
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void apply_attrs(RTLIL::Cell *cell, const RTLIL::SwitchRule *sw, const RTLIL::CaseRule *cs)
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{
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cell->attributes = sw->attributes;
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cell->add_strpool_attribute(ID::src, cs->get_strpool_attribute(ID::src));
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}
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RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
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{
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std::stringstream sstr;
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sstr << "$procmux$" << (autoidx++);
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RTLIL::Wire *cmp_wire = mod->addWire(sstr.str() + "_CMP", 0);
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for (auto comp : compare)
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{
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RTLIL::SigSpec sig = signal;
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// get rid of don't-care bits
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log_assert(sig.size() == comp.size());
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for (int i = 0; i < comp.size(); i++)
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if (comp[i] == RTLIL::State::Sa) {
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sig.remove(i);
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comp.remove(i--);
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}
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if (comp.size() == 0)
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return RTLIL::SigSpec();
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if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1) && !ifxmode)
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{
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mod->connect(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
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}
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else
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{
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// create compare cell
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RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
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apply_attrs(eq_cell, sw, cs);
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eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0);
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eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
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eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size());
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eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
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eq_cell->setPort(ID::A, sig);
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eq_cell->setPort(ID::B, comp);
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eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
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}
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}
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RTLIL::Wire *ctrl_wire;
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if (cmp_wire->width == 1)
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{
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ctrl_wire = cmp_wire;
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}
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else
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{
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ctrl_wire = mod->addWire(sstr.str() + "_CTRL");
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// reduce cmp vector to one logic signal
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RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or));
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apply_attrs(any_cell, sw, cs);
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any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
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any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
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any_cell->setPort(ID::A, cmp_wire);
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any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
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}
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return RTLIL::SigSpec(ctrl_wire);
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}
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RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
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{
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log_assert(when_signal.size() == else_signal.size());
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std::stringstream sstr;
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sstr << "$procmux$" << (autoidx++);
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// the trivial cases
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if (compare.size() == 0 || when_signal == else_signal)
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return when_signal;
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// compare results
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RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
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if (ctrl_sig.size() == 0)
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return when_signal;
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log_assert(ctrl_sig.size() == 1);
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// prepare multiplexer output signal
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RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
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// create the multiplexer itself
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RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux));
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apply_attrs(mux_cell, sw, cs);
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mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
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mux_cell->setPort(ID::A, else_signal);
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mux_cell->setPort(ID::B, when_signal);
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mux_cell->setPort(ID::S, ctrl_sig);
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mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire));
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last_mux_cell = mux_cell;
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return RTLIL::SigSpec(result_wire);
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}
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void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
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{
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log_assert(last_mux_cell != NULL);
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log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());
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if (when_signal == last_mux_cell->getPort(ID::A))
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return;
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RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
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log_assert(ctrl_sig.size() == 1);
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last_mux_cell->type = ID($pmux);
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RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
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new_s.append(ctrl_sig);
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last_mux_cell->setPort(ID::S, new_s);
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RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B);
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new_b.append(when_signal);
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last_mux_cell->setPort(ID::B, new_b);
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last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size();
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}
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const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)
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{
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if (!swcache.full_case_bits_cache.count(sw))
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{
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pool<SigBit> bits;
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if (sw->get_bool_attribute(ID::full_case))
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{
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bool first_case = true;
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for (auto cs : sw->cases)
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{
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pool<SigBit> case_bits;
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for (auto it : cs->actions) {
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for (auto bit : it.first)
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case_bits.insert(bit);
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}
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for (auto it : cs->switches) {
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for (auto bit : get_full_case_bits(swcache, it))
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case_bits.insert(bit);
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}
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if (first_case) {
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first_case = false;
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bits = case_bits;
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} else {
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pool<SigBit> new_bits;
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for (auto bit : bits)
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if (case_bits.count(bit))
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new_bits.insert(bit);
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bits.swap(new_bits);
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}
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}
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}
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bits.swap(swcache.full_case_bits_cache[sw]);
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}
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return swcache.full_case_bits_cache.at(sw);
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}
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RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, dict<RTLIL::SwitchRule*, bool> &swpara,
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RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval, bool ifxmode)
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{
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RTLIL::SigSpec result = defval;
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for (auto &action : cs->actions) {
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sig.replace(action.first, action.second, &result);
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action.first.remove2(sig, &action.second);
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}
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for (auto sw : cs->switches)
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{
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if (!swcache.check(sw))
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continue;
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// detect groups of parallel cases
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std::vector<int> pgroups(sw->cases.size());
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bool is_simple_parallel_case = true;
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if (!sw->get_bool_attribute(ID::parallel_case)) {
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if (!swpara.count(sw)) {
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pool<Const> case_values;
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for (size_t i = 0; i < sw->cases.size(); i++) {
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RTLIL::CaseRule *cs2 = sw->cases[i];
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for (auto pat : cs2->compare) {
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if (!pat.is_fully_def())
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goto not_simple_parallel_case;
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Const cpat = pat.as_const();
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if (case_values.count(cpat))
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goto not_simple_parallel_case;
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case_values.insert(cpat);
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}
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}
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if (0)
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not_simple_parallel_case:
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is_simple_parallel_case = false;
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swpara[sw] = is_simple_parallel_case;
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} else {
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is_simple_parallel_case = swpara.at(sw);
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}
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}
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if (!is_simple_parallel_case) {
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BitPatternPool pool(sw->signal.size());
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bool extra_group_for_next_case = false;
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for (size_t i = 0; i < sw->cases.size(); i++) {
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RTLIL::CaseRule *cs2 = sw->cases[i];
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if (i != 0) {
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pgroups[i] = pgroups[i-1];
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if (extra_group_for_next_case) {
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pgroups[i] = pgroups[i-1]+1;
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extra_group_for_next_case = false;
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}
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for (auto pat : cs2->compare)
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if (!pat.is_fully_const() || !pool.has_all(pat))
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pgroups[i] = pgroups[i-1]+1;
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if (cs2->compare.empty())
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pgroups[i] = pgroups[i-1]+1;
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if (pgroups[i] != pgroups[i-1])
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pool = BitPatternPool(sw->signal.size());
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}
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for (auto pat : cs2->compare)
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if (!pat.is_fully_const())
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extra_group_for_next_case = true;
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else if (!ifxmode)
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pool.take(pat);
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}
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}
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// mask default bits that are irrelevant because the output is driven by a full case
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const pool<SigBit> &full_case_bits = get_full_case_bits(swcache, sw);
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for (int i = 0; i < GetSize(sig); i++)
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if (full_case_bits.count(sig[i]))
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result[i] = State::Sx;
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// evaluate in reverse order to give the first entry the top priority
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RTLIL::SigSpec initial_val = result;
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RTLIL::Cell *last_mux_cell = NULL;
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for (size_t i = 0; i < sw->cases.size(); i++) {
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int case_idx = sw->cases.size() - i - 1;
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RTLIL::CaseRule *cs2 = sw->cases[case_idx];
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RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, cs2, sig, initial_val, ifxmode);
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if (last_mux_cell && pgroups[case_idx] == pgroups[case_idx+1])
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append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, cs2, ifxmode);
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else
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result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, cs2, ifxmode);
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}
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}
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return result;
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}
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void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode)
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{
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log("Creating decoders for process `%s.%s'.\n", mod->name.c_str(), proc->name.c_str());
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SigSnippets sigsnip;
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sigsnip.insert(&proc->root_case);
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SnippetSwCache swcache;
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swcache.snippets = &sigsnip;
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swcache.insert(&proc->root_case);
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dict<RTLIL::SwitchRule*, bool> swpara;
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int cnt = 0;
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for (int idx : sigsnip.snippets)
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{
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swcache.current_snippet = idx;
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RTLIL::SigSpec sig = sigsnip.sigidx[idx];
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log("%6d/%d: %s\n", ++cnt, GetSize(sigsnip.snippets), log_signal(sig));
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RTLIL::SigSpec value = signal_to_mux_tree(mod, swcache, swpara, &proc->root_case, sig, RTLIL::SigSpec(RTLIL::State::Sx, sig.size()), ifxmode);
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mod->connect(RTLIL::SigSig(sig, value));
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}
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}
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struct ProcMuxPass : public Pass {
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ProcMuxPass() : Pass("proc_mux", "convert decision trees to multiplexers") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_mux [options] [selection]\n");
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log("\n");
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log("This pass converts the decision trees in processes (originating from if-else\n");
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log("and case statements) to trees of multiplexer cells.\n");
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log("\n");
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log(" -ifx\n");
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log(" Use Verilog simulation behavior with respect to undef values in\n");
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log(" 'case' expressions and 'if' conditions.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool ifxmode = false;
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log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-ifx") {
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ifxmode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->all_selected_modules())
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for (auto proc : mod->selected_processes())
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proc_mux(mod, proc, ifxmode);
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|
}
|
|
} ProcMuxPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|