mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
70 lines
1.9 KiB
Text
70 lines
1.9 KiB
Text
read_rtlil << EOF
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autoidx 524
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attribute \top 1
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attribute \library "work"
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attribute \hdlname "main"
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module \main
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attribute \force_downto 1
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wire width 18 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0]
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wire width 12 $delete_wire$514
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wire width 4 $test
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attribute \module_not_derived 1
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cell \SB_MAC16 $verific$mult_4$garbage/usb.v:12$388.etc.sliceB[0].mul
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parameter \A_REG 1'0
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parameter \A_SIGNED 0
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parameter \BOTADDSUB_CARRYSELECT 2'00
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parameter \BOTADDSUB_LOWERINPUT 2'00
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parameter \BOTADDSUB_UPPERINPUT 1'0
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parameter \BOTOUTPUT_SELECT 2'11
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parameter \BOT_8x8_MULT_REG 1'0
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parameter \B_REG 1'0
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parameter signed \B_SIGNED 0
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parameter \C_REG 1'0
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parameter \D_REG 1'0
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parameter \MODE_8x8 1'0
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parameter \NEG_TRIGGER 1'0
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parameter \PIPELINE_16x16_MULT_REG1 1'0
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parameter \PIPELINE_16x16_MULT_REG2 1'0
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parameter \TOPADDSUB_CARRYSELECT 2'00
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parameter \TOPADDSUB_LOWERINPUT 2'00
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parameter \TOPADDSUB_UPPERINPUT 1'0
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parameter \TOPOUTPUT_SELECT 2'11
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parameter \TOP_8x8_MULT_REG 1'0
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connect \A 16'x
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connect \B 16'x
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connect \O { $test $delete_wire$514 14'x $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0] }
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end
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cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.etc.sliceA.last.$add$/home/emil/pulls/yosys/share/mul2dsp.v:216$483
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parameter \A_SIGNED 0
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parameter \A_WIDTH 18
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parameter \B_SIGNED 0
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parameter \B_WIDTH 2
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parameter \Y_WIDTH 19
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connect \A 18'x
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connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0]
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connect \Y 19'x
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end
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cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.$add$/home/emil/pulls/yosys/share/mul2dsp.v:173$480
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parameter \A_SIGNED 0
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parameter \A_WIDTH 2
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parameter \B_SIGNED 0
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parameter \B_WIDTH 2
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parameter \Y_WIDTH 2
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connect \A $delete_wire$514 [1:0]
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connect \B 2'x
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connect \Y 2'x
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end
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end
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EOF
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ice40_dsp
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