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https://github.com/YosysHQ/yosys
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51 lines
1.4 KiB
C++
51 lines
1.4 KiB
C++
#ifndef PATCH_H
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#define PATCH_H
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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YOSYS_NAMESPACE_BEGIN
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struct RTLIL::Patch final : public CellAdderMixin<RTLIL::Patch>
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{
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Hasher::hash_t hashidx_;
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[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
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private:
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void collect_src(Cell* old_cell);
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void gc(Cell* old_cell);
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protected:
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void add(RTLIL::Wire *wire);
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void add(RTLIL::Cell *cell);
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void add(RTLIL::Process *process);
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public:
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Module *mod;
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// SigMap map;
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vector<std::unique_ptr<Wire>> wires_;
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vector<std::unique_ptr<Cell>> cells_;
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Cell* root;
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pool<Wire*> leaves;
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// vector<RTLIL::SigSig> connections_;
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pool<string> src;
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void connect(const RTLIL::SigSig &conn);
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void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
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const std::vector<RTLIL::SigSig> &connections() const;
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void patch(Cell* old_cell, Cell* new_cell);
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RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
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RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
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RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
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RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
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RTLIL::Cell* addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
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RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src);
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};
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YOSYS_NAMESPACE_END
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#endif
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