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3006280d70
run_fixed inferred a fixed length shift register from a chain of FDRE flops but assigned it ENPOL 2, which the cells_map template reads as no enable and ties the enable high. FDRE has an active high clock enable, so the shift register shifted every cycle and ignored stalls. Give FDRE and FDRE_1 chains ENPOL 1 so the active high enable is kept. Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
46 lines
1.4 KiB
Text
46 lines
1.4 KiB
Text
# Regression test for a xilinx_srl bug where a fixed shift register inferred
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# from FDRE cells dropped the clock enable. FDRE has an active high clock
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# enable but run_fixed assigned it ENPOL 2 (no enable) instead of ENPOL 1,
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# so the resulting shift register shifted every cycle and ignored stalls.
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read_verilog <<EOT
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module xilinx_srl_enable_test(input i, clk, ce, output q);
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reg [3:0] shift = 4'b0000;
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always @(posedge clk)
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if (ce)
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shift <= {shift[2:0], i};
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assign q = shift[3];
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endmodule
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module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
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parameter CLKPOL = 1;
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parameter ENPOL = 1;
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parameter DEPTH = 2;
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parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
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reg [DEPTH-1:0] r = INIT;
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wire ce = (ENPOL == 2) ? 1'b1 : (ENPOL == 1) ? E : ~E;
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always @(posedge C)
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if (ce)
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r <= { r[DEPTH-2:0], D };
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assign Q = r[L];
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endmodule
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EOT
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design -copy-to model $__XILINX_SHREG_
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hierarchy -top xilinx_srl_enable_test
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prep
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design -save gold
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synth_xilinx -noiopad -noclkbuf -run begin:map_luts
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opt_expr -mux_undef -noclkinv
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techmap -map +/xilinx/ff_map.v
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xilinx_srl -fixed
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opt
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select -assert-count 1 t:$__XILINX_SHREG_
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
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prep
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports -seq 6 miter
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