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yosys/tests/arch/xilinx
History
drewbabel 3006280d70
xilinx_srl: keep the clock enable on FDRE shift registers 
run_fixed inferred a fixed length shift register from a chain of FDRE
flops but assigned it ENPOL 2, which the cells_map template reads as no
enable and ties the enable high. FDRE has an active high clock enable, so
the shift register shifted every cycle and ignored stalls. Give FDRE and
FDRE_1 chains ENPOL 1 so the active high enable is kept.

Add tests/arch/xilinx/xilinx_srl_enable.ys covering the FDRE path.
2026-07-20 23:59:40 -07:00
..
.gitignore Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
abc9_dff.ys tests/arch/xilinx: Fix for warnings on boxes 2025-04-08 16:58:59 +12:00
add_sub.ys xilinx: Initial support for LUT4 devices. 2020-02-07 09:03:22 +01:00
adffs.ys Make test without iopads 2019-12-28 16:22:24 +01:00
asym_ram_sdp.ys End of file fix 2026-06-23 07:23:41 +02:00
asym_ram_sdp_read_wider.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
asym_ram_sdp_write_wider.v End of file fix 2026-06-23 07:23:41 +02:00
attributes_test.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
blockram.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
bug1460.ys Make test without iopads 2019-12-28 16:22:24 +01:00
bug1462.ys xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
bug1480.ys Cleanup tests 2020-02-27 10:17:29 -08:00
bug1598.ys Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
bug1605.ys Added a test case 2020-01-01 16:24:30 +01:00
bug3670.v ABC9: Cell Port Bug Patch (#3670) 2023-04-22 16:24:36 -07:00
bug3670.ys ABC9: Cell Port Bug Patch (#3670) 2023-04-22 16:24:36 -07:00
counter.ys Fix tests 2020-01-10 14:48:01 +01:00
dffs.ys End of file fix 2026-06-23 07:23:41 +02:00
dsp_abc9.ys tests/arch/xilinx: Fix for warnings on boxes 2025-04-08 16:58:59 +12:00
dsp_cascade.ys End of file fix 2026-06-23 07:23:41 +02:00
dsp_fastfir.ys Make test without iopads 2019-12-28 16:22:24 +01:00
dsp_preadder_sub.ys Simplify test 2026-02-09 09:38:45 -08:00
dsp_simd.ys Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
dynamic_upto_select.ys Replace suitable (2^k-1)-x with ~x. 2026-06-10 11:29:55 +02:00
fsm.ys FfData: some refactoring. 2021-10-07 04:24:06 +02:00
generate_mk.py Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
latches.ys opt_expr: Remove -clkinv option, make it the default. 2020-07-31 00:08:15 +02:00
logic.ys Make test without iopads 2019-12-28 16:22:24 +01:00
lutram.ys xilinx: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
macc.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
macc.v tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
macc.ys tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
macc_tb.v Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
mul.ys Fix new tests 2019-12-28 16:43:19 +01:00
mul_unsigned.v Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
mul_unsigned.ys Fix new tests 2019-12-28 16:43:19 +01:00
mux.ys xilinx_dffopt: Don't crash on missing IS_*_INVERTED. 2021-01-27 00:32:00 +01:00
mux_lut4.ys Update tests 2023-06-09 14:41:45 +02:00
nosrl.ys xilinx: Fix srl regression. 2020-07-12 23:41:27 +02:00
opt_lut_ins.ys Remove references to ilang 2024-11-05 12:36:31 +13:00
pmgen_xilinx_srl.ys satgen: Add support for dffe, sdff, sdffe, sdffce cells. 2020-07-24 03:19:21 +02:00
priority_memory.v URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
priority_memory.ys URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
shifter.ys Make test without iopads 2019-12-28 16:22:24 +01:00
tribuf.sh Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
tribuf.ys Addressed review comments 2019-12-21 20:23:23 +01:00
xilinx_dffopt.ys Fix tests for check in equiv_opt 2022-10-07 16:04:51 +02:00
xilinx_dffopt_blacklist.txt xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
xilinx_dsp.ys tests: read +/xilinx/cell_sim.v before xilinx_dsp test 2020-04-22 17:50:30 -07:00
xilinx_srl.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
xilinx_srl.ys Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
xilinx_srl_enable.ys xilinx_srl: keep the clock enable on FDRE shift registers 2026-07-20 23:59:40 -07:00