yosys/tests/various/reg_wire_error.ys at 9dca024a30e5f6cfb06e1abb584ce1320fb81f16 - mirrors/yosys - Libre-Chip.org

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Udi Finkelstein 80d9d15f1c reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files

2018-06-05 18:00:06 +03:00

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read_verilog -sv reg_wire_error.sv