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yosys/techlibs/ice40
2019-06-10 11:02:54 -07:00
..
tests
.gitignore
abc_hx.box Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) 2019-06-03 12:34:55 -07:00
abc_hx.lut Fix rename 2019-04-18 09:04:34 -07:00
abc_lp.box Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) 2019-06-03 12:34:55 -07:00
abc_lp.lut
abc_u.box Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) 2019-06-03 12:34:55 -07:00
abc_u.lut
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v Ooopsie 2019-06-03 09:33:42 -07:00
cells_sim.v Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-10 11:02:54 -07:00
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc
ice40_unlut.cc
latches_map.v
Makefile.inc Also update Makefile.inc 2019-04-18 09:58:34 -07:00
synth_ice40.cc Consistent with xilinx 2019-06-03 09:23:43 -07:00